A semiconductor structure and a manufacturing method thereof

Abstract

A semiconductor device and a manufacturing method thereof. The semiconductor device may include a first wafer (300), a second wafer (400), and a contact plug (360). The first wafer (300) may include a first dielectric layer (320), and a first pad (330) is disposed in the first dielectric layer (320). The second wafer (400) is bonded to the first wafer (300). The second wafer (400) includes a second dielectric layer (420), and a second pad (430) is disposed in the second dielectric layer (420). The contact plug (360) is a conductive material filled in a vertical through-hole for electrically connecting the first pad (330) and the second pad (430). The vertical through-hole is a through-hole formed by etching that penetrates the first wafer (300) and partially penetrates the second wafer (400) to the upper surface and / or sidewall of the second pad (430). The first pad (330) is located in the vertical through-hole, and the first dielectric layer (320) under the first pad (330) is not etched. The contact plug (360) can contact the second pad (430) from around the first pad (330), thereby realizing a reliable connection between the contact plug (360) and the second pad (430) by using a simple process.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In recent years, the integration density and power density of semiconductor devices and integrated circuits have increased rapidly. Due to limited planar space, Moore's Law has reached a bottleneck. The three-dimensional stacking technology is the current mainstream breakthrough solution. Using the three-dimensional stacking technology, multi-layer or 3D structures can be formed. 3D structures such as three-dimensional integrated circuits (3D-IC), Micro-Electro-Mechanical System (MEMS), complementary metal oxide semiconductor (CMOS) image sensors (CMOS image sensor, CIS), etc. In the three-dimensional stacking technology, bonding is the core process, which has experienced a technological iteration process from micro-bump bonding, Cu pillar bonding to wafer bonding technology. Currently, the three-dimensional stacking technology is mainly based on wafer bonding technology, and the wafer bonding technology has become the key in the competition of three-dimensional stacking technology among various manufacturers.

[0003] Wafer bonding is a technology that bonds the surfaces of wafers and forms mechanical and electrical connections. Dielectric layer bonding is an implementation method of wafer bonding. It is a wafer bonding technology that forms covalent bonds between dielectric layers. At this time, the two wafers bonded to each other do not achieve electrical connection. To realize the interconnection of dielectric layer bonded wafers, the Through Silicon Via (TSV) technology can be used. The TSV technology forms a through-hole from the back of the wafer and fills it with a conductive material to achieve vertical interconnection between wafers. For example, two through-holes are respectively penetrated into different wafers and filled with a conductive material to obtain contact plugs respectively connected to these two wafers, and then connection lines respectively connected to the two are set, thus realizing the connection between different wafers. However, in this method, the connection between the two wafers is achieved by using contact plugs and connection lines, and the wiring between them is relatively long. Therefore, there is a long signal delay and it cannot meet the actual needs in some scenarios. At the same time, using multiple contact plugs to achieve three-dimensional interconnection occupies more planar space and is not conducive to improving the integration density of devices. Summary of the Invention

[0004] In view of this, the first aspect of this application provides a semiconductor structure and a manufacturing method thereof, which reduces the signal delay between wafers.

[0005] In the first aspect of the embodiments of the present application, a semiconductor device is provided. The semiconductor device may include: a first wafer, a second wafer, and a contact plug. Among them, the first wafer may include a first dielectric layer, and a first connection pad may be provided in the first dielectric layer. The first connection pad may be used for leading out the signals of the first wafer. The second wafer is bonded to the first wafer. The second wafer may include a second dielectric layer, and a second connection pad may be provided in the second dielectric layer. The second connection pad may be used for leading out the signals of the second wafer. The contact plug may be a conductive material filled in a vertical through-hole and is used for electrically connecting the first connection pad and the second connection pad. The vertical through-hole is a through-hole formed by etching that penetrates the first wafer and partially penetrates the second wafer to the upper surface and / or sidewall of the second connection pad. The first connection pad is located in the vertical through-hole and the first dielectric layer located below the first connection pad is not etched. In this way, the contact plug in the vertical through-hole can realize the electrical connection between the first connection pad and the second connection pad by contacting the upper surface of the first connection pad and the upper surface and / or sidewall of the second connection pad, thereby realizing the vertical interconnection between the first wafer and the second wafer. The contact plug serves as a signal transmission channel between the first connection pad and the second connection pad, and its path is short, reducing signal delay. At the same time, the vertical through-hole is formed by an etching process and penetrates from the sidewall of the first connection pad to the second connection pad. The contact plug therein can contact the second connection pad from around the first connection pad, thereby realizing a reliable connection between the contact plug and the second connection pad by a simple process. In addition, there is only one metal plug in the embodiments of the present application, and there is no need to consider the distance between two metal plugs. Therefore, the lateral dimension can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.

[0006] As a possible implementation manner, the second connection pad is longitudinally and directly opposite to the first connection pad, and the sidewall of at least one side of the second connection pad extends laterally beyond the sidewall of the first connection pad. Then, the vertical through-hole exposes the upper surface adjacent to the sidewall of the second connection pad and the at least one side, or the sidewall of the second connection pad and the at least one side and the adjacent upper surface.

[0007] In the embodiments of the present application, the sidewall of at least one side of the second connection pad extends laterally beyond the sidewall of the first connection pad. At this time, the vertical through-hole can be made to expose at least the upper surface of the second connection pad adjacent to the sidewall extending beyond the first connection pad to realize the contact between the contact plug and the second connection pad. Of course, the vertical through-hole can also expose the sidewall of the second connection pad extending beyond the first connection pad, so as to improve the contact reliability between the contact plug and the second connection pad to a certain extent, thereby improving the reliability of the electrical connection between the first connection pad and the second connection pad.

[0008] As a possible implementation manner, the vertical through-hole exposes the sidewall of the first connection pad; or in the vertical through-hole, a first dielectric layer is retained on the sidewall of the first connection pad.

[0009] In the embodiment of the present application, the vertical through hole may expose the side wall of the first connection pad, so that the contact reliability between the contact plug formed in the vertical through hole and the first connection pad can be improved. Of course, the side wall of the first connection pad may not be exposed in the vertical through hole, but the first dielectric layer on the side wall of the first connection pad may be retained during the etching process. In this way, the first dielectric layer can protect the side wall of the first connection pad, thereby improving the structural integrity of the first connection pad and further improving the functional integrity of the first connection pad.

[0010] As a possible implementation manner, the second connection pad is longitudinally and directly opposite to the first connection pad, and at least one side wall of the second connection pad is flush with the side wall of the first connection pad. Then, the vertical through hole exposes at least one side wall of the second connection pad and the side wall of the first connection pad flush with the second connection pad.

[0011] In the embodiment of the present application, at least one side wall of the second connection pad is flush with the side wall of the first connection pad. At this time, the side walls of the first connection pad and the second connection pad can be exposed by using the vertical through hole, so that the side walls of the first connection pad and the second connection pad can be connected by using the contact plug to realize the electrical connection between the first connection pad and the second connection pad, reduce the redundant lateral area of the vertical interconnection structure, thereby reducing the device area and improving the device integration degree.

[0012] As a possible implementation manner, the second connection pad and the first connection pad are longitudinally staggered, and the size of the top opening of the vertical through hole is greater than or equal to the lateral distance between the second connection pad and the first connection pad.

[0013] In the embodiment of the present application, the second connection pad and the first connection pad may be longitudinally staggered. At this time, there is no overlapping area between the first connection pad and the second connection pad in the longitudinal direction, and there is a lateral distance in the transverse direction. Then, the size of the top opening of the vertical through hole may be greater than or equal to the lateral distance between the second connection pad and the first connection pad, so as to smoothly expose the first connection pad and the second connection pad to realize the electrical connection between the two and improve the reliability of the electrical connection.

[0014] As a possible implementation manner, the semiconductor device further includes: a third wafer;

[0015] The third wafer has a third connection pad; the third wafer is bonded to the first wafer to realize the electrical connection between the third connection pad and the contact plug.

[0016] In the embodiment of the present application, the semiconductor device may further include a third wafer. The third connection pad in the third wafer can be connected to the first wafer and the second wafer by being electrically connected to the contact plug. Specifically, the third wafer can be bonded to the first wafer, thereby further improving the integration degree of the device.

[0017] As a possible implementation, the vertical through hole penetrates in the direction of the multi-side side walls of the first connection pad.

[0018] In the embodiment of the present application, the vertical through hole can penetrate in the direction of the multi-side side walls of the first connection pad, so that the contact plug formed in the vertical through hole can surround the first connection pad on multiple sides, thereby improving the contact reliability between the contact plug and the first connection pad, and can also increase the contact area between the contact plug and the second connection pad to a certain extent, so as to improve the contact reliability between the contact plug and the second connection pad.

[0019] In the second aspect of the embodiment of the present application, a manufacturing method of a semiconductor device is provided, including:

[0020] Providing a first wafer and a second wafer that have been completed with bonding; the first wafer includes a first dielectric layer, and the first connection pad is disposed in the first dielectric layer; the second wafer includes a second dielectric layer, and the second connection pad is disposed in the second dielectric layer;

[0021] Using the first connection pad as a barrier layer, etching the first wafer from top to bottom to form a vertical through hole, the vertical through hole penetrates the first wafer to the upper surface of the first connection pad, and penetrates the second wafer along the side wall of the first connection pad to the second connection pad, and exposes the upper surface and / or side wall of the second connection pad;

[0022] Filling a conductive material in the vertical through hole to form a contact plug, and the contact plug is used to realize the electrical connection between the first connection pad and the second connection pad.

[0023] As a possible implementation, the second connection pad is longitudinally and directly opposite to the first connection pad, then using the first connection pad as a barrier layer, etching the first wafer from top to bottom to form a vertical through hole includes:

[0024] Etching from the upper surface of the first wafer to obtain a first opening; the first opening is located above the first connection pad, and at least one side wall of the first opening laterally exceeds the side wall of the first connection pad;

[0025] Etching at the bottom of the position where the side wall of the first opening laterally exceeds the first connection pad to form a second opening;

[0026] Using the first connection pad as a barrier layer, deepening the first opening and the second opening together, so that the deepened first opening exposes the upper surface of the first connection pad, and the deepened second opening exposes the upper surface and / or side wall of the second connection pad.

[0027] As a possible implementation, in the direction where the sidewall of the first opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad. The deepened second opening exposes the upper surface adjacent to the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad, or the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad and its adjacent upper surface;

[0028] And / or, in the direction where the sidewall of the first opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad is flush with the sidewall of the first connection pad. Then the deepened second opening exposes the sidewall of the second connection pad that is flush with the first connection pad.

[0029] As a possible implementation, in the direction where the sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad, a first dielectric layer is retained on the sidewall of the first connection pad in the deepened second opening.

[0030] As a possible implementation, the second connection pad is longitudinally and directly opposite to the first connection pad, and a third opening is formed in the first dielectric layer. Then, using the first connection pad as a barrier layer, etching the first wafer from top to bottom to form a vertical through hole includes:

[0031] Etching a first opening from the upper surface of the first wafer; the first opening is located above the first connection pad, and at least one sidewall of the first opening extends laterally beyond the sidewall of the first connection pad;

[0032] Using the first connection pad as a barrier layer, etching the first dielectric layer and the second dielectric layer at the bottom of the first opening to connect the deepened first opening and the third opening, and deepening the third opening during the etching process; the deepened first opening exposes the upper surface of the first connection pad, and the deepened third opening exposes the upper surface and / or sidewall of the second connection pad.

[0033] As a possible implementation, in the direction where the sidewall of the first opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad. The deepened third opening exposes the upper surface adjacent to the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad, or the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad and its adjacent upper surface;

[0034] And / or, in the direction that the sidewall of the first opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad is flush with the sidewall of the first connection pad, so that the deepened third opening exposes the sidewall of the second connection pad that is flush with the first connection pad.

[0035] As a possible implementation, in the direction that the sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad, a first dielectric layer is retained on the sidewall of the first connection pad in the deepened third opening.

[0036] As a possible implementation, the second connection pad is longitudinally and directly opposite to the first connection pad. Then, using the first connection pad as a barrier layer, etching the first wafer from top to bottom to form a vertical through hole includes:

[0037] Etching from the upper surface of the first wafer to obtain a first opening; the first opening is located above the first connection pad, and at least one sidewall of the first opening extends laterally beyond the sidewall of the first connection pad;

[0038] Using the first connection pad as a barrier layer, deepening the first opening so that the deepened first opening exposes the upper surface of the first connection pad, as well as the upper surface and / or sidewall of the second connection pad.

[0039] As a possible implementation, in the direction that the sidewall of the first opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad, and the deepened first opening exposes the upper surface adjacent to the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad, or the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad and its adjacent upper surface;

[0040] And / or, in the direction that the sidewall of the first opening extends laterally beyond the first connection pad, at least one sidewall of the second connection pad is flush with the sidewall of the first connection pad, so that the deepened first opening exposes the sidewall of the second connection pad that is flush with the first connection pad.

[0041] As a possible implementation, the second connection pad is longitudinally and directly opposite to the first connection pad. Then, using the first connection pad as a barrier layer, etching the first wafer from top to bottom to form a vertical through hole includes:

[0042] Etching from the upper surface of the first wafer to obtain a fourth opening; at least one sidewall of the fourth opening extends laterally beyond the sidewall of the first connection pad;

[0043] Using the first connection pad as a barrier layer, etching is performed above the first connection pad and at the bottom of the fourth opening to expose the upper surface of the first connection pad. The deepened fourth opening exposes the upper surface and / or sidewall of the second connection pad.

[0044] As a possible implementation, in the direction where the sidewall of the fourth opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad extends laterally beyond the sidewall of the first connection pad. The deepened fourth opening exposes the upper surface adjacent to the sidewall of the second connection pad that extends laterally beyond the sidewall of the first connection pad, or the sidewall and its adjacent upper surface of the second connection pad that extend laterally beyond the sidewall of the first connection pad.

[0045] And / or, in the direction where the sidewall of the fourth opening extends laterally beyond the sidewall of the first connection pad, at least one sidewall of the second connection pad is flush with the sidewall of the first connection pad. Then the deepened fourth opening exposes the sidewall of the second connection pad that is flush with the first connection pad.

[0046] As a possible implementation, filling the vertical through hole with a conductive material to form a contact plug includes:

[0047] Forming a conductive material in the vertical through hole and on the upper surface of the first wafer by using an electroplating or deposition process;

[0048] Removing the conductive material on the upper surface of the first wafer by using a planarization process to form the contact plug in the vertical through hole.

[0049] Compared with the prior art, the present application has the following beneficial effects:

[0050] Based on the above technical solutions, the present application provides a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first wafer, a second wafer, and a contact plug. The first wafer may include a first dielectric layer, and a first connection pad is disposed in the first dielectric layer. The second wafer is bonded to the first wafer. The second wafer includes a second dielectric layer, and a second connection pad is disposed in the second dielectric layer. The contact plug is a conductive material filled in a vertical through hole for electrically connecting the first connection pad and the second connection pad. The vertical through hole is a through hole formed by etching that penetrates the first wafer and partially penetrates the second wafer to the upper surface and / or side wall of the second connection pad. The first connection pad is located in the vertical through hole, and the first dielectric layer below the first connection pad is not etched. That is to say, the vertical through hole may expose the upper surface of the first wafer, as well as the upper surface and / or side wall of the second connection pad. In this way, the contact plug in the vertical through hole can be in contact with both the first connection pad and the second connection pad simultaneously, thereby realizing the electrical connection between the first connection pad and the second connection pad. The contact plug serves as a signal transmission path between the first connection pad and the second connection pad, and its path is short, reducing signal delay. At the same time, the vertical through hole is formed by an etching process, penetrating from the side wall of the first connection pad to the second connection pad, and the contact plug therein can contact the second connection pad from the periphery of the first connection pad, thereby realizing a reliable connection between the contact plug and the second connection pad by a simple process. In addition, there is only one metal plug in the embodiments of the present application, and there is no need to consider the distance between two metal plugs. Therefore, the lateral dimension can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] To clearly understand the specific embodiments of the present application, the drawings used in the specific embodiments of the present application will be briefly described below. Obviously, these drawings are only partial embodiments of the present application.

[0052] Figure 1 FIG. 9 is a schematic diagram of a bonding structure in the prior art;

[0053] Figure 2 FIG. 13 is a top view of a three-dimensional interconnection structure in the prior art;

[0054] Figure 3 FIG. 17 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application;

[0055] Figure 4 FIG. 21 is a schematic diagram of a shape of a first connection pad and a second connection pad in an embodiment of the present application;

[0056] Figure 5 FIG. 25 is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application;

[0057] Figure 6 FIG. 29 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present application;

[0058] Figure 7 Schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0059] Figure 8 Schematic diagram of a three-dimensional interconnect structure provided by an embodiment of the present application;

[0060] Figure 9 Top view of the three-dimensional interconnect structure provided by an embodiment of the present application;

[0061] Figure 10 Schematic diagram of yet another semiconductor device provided by an embodiment of the present application;

[0062] Figure 11 Another shape schematic diagram of the first connection pad and the second connection pad in an embodiment of the present application;

[0063] Figure 12 Schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0064] Figure 13 Schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0065] Figure 14 Schematic diagram of still another semiconductor device provided by an embodiment of the present application;

[0066] Figure 15 Flow chart of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0067] Figures 16 - 20 Schematic diagram of a semiconductor device during the manufacturing process of the semiconductor device in an embodiment of the present application. Detailed implementation manners

[0068] To make the above objects, features, and advantages of the present application more obvious and understandable, the following detailed description of the specific implementation manners of the present application will be made with reference to the accompanying drawings.

[0069] In the following description, many specific details are set forth to facilitate a thorough understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0070] Second, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present application herein. In addition, in actual manufacturing, three-dimensional spatial dimensions including length, width, and depth should be included.

[0071] In view of this, the present application provides a semiconductor device and a manufacturing method thereof to reduce signal delay and the occupied area and improve the integration density of the device.

[0072] As described in the background art, the three-dimensional stacking technology can bond different wafers together, reduce the planar space of three-dimensional devices, and improve the integration density.

[0073] For example, referring to Figure 1 As shown, it is a schematic diagram of a bonding structure in the prior art. In the first wafer 100, a first device 130 can be formed. The first device 130 can be, for example, a CIS. In the second wafer 200, a second device 230 can be formed. The second device 230 can be, for example, an image system processor (ISP). Then, the first wafer 100 and the second wafer 200 are bonded together to form an image sensor system. The first device is formed in the dielectric layer 120 on the substrate 110, and the second device is formed in the dielectric layer 220 on the substrate 210. A bonding surface 1001 is formed between the bonded first wafer 100 and second wafer 200.

[0074] Specifically, the first wafer 100 and the second wafer 200 can be bonded by the dielectric layer, and the through-silicon via technology is used to etch from the substrate 110 of the first wafer 100 to form through-silicon vias penetrating to the CIS and through-silicon vias penetrating to the ISP. After forming a metal material in the two through-silicon vias, two metal plugs 140 and 240 respectively connected to the CIS and the ISP are obtained. The metal plugs 140 and 240 can realize the transmission of signals in the vertical direction in the bonding structure. Then, a horizontal redistribution layer (RDL) 150 is formed on the back surface of the substrate 110 of the first wafer 100 to realize the electrical connection of the two metal plugs 140 and 240. In this way, the CIS and the ISP are electrically connected through the two metal plugs 140 and 240 and the redistribution layer 150, that is, three-dimensional interconnection is realized between wafers of different layers.

[0075] However, in the connection method using dielectric layer bonding and through-silicon via technology, the signal of the ISP in the second wafer 200 needs to be transmitted upward through the metal plug 240 connected to the ISP first, and then transmitted through the horizontal redistribution layer 150 to the metal plug 140 connected to the ISP and then transmitted downward to reach the CIS in the first wafer 100. Referring toFigure 1 The dotted line in the figure indicates the direction. That is to say, the signal needs to pass through a relatively long π-shaped path, and the delay time is related to the resistance and capacitance in the path, resulting in a relatively long delay time for signal transmission, which cannot meet the actual needs in some scenarios. At the same time, two metal plugs are required to achieve the connection between the CIS and the ISP. Refer to Figure 2 As shown in the figure, it is a top view of a three-dimensional interconnection structure in the prior art. Among them, there are certain limitations on the minimum dimensions of the two metal plugs 140 and 240, and there are also certain limitations on the minimum distance between the two metal plugs 140 and 240 during the formation process. This determines that the setting of the two metal plugs 140 and 240 requires a relatively large planar space. Correspondingly, the wiring layers of the first device 130 and the second device 140 in contact with the two metal plugs 140 and 240 cannot be too close. Therefore, this connection method is not conducive to the integration density of the device.

[0076] Based on the above technical problems, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device may include a first wafer, a second wafer, and a contact plug. The first wafer may include a first dielectric layer, and a first connection pad is provided in the first dielectric layer. The second wafer is bonded to the first wafer. The second wafer includes a second dielectric layer, and a second connection pad is provided in the second dielectric layer. The contact plug is a conductive material filled in a vertical through hole for electrically connecting the first connection pad and the second connection pad. The vertical through hole is a through hole formed by etching that penetrates the first wafer and partially penetrates the second wafer to the upper surface and / or side wall of the second connection pad. The first connection pad is located in the vertical through hole, and the first dielectric layer below the first connection pad is not etched. That is to say, the vertical through hole can expose the upper surface of the first wafer, as well as the upper surface and / or side wall of the second connection pad. In this way, the contact plug in the vertical through hole can contact the first connection pad and the second connection pad at the same time, thereby realizing the electrical connection between the first connection pad and the second connection pad. The contact plug serves as a signal transmission channel between the first connection pad and the second connection pad, and its path is short, reducing the signal delay. At the same time, the vertical through hole is formed by an etching process, penetrating from the side wall of the first connection pad to the second connection pad, and the contact plug therein can contact the second connection pad from the periphery of the first connection pad, thereby realizing a reliable connection between the contact plug and the second connection pad by a simple process. In addition, there is only one metal plug in the embodiments of the present application, and there is no need to consider the distance between the two metal plugs. Therefore, the lateral dimension can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.

[0077] In order to more clearly understand the specific implementation manners of the present application, the semiconductor device provided by the present application will be described in detail below with reference to the accompanying drawings.

[0078] Refer to Figure 3As shown, it is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application. Among them, the semiconductor device may include a first wafer 300, a second wafer 400, and a contact plug 360 for realizing vertical interconnection between the first wafer 300 and the second wafer 400. The first wafer 300 may include a first substrate 310, a first dielectric layer 320 on the first substrate 3l0, and a first pad 330 in the first dielectric layer 320. The second wafer 400 may include a second substrate 410, a second dielectric layer 420 on the second substrate 410, and a second pad 430 in the second dielectric layer 420.

[0079] Among them, the first substrate 310 and the second substrate 410 may be semiconductor substrates, such as Si substrates, Ge substrates, SiGe substrates, SOI (Silicon On Insulator), or GOI (Germanium On Insulator), etc. In other embodiments, the first substrate 310 and the second substrate 410 may also be substrates including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC, etc., may also be a stacked structure, such as Si / SiGe, etc., may also be other epitaxial structures, such as SGOI (Silicon Germanium On Insulator), etc. The first substrate 310 and the second substrate 410 may be the same material or different materials. In this embodiment, the first substrate 310 and the second substrate 410 may both be silicon substrates.

[0080] All processes before bonding may have been completed on the first substrate 310 and the second substrate 410. For example, device structures and interconnection structures for electrically connecting the device structures have been formed on the first substrate 310 and the second substrate 410. The device structures are covered by an interlayer dielectric layer, which may be silicon oxide. The interconnection structures are formed in a dielectric material. The device structures may be MOS devices, memory devices, and / or other passive devices. The interconnection structures may be multi-layer structures. The interconnection structures may include contact plugs, vias, or connection layers. The connection layer may be located at the top layer of the interconnection structure and serve as the lead-out structure of the interconnection structure. The connection layer may include multiple pads. The interconnection structures may be made of metal materials, such as tungsten, aluminum, copper, etc. In the illustration of the embodiment of the present application, only the top connection layer is shown. This is only for simplifying the drawings. It can be understood that this is only an example. In different designs and applications, the required number of layers of interconnection structures may be formed according to needs.

[0081] The same device structure or different device structures may be formed on the first substrate 310 and the second substrate 410. For example, the devices on the first substrate 310 and the second substrate 410 may both be DRAM devices, or both be logic devices, or may be two types of devices among DRAM and logic devices respectively, or may be two types of devices among SRAM and logic devices respectively, or may be two types of devices among CIS and ISP, etc.

[0082] The same interconnect structure or different interconnect structures may be formed on the first substrate 310 and the second substrate 410. The pads in the interconnect structures on the first substrate 310 and the second substrate 410 may have the same structure or different structures. For the convenience of distinction, in the embodiments of the present application, the first pad 330 in the interconnect structure on the first substrate 310 and the second pad 430 in the interconnect structure on the second substrate 410 are taken as examples to illustrate the interconnect structures between different wafers.

[0083] The first pad 330 is the pad in the interconnect structure of the first wafer 300 before bonding, and may be the top metal layer in the first wafer 300. The material of the first pad 330 may be copper. The first pad 330 may be covered by the first dielectric layer 320 to achieve isolation between different first pads 330. The first dielectric layer 320 may be a silicon oxide layer or a stacked structure, for example, may include a silicon nitride layer and the silicon oxide layer thereon.

[0084] Similarly, the second pad 430 is the pad in the interconnect structure of the second wafer 400 before bonding, and may be the top metal layer in the second wafer 400. The material of the second pad 430 may be copper. The second pad 430 may be covered by the second dielectric layer 420 to achieve isolation between different second pads 430. The second dielectric layer 420 may be silicon oxide or a stacked structure, for example, may include a silicon nitride layer and the silicon oxide layer thereon.

[0085] For the convenience of description, the surface on which the device structure is formed on the first substrate 310 is taken as the front surface of the first wafer 300, and the surface opposite to the surface of the first substrate 310 on which the device is formed is the back surface of the first wafer 300. The surface on which the device structure is formed on the second substrate 410 is taken as the front surface of the second wafer 400, and the surface opposite to the surface of the second substrate 410 on which the device is formed is the back surface of the second wafer 400.

[0086] In the embodiments of the present application, the first wafer 300 and the second wafer 400 can be bonded together. In fact, the first wafer 300 and the second wafer 400 can be two wafers among multiple bonded wafers. The front side of the first wafer 300 can be bonded to the front side of the second wafer 400 in a face-to-face manner. The front side of the first wafer 300 can also be bonded to the back side of the second wafer 400 in a face-to-back manner. The back side of the first wafer 300 can also be bonded to the front side of the second wafer 400 in a back-to-face manner. The back side of the first wafer 300 can also be bonded to the back side of the second wafer 400 in a back-to-back manner. The surfaces of the first wafer 300 and the second wafer 400 for bonding are bonding surfaces, and a material layer for bonding can be formed on the bonding surfaces. The bonding material layer can be an adhesive layer of a dielectric material, such as silicon oxide and silicon nitride. The bonding of the two wafers is achieved through the molecular force between the adhesive layers.

[0087] It should be noted that in the embodiments of the present application, "up" and "down" are relative and related to the bonding method of the first wafer 300 and the second wafer. Specifically, the first wafer 300 can be used as the upper wafer, and the second wafer 400 can be used as the lower wafer. When the front side of the first wafer 300 is used as the bonding surface, the first wafer 300 is flipped, so the original "up" becomes "down". When the back side of the first wafer 300 is used as the bonding surface, the first wafer 300 is not flipped, so the original "up" remains "up". Similarly, when the front side of the second wafer 400 is used as the bonding surface, the second wafer 400 is not flipped, so the original "up" remains "up". When the back side of the second wafer 400 is used as the bonding surface, the second wafer is flipped, so the original "up" becomes "down". In addition, descriptions such as up, down, left, right, front, back, top, and bottom are only for conveniently reflecting the relative positions and / or directions between various components, and do not imply any specific fixed direction.

[0088] After the first wafer 300 and the second wafer 400 are bonded, since the two are bonded through a dielectric layer, the first connection pad 330 in the first wafer 300 and the second connection pad 430 in the second wafer 400 are not yet electrically connected. Therefore, a vertical through hole 359 is required to connect the first wafer 300 and the second wafer 400. In the embodiments of the present application, the first wafer 300 can be used as the upper wafer in the bonding structure, and thus etching can be performed from the upper surface of the first wafer 300 to form the vertical through hole 359. It can be understood that when the back side of the first wafer 300 is used as the bonding surface 1001, etching can be performed from the front side of the first wafer 300. When the front side of the first wafer 300 is used as the bonding surface 1001, etching can be performed from the back side of the first wafer 300.

[0089] Currently, the TSV technology can be used to etch from the upper surface of the first wafer to form two through-silicon vias that penetrate to the first connection pad and the second connection pad respectively. Then, a metal material is filled in the through-silicon vias as contact plugs. After that, wiring is performed on the upper surface of the first wafer to establish a connection between the two contact plugs. However, in this connection method, the channel between the first connection pad and the second connection pad is relatively long, and the size of each contact plug is limited by the etching process and cannot be infinitely reduced. The distance between the contact plugs is also limited. Therefore, the planar area occupied by the two three-dimensional interconnect structures in this process is relatively large. At the same time, since the contact plug is in contact with the first connection pad or the second connection pad, the sizes of the first connection pad and the second connection pad are also limited by the etching process and match the size of the contact plug. Therefore, the sizes of the first connection pad and the second connection pad are relatively large. At the same time, the distance between the first connection pad and the second connection pad corresponds to the lateral distance of the contact plug, and its minimum distance is limited. Therefore, the wiring design is also limited.

[0090] To solve the above problems, in the embodiments of the present application, etching can start from the upper surface of the first wafer 300, using the first connection pad 330 as a barrier layer to form a vertical via 359. In this vertical via 359, the upper surface of the first connection pad 330, as well as the upper surface and / or sidewall of the second connection pad 430, are exposed. The first connection pad 330 can protect the first dielectric layer and the second dielectric layer below it from being etched. In this way, after filling the vertical via 359 with metal, the formed contact plug 360 is in contact with the upper surface of the first connection pad 330 and at the same time in contact with the upper surface and / or sidewall of the second connection pad 430, that is, the formed contact plug 360 is in contact with both the first connection pad 330 and the second connection pad 430, constituting the connection between the first connection pad 330 and the second connection pad 430. The contact plug 360 can surround the first connection pad 330 on at least one side, and has low requirements for the planar size of the first connection pad 330. Therefore, the planar area of the device can be further reduced.

[0091] The vertical via 359 can be a via with uneven upper and lower dimensions. Specifically, it can penetrate the first wafer to the upper surface of the first connection pad 330, thereby exposing the upper surface of the first connection pad 330. The vertical via 359 can also penetrate the first wafer and the second wafer along the sidewall of the first connection pad 330 to the second connection pad 430, thereby exposing the upper surface and / or sidewall of the second connection pad 430. That is to say, the via above the first connection pad 330 can have a relatively large via size, while the via between the first connection pad 330 and the second connection pad 430 can have a relatively small via size.

[0092] Specifically, the vertical through-hole 359 may expose the entire upper surface of the first connection pad 330, or may expose a partial upper surface of the first connection pad 330; the vertical through-hole 359 may expose one or more side walls of the first connection pad 330, or may not expose the side walls of the first connection pad 330. At this time, the side walls of the first connection pad 330 are covered by a partial first dielectric layer, thereby providing a protective effect on the first connection pad 330; the vertical through-hole 359 may expose the entire upper surface of the second connection pad 430, or may expose a partial upper surface of the second connection pad 430; the vertical through-hole 359 may expose one or more side walls of the second connection pad 430, or may not expose the side walls of the second connection pad 430. At this time, the side walls of the second connection pad 430 are covered by a second dielectric layer.

[0093] Reference Figure 4 As shown, it is a schematic diagram of a shape of the first connection pad and the second connection pad in an embodiment of the present application. The first connection pad 330 may be polygonal or circular, and the second connection pad 430 may be polygonal or circular. The shapes of the first connection pad 330 and the second connection pad 430 may be the same or different. Of course, the lateral distance between the first connection pad 330 and the second connection pad 430 is relatively close, and there may be an overlapping projection in the longitudinal direction, or there may be no overlapping projection in the longitudinal direction. The polygon may be, for example, a strip, and the circle may be, for example, a regular circle or an ellipse. As an example, the first connection pad 330 is a strip, and the second connection pad 430 is also a strip. The sizes of the first connection pad 330 and the second connection pad 430 may be the same or different.

[0094] As a possible implementation manner, reference Figure 5 As shown, it is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. The second connection pad 430 and the first connection pad 330 may be disposed opposite to each other in the longitudinal direction. That is to say, the first connection pad 330 and the first connection pad 330 have an overlapping area in the direction perpendicular to the bonding surface 1001, and at least one side wall of the second connection pad 430 is flush with at least one side wall of the first connection pad 330. In this way, the side walls of the second connection pad 430 and the first connection pad 330 can be exposed in the vertical through-hole 359, and the exposed side walls of the second connection pad 430 and the first connection pad 330 are flush. In this way, the contact plugs 360 filled in the vertical through-hole 359 are respectively connected to the side wall of the second connection pad 430 and the side wall of the first connection pad 330, so that the first connection pad 330 and the second connection pad 430 can be electrically connected. Specifically, the second connection pad 430 and the first connection pad 330 may be aligned on one side, and one side wall of the first connection pad 330 extends beyond the side wall of the second connection pad 430 in the lateral direction. The contact plug 360 can contact the upper surface and one side wall of the first connection pad 330, and one side wall of the second connection pad 430. Reference Figure 5(a) As shown; the second connection pad 430 and the first connection pad 330 can be aligned on multiple sides, and the contact plug 360 can contact the upper surface and multiple side walls of the first connection pad 330, as well as the multiple side walls of the second connection pad 430. Refer to Figure 5 (b) As shown.

[0095] As another possible implementation, refer to Figure 6 As shown, it is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application. The second connection pad 430 and the first connection pad 330 can be arranged opposite to each other longitudinally, and at least one side wall of the second connection pad 430 extends beyond the side wall of the first connection pad 330 transversely. Then, at least a part of the surface of the second connection pad 430 that extends beyond the first connection pad 330 transversely is exposed in the formed vertical through hole 359, that is, it can expose the upper surface adjacent to the side wall of the second connection pad 430 that extends beyond the first connection pad 330 transversely, or it can also expose the side wall of the second connection pad 430 that extends beyond the first connection pad 330 transversely and its adjacent upper surface. In this way, the contact plug 360 filled in the vertical through hole 359 contacts at least the upper surface of the second connection pad 430. At the same time, the upper surface of the first connection pad 330 can also be exposed in the vertical through hole 359, so that the contact plug 360 can connect the first connection pad 330 and the second connection pad 430.

[0096] Specifically, one side wall of the second connection pad 430 can extend beyond the first connection pad 330 transversely. Refer to Figure 6 (b) As shown, one side wall of the second connection pad 430 can be aligned with the first connection pad 330, and the other side wall extends beyond the side wall of the first connection pad 330 transversely. The contact plug 360 can contact the upper surface and multiple side walls of the first connection pad 330, as well as one side wall and the other upper surface of the second connection pad 430. Refer to Figure 6 (a) As shown; refer to Figure 6 (b) As shown, one side wall of the second connection pad 430 can extend beyond the first connection pad 330 transversely, and the other side wall is recessed relative to the first connection pad 330. The contact plug 360 can contact the upper surface and one side wall of the first connection pad 330, as well as the upper surface of the second connection pad 430 on the side that extends beyond the first connection pad 330 transversely. Refer to Figure 6 (b) As shown.

[0097] Specifically, multiple side walls of the second connection pad 430 can extend beyond the first connection pad 330 transversely. Refer to Figure 7 As shown, it is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application. Among them, the contact plug 360 can contact the upper surface and one side wall of the first connection pad 330, as well as the upper surface of the second connection pad 430 on the side that extends beyond the first connection pad 330 transversely. Refer to Figure 7(as shown in (a)); the contact plug 360 can contact the upper surface and multiple side walls of the first connection pad 330, and the upper surface of the second connection pad 430, refer to Figure 7 (b) and Figure 3 (as shown); the contact plug 360 can contact the upper surface and multiple side walls of the first connection pad 330, and the upper surface and multiple side walls of the second connection pad 430, refer to Figure 7 (as shown in (c)).

[0098] Of course, in the above example, a part of the first dielectric layer may also be reserved between the contact plug 360 and the first connection pad 330, so as to protect the first connection pad 330 during the etching process.

[0099] In summary, in the embodiment of the present application, the contact plug 360 can connect the first connection pad 330 and the second connection pad 430 from multiple sides of the first connection pad 330, which can improve the contact area between the contact plug 360 and the second connection pad 430 to a certain extent and improve the contact reliability between the contact plug 360 and the second connection pad 430.

[0100] Refer to Figure 8 (as shown), which is a schematic structural diagram of the three-dimensional interconnection structure provided by the embodiment of the present application, refer to Figure 9 (as shown), which is a top view of the three-dimensional interconnection structure provided by the embodiment of the present application. The contact plug 360 forms an arch structure to realize the connection with the first connection pad 330 and the second connection pad 430. Among them, the contact plug 360 is formed on the left and right sides of the first connection pad 330, so the left-right width of the first connection pad 330 can be smaller. At the same time, there may be an overlapping area between the first connection pad 330 and the second connection pad 430, and there is no need to set a large spacing, so as to reduce the wiring area to a certain extent.

[0101] As another possible implementation manner, refer to Figure 10As shown in the figure, it is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application. The second connection pad 430 and the first connection pad 330 are arranged staggered in the longitudinal direction, that is, there is no overlapping area between the second connection pad 430 and the first connection pad 330 in the direction perpendicular to the bonding surface 1001. Therefore, the size of the top opening of the vertical through hole 359 is greater than or equal to the lateral distance between the second connection pad 430 and the first connection pad 330. Specifically, when the size of the top opening of the vertical through hole 359 is equal to the lateral distance between the second connection pad 430 and the first connection pad 330, the vertical through hole 359 can expose the opposite side walls of the first connection pad 330 and the second connection pad 430, that is, expose the side wall of the first connection pad 330 facing the second connection pad 430 and expose the side wall of the second connection pad 430 facing the first connection pad 330. Then, at different depths of the vertical through hole 359, its lateral size is uniform, so that the metal plug 360 in the vertical through hole 359 can connect the exposed side walls of the first connection pad 330 and the second connection pad 430 to realize the electrical connection between the two; when the size of the top opening of the vertical through hole 359 is greater than the lateral size of the second connection pad 430 and the first connection pad 330, in addition to exposing the opposite side walls of the first connection pad 330 and the second connection pad 430, the vertical through hole 359 can also expose a part of the upper surface of the first connection pad 330 and / or the second connection pad 430. Refer to Figure 10 (a) shown to improve the reliability of contact. In fact, on the basis that the vertical through hole 359 exposes the upper surface of the first connection pad 330, a part of the first dielectric layer can be reserved on the side wall of the first connection pad 330 to protect the first connection pad 330. Refer to Figure 10 (b) shown.

[0102] Refer to Figure 11 As shown in the figure, it is another schematic diagram of the shape of the first connection pad and the second connection pad in an embodiment of the present application. The shape of the first connection pad 330 can also be a slit type or a comb type. At this time, the shape of the second connection pad 430 can be a polygon, a circle, a slit type or a comb type; of course, when the shape of the first connection pad 330 is a polygon or a circle, the shape of the second connection pad 430 can be a slit type or a comb type. The slit type can be a single-slit type or a multi-slit type. Among them, the slit type can include the single-slit type. Refer to Figure 11 (a), and the multi-slit type. Refer to Figure 11 (b) and 11(c), and the comb type refers to Figure 11 (d). The number of teeth in the comb type can be determined according to the actual situation.

[0103] When the shapes of the first connection pad 330 and the second connection pad 430 are slit-shaped or comb-shaped, the slit-shaped or comb-shaped can be regarded as a combination of multiple lines, and the connection method of each line can refer to the connection method between the above lines, that is, the formed vertical through hole 359 can expose the side wall of the connection pad of the slit-shaped or comb-shaped, or can not expose its side wall, as long as it can expose the partial upper surfaces of the first connection pad 330 and the second connection pad 430 at the same time, so as to realize the contact between the contact plug 360 and the first connection pad 330 and the second connection pad 430 respectively.

[0104] Reference Figure 12 As shown, it is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application. Taking the second connection pad 430 as a single-slit type as an example, the contact plug 360 can be connected to the upper surface and side wall of the first connection pad 330, and the upper surface of the second connection pad 430, reference Figure 12 (a) shown; the contact plug 360 can be connected to the upper surface and side wall of the first connection pad 330, and the upper surface and side wall of the second connection pad 430, reference Figure 12 (b) shown. Taking the second connection pad 430 as a double-slit as an example, the contact plug 360 can be connected to the upper surface and side wall of the first connection pad 330, and the side wall of the second connection pad 430, reference Figure 12 (c) shown.

[0105] That is to say, the vertical through hole 359 can be a through hole that penetrates from the upper surface of the first wafer 300 to the upper surface of the first connection pad 330 and penetrates from the periphery of the first connection pad 330 to the upper surface of the second connection pad 430. The upper surface of the first connection pad 330, and the upper surface and / or side wall of the second connection pad 430 are exposed in the through hole, so as to form a vertical through hole 359 with a larger upper size and a smaller lower size.

[0106] In the embodiment of the present application, due to the influence of the etching process, the diameters of the vertical through holes 359 above and below an interface can be different, reference Figure 13 As shown, it is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application. Specifically, the diameters of the vertical through holes 359 in the first substrate 310 and the first dielectric layer 320 can be different, reference Figure 3 shown; the diameters of the vertical through holes 359 above and below the upper surface of the first connection pad 330 can be different, reference Figure 13 (a) and 13(c) shown; the diameters of the vertical through holes 359 above and below the lower surface of the first connection pad 330 can be different, reference Figure 13 (b) shown; the diameters of the vertical through holes 359 above and below the upper surface of the second connection pad 430 can be different, reference Figure 12 (b) shown.

[0107] It is understandable that the above drawings are only for illustrative purposes and do not cover all the situations provided by the embodiments of the present application. For the sake of brevity, no further examples will be given here. Those skilled in the art can set up other structures based on the above description, which should be within the protection scope of the present application.

[0108] In the semiconductor device provided by the embodiment of the present application, a third wafer may further be included. Refer to Figure 14 As shown, it is a schematic structural diagram of another semiconductor device provided by the embodiment of the present application. The first wafer 300, the second wafer 400, and the third wafer 500 form a three-layer stack. The third wafer 500 may include a third substrate 510. A third dielectric layer 520 may be formed on the third substrate 510. A third connection pad 530 may be provided in the third dielectric layer 520. The third wafer 500 may be disposed above the first wafer 300. The third connection pad 530 in the third wafer 500 and the contact plug 360 are electrically connected through the bonding of the first wafer 300 and the third wafer 500. The third connection pad 530 and the contact plug 360 may also be connected by forming other contact plugs (not shown in the figure) using a manufacturing process similar to that of the contact plug 360 after the dielectric layers of the first wafer 300 and the third wafer 500 are bonded. The bonding surface 5001 of the first wafer 300 and the third wafer 500 may be referred to Figure 14 as shown.

[0109] An embodiment of the present application provides a semiconductor device, including a first wafer, a second wafer, and a contact plug. The first wafer may include a first dielectric layer, and a first connection pad is disposed in the first dielectric layer. The second wafer is bonded to the first wafer. The second wafer includes a second dielectric layer, and a second connection pad is disposed in the second dielectric layer. The contact plug is a conductive material filled in a vertical through hole for electrically connecting the first connection pad and the second connection pad. The vertical through hole is a through hole formed by etching that penetrates the first wafer and partially penetrates the second wafer to the upper surface and / or sidewall of the second connection pad. The first connection pad is located in the vertical through hole, and the first dielectric layer located under the first connection pad is not etched. In this way, the contact plug in the vertical through hole can be in contact with the upper surface of the first connection pad and the upper surface and / or sidewall of the second connection pad to achieve electrical connection between the first connection pad and the second connection pad, thereby realizing vertical interconnection between the first wafer and the second wafer. The contact plug serves as a signal transmission channel between the first connection pad and the second connection pad, and its path is short, reducing signal delay. At the same time, the vertical through hole is formed by an etching process, penetrating from the sidewall of the first connection pad to the second connection pad, and the contact plug therein can contact the second connection pad from around the first connection pad, thereby realizing reliable connection between the contact plug and the second connection pad by a simple process. In addition, there is only one metal plug in the embodiment of the present application, and there is no need to consider the distance between two metal plugs. Therefore, the lateral dimension can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.

[0110] Based on the semiconductor device provided in the above embodiment, the embodiment of the present application further provides a manufacturing method of a semiconductor device. Refer to Figure 15 As shown, it is a flowchart of a manufacturing method of a semiconductor device provided by the embodiment of the present application. Figures 16 - 20 As shown, it is a schematic diagram of a semiconductor device during the manufacturing process of the semiconductor device in the embodiment of the present application. The method may include the following steps:

[0111] S101, provide the bonded first wafer 300 and second wafer 400. Refer to Figure 16 (a), 17(a) 18(a), 19(a) and 20(a).

[0112] In an embodiment of the present application, the first wafer 300 may include a first substrate 310, a first dielectric layer 320 on the first substrate 310, and a first pad 330 in the first dielectric layer 320. The second wafer 400 may include a second substrate 410, a second dielectric layer 420 on the second substrate 410, and a second pad 430 in the second dielectric layer 420. The same device structure or different device structures may be formed on the first substrate 310 and the second substrate 410. For example, the devices on the first substrate 310 and the second substrate 410 may both be DRAM devices, or both be logic devices, or may be two types of devices among DRAM and logic devices respectively, or may be two types of devices among SRAM and logic devices respectively, or may be two types of devices among CIS and ISP respectively, etc.

[0113] The first pad 330 is a pad in the interconnection structure of the first wafer 300 before bonding, and may be the top metal layer in the first wafer 300. The material of the first pad 330 may be copper. The first pad 330 may be covered by the first dielectric layer 320 to achieve isolation between different first pads 330. The first dielectric layer 320 may be a silicon oxide layer or a stacked structure, for example, may include a silicon nitride layer and a silicon oxide layer thereon.

[0114] Similarly, the second pad 430 is a pad in the interconnection structure of the second wafer 400 before bonding, and may be the top metal layer in the second wafer 400. The material of the second pad 430 may be copper. The second pad 430 may be covered by the second dielectric layer 420 to achieve isolation between different second pads 430. The second dielectric layer 420 may be silicon oxide or a stacked structure, for example, may include a silicon nitride layer and a silicon oxide layer thereon.

[0115] For ease of description, the surface of the first substrate 310 on which the device structure is formed is taken as the front side of the first wafer 300, and the surface opposite to the surface of the first substrate 310 on which the device is formed is the back side of the first wafer 300. The surface of the second substrate 410 on which the device structure is formed is taken as the front side of the second wafer 400, and the surface opposite to the surface of the second substrate 410 on which the device is formed is the back side of the second wafer 400.

[0116] In the embodiments of the present application, the first wafer 300 and the second wafer 400 can be bonded together. In fact, the first wafer 300 and the second wafer 400 can be two wafers among multiple bonded wafers. The front surface of the first wafer 300 can be bonded opposite to the front surface of the second wafer 400, the front surface of the first wafer 300 can also be bonded opposite to the back surface of the second wafer 400, the back surface of the first wafer 300 can also be bonded opposite to the front surface of the second wafer 400, and the back surface of the first wafer 300 can also be bonded opposite to the back surface of the second wafer 400. The surfaces of the first wafer 300 and the second wafer 400 for bonding can be formed with a bonding material layer, and the bonding material layer can be an adhesive layer of a dielectric material, such as silicon oxide and silicon nitride. The bonding of the two wafers is achieved through the molecular force between the adhesive layers.

[0117] After the first wafer 300 and the second wafer 400 are bonded, since the two are bonded through a dielectric layer, the first connection pad 330 in the first wafer 300 and the second connection pad 430 in the second wafer 400 have not yet achieved vertical interconnection. Therefore, it is necessary to connect the two.

[0118] S102: Using the first connection pad 330 as a barrier layer, etch the first wafer 300 from top to bottom to form a vertical through-hole 359. The vertical through-hole 359 penetrates the upper surface of the first connection pad 330 of the first wafer, and penetrates the first wafer and the second wafer along the side wall of the first connection pad 330 to the second connection pad 430, and exposes the upper surface and / or side wall of the second connection pad 430.

[0119] In the embodiments of the present application, the first wafer 300 can be used as the upper wafer in the bonding structure, so as to etch from the upper surface of the first wafer 300 to form a vertical through-hole 359. It can be understood that when the back surface of the first wafer 300 is the bonding surface 1001, etching can be performed from the front surface of the first wafer 300, and when the front surface of the first wafer 300 is the bonding surface 1001, etching can be performed from the back surface of the first wafer 300.

[0120] Specifically, the vertical through-hole 359 can expose the entire upper surface of the first connection pad 330, or can expose a part of the upper surface of the first connection pad 330; the vertical through-hole 359 can expose one side or multiple side walls of the first connection pad 330, or can not expose the side wall of the first connection pad 330. At this time, the side wall of the first connection pad 330 is covered by a part of the first dielectric layer, so as to protect the first connection pad 330; the vertical through-hole 359 can expose the entire upper surface of the second connection pad 430, or can expose a part of the upper surface of the second connection pad 430; the vertical through-hole 359 can expose one side or multiple side walls of the second connection pad 430, or can not expose the side wall of the second connection pad 430. At this time, the side wall of the second connection pad 430 is covered by the second dielectric layer.

[0121] Taking the bonding of the front side of the first wafer 300 and the second wafer 400 as an example for illustration, there are various ways to etch and form the vertical through-hole 359. Different vertical through-hole 359 structures and different connection pads can have different etching methods. The following is an exemplary description.

[0122] As a possible implementation manner, the second connection pad 430 is longitudinally disposed opposite to the first connection pad 330, the second connection pad 430 is located below the first connection pad 330, and the side wall of the second connection pad 430 can be flush with the side wall of the first connection pad 330, or the side wall can extend beyond the side wall of the first connection pad 330 in the transverse direction. The method of forming the vertical through-hole 359 can be specifically as follows: First, etch the upper surface of the first wafer to form a first opening. The first opening is located above the first connection pad 330, and at least one side wall of the first opening can extend beyond the side wall of the first connection pad 330 in the transverse direction. In this way, deepening the first opening can expose the first connection pad 330. Etching the position at the bottom of the first opening where the side wall extends beyond the side wall of the first connection pad 330 in the transverse direction can form a second opening penetrating through to the second connection pad 430 around the first connection pad 330, thereby forming the vertical through-hole 359. When etching and forming the opening penetrating through to the second connection pad 430, the first connection pad 330 can protect the first dielectric layer and the second dielectric layer thereunder. Generally speaking, the position of the second opening can be determined according to the position of the second connection pad 430 relative to the first connection pad 330. The direction in which the side wall of the second connection pad 430 extends beyond the side wall of the first connection pad 330 in the transverse direction can be the same as the direction in which the side wall of the second opening extends beyond the side wall of the first connection pad 330 in the transverse direction.

[0123] Refer to Figure 16 As shown, the side walls of the second connection pad 430 extend beyond the side walls of the first connection pad 330 on multiple sides. First, etching can be performed from the back side of the first wafer 300, that is, etching from the back side of the first substrate 310 to form a first opening 350. Refer to Figure 16 (b) As shown, the first opening 350 can be above the first connection pad 330, and the side walls of the first opening 350 extend beyond the side walls of the first connection pad 330 on multiple sides. The etching of the first opening 350 can stop at the lower surface position of the first substrate 310, or can over-etch a part of the first dielectric layer 320 (not shown in the figure) and stop in the first dielectric layer 320; deposit an insulating layer 361 to protect the side walls of the first opening 350; etch at the bottom of the side walls of the first opening 350 where the side walls extend beyond the first connection pad 330 in the transverse direction (this etching can expose the side walls of the first connection pad 330, or can retain a part of the first dielectric layer 320 without exposing the side walls of the first connection pad 330) to form a second opening 351 penetrating through to the bonding surface 1001. Refer to Figure 16(c); then, using the first connection pad 330 as a stop layer, the first opening 350 and the second opening 351 are deepened together, thereby removing the first dielectric layer 320 above the first connection pad 330 and the second dielectric layer 420 above the second connection pad 430, so as to form a vertical through-hole 359. Refer to Figure 16 (d). The formed vertical through-hole 359 exposes the upper surface of the first connection pad 330 and the upper surfaces of multiple sides of the second connection pad 430 that laterally extend beyond the first connection pad 330. Among them, retaining a part of the first dielectric layer 320 on the sidewall of the first connection pad 330 is beneficial to protecting the first connection pad 330 and avoiding damage or collapse caused by etching of the first connection pad 330.

[0124] In addition, when the size of the second connection pad 430 that laterally extends beyond the first connection pad 330 is small, the second dielectric layer on the sidewall of the second connection pad 430 can be etched away together to expose the sidewall of the second connection pad 430. Refer to Figure 17 As shown, etching is performed from the back surface of the first wafer 300, that is, from the back surface of the first substrate 310, to form the first opening 350. Refer to Figure 17 (b). Of course, the etching of the first opening 350 can be stopped at the lower surface position of the first substrate 310, or can be over-etched through a part of the first dielectric layer 320 (not shown in the figure) and stopped in the first dielectric layer 320; an insulating layer 361 is deposited to protect the sidewall of the first opening 350. Refer to Figure 17 (c). Etching is performed at the bottom of the position where the sidewall of the first opening 350 laterally extends beyond the first connection pad 330 to form a second opening 351 that penetrates to the bonding surface 1001. Refer to Figure 17 (c); then, using the first connection pad 330 as a stop layer, the first opening 350 and the second opening 351 are deepened together, and the deepened second opening 351 stops at the lower surface of the second connection pad 430. During the etching process, the first connection pad 330 can protect the first dielectric layer and the second dielectric layer below it, so as to form a vertical through-hole 359. The vertical through-hole 359 exposes the upper surface of the first connection pad 330, as well as the upper surfaces of multiple sides of the second connection pad 430 that laterally extend beyond the first connection pad 330 and its sidewall.

[0125] In addition, in the direction where the second connection pad 430 is flush with the first connection pad 330, the dielectric layers on the sidewalls of the first connection pad 330 and the second connection pad 430 can be etched away to expose the sidewalls of the first connection pad 330 and the second connection pad 430. For the specific operation steps, reference can be made to Figure 16 the steps shown, which will not be elaborated here.

[0126] As another possible implementation, the second connection pad 430 is longitudinally disposed opposite to the first connection pad 330, the second connection pad 430 is located below the first connection pad 330, and the side wall of the second connection pad 430 may be flush with the side wall of the first connection pad 330, or the side wall may extend beyond the side wall of the first connection pad 330 in the transverse direction. Before wafer bonding, a third opening may be formed in the first wafer, and the third opening is formed in the first dielectric layer around the first connection pad 330, which can reduce the etching load after bonding. The specific method of forming the vertical through hole may be: after wafer bonding, the upper surface of the first wafer is etched to form a first opening, the first opening is located above the first connection pad 330, and the side wall of the first opening may extend beyond the side wall of the first connection pad 330 in at least one side in the transverse direction. In this way, deepening the first opening can expose the first connection pad 330, and at the same time, the first opening and the third opening can be connected, and the third opening can be deepened. The deepened third opening can expose the second connection pad 430 to form a vertical through hole 359. When etching to form an opening penetrating to the second connection pad 430, the first connection pad 330 can protect the first dielectric layer and the second dielectric layer thereunder. Generally speaking, the position of the third opening can be determined according to the position of the second connection pad 430 relative to the first connection pad 330, and the direction in which the side wall of the second connection pad 430 extends beyond the side wall of the first connection pad 330 in the transverse direction can be consistent with the setting direction of the third opening in the first dielectric layer.

[0127] Refer to Figure 18 As shown, the side walls of the second connection pad 430 extend beyond the side walls of the first connection pad 330 on multiple sides. A third opening 352 may be formed in the first wafer 300, and the third opening 352 is formed in the first dielectric layer 320 around the first connection pad 330. That is, before bonding the first wafer 300 and the second wafer 400, the first dielectric layer 320 can be etched to form a third opening 352 around the first connection pad 330. Refer to Figure 18 (a). In this way, after wafer bonding, etching can be performed from the back surface of the first wafer 300, that is, from the back surface of the first substrate 310, to form a first opening 350. Refer to Figure 18 (b). The first opening 350 may be above the first connection pad 330, and the side walls of the first opening 350 extend beyond the side walls of the first connection pad 330 on multiple sides. Of course, the etching of the first opening 350 can stop at the lower surface position of the first substrate 310, or can over-etch a part of the first dielectric layer 320 (not shown in the figure) and stop in the first dielectric layer 320; deposit an insulating layer 361 to protect the side walls of the first opening 350. Refer to Figure 18(as shown in (c)); using the first connection pad 330 as a barrier layer, deepen the first opening 350 to connect the first opening 350 and the third opening 352, and then continue etching to deepen the third opening 352, so that the deepened first opening 350 exposes the upper surface of the first connection pad 330, and the deepened third opening 352 exposes the upper surface of the second connection pad 430, thereby forming a vertical through hole 359. Refer to Figure 18 (as shown in (d)).

[0128] In addition, when the size of the second connection pad 430 laterally exceeding the first connection pad 330 is small, the second dielectric layer on the side wall of the second connection pad 430 can be etched away together to expose the side wall of the second connection pad 430, and no example is given here. In the direction where the second connection pad 430 is flush with the first connection pad 330, the dielectric layers on the side walls of the first connection pad 330 and the second connection pad 430 can be etched away to expose the side walls of the first connection pad 330 and the second connection pad 430. For the specific operation steps, reference can be made to Figure 18 the steps shown, which will not be elaborated here.

[0129] As another possible implementation manner, the second connection pad 430 is longitudinally and directly opposite to the first connection pad 330, the second connection pad 430 is located below the first connection pad 330, and the side wall of the second connection pad 430 can be flush with the side wall of the first connection pad 330, or the side wall can laterally exceed the side wall of the first connection pad 330. The method of forming the vertical through hole 359 can be specifically as follows: First, etch the upper surface of the first wafer to form a first opening. The first opening is located above the first connection pad 330, and the side wall of the first opening can laterally exceed the side wall of the first connection pad 330 on at least one side. In this way, deepening the first opening can expose the first connection pad 330. Continue to deepen the first opening. At this time, the first connection pad 330 can protect the first dielectric layer and the second dielectric layer below it, and etch the first dielectric layer and the second dielectric layer at the position where the first opening laterally exceeds the first connection pad 330, so that around the first connection pad 330, the deepened first opening penetrates through to the second connection pad 430, thereby forming a vertical through hole 359.

[0130] Refer to Figure 19 As shown, the side walls of the second connection pad 430 laterally exceed the side walls of the first connection pad 330 on multiple sides. Etch from the back surface of the first wafer, that is, etch from the back surface of the first substrate 310, to form a first opening 350. Refer to Figure 19As shown in (b), the first opening 350 may be above the first connection pad 330, and the sidewall of the first opening 350 laterally extends beyond the sidewall of the first connection pad 330 on multiple sides. Of course, the etching of the first opening 350 may stop at the lower surface position of the first substrate 310, or may over-etch a portion of the first dielectric layer 320 (not shown in the figure) and stop in the first dielectric layer 320; deposit an insulating layer 361 to protect the sidewall of the first opening 350, refer to Figure 19 As shown in (c); deepen the first opening 350, using the second connection pad 430 as an etch stop layer. During the etching process, the first connection pad 330 protects the first dielectric layer and the second dielectric layer thereunder until the upper surface of the second connection pad 430 is exposed. At this time, the upper surface of the first connection pad 330 is also exposed in the deepened first opening 350, forming a vertical through hole 359, refer to Figure 19 As shown in (d).

[0131] As still another possible implementation manner, the second connection pad 430 is longitudinally and directly opposite to the first connection pad 330, the second connection pad 430 is located below the first connection pad 330, and the sidewall of the second connection pad 430 may have a sidewall flush with the sidewall of the first connection pad 330, or may have a sidewall that laterally extends beyond the sidewall of the first connection pad 330. The specific manner of forming the vertical through hole 359 may be: etching is performed from the upper surface of the first wafer to form a fourth opening, and the sidewall of the fourth opening laterally extends beyond the sidewall of the first connection pad 330 on at least one side. Then, using the first connection pad 330 as a barrier layer, etching is performed above the first connection pad 330 and at the bottom of the fourth opening to expose the upper surface of the first connection pad 330, and at the same time, the deepened fourth opening exposes the upper surface and / or sidewall of the second connection pad 430. During the etching process, the first connection pad 330 may protect the first dielectric layer and the second dielectric layer thereunder.

[0132] Refer to Figure 20 As shown, the sidewall of the second connection pad 430 laterally extends beyond the sidewall of the first connection pad 330 on multiple sides. Etching is performed from the back surface of the first wafer 300, that is, from the back surface of the first substrate 310. The etching position is around the first connection pad 330 until etching reaches the lower surface position or the upper surface position of the first connection pad 330, obtaining a fourth opening 353, refer to Figure 20 As shown in (b); then deposit an insulating layer 361 to protect the sidewall of the fourth opening 353, refer to Figure 20 Etch the first dielectric layer 320 above the first connection pad 330, and the first dielectric layer 320 and the second dielectric layer 420 at the bottom of the fourth opening 353 around the first connection pad 330 to expose the upper surface and sidewall of the first connection pad 330, and the upper surface of the second connection pad 430, thereby forming a vertical through hole 359, refer to Figure 20(as shown in (d)).

[0133] In the above method of forming the vertical through-hole 359, when etching the vertical through-hole 359, the first connection pad 330 of the upper wafer is used as a barrier layer until the second connection layer 430 of the lower wafer is exposed. Generally speaking, the first connection pad 330 is made of a conductive material, which can be set as a material having a high etching selectivity ratio with the first dielectric layer and the second dielectric layer, such as a metal material or a doped semiconductor material. Among them, the etching selectivity ratio between the metal and the dielectric layer is large. For example, SiO2:Al approaches 20:1, and SiO2:W approaches 80:1. Therefore, it will not cause great damage to the first connection pad 330 and the second connection layer 430. Therefore, it can be ensured that the first connection pad 330 still exists before the second connection layer 430 is etched open. Until the first dielectric layer 320 and the second dielectric layer 420 are completely etched open, the etching is stopped by means of the second connection layer 430 of the lower wafer, and the etching process is relatively simple.

[0134] S103, filling a conductive material in the vertical through-hole 359 to form a contact plug 360, refer to Figure 16 (e), 17(e), 18(e), 19(e) and 20(e).

[0135] In the embodiment of the present application, etching can be started from the upper surface of the first wafer 300 to form a vertical through-hole 359 as the vertical through-hole 359. In this vertical through-hole 359, the upper surface of the first connection pad 330, as well as the upper surface and / or side wall of the second connection pad 430 are exposed. In this way, after filling the vertical through-hole 359 with metal, the formed contact plug 360 contacts the upper surface of the first connection pad 330, and at the same time contacts the upper surface and / or side wall of the second connection pad 430, that is, the formed contact plug 360 contacts both the first connection pad 330 and the second connection pad 430, realizing the electrical connection between the first connection pad 330 and the second connection pad 430.

[0136] To form the contact plug 360 in the vertical through-hole 359, a conductive material can be formed in the vertical through-hole 359 by electroplating or deposition, and then a planarization process, such as chemical mechanical polishing process, is used to remove the conductive material outside the vertical through-hole 359, thereby forming the contact plug 360. The material of the contact plug 360 can be copper or aluminum, and can be other conductive metal materials or non-metal materials, such as doped silicon.

[0137] In a manufacturing method of a semiconductor device provided by an embodiment of the present application, a first wafer and a second wafer that have completed bonding are provided. The first wafer includes a first dielectric layer, and a first pad is provided in the first dielectric layer. The second wafer includes a second dielectric layer, and a second pad is provided in the second dielectric layer. Using the first pad as a barrier layer, a vertical through hole can be formed by etching from the top down of the first wafer. The vertical through hole penetrates the first wafer to the upper surface of the first pad, and penetrates the second wafer along the sidewall of the first pad to the second pad, and exposes the upper surface and / or sidewall of the second pad. A conductive material is filled in the vertical through hole to form a contact plug. That is to say, the vertical through hole can expose the upper surface of the first wafer, and the upper surface and / or sidewall of the second pad. In this way, the contact plug in the vertical through hole can be in contact with both the first pad and the second pad at the same time, so as to realize the electrical connection between the first pad and the second pad. The contact plug serves as a signal transmission channel between the first pad and the second pad, and its path is short, reducing signal delay. At the same time, the vertical through hole is formed by an etching process and penetrates from the sidewall of the first pad to the second pad. The contact plug therein can contact the second pad from the periphery of the first pad, so as to realize a reliable connection between the contact plug and the second pad by a simple process. In addition, there is only one metal plug in the embodiment of the present application, and there is no need to consider the distance between two metal plugs. Therefore, the lateral dimension can be reduced to a certain extent, the device size can be reduced, and the integration degree of the device can be improved.

[0138] It should be noted that the various embodiments in the embodiments of the present application can refer to each other. For the device embodiments, the description of the method embodiments can be referred to, and the method embodiments can also refer to the description of the device embodiments.

[0139] The above is the specific implementation manner of the present application. It should be understood that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the various embodiments of the present application.

Claims

1. A semiconductor device, characterized in that, comprising: a first wafer, a second wafer and a contact plug; the first wafer includes a first dielectric layer, and a first pad is provided in the first dielectric layer; the second wafer is bonded to the first wafer, the second wafer includes a second dielectric layer, and a second pad is provided in the second dielectric layer; the contact plug is a conductive material filled in a vertical through hole for electrically connecting the first pad and the second pad; the vertical through hole is a through hole formed by etching through the first wafer and partially through the second wafer to the upper surface and / or side wall of the second pad, the first pad is located in the vertical through hole and the first dielectric layer below the first pad is not etched, and the side walls on two or three sides of the first pad are in contact with the contact plug.

2. The semiconductor device according to claim 1, characterized in that, the second pad is longitudinally and directly opposite to the first pad, and the side wall on at least one side of the second pad extends laterally beyond the side wall of the first pad, so that the vertical through hole exposes the upper surface adjacent to the side wall on at least one side of the second pad, or the side wall on at least one side of the second pad and the adjacent upper surface.

3. The semiconductor device according to claim 1 or 2, characterized in that, the vertical through hole exposes the side wall of the first pad; or in the vertical through hole, a first dielectric layer remains on the side wall of the first pad.

4. The semiconductor device according to claim 1 or 2, characterized in that, the second pad is longitudinally and directly opposite to the first pad, and the side wall on at least one side of the second pad is flush with the side wall of the first pad, so that the vertical through hole exposes at least one side wall of the second pad and the side wall of the first pad flush with the second pad.

5. The semiconductor device according to claim 1, characterized in that, the second pad is longitudinally staggered with the first pad, and the size of the top opening of the vertical through hole is greater than or equal to the lateral distance between the second pad and the first pad.

6. The semiconductor device according to any one of claims 1-2, characterized in that, further comprising: a third wafer; a third pad is provided in the third wafer; the third wafer is bonded to the first wafer to realize electrical connection between the third pad and the contact plug.

7. The semiconductor device according to any one of claims 1-2, characterized in that, the vertical through hole penetrates in the direction of the side walls on multiple sides of the first pad.

8. A manufacturing method of a semiconductor device, characterized in that, comprising: providing a first wafer and a second wafer that have been bonded; the first wafer includes a first dielectric layer, and a first pad is provided in the first dielectric layer; the second wafer includes a second dielectric layer, and a second pad is provided in the second dielectric layer; Using the first connection disk as a barrier layer, etching the first wafer from top to bottom to form a vertical through-hole that penetrates the first wafer to the upper surface of the first connection disk, and penetrates the second wafer along the sidewall of the first connection disk to the second connection disk, and exposes the upper surface and / or sidewall of the second connection disk. The first connection disk is located in the vertical through-hole and the first dielectric layer below the first connection disk is not etched. Filling the vertical through-hole with a conductive material to form a contact plug for realizing electrical connection between the first connection disk and the second connection disk. The contact plug contacts the sidewalls on two or three sides of the first connection disk.

9. The method according to claim 8, characterized in that, if the second connection disk is longitudinally and directly opposite to the first connection disk, then using the first connection disk as a barrier layer and etching the first wafer from top to bottom to form a vertical through-hole includes: etching from the upper surface of the first wafer to obtain a first opening. The first opening is located above the first connection disk, and at least one sidewall of the first opening laterally extends beyond the sidewall of the first connection disk. etching at the bottom of the position where the sidewall of the first opening laterally extends beyond the first connection disk to form a second opening. Using the first connection disk as a barrier layer, deepening the first opening and the second opening together so that the deepened first opening exposes the upper surface of the first connection disk, and the deepened second opening exposes the upper surface and / or sidewall of the second connection disk.

10. The method according to claim 9, characterized in that, in the direction where the sidewall of the first opening laterally extends beyond the sidewall of the first connection disk, at least one side of the sidewall of the second connection disk laterally extends beyond the sidewall of the first connection disk, and the deepened second opening exposes the upper surface adjacent to the sidewall of the second connection disk that laterally extends beyond the sidewall of the first connection disk, or the upper surface of the sidewall of the second connection disk that laterally extends beyond the sidewall of the first connection disk and its adjacent upper surface; and / or, in the direction where the sidewall of the first opening laterally extends beyond the sidewall of the first connection disk, at least one side of the sidewall of the second connection disk is flush with the sidewall of the first connection disk, and the deepened second opening exposes the sidewall of the second connection disk that is flush with the first connection disk.

11. The method according to claim 10, characterized in that, in at least one side of the sidewall of the second connection disk that laterally extends beyond the sidewall of the first connection disk, a first dielectric layer is reserved on the sidewall of the first connection disk in the deepened second opening.

12. The method according to claim 8, characterized in that, the second connection disk is longitudinally and directly opposite to the first connection disk, and there is a third opening in the first dielectric layer. Then using the first connection disk as a barrier layer and etching the first wafer from top to bottom to form a vertical through-hole includes: Etch a first opening from the upper surface of the first wafer; the first opening is located above the first connection pad, and at least one side wall of the first opening extends laterally beyond the side wall of the first connection pad; Using the first connection pad as a barrier layer, etch the first dielectric layer and the second dielectric layer at the bottom of the first opening, so that the deepened first opening communicates with the third opening, and deepen the third opening during the etching process; the deepened first opening exposes the upper surface of the first connection pad, and the deepened third opening exposes the upper surface and / or side wall of the second connection pad.

13. The method according to claim 12, wherein, In the direction that the side wall of the first opening extends laterally beyond the side wall of the first connection pad, at least one side of the side wall of the second connection pad extends laterally beyond the side wall of the first connection pad, and the deepened third opening exposes the upper surface adjacent to the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad, or the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad and its adjacent upper surface; and / or, in the direction that the side wall of the first opening extends laterally beyond the side wall of the first connection pad, at least one side of the side wall of the second connection pad is flush with the side wall of the first connection pad, then the deepened third opening exposes the side wall of the second connection pad that is flush with the first connection pad.

14. The method according to claim 13, wherein, In at least one side of the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad, a first dielectric layer is retained on the side wall of the first connection pad in the deepened third opening.

15. The method according to claim 8, wherein, The second connection pad and the first connection pad are longitudinally and oppositely arranged, then using the first connection pad as a barrier layer, etching a vertical through hole from top to bottom in the first wafer includes: Etch a first opening from the upper surface of the first wafer; the first opening is located above the first connection pad, and at least one side wall of the first opening extends laterally beyond the side wall of the first connection pad; Using the first connection pad as a barrier layer, deepen the first opening so that the deepened first opening exposes the upper surface of the first connection pad, and the upper surface and / or side wall of the second connection pad.

16. The method according to claim 15, wherein, In the direction that the side wall of the first opening extends laterally beyond the side wall of the first connection pad, at least one side of the side wall of the second connection pad extends laterally beyond the side wall of the first connection pad, and the deepened first opening exposes the upper surface adjacent to the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad, or the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad and its adjacent upper surface; And / or, in the direction where the side wall of the first opening extends laterally beyond the first connection pad, at least one side of the side wall of the second connection pad is flush with the side wall of the first connection pad, so that the deepened first opening exposes the side wall of the second connection pad that is flush with the first connection pad.

17. The method according to claim 8, wherein, the second connection pad is longitudinally opposite to the first connection pad, and then, with the first connection pad as a barrier layer, etching is performed on the first wafer from top to bottom to form a vertical through hole, including: etching from the upper surface of the first wafer to obtain a fourth opening; at least one side wall of the fourth opening extends laterally beyond the side wall of the first connection pad; with the first connection pad as a barrier layer, etching is performed above the first connection pad and at the bottom of the fourth opening to expose the upper surface of the first connection pad, and the deepened fourth opening exposes the upper surface and / or side wall of the second connection pad.

18. The method according to claim 17, wherein, in the direction where the side wall of the fourth opening extends laterally beyond the side wall of the first connection pad, at least one side of the side wall of the second connection pad extends laterally beyond the side wall of the first connection pad, and the deepened fourth opening exposes the upper surface adjacent to the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad, or the side wall of the second connection pad that extends laterally beyond the side wall of the first connection pad and its adjacent upper surface; and / or, in the direction where the side wall of the fourth opening extends laterally beyond the side wall of the first connection pad, at least one side of the side wall of the second connection pad is flush with the side wall of the first connection pad, so that the deepened fourth opening exposes the side wall of the second connection pad that is flush with the first connection pad.

19. The method according to any one of claims 8-18, wherein, filling the vertical through hole with a conductive material to form a contact plug, including: forming a conductive material in the vertical through hole and on the upper surface of the first wafer by using an electroplating or deposition process; removing the conductive material on the upper surface of the first wafer by using a planarization process to form a contact plug in the vertical through hole.

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