Test circuit, test board and test system

Abstract

The application discloses a test circuit, a test board and a test system. The test circuit comprises an amplification circuit and a voltage conversion circuit. An input end of the amplification circuit is used for being connected with a signal output end of a chip to be tested, and an output end of the amplification circuit is used for being connected with a test device; the amplification circuit is used for amplifying an audio signal output by the chip to be tested and outputting the audio signal to the test device. An input end of the voltage conversion circuit is used for being connected with the test device, and an output end of the voltage conversion circuit is connected with a power supply end of the amplification circuit; the voltage conversion circuit is used for converting a voltage of a power supply end of the chip to be tested into a first voltage and outputting the first voltage to the amplification circuit to supply power to the amplification circuit. The input end of the voltage conversion circuit is connected with the test device, the voltage conversion circuit converts a power supply voltage output by the test device to the chip to be tested into the first voltage required by the amplification circuit to work, and the test device can supply power to the amplification circuit through the voltage conversion circuit while supplying power to the chip to be tested.

Description

Technical Field

[0001] This invention relates to the field of chip testing, and more specifically to a test circuit, a test board, and a test system. Background Technology

[0002] Every ASIC (Application Specific Integrated Circuit) requires thorough performance verification from design completion to successful mass production to ensure that all performance indicators meet design requirements in real-world applications. Existing general-purpose ASIC-only verification test boards are cumbersome to connect in actual verification, greatly increasing the preparation and debugging work before testing. Summary of the Invention

[0003] The main objective of this invention is to provide a test circuit, test board, and test system for more efficient chip testing.

[0004] To achieve the above objectives, this invention proposes a test circuit for packaging testing of microphone-specific integrated circuit chips, the test circuit comprising:

[0005] An amplifier circuit is provided, wherein the input terminal of the amplifier circuit is connected to the signal output terminal of the chip under test, and the output terminal of the amplifier circuit is connected to the test equipment; the amplifier circuit is used to amplify the audio signal output by the chip under test and output it to the test equipment.

[0006] A voltage conversion circuit is provided, wherein the input terminal of the voltage conversion circuit is used to connect to the test equipment, and the output terminal of the voltage conversion circuit is connected to the power supply terminal of the amplifier circuit; the voltage conversion circuit is used to convert the voltage of the power supply terminal of the chip under test into a first voltage and output it to the amplifier circuit to power the amplifier circuit.

[0007] In one embodiment, the test circuit further includes a current test port;

[0008] The current test port is used to electrically connect to the power supply terminal of the chip under test when no current test is being performed; the current test port is also used to connect an ammeter to measure the current of the chip under test when a current test is being performed.

[0009] In one embodiment, the current test port has a first connection terminal and a second connection terminal, the first connection terminal being connected to the power supply terminal of the chip under test, and the second connection terminal being grounded;

[0010] The current test port is used to disconnect the path between the first connection terminal and the second connection terminal when performing a current test on the chip under test, and to connect the path between the first connection terminal and the second connection terminal when not performing a current test on the chip under test.

[0011] In one embodiment, there are multiple current test ports; the first connection terminals of the multiple current test ports are respectively used to connect to multiple power supply terminals of the chip under test, and the second connection terminals of the multiple current test ports are used to connect to the device under test.

[0012] The present invention also provides a test board, the test board including a circuit board and the above-described test circuit, the test circuit being disposed on the circuit board;

[0013] The test board also includes a placement slot for placing the chip to be tested.

[0014] In one embodiment, the test board includes:

[0015] Multiple test terminals are provided on the circuit board;

[0016] The multiple test terminals are used to electrically connect the chip under test to the placement slot when the chip under test is inserted into the placement slot, and the test terminals are also used to connect to the test equipment.

[0017] In one embodiment, the test terminal is a BNC interface.

[0018] In one embodiment, the test board includes N wiring layers, where N is greater than 2;

[0019] The Mth wiring layer of the test board has multiple signal lines, where M is greater than 2 and M is less than N; one end of each signal line is electrically connected to one of the multiple test terminals through vias, and the other end of each signal line is electrically connected to the chip under test through the placement slot.

[0020] The test board has a first ground plane on the (M-1)th wiring layer corresponding to the position of the signal line; the test board has a second ground plane on the (M+1)th wiring layer corresponding to the position of the signal line.

[0021] In one embodiment, the test board further includes communication terminals;

[0022] The communication terminal is used to electrically connect the chip under test to the placement slot when the chip under test is inserted into the placement slot, and the communication terminal is also used to electrically connect to the host computer.

[0023] The present invention also provides a testing system, the testing system comprising a host computer, testing equipment and the aforementioned testing board;

[0024] The communication terminals of the test board are electrically connected to the host computer, and the multiple test terminals of the test board are electrically connected to the test equipment, which is also electrically connected to the host computer.

[0025] The host computer is used to control the operation of the test board, and the test equipment is used to acquire the operating parameter signals of the test board and output the operating parameter signals to the host computer.

[0026] This invention connects to the test equipment via the input terminal of a voltage conversion circuit, converting the supply voltage output from the test equipment to the chip under test (DUT) into the first voltage required for the amplifier circuit to operate. This allows the test equipment to supply power to the DUT while simultaneously supplying power to the amplifier circuit via the voltage conversion circuit. Thus, during testing, only a single connection operation between the corresponding test terminals and the test equipment via signal lines is required to power both the DUT and the amplifier circuit. This eliminates the need for a separate power supply to power the amplifier circuit, reducing testing steps and improving efficiency. It also simplifies power signal wiring and reduces the amount of test equipment used. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the structure of an embodiment of the test circuit of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of an embodiment of the test board of the present invention.

[0030] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0033] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0034] Every ASIC requires thorough performance verification from design completion to successful mass production to ensure that all performance indicators meet design requirements in real-world applications. Existing verification test boards, however, require an external power supply to provide operating voltage to the amplifier for the originally only-packaged MIC (microphone) ASIC, increasing the number of testing steps and equipment required.

[0035] To address the above problems, this invention provides a test circuit for packaging testing of microphone-specific integrated circuit chips. The test circuit includes:

[0036] An amplifier circuit 100 is provided, wherein the input terminal of the amplifier circuit 100 is used to connect to the signal output terminal of the chip under test, and the output terminal of the amplifier circuit 100 is used to connect to a test device; the amplifier circuit 100 is used to amplify the audio signal output by the chip under test and output it to the test device.

[0037] A voltage conversion circuit 200 is provided, wherein the input terminal of the voltage conversion circuit 200 is used to connect to the test equipment, and the output terminal of the voltage conversion circuit 200 is connected to the power supply terminal of the amplifier circuit 100; the voltage conversion circuit 200 is used to convert the voltage of the power supply terminal of the chip under test into a first voltage and output it to the amplifier circuit 100 to power the amplifier circuit 100.

[0038] The amplifier circuit 100 may use one or more amplifiers. In this embodiment, the amplifier circuit 100 includes an amplifier and a capacitor. The non-inverting input terminal of the amplifier is connected to the signal output terminal of the chip under test, the inverting input terminal of the amplifier is connected to the output terminal of the amplifier, and the power supply terminal of the amplifier is connected to the output terminal of the voltage conversion circuit 200. The first terminal of the capacitor is connected to the power supply terminal of the amplifier, and the second terminal of the capacitor is grounded. The amplifier amplifies the audio signal output by the chip under test and outputs it to the test equipment so that the test equipment can acquire and display the performance parameters of the chip under test. The test equipment may be an audio test analyzer.

[0039] During testing, the chip under test (DUT) requires power, which is supplied by the testing equipment. The DUT is connected to the testing circuit, so the testing circuit can be powered by the DUT's power supply. Specifically, the testing circuit is located on a test board with multiple test terminals. The testing equipment is electrically connected to the DUT through the first test terminal RF1 on the test board and supplies power to the DUT. The DUT can be a microcontroller (MIC) chip or an integrated circuit board containing a MIC chip. The input of the voltage conversion circuit 200 is electrically connected to the first test terminal RF1 on the test board, converting the supply voltage from the testing equipment into the first voltage output required by the amplifier circuit 100. In this way, the testing equipment can simultaneously power both the DUT and the amplifier circuit 100 without requiring an additional power supply for the amplifier circuit 100. This simplifies the power signal wiring of the amplifier circuit 100, reduces the amount of testing equipment used, and consequently reduces the number of testing steps, improving testing efficiency.

[0040] This invention connects to the test equipment via the input terminal of a voltage conversion circuit, converting the supply voltage output from the test equipment to the chip under test (DUT) into the first voltage required for the amplifier circuit to operate. This allows the test equipment to supply power to the DUT while simultaneously supplying power to the amplifier circuit via the voltage conversion circuit. Thus, during testing, only a single connection operation between the corresponding test terminals and the test equipment via signal lines is required to power both the DUT and the amplifier circuit. This eliminates the need for a separate power supply to power the amplifier circuit, reducing testing steps and improving efficiency. It also simplifies power signal wiring and reduces the amount of test equipment used.

[0041] In one embodiment, the test circuit further includes a current test port;

[0042] The current test port is used to electrically connect to the power supply terminal of the chip under test when no current test is being performed; the current test port is also used to connect an ammeter to measure the current of the chip under test when a current test is being performed.

[0043] Existing test circuits do not have a dedicated port for current testing on the VDD-GND loop of the chip under test. Whenever the current is tested, an ammeter must be connected in series with the external power supply of the VDD pin, which is inconvenient.

[0044] This embodiment adds a current test port to the VDD-GND circuit of the chip under test (TBT) for connecting an ammeter. Specifically, during testing, the TBT is connected to the test equipment via the first test terminal RF1. When a current test is required, the current test port is controlled to disconnect the TBT from the first test terminal RF1, i.e., disconnect the VDD-GND circuit, connect the ammeter, and read and record the current value of the TBT. For other tests, the current test port is controlled to connect the VDD-GND circuit to supply power to the TBT. The current test port can consist of two pads, connected to the VDD and GND pins respectively. When current testing is required, the positive and negative terminals of the ammeter are connected to the two pads respectively. For other tests, the two pads can be connected by soldering resistors to connect the VDD-GND circuit. Alternatively, the current test port can also consist of two metal electrodes, connected to the VDD and GND pins respectively. When testing the current, connect the positive and negative terminals of the ammeter to the two metal electrodes respectively. For other tests, the two metal electrodes can be connected by a jumper cap to connect the VDD-GND circuit.

[0045] This embodiment adds a current test port to the loop corresponding to the VDD-GND pins of the chip under test in the test circuit, which facilitates direct connection of an ammeter for current testing. This eliminates the need to connect an ammeter in series with the power supply of an external test device, simplifying the test steps and improving test efficiency.

[0046] In one embodiment, the current test port has a first connection terminal and a second connection terminal, the first connection terminal being connected to the power supply terminal of the chip under test, and the second connection terminal being grounded;

[0047] The current test port is used to disconnect the path between the first connection terminal and the second connection terminal when performing a current test on the chip under test, and to connect the path between the first connection terminal and the second connection terminal when not performing a current test on the chip under test.

[0048] In this embodiment, when a current test is required, the first and second connection terminals of the current test port are disconnected, and an ammeter is connected to read and record the current value of the chip under test. For other tests, the first and second connection terminals of the current test port are connected to supply power to the chip under test. Further, the first and second connection terminals can be metal electrodes (e.g., pins). When no current test is being performed, a jumper cap is used to short-circuit the two metal electrodes to supply power to the chip under test. When a current test is required, the jumper cap is removed, and the two metal electrodes are connected to the positive and negative terminals of the ammeter, respectively, to perform a current test on the chip under test.

[0049] This embodiment disconnects the path between the first and second connection terminals of the current test port during current testing to allow the ammeter to be connected for current measurement; when not performing current testing, the path between the first and second connection terminals of the current test port is connected to supply power to the chip under test for other tests. This facilitates current testing without affecting other testing items.

[0050] In one embodiment, there are multiple current test ports; the first connection terminals of the multiple current test ports are respectively used to connect to multiple power supply terminals of the chip under test, and the second connection terminals of the multiple current test ports are used to connect to the device under test.

[0051] In this embodiment, H3 and H9 are both current test ports. The first connection terminal of H9 is used to connect to the VDD pin of the chip under test, and the second connection terminal of H9 is connected to the test equipment via the first test terminal RF2. The first connection terminal of H3 is used to connect to the SUB pin of the chip under test, and the second connection terminal of H3 is connected to the test equipment via the second test terminal RF1. The test equipment can supply power to the VDD pin of the chip under test via the first test terminal RF2, or to the SUB pin via the second test terminal RF1. The current of the VDD pin and SUB pin of the chip under test can be tested respectively through the current test ports H3 and H9.

[0052] This embodiment allows for the configuration of multiple current test ports to perform current tests on multiple pins of the chip under test, based on actual needs. During current testing, the connection between the first and second terminals of the current test port is disconnected to allow an ammeter to be connected for testing. When not performing current testing, the connection between the first and second terminals of the current test port is connected to supply power to the chip under test for other tests. This process ensures that current testing does not interfere with other tests.

[0053] The present invention also provides a test board, the test board including a circuit board and the above-described test circuit, the test circuit being disposed on the circuit board;

[0054] The test board also includes a placement slot for placing the chip to be tested.

[0055] Metal electrodes are positioned on the surface of the placement slot corresponding to multiple pins of the chip under test. When the chip under test is located inside the placement slot, it is electrically connected to the test circuit through the multiple metal electrodes on the surface of the placement slot.

[0056] The detailed structure of the test circuit can be referred to in the above embodiments, and will not be repeated here. It is understood that since the above test circuit is used in the test board of the present invention, the embodiments of the test board of the present invention include all the technical solutions of all the embodiments of the above test circuit, and the technical effects achieved are exactly the same, and will not be repeated here.

[0057] In one embodiment, the test board includes:

[0058] Multiple test terminals are provided on the circuit board;

[0059] The multiple test terminals are used to electrically connect the chip under test to the placement slot when the chip under test is inserted into the placement slot, and the test terminals are also used to connect to the test equipment.

[0060] In this embodiment, multiple test terminals are electrically connected to multiple metal electrodes on the surface of the placement slot, thereby realizing the electrical connection between multiple pins of the chip under test and the test equipment.

[0061] In one embodiment, the test terminal is a BNC (Bayonet Nut Connector) interface. A BNC interface is a connector used for coaxial cables that can isolate video input signals, reducing interference between signals and achieving better signal response.

[0062] This embodiment uses a shielded BNC interface instead of a header to connect to the test equipment, making the connection simple and stable, greatly shortening the debugging time before testing and improving testing efficiency.

[0063] In one embodiment, the test board includes N wiring layers, where N is greater than 2;

[0064] The Mth wiring layer of the test board has multiple signal lines, where M is greater than 2 and M is less than N; one end of each signal line is electrically connected to one of the multiple test terminals through vias, and the other end of each signal line is electrically connected to the chip under test through the placement slot.

[0065] The test board has a first ground plane on the (M-1)th wiring layer corresponding to the position of the signal line; the test board has a second ground plane on the (M+1)th wiring layer corresponding to the position of the signal line.

[0066] In this embodiment, the test board includes a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer, arranged sequentially from top to bottom. Multiple test terminals are located on the first wiring layer, and the third wiring layer has multiple signal lines. One end of each signal line is electrically connected to one of the test terminals on the first wiring layer via vias, and the other end of each signal line is electrically connected to the chip under test via a slot. Ground planes are provided at the corresponding positions of the signal lines on the second and fourth wiring layers to shield and protect susceptible signal traces (e.g., VIN and VMIC), ensuring test stability.

[0067] This embodiment shields external interference by setting ground planes on adjacent wiring layers of signal traces that are susceptible to interference, ensuring the stability of the test and making the test results more accurate and reliable.

[0068] In one embodiment, the test board further includes communication terminals;

[0069] The communication terminal is used for electrical connection with the chip under test, and the communication terminal is also used for electrical connection with the host computer.

[0070] In this embodiment, the communication terminal establishes a communication connection between the chip under test (TBT) and the host computer. The host computer selects the desired test item and sends corresponding control signals and instructions to the TBT, controlling the state of the corresponding pins and the on / off state of the corresponding signal traces on the test board. The test equipment acquires and displays the test data of the TBT and returns the test data to the host computer, which then generates a test report for user analysis.

[0071] For example, during DC open-loop testing, control H5 is shorted to connect the path between the INN pin of the chip under test and the third test terminal RF5; and control H1 is opened to disconnect the path between the VMIC pin of the chip under test and the third test terminal RF5. The test equipment sends a test signal to the INN pin of the chip under test through the third test terminal RF5 to perform DC open-loop testing. During AC open-loop testing, control H1 is shorted to connect the path between the VMIC pin of the chip under test and the third test terminal RF5, and control H5 is opened to disconnect the path between the INN pin of the chip under test and the third test terminal RF5. The test equipment sends a test signal to the INN pin of the chip under test through the third test terminal RF5. Since the VMIC pin is an output terminal, it does not pick up the input test signal. The test signal reaches the INN pin through the internal circuitry of the chip under test, thus achieving AC open-loop testing. During AC closed-loop testing, both H1 and H5 are disconnected to break the path between the INN and VMIC pins of the chip under test and the third test terminal RF5, allowing signals to be input from other pins (such as the DATE or CLK pins) to achieve AC closed-loop testing. H1 and H5 can be shorted and disconnected using two metal electrodes or a switching chip.

[0072] The present invention also provides a testing system, the testing system comprising a host computer, testing equipment and the aforementioned testing board;

[0073] The communication terminals of the test board are electrically connected to the host computer, and the multiple test terminals of the test board are electrically connected to the test equipment, which is also electrically connected to the host computer.

[0074] The host computer is used to control the operation of the test board, and the test equipment is used to acquire the operating parameter signals of the test board and output the operating parameter signals to the host computer.

[0075] The detailed structure of the test board can be referred to in the above embodiments, and will not be repeated here. It is understood that since the above test board is used in the test system of the present invention, the embodiments of the test system of the present invention include all the technical solutions of all the embodiments of the above test board, and the technical effects achieved are exactly the same, and will not be repeated here.

[0076] The above are merely optional embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A test circuit applied to a package test of a microphone application specific integrated circuit chip, characterized in that, The test circuit comprises: an amplification circuit, an input end of the amplification circuit being used for being connected with a signal output end of the chip to be tested, and an output end of the amplification circuit being used for being connected with a test device; the amplification circuit is used for amplifying an audio signal output by the chip to be tested and outputting the amplified audio signal to the test device; a voltage conversion circuit, an input end of the voltage conversion circuit being used for being connected with the test device to receive a voltage output by the test device to a power supply end of the chip to be tested, and an output end of the voltage conversion circuit being connected with a power supply end of the amplification circuit; the voltage conversion circuit is used for converting the voltage of the power supply end of the chip to be tested into a first voltage and outputting the first voltage to the amplification circuit to supply power to the amplification circuit.

2. The test circuit of claim 1, wherein, The test circuit further comprises a current test port; the current test port is used for being electrically connected with the power supply end of the chip to be tested when no current test is performed, and the current test port is further used for being connected with an ammeter to measure the current of the chip to be tested when the current test is performed.

3. The test circuit of claim 2, wherein, The current test port has a first connection end and a second connection end, the first connection end is connected with the power supply end of the chip to be tested, and the second connection end is grounded; the current test port is used for disconnecting a path between the first connection end and the second connection end when the current test of the chip to be tested is performed, and the current test port is used for connecting the path between the first connection end and the second connection end when no current test of the chip to be tested is performed.

4. The test circuit of claim 3, wherein, The number of the current test ports is plural; the first connection ends of the plural current test ports are respectively used for being connected with plural power supply ends of the chip to be tested, and the second connection ends of the plural current test ports are used for being connected with the test device.

5. A test plate characterized by, The test board comprises a circuit board and the test circuit according to any one of claims 1 to 4, and the test circuit is arranged on the circuit board; The test board further comprises a placing groove, and the placing groove is used for placing the chip to be tested.

6. The test panel of claim 5, wherein, The test board comprises: a plurality of test terminals arranged on the circuit board; the test terminals are respectively used for being electrically connected with the chip to be tested through the placing groove when the chip to be tested is inserted into the placing groove, and the test terminals are further used for being connected with the test device.

7. The test panel of claim 6, wherein, The test terminals are BNC interfaces.

8. The test panel of claim 6, wherein, The test board comprises N wiring layers, and N is greater than 2; an Mth wiring layer of the test board is provided with a plurality of signal lines, M is greater than 2 and less than N; one end of the plurality of signal lines is electrically connected with the plurality of test terminals through a via one by one, and the other end of the plurality of signal lines is electrically connected with the chip to be tested through the placing groove; an M-1th wiring layer of the test board is provided with a first grounding surface at positions corresponding to the signal lines; and an M+1th wiring layer of the test board is provided with a second grounding surface at positions corresponding to the signal lines.

9. The test panel of claim 5, wherein, The test board further comprises a communication terminal; the communication terminal is used for being electrically connected with the chip to be tested through the placing groove when the chip to be tested is inserted into the placing groove, and the communication terminal is further used for being electrically connected with a host computer.

10. A test system, characterized by The test system comprises the host computer, the test device and the test board according to any one of claims 5 to 9. The communication terminal of the test board is electrically connected with the host computer, and the plurality of test terminals of the test board are respectively electrically connected with the test equipment, and the test equipment is also electrically connected with the host computer; The host computer is used for controlling the test board to work, and the test equipment is used for acquiring the working parameter signal of the test board and outputting the working parameter signal to the host computer.

Images