Event-triggered chip reset verification method, device, equipment and medium

Abstract

An embodiment of the present invention provides a chip reset verification method, device, equipment and medium using event triggering. The method includes: in a verification platform, encapsulating an independent and reusable general verification component for a reset signal; driving the reset signal to the reset signal input port of a design under test at a random time point through the general verification component to trigger the design under test to perform a reset operation; using a verification component related to the reset signal to monitor the state of the reset signal; after detecting that the reset signal is released, controlling the UVC encapsulated by the input port to drive a random input test sequence to an input interface bus to obtain an actual response of the design under test to the random input test sequence; comparing the actual response with a predicted response to verify the reset function of the design under test. The present invention can be easily embedded and encapsulated into a verification component to improve the reusability of code, thereby improving code efficiency and work efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip design, and in particular to a chip reset verification method, device, equipment and medium using event triggering. Background Art

[0002] When verifying the design under test (DUT) during chip design, it is often necessary to verify the reset scenario, that is, during the normal simulation operation of the DUT, the reset signal is set to a valid state to reset the DUT, and after a delay of a clock cycle, the reset signal is released to restart the DUT, and verify whether the restarted DUT can work normally. Resetting the DUT at any time during the simulation process is likely to disrupt the running state of the testbench, causing unexpected problems.

[0003] The existing solution is to provide a reset_pkg package file to provide the relevant components and interface methods required for reset testing. Figure 1 As shown, the reset signal monitor ( Figure 1 The monitor in the reset agent monitors the changes of the reset signal on the bus interface, and then calls the reset notifier according to the changes of the reset signal and the configured reset mode. Figure 1 The notification method of reset_blogger) is used to make message notifications. The content of the notification includes:

[0004] SUSPEND: Suspend the process

[0005] TERMINATE: Terminate a process

[0006] RESUME: Resume process

[0007] ACTIVATE: Start the process

[0008] Then all the verification components related to the reset signal will be passed as parameters and instantiated into reset subscribers ( Figure 1 reset_subscriber), these reset subscribers complete the subscription to the reset notifier message and are written to the reset subscriber's queue.

[0009] Next, the reset notifier broadcasts the message received from the reset signal monitor to all subscribing component members in the reset subscriber queue. Finally, these component members will call their internally implemented methods run_phase_new or clean_up to perform corresponding actions, thereby completing the synchronization with the synchronization logic of the DUT. At the same time, the process handler ( Figure 1 The process_handler) will also suspend, resume or terminate the process according to the notification message.

[0010] Through the above process, the verification test of the DUT function in the reset scenario is finally achieved in the verification environment.

[0011] The above solution has the following two defects:

[0012] (1) The above solution requires adding a new phase, run_phase_new, to almost all reset-related components, and using this phase to replace the run_phase provided in the original UVM verification methodology, which destroys the original usage habits of verification engineers and thus brings inconvenience in use.

[0013] (2) The above solution is relatively complex to use, which increases the difficulty of reusing project codes and reduces work efficiency to a certain extent. Summary of the invention

[0014] In view of this, an object of the present invention is to provide a chip reset verification method, device, equipment and medium method, device, equipment and medium using event triggering to improve the above-mentioned problems.

[0015] An embodiment of the present invention provides a chip reset verification method using event triggering, which includes:

[0016] In the verification platform, an independent reusable general verification component is encapsulated for the reset signal;

[0017] Driving a reset signal to a reset signal input port of the design to be tested at a random time point by the universal verification component;

[0018] Using a verification component related to the reset signal to monitor the state of the reset signal to trigger the design under test to perform a reset operation;

[0019] After monitoring that the reset signal is released, controlling the UVC packaged in the input port to drive a random input test sequence to the input interface bus to obtain an actual response of the design under test to the random input test sequence;

[0020] Compare the actual response with the predicted response to verify the reset function of the design under test.

[0021] Preferably, encapsulating an independent reusable general verification component for the reset signal specifically includes:

[0022] Create a reset interface model to transmit the reset signal to the design under test;

[0023] Create a transaction data type related to the reset signal. The transaction data type contains two data variable members, which are respectively used to represent the delay time before reset and the duration for which the reset signal is valid, and constrain the above two times to a reasonable expected range;

[0024] Create an excitation sequence for generating the reset signal;

[0025] Create a driver for the excitation sequence for driving the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test;

[0026] Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type;

[0027] Create a reset sequencer to arbitrate the excitation sequence of the reset signal and transmit it to the driver;

[0028] Encapsulate the above components into an agent to generate a reusable general verification component.

[0029] Preferably, the verification component related to the reset signal uses the interface method provided in the interface bus model for monitoring the synchronous hardware reset signal to monitor the status of the reset signal; wherein, the interface method is passed to the verification components in the verification platform that will be affected by the reset signal through the configuration database.

[0030] Preferably, using the verification component related to the reset signal to monitor the status of the reset signal includes:

[0031] Provide interface methods for monitoring the synchronous hardware reset signal in the reset interface model, which are respectively used to wait for the reset signal to be activated and wait for the reset signal to be released.

[0032] Preferably, using the verification component related to the reset signal to monitor the status of the reset signal further includes:

[0033] Implement two parallel threads in the monitor for the input and output port signals of the design under test. One thread is used to monitor the data on the input and output port signals of the design under test, encapsulate it into a transaction data type, and broadcast it to other components in the verification platform. The other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, stop monitoring, encapsulating, and broadcasting the port signals of the design under test.

[0034] Preferably, the monitoring of the status of the reset signal by using a verification component related to the reset signal further includes:

[0035] Implement two parallel threads in the driver for driving the input signal sequence. One thread is used to obtain the input excitation sequence of the design under test and drive it to the input port of the design under test. The other thread is used to monitor and wait for the reset signal to be activated. When the reset signal is valid, stop driving and reset the signals on the input interface bus.

[0036] Preferably, the monitoring of the status of the reset signal by using a verification component related to the reset signal further includes:

[0037] In the sequencer for arbitrating and transmitting the input excitation sequence, continuously monitor and wait for the reset signal to be activated. Once the reset signal is valid, stop all the sequences that are arbitrating and running on the sequencer, and reset the sequencer to an idle state.

[0038] An embodiment of the present invention further provides a chip reset verification device triggered by events, which includes:

[0039] An encapsulation unit, used to encapsulate an independent and reusable general verification component for the reset signal in the verification platform;

[0040] A reset driving unit, used to drive the reset signal to the reset signal input port of the design under test at a random time point through the general verification component to trigger the design under test to perform a reset operation;

[0041] A monitoring unit, used to monitor the status of the reset signal by using a verification component related to the reset signal;

[0042] A sequence driving unit, used to control the UVC encapsulated at the input port to drive a random input test sequence to the input interface bus after monitoring that the reset signal is released, so as to obtain the actual response of the design under test to the random input test sequence;

[0043] A verification unit, used to compare the actual response with the predicted response to verify the reset function of the design under test.

[0044] An embodiment of the present invention further provides a chip reset verification device triggered by events, which includes a memory and a processor. A computer program is stored in the memory and can be executed by the processor to implement the chip reset verification method triggered by events as described above.

[0045] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program that can be executed by a processor of a device where the computer-readable storage medium is located to implement the chip reset verification method triggered by events as described above.

[0046] In summary, in this embodiment, during the simulation run, the reset package UVC ( Figure 3 the reset UVC therein) drives a reset signal to the reset input port interface signal of the design under test at random time points, thereby resetting the design under test. The reset is repeated several times and the UVC of the input port package ( Figure 3 the input UVC therein) is controlled to drive a random input test sequence to the input interface bus, and the predicted expected result is compared with the actual output result of the design under test, thereby completing the functional verification of the design under test.

[0047] Compared with the prior art, this embodiment has at least the following advantages:

[0048] (1) It can be easily embedded into the verification component to improve the code reusability;

[0049] (2) A reset signal can be inserted at any time point during the simulation, and the verification component can perform corresponding processing actions according to the monitored reset signal status;

[0050] (3) After the reset signal is released, an input excitation sequence can be automatically resented for simulation verification;

[0051] (4) The solution is simple and easy to implement, and does not affect the coding habits of existing verification engineers. Even for newly recruited verification engineers, they can quickly get started and apply it, improving work efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0053] Figure 1 It is the verification platform structure for the reset scenario in the existing solution.

[0054] Figure 2 It is a schematic flow chart of a chip reset verification method triggered by events provided by the first embodiment of the present invention.

[0055] Figure 3 It is a verification platform structure for the reset scenario provided by the first embodiment of the present invention.

[0056] Figure 4 It is a schematic structural diagram of a chip reset verification device triggered by events provided by the second embodiment of the present invention. Detailed implementation manners

[0057] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0058] To better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0060] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0061] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners:

[0062] Please refer to Figure 2 and Figure 3 , the first embodiment of the present invention provides a chip reset verification method triggered by events, which includes:

[0063] S101. In the verification platform, encapsulate an independent and reusable general verification component for the reset signal.

[0064] Specifically, in this embodiment, step S101 includes:

[0065] Create a reset interface model to transmit the reset signal to the design under test;

[0066] Create a transaction data type related to the reset signal, where the transaction data type contains two data variable members, which are respectively used to represent the delay time before reset and the duration for which the reset signal is valid, and constrain the above two times to a reasonable expected range;

[0067] Create an excitation sequence for generating a reset signal;

[0068] Create a driver for the excitation sequence that drives the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test;

[0069] Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type;

[0070] Create a reset sequencer to arbitrate the excitation sequence of the reset signal and transmit it to the driver;

[0071] Encapsulate the above components into an agent to generate a reusable general verification component.

[0072] S102, drive the reset signal to the reset signal input port of the design under test at a random time point through the general verification component to trigger the design under test to perform a reset operation.

[0073] In this embodiment, after obtaining the general verification component, by declaring and instantiating a reset signal excitation sequence (reset_sequence), it can be randomly started at any random time point during the simulation process to generate a reset signal to the reset signal input port of the design under test. Among them, the number of reset activations can be arbitrarily set. In this way, after the set number of reset activations is completed, enter a waiting sleep state.

[0074] S103, use the verification component related to the reset signal to monitor the state of the reset signal.

[0075] In this embodiment, as Figure 3 shown, pass the interface bus model ( Figure 3 the interface in) to the verification components in the verification platform that will be affected by the reset signal (mainly the UVC encapsulated by the input and output ports, that is, Figure 3 the uvm_config_db in), and then these verification components use the interface method provided in the interface bus model to monitor the synchronous hardware reset signal ( Figure 3 the input&output UVC in), and then these verification components use the interface method provided in the interface bus model to monitor the synchronous hardware reset signal ( Figure 3Use the reset monitor api) to monitor the status of the reset signal and perform corresponding synchronization processing actions, while these verification components maintain the functions they originally executed in the normal state.

[0076] Specifically, it includes:

[0077] Provide interface methods in the reset interface model to monitor the synchronous hardware reset signal, which are respectively used to wait for the reset signal to be activated and wait for the reset signal to be released.

[0078] Implement two parallel threads in the monitor of the input and output port signals of the design under test. One thread is used to monitor the data on the input and output port signals of the design under test, encapsulate it into a transaction data type, and broadcast it to other components in the verification platform. The other thread is used to monitor waiting for the reset signal to be activated. When the reset signal is valid, stop monitoring, encapsulating, and broadcasting the port signals of the design under test. After that, wait for the reset signal to be released, and when the design under test enters the normal working state, continuously repeat the above process.

[0079] Implement two parallel threads in the driver (driver) for driving the input signal sequence. One thread is used to obtain the input stimulus sequence elements (sequence_item) of the design under test and drive them to the input ports of the design under test. The other thread is used to monitor

[0080] Wait for the reset signal to be activated. When the reset signal is valid, stop driving and reset the signals on the input interface bus. After that, wait for the reset signal to be released, and when the design under test enters the normal working state, continuously repeat the above process.

[0081] In the sequencer for arbitrating and transmitting the input stimulus sequence, continuously monitor and wait for the reset signal to be activated. Once the reset signal is valid, stop all sequences that are arbitrating and running on the sequencer, and reset the sequencer to an idle state. After that, wait for the reset signal to be released, and when the design under test enters the normal working state, then monitor again whether the reset signal is activated and valid and repeat the above process.

[0082] S104, after detecting that the reset signal is released, control the UVC encapsulated in the input port to drive a random input test sequence to the input interface bus to obtain the actual response of the design under test to the random input test sequence.

[0083] S105, compare the actual response with the predicted response to verify the reset function of the design under test.

[0084] In this embodiment, after the reset signal is detected as released by the above verification component, a random input excitation sequence (random_sequence) of the design under test is instantiated through the UVC declaration encapsulated in the input port. Wait for the design under test to complete the operation on the input excitation sequence and the actual response, and compare the actual response with the predicted response to verify the reset function of the design under test.

[0085] In summary, in this embodiment, during the simulation run, by controlling the reset encapsulation UVC ( Figure 3 the reset UVC in it) to drive the reset signal to the reset input port interface signal of the design under test at random time points, the design under test is reset. Repeat the reset several times and control the UVC encapsulated in the input port ( Figure 3 the input UVC in it) to drive a random input test sequence to the input interface bus, and compare the predicted expected result with the result actually output by the design under test, so as to complete the functional verification of the design under test.

[0086] Compared with the prior art, this embodiment has at least the following advantages:

[0087] (1) It can be easily embedded and encapsulated into the verification component to improve the reusability of the code;

[0088] (2) The reset signal can be inserted at any time point during the simulation process, and the verification component can perform corresponding processing actions according to the detected state of the reset signal;

[0089] (3) After the reset signal is released, the input excitation sequence can be automatically resent for simulation verification;

[0090] (4) The solution is simple and easy to implement, and does not affect the coding habits of existing verification engineers. Even for newly recruited verification engineers, they can quickly get started and apply it, improving work efficiency.

[0091] Please refer to Figure 4 , the second embodiment of the present invention also provides a chip reset verification device using event triggering, which includes:

[0092] An encapsulation unit 210, configured to encapsulate an independent and reusable general verification component for the reset signal in the verification platform;

[0093] A reset driving unit 220, configured to drive the reset signal to the reset signal input port of the design under test at a random time point through the general verification component to trigger the design under test to perform a reset operation;

[0094] A monitoring unit 230, configured to monitor the state of the reset signal by using a verification component related to the reset signal;

[0095] A sequence driving unit 240, configured to control the UVC driver encapsulated in the input port to input a random input test sequence to the input interface bus after detecting that the reset signal is released, so as to obtain the actual response of the design under test to the random input test sequence;

[0096] A verification unit 250, configured to compare the actual response with the predicted response to verify the reset function of the design under test.

[0097] The third embodiment of the present invention further provides an event-triggered chip reset verification device, which includes a memory and a processor. A computer program is stored in the memory, and the computer program can be executed by the processor to implement the event-triggered chip reset verification method as described above.

[0098] The fourth embodiment of the present invention further provides a computer-readable storage medium, which stores a computer program. The computer program can be executed by the processor of the device where the computer-readable storage medium is located to implement the event-triggered chip reset verification method as described above.

[0099] In several embodiments provided by the embodiments of the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device and method embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code includes one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0100] In addition, each functional module in various embodiments of the present invention may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.

[0101] When the above-described functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes. It should be noted that in this article, the terms "include", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or device. Without further limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

[0102] The foregoing are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip reset verification method using event triggering, characterized in that, Including: In the verification platform, encapsulate an independent and reusable general verification component for the reset signal; Drive the reset signal to the reset signal input port of the design under test at random time points through the general verification component to trigger the design under test to perform a reset operation; Monitor the status of the reset signal using the verification component related to the reset signal; After detecting that the reset signal is released, control the UVC encapsulated in the input port to drive a random input test sequence to the input interface bus to obtain the actual response of the design under test to the random input test sequence; Compare the actual response with the predicted response to verify the reset function of the design under test.

2. The chip reset verification method triggered by events according to claim 1, wherein Specifically, encapsulating an independent and reusable general verification component for the reset signal includes: Create a reset interface model to transmit the reset signal to the design under test; Create a transaction data type related to the reset signal, and the transaction data type includes two data variable members, which are respectively used to represent the delay time before reset and the duration for which the reset signal is valid, and constrain the delay time and duration within a reasonable expected range; Create an excitation sequence for generating the reset signal; Create a driver for the excitation sequence for driving the reset signal, and drive the reset signal according to the reset delay and duration information in the transaction data type related to the reset signal and apply it to the reset signal input port of the design under test; Create a reset monitor to monitor the reset signal and encapsulate it into a corresponding transaction data type; Create a reset sequencer to arbitrate the excitation sequence of the reset signal and transmit it to the driver; Encapsulate the above components into an agent to generate a reusable general verification component.

3. The chip reset verification method triggered by events according to claim 1, wherein The verification component related to the reset signal uses the interface method for monitoring the synchronous hardware reset signal provided in the interface bus model to monitor the status of the reset signal; wherein, the interface method for monitoring the synchronous hardware reset signal of the interface bus model is passed to the verification components in the verification platform that will be affected by the reset signal through the configuration database.

4. The chip reset verification method triggered by an event according to claim 3, wherein Monitoring the status of the reset signal using the verification component related to the reset signal includes: Provide interface methods for monitoring the synchronous hardware reset signal in the reset interface model, which are respectively used to wait for the reset signal to be activated and wait for the reset signal to be released.

5. The chip reset verification method triggered by events according to claim 4, characterized in that, Monitoring the status of the reset signal using the verification component related to the reset signal further includes: Implement two parallel threads in the monitor of the input / output port signals of the design under test. One thread is used to monitor the data on the input / output port signals of the design under test, encapsulate it into a transaction data type, and broadcast it to other components in the verification platform; the other thread is used to monitor and wait for the reset signal to be activated, and when the reset signal is valid, stop monitoring, encapsulating, and broadcasting the port signals of the design under test.

6. The chip reset verification method triggered by an event according to claim 5, characterized in that, Monitoring the status of the reset signal using the verification component related to the reset signal further includes: Implement two parallel threads in a driver for driving an input signal sequence, where one thread is used to obtain an input excitation sequence of a design under test and drive it to the input port of the design under test, and the other thread is used to monitor and wait for a reset signal to be activated. When the reset signal is valid, stop driving and reset the signals on the input interface bus.

7. The chip reset verification method triggered by an event according to claim 6, characterized in that, Monitoring the status of the reset signal using a verification component associated with the reset signal further includes: In a sequencer for arbitrating and transmitting an input excitation sequence, continuously monitor and wait for the reset signal to be activated; when it is determined that the reset signal is valid, stop all sequences that are arbitrating and running on the sequencer, and reset the sequencer to the idle state.

8. An event-triggered chip reset verification device, characterized in that, It includes: An encapsulation unit for encapsulating an independent and reusable general verification component for the reset signal in a verification platform; A reset driving unit for driving the reset signal to the reset signal input port of the design under test at a random time point through the general verification component to trigger the design under test to perform a reset operation; A monitoring unit for monitoring the status of the reset signal using a verification component associated with the reset signal; A sequence driving unit for, after detecting that the reset signal is released, controlling the UVC encapsulated at the input port to drive a random input test sequence to the input interface bus to obtain the actual response of the design under test to the random input test sequence; A verification unit for comparing the actual response with the predicted response to verify the reset function of the design under test.

9. An event-triggered chip reset verification device, characterized in that, It includes a memory and a processor, and a computer program is stored in the memory. The computer program can be executed by the processor to implement the chip reset verification method using event triggering as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, A computer program is stored, and the computer program can be executed by the processor of the device where the computer-readable storage medium is located to implement the chip reset verification method using event triggering as described in any one of claims 1 to 7.

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