Scanning drive circuit, driving method thereof, and display panel

Abstract

The present invention discloses a scanning driving circuit and a driving method thereof, and a display panel. The scanning driving circuit includes a plurality of cascaded shift registers, the plurality of cascaded shift registers include a first shift register, the first shift register includes a first input module, a second input module, a first output module, and a second output module; the first control end of the first input module is connected to a reset signal, and the second control end of the first input module is connected to a first clock signal; wherein, in the start-up phase of the scanning driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output end of the first shift register. The technical solution provided by the embodiment of the present invention can ensure the stability and reliability of the output signal of the scanning driving circuit at the first frame moment, thereby preventing the abnormal display brightness of the first frame of the display panel from occurring.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a scanning driving circuit and a driving method thereof, and a display panel. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the performance of display panels.

[0003] The display panel usually includes a scan driving circuit. The existing scan driving circuit has the problem of unstable output signal, which easily causes abnormal brightness of the first frame of the display panel, affecting the display effect of the display panel. Summary of the invention

[0004] The present invention provides a scan driving circuit and a driving method thereof, and a display panel, so as to improve the stability of the output signal of the scan driving circuit and enhance the display effect of the display panel.

[0005] According to one aspect of the present invention, there is provided a scan driving circuit, comprising a plurality of cascaded shift registers, wherein the plurality of cascaded shift registers comprises a first shift register, wherein the first shift register comprises a first input module, a second input module, a first output module and a second output module;

[0006] A first control terminal of the first input module is connected to a reset signal, a second control terminal of the first input module is connected to a first clock signal, and the first input module is used to control the potential of the control terminal of the first output module according to the reset signal or the first clock signal;

[0007] The second input module is used to control the potential of the control terminal of the second output module;

[0008] The output end of the first output module and the output end of the second output module are both connected to the output end of the first shift register, the first output module is used to output a first signal according to the potential of its control end, and the second output module is used to output a second signal according to the potential of its control end;

[0009] Wherein, in the start-up phase of the scan driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output end of the first shift register.

[0010] Optionally, the first shift register includes at least part of the shift registers of the second to nth stages in the scan driving circuit, where n represents the total number of stages of the shift registers in the scan driving circuit, and n is an integer greater than 2;

[0011] Optionally, the reset signal is a start signal connected to a trigger signal input terminal of a first-stage shift register in the scan drive circuit;

[0012] Optionally, the first shift register further includes a first-stage shift register in the scan drive circuit;

[0013] Optionally, the first control terminals of the first input modules of a plurality of the first shift registers are connected to the same reset signal.

[0014] Optionally, the first end of the first input module is connected to a first voltage signal, and the second end of the first input module is connected to a control end of the first output module;

[0015] Preferably, the first input module comprises a first transistor, the first transistor is a dual-gate transistor, the first gate of the first transistor is the second control terminal of the first input module, and the second gate of the first transistor is the first control terminal of the first input module;

[0016] Preferably, the first gate of the first transistor is a top gate, and the second gate of the first transistor is a bottom gate.

[0017] Optionally, the first input module includes two transistors connected in parallel, a gate of one of the two transistors is a first control terminal of the first input module, and a gate of the other transistor is a second control terminal of the first input module.

[0018] Optionally, the control end of the second input module is connected to the first clock signal, the first end of the second input module serves as the trigger signal input end of the first shift register, and the second end of the second input module is connected to the control end of the second output module;

[0019] Preferably, the second input module includes a second transistor, a first pole of the second transistor is a first end of the second input module, a gate of the second transistor is a control end of the second input module, and a second pole of the second transistor is a second end of the second input module.

[0020] Optionally, the first shift register further includes: a first output control module and a second output control module, wherein the output end of the first output control module is connected to the control end of the first output module, and the output end of the second output control module is connected to the control end of the second output module;

[0021] Preferably, the first output control module comprises a third transistor, the gate of the third transistor is connected to the second end of the second input module, the first pole of the third transistor is connected to the first clock signal, and the second pole of the third transistor is the output end of the first output control module;

[0022] The second output control module includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the control end of the first output module, the first pole of the fourth transistor inputs a second voltage signal, the second pole of the fourth transistor is connected to the first pole of the fifth transistor, the second pole of the fifth transistor is the output end of the second output control module, and the gate of the fifth transistor is connected to the second clock signal.

[0023] Optionally, the first output module includes a sixth transistor and a first capacitor, the gate of the sixth transistor serves as a control terminal of the first output module, the first electrode of the sixth transistor inputs a second voltage signal, the second electrode of the sixth transistor serves as an output terminal of the first output module, and the first capacitor is connected between the first electrode and the gate of the sixth transistor; and / or,

[0024] The second output module includes a seventh transistor and a second capacitor, the gate of the seventh transistor serves as the control end of the second output module, the first electrode of the seventh transistor is connected to the second clock signal, the second electrode of the seventh transistor serves as the output end of the second output module, and the second capacitor is connected between the second electrode and the gate of the seventh transistor.

[0025] Optionally, the first shift register further includes a protection module, wherein the protection module is connected between the second end of the second input module and the control end of the second output module;

[0026] Preferably, the protection module includes an eighth transistor, a first electrode of the eighth transistor is connected to the output end of the second input module, a second electrode of the eighth transistor is connected to the control end of the second output module, and a gate of the eighth transistor inputs the first voltage signal.

[0027] Optionally, in the plurality of cascaded shift registers, a trigger signal connected to the next stage shift register is provided by a signal output terminal of the previous stage shift register, wherein the trigger signal of the first stage shift register is provided by a start signal line;

[0028] Preferably, in the multiple cascaded shift registers, the first clock signal connected to the odd-numbered shift register and the second clock signal connected to the even-numbered shift register are both provided by the first clock signal line, and the second clock signal of the odd-numbered shift register and the first clock signal of the even-numbered shift register are both provided by the second clock signal line.

[0029] According to another aspect of the present invention, a driving method of a scan driving circuit is provided, which is used to drive the scan driving circuit provided by any embodiment of the present invention;

[0030] The driving method of the scanning driving circuit comprises:

[0031] In the start-up phase of the scan driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output end of the first shift register.

[0032] According to another aspect of the present invention, a display panel is provided, comprising the scan driving circuit provided by any embodiment of the present invention.

[0033] Preferably, the display panel further comprises a first clock signal line, a second clock signal line, a first potential signal line and a second potential signal line;

[0034] The first clock signal line is used to transmit the first clock signal to the odd-numbered shift register, and to transmit the second clock signal to the even-numbered shift register; the second clock signal line is used to transmit the second clock signal to the odd-numbered shift register, and to transmit the first clock signal to the even-numbered shift register; the first potential signal line is used to transmit the first voltage signal to the scanning drive circuit, and the second potential signal line is used to transmit the second voltage signal to the scanning drive circuit.

[0035] The technical solution provided by the embodiment of the present invention controls the first input module in each level of the first shift register to respond to the reset signal when the scan drive circuit is turned on, so that the first output module is turned on to reset the potential of the output end of the first shift register. Compared with the prior art, the technical solution provided by the embodiment of the present invention can reset the output signal of the output end of the first shift register to the first signal when the first-stage shift register is working normally during the start-up phase of the scan drive circuit, so as to ensure the stability and reliability of the output signal of the scan drive circuit, prevent the display brightness of the first frame of the display panel from being abnormal, and help improve the display effect of the display panel. The scan drive circuit provided by this embodiment can be applied to a display panel to provide a gate drive signal to a pixel circuit in the display panel.

[0036] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic diagram of the structure of a scan drive circuit provided by an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of the structure of a shift register provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0043] Figure 6 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0044] Figure 7 A schematic structural diagram of another scan drive circuit provided by an embodiment of the present invention;

[0045] Figure 8 A control timing diagram of a shift register provided by an embodiment of the present invention;

[0046] Fig. 9 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0047] Fig.10 A schematic diagram of the structure of another shift register provided by an embodiment of the present invention;

[0048] Fig.11 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0051] As described in the background technology, the existing scanning drive circuit has the problem of unstable output signal, and it is easy to have abnormal brightness of the first frame of the display panel, which affects the display effect of the display panel. The inventor has found that the reason for the above problem is that the display panel includes a light-emitting device and a pixel circuit that drives the light-emitting device to work, and the pixel circuit includes a driving transistor, a data writing transistor, a transistor for initializing the anode of the light-emitting device, and a transistor for initializing the gate of the driving transistor. The scanning drive circuit composed of a multi-stage shift register can provide a gate drive signal to each transistor in the pixel circuit. The signal output by the existing shift register is transmitted downward step by step. At the first frame moment, the first-stage shift register works normally, but due to the uncertainty of the input signal of the other-stage shift register, the voltage of some nodes in the other-stage shift register is unknown. In the case of residual potential at the node, the voltage of the node changes abnormally, and then the output signal of the shift register is abnormal, causing the pixel circuit to fail to work normally and the display brightness to be abnormal.

[0052] In view of the above problems, an embodiment of the present invention provides a scan driving circuit to solve the problem of abnormal output signals of a shift register. Figure 1 A schematic diagram of the structure of a scan drive circuit provided by an embodiment of the present invention is provided. Figure 2 A schematic diagram of a shift register structure provided by an embodiment of the present invention, referring to Figure 1 and Figure 2The scan driving circuit 10 includes a plurality of cascaded shift registers 100, the plurality of cascaded shift registers 100 include a first shift register 11, the first shift register 11 includes a first input module 101, a second input module 102, a first output module 103 and a second output module 104;

[0053] The first control terminal of the first input module 101 is connected to the reset signal VREF, and the second control terminal of the first input module 101 is connected to the first clock signal SCK1. The first input module 101 is used to control the potential of the control terminal of the first output module 103 according to the reset signal VREF or the first clock signal SCK1; the second input module 102 is used to control the potential of the control terminal of the second output module 104;

[0054] The output end of the first output module 103 and the output end of the second output module 104 are both connected to the output end OUT of the first shift register 11, the first output module 103 is used to output a first signal VC1 according to the potential of its control end, and the second output module 104 is used to output a second signal VC2 different from the first signal VC1 according to the potential of its control end;

[0055] In the start-up phase of the scan driving circuit, the first input module 101 of the first shift register 11 responds to the reset signal VREF, so that the first output module 101 is turned on to reset the potential of the output end of the first shift register 11 .

[0056] Specifically, each shift register 100 is connected in a cascade manner, the output terminal OUT of the first-stage shift register outputs the first-stage drive signal S1, and the first-stage drive signal S1 is input to the trigger signal input terminal IN of the second-stage shift register as the input signal of the second-stage shift register, the second-stage shift register outputs the second-stage drive signal S2, and the second-stage drive signal S2 is input to the trigger signal input terminal IN of the third-stage shift register as the input signal of the third-stage shift register... and so on, until the n-stage shift register outputs the n-stage drive signal Sn; wherein the signal input terminal IN of the first-stage shift register 100 can input the start signal SIN.

[0057] The plurality of cascaded shift registers 100 include a first shift register 11, which is at least a portion of the shift registers in the plurality of cascaded shift registers 100. The first input module 101 in the first shift register 11 can be turned on in response to a reset signal VREF or a first clock signal SCK1 to control the potential of the control end of the first output module 103, that is, to control the potential at the first node N1. Here, as long as at least one of the reset signal VREF and the first clock signal SCK1 is a valid signal (the valid signal is a signal that can turn on the first input module 101), the first input module 101 can be turned on. The reset signal VREF can be connected by the reset end RE of the first shift register 11, and the first clock signal SCK1 can be connected by the first clock signal end SC1 of the first shift register 11.

[0058] The first end of the second input module 102 of the first shift register 11 can be connected to the trigger signal input terminal IN of the first shift register 11, and is used to control the potential of the control terminal of the second output module 104, that is, to control the potential at the second node N2. For example, the second input module 102 can be turned on according to the signal of its control terminal (not shown in the figure), and transmit the signal of its first terminal (for example, the output signal of the previous stage shift register) to the control terminal of the second output module 104, thereby controlling the potential of the control terminal of the second output module 104.

[0059] The output end of the first output module 103 is connected to the output end OUT of the first shift register 11, and is used to output the first signal VC1 when the potential of the first node N1 is turned on. The output end of the second output module 104 is also connected to the output end OUT of the first shift register 11, and is used to output the second signal VC2 when the potential of the second node N2 is turned on. The first signal is different from the second signal, for example, the first signal VC1 is a low level signal, and the second signal VC2 is a high level signal; or the first signal VC1 is a high level signal, and the second signal VC2 is a low level signal.

[0060] In the prior art, when the scan drive circuit is turned on, the first frame scan begins, the first-stage shift register works normally, and the first output module 103 is turned on normally, so the signal at the signal output terminal OUT of the shift register 100 is the first signal VC1. However, the signal at the trigger signal input terminal IN of the other stages of the shift register is unknown, which makes the potential of the second node N2 inaccurate (it may be the residual potential during the previous scan), and the second output module 104 is mis-conducted, transmitting the second signal VC2 to the output terminal OUT of the shift register 100, so that the other stages of the shift register should output the first signal VC1 but instead output the second signal VC2, resulting in abnormal output of the scan drive circuit 10 (such as causing the first row of pixel circuits to be written with data of other rows), resulting in abnormal display brightness.

[0061] In this embodiment, since the first control terminal of the first input module 101 is connected to the reset signal VREF, when the scan drive circuit is turned on, the first-stage shift register 100 works normally and outputs the first signal VC1, and the first input modules 101 of the first shift registers 11 at other stages are turned on at the same time under the action of the reset signal VREF to ensure that the signal output by the output terminal OUT of the first shift register 11 is the first signal VC1, thereby forcibly resetting the potential at the second node N2 to the level corresponding to the first signal VC1, ensuring the off-state effect of the second output module 104, and further ensuring that the output signals of the first shift register 11 are all the first signals, and the pixel circuits of the corresponding rows can work normally, thereby solving the problem of abnormal display brightness in the first frame.

[0062] The scanning drive circuit provided in the embodiment of the present invention controls the first input module in the first shift register to respond to the reset signal when the scanning drive circuit is turned on, so that the first output module is turned on, so as to reset the potential of the output end of the first shift register. Compared with the prior art, the technical solution provided in the embodiment of the present invention can reset the output signal of the output end of the first shift register to the first signal when the first-stage shift register is working normally during the start-up phase of the scanning drive circuit, so that the second output module will not be mis-conducted, so as to ensure the stability and reliability of the output signal of the scanning drive circuit.

[0063] The scan drive circuit provided in this embodiment can be applied to a display panel to provide a gate drive signal to a pixel circuit in the display panel. In the start-up phase of the scan drive circuit, the gate drive signal is written to the gate of the data write transistor in the pixel circuit by the scan drive circuit, so that the data write transistor is turned off, ensuring that the pixel circuit of the corresponding row will not write the data voltage of other rows, thereby preventing the display brightness of the first frame of the display panel from being abnormal, which is conducive to improving the display effect of the display panel.

[0064] Optionally, continue to refer to Figure 1 and Figure 2 In this embodiment, the first shift register 11 includes at least part of the shift registers in the second to n-th stages of the scan drive circuit, n represents the total number of shift registers 100 in the scan drive circuit, and n is an integer greater than 2. In other words, in a plurality of cascaded shift registers 100, at least part of the shift registers in the second to n-th stages 100 are first shift registers 11. As a preferred implementation of this embodiment, the shift registers in the second to n-th stages can all be first shift registers 11, so that in the start-up phase of the scan drive circuit, the potentials of the output terminals OUT of the second to n-th stages of the shift registers are reset to the level corresponding to the first signal VC1, so that the second output modules 104 in the shift registers will not be mis-turned on, which is beneficial to improving the reliability of the entire scan drive circuit.

[0065] Optionally, in this embodiment, since the first-stage shift register is in a normal working state when the scan driving circuit 10 is turned on, the signal outputted by its output terminal OUT is the first signal VC1, and therefore the first-stage shift register may not be connected to the reset signal VREF. Of course, the first-stage shift register in the scan driving circuit may also be the first shift register 11, so that the first-stage shift register can also control the signal at the output terminal OUT to be the first signal VC1 through the action of the reset signal VREF, thereby preventing the first-stage shift register from having an abnormal output due to the inaccuracy of the first clock signal SCK1.

[0066] Further, the trigger signal input terminal IN of the first-stage shift register 100 can input the start signal SIN. Except for the first stage, the signals input to the trigger signal input terminals IN of the other stages of the shift register 100 are all output signals of the output terminals OUT of the previous stage of the shift register 100. Among them, the start signal SIN is a screen signal on the display panel. In this embodiment, the reset signal VREF can be the start signal SIN, and the reset signal connected to the first control terminal of the first input module 101 of the plurality of first shift registers 11 is the same signal (such as all the start signal SIN), thereby reducing the number of signals of the shift register 100, which is conducive to realizing a narrow frame of the display panel.

[0067] It should be noted that the reset signal can be the starting signal connected to the trigger signal input terminal of the first-stage shift register in the scan driving circuit, or it can be a signal other than the starting signal connected to the trigger signal input terminal of the first-stage shift register. For example, the reset signal can be the same signal as the starting signal, which is not specifically limited here.

[0068] Figure 3 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 3On the basis of the above technical solutions, the first end of the first input module 101 is connected to the first voltage signal VGL, and the second end of the first input module 101 is connected to the control end of the first output module 103. The first end of the first input module 101 is the input end, and the second end of the first input module 101 is the output end of the first input module 101. The first input module 101 is turned on under the action of the reset signal VREF or the first clock signal SCK1, and transmits the first voltage signal VGL to the control end of the first output module 103. At this time, the potential at the first node N1 is the level corresponding to the first voltage signal VGL.

[0069] Optionally, the first input module 101 includes a first transistor M1, which is a dual-gate transistor, wherein the first gate of the first transistor M1 is connected to the first clock signal SCK1, the second gate is input with a reset signal VREF, the first electrode is input with a first voltage signal VGL, and the second electrode is connected with the control end of the first output module 103. The first electrode of the first transistor M1 is one of a source and a drain, and the second electrode of the first transistor M1 is the other of a source and a drain.

[0070] In this embodiment, the input end of the first output module 103 can be connected to the second voltage signal VGH, and the second voltage signal VGH is a high level signal. Take the first transistor M1 as a P-channel transistor as an example, wherein, when the scan drive circuit 10 is turned on, the first clock signal SCK1 is low level, the reset signal VREF is the start signal SIN, and the start signal SIN is low level at this time. Under the control of the start signal SIN, the first transistor M1 of each first shift register 11 is in a conducting state, and the first voltage signal VGL is transmitted to the control end of the first output module 103, that is, the potential of the first node N1 is the level corresponding to the first voltage signal VGL. The first output module 103 is turned on according to the first voltage signal VGL to transmit the second voltage signal VGH to the output end OUT, that is, the first signal VC1 output by the first output module 103 to the output end OUT of the first shift register 11 is high level (corresponding to the second voltage signal VGH). Then the signal input to the trigger signal input terminal IN of the next-stage shift register is also high level (second voltage signal VGH), and the second input module 102 is turned on by the signal at its control terminal, and the second voltage signal VGH is transmitted to the control terminal of the second output module 104, that is, the potential of the second node N2 is reset to the second voltage signal VGH, and the second output module 104 is turned off to ensure that the output signals of each first shift register 11 are all high level at this time, thereby ensuring the reliability of the output signal of the scanning drive circuit 10 in the first frame.

[0071] Preferably, in this embodiment, the first transistor M1 is a vertical dual-gate transistor, the first gate of the first transistor M1 is a top gate, the second gate of the first transistor M1 is a bottom gate, and the second gates of the first transistors M1 of the first shift registers 11 of each stage are connected in parallel and directly connected to the start signal input terminal on the display panel. The start signal terminal is used to input the start signal SIN.

[0072] Figure 4 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 4 On the basis of the above technical solutions, optionally, the control end of the second input module 102 is connected to the first clock signal SCK1, the first end of the second input module 102 is used as the trigger signal input end IN of the first shift register 11, and the second end of the second input module 102 is connected to the control end of the second output module 104. Specifically, the second input module 102 includes a second transistor M2, the first pole of the second transistor M2 is the first end of the second input module 102, the gate of the second transistor M2 is the control end of the second input module 102, and the second pole of the second transistor M2 is the second end of the second input module 102.

[0073] When the first shift register 11 of the previous stage outputs a high level, the signal input to the trigger signal input terminal IN of the next stage shift register is also a high level, and the second transistor M2 is turned on by the first clock signal SCK1 at its control terminal, and the second voltage signal VGH is transmitted to the control terminal of the second output module 104, that is, the potential of the second node N2 is reset to the second voltage signal VGH, and the second output module 104 is turned off.

[0074] Figure 5 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 5 On the basis of the above technical solutions, optionally, the first shift register 11 further includes a first output control module 105 and a second output control module 106, wherein the output end of the first output control module 105 is connected to the control end of the first output module 103, and the output end of the second output control module 106 is connected to the control end of the second output module 104. The control end of the first output control module 105 and the second end of the second input module 102 are connected to the third node N3.

[0075] Figure 6 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Figure 6Specifically, the first output control module 105 includes a third transistor M3, the gate of the third transistor M3 is connected to the second end of the second input module 102, the first electrode of the third transistor M3 is connected to the first clock signal SCK1, and the second electrode of the third transistor M3 is the output end of the first output control module 105. The second output control module 106 includes a fourth transistor M4 and a fifth transistor M5, the gate of the fourth transistor M4 is connected to the control end of the first output module 103, the first electrode of the fourth transistor M4 inputs the second voltage signal VGH, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5, the second electrode of the fifth transistor M5 is the output end of the second output control module 106, and the gate of the fifth transistor M5 is connected to the second clock signal SCK2.

[0076] In this embodiment, the gate of the second transistor M2 is connected to the first clock signal SCK1, the first electrode of the second transistor M2 is connected to the trigger signal input terminal IN, the second electrode of the second transistor M2 is connected to the control terminal of the second output module 104, the gate of the third transistor M3 is connected to the second electrode of the second transistor M2, the first electrode of the third transistor M3 is connected to the first clock signal SCK1, the second electrode of the third transistor M3 is connected to the control terminal of the first output module 103, the gate of the fourth transistor M4 is connected to the control terminal of the first output module 103, the first electrode of the fourth transistor M4 inputs the second voltage signal VGH, the second electrode of the fourth transistor M4 is connected to the first electrode of the fifth transistor M5, the second electrode of the fifth transistor M5 is connected to the second electrode of the second transistor M2, and the gate of the fifth transistor M5 is connected to the second clock signal terminal SCK2. Among them, the input end of the first output module 103 inputs the second voltage signal VGH, and the output end of the first output module 103 is connected to the output end OUT of the first shift register 11; the input end of the second output module 104 is connected to the second clock signal SCK2, and the output end of the second output module 104 is connected to the output end OUT of the first shift register 11.

[0077] Continue to refer Figure 6The first output module 103 includes a sixth transistor M6 and a first capacitor C1. The gate of the sixth transistor M6 is connected to the second end of the first input module 101 as the control end of the first output module 103. The first electrode of the sixth transistor M6 inputs the second voltage signal VGH. The second electrode of the sixth transistor M6 serves as the output end of the first output module 103. The first capacitor C1 is connected between the first electrode and the gate of the sixth transistor M6. The second output module 104 includes a seventh transistor M7 and a second capacitor C2. The gate of the seventh transistor M7 is connected to the second electrode of the second transistor M2 as the control end of the second output module 104. The first electrode of the seventh transistor M7 is connected to the second clock signal SCK2. The second electrode of the seventh transistor M7 serves as the output end of the second output module 104. The second capacitor C2 is connected between the second electrode and the gate of the seventh transistor M7.

[0078] It should be noted that this embodiment is described by taking P-type transistors as an example. In other embodiments, each transistor may also be an N-type transistor.

[0079] Figure 7 A schematic diagram of another scanning driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 7 , the trigger signal input terminal IN of the next stage shift register 100 is connected to the output terminal OUT of the previous stage shift register 100, wherein the trigger signal input terminal IN of the first stage shift register 100 inputs the start signal SIN. Here, the start signal SIN can be provided by the start signal line, and each stage shift register 100 is the first shift register 11.

[0080] In the present embodiment, in a plurality of cascaded shift registers 100, the first clock signal SCK1 connected to the odd-numbered shift register and the second clock signal SCK2 connected to the even-numbered shift register are both provided by the first clock signal line CLK1, and the second clock signal SCK2 connected to the odd-numbered shift register and the first clock signal SCK1 connected to the even-numbered shift register are both provided by the second clock signal line CLK2. In other words, the first clock signal terminal SC1 of the odd-numbered shift register and the second clock signal terminal SC2 of the even-numbered shift register are both connected to the first clock signal line CLK1, and the second clock signal terminal SC2 of the odd-numbered shift register and the first clock signal terminal SC1 of the even-numbered shift register are both connected to the second clock signal line CLK2, so as to realize the shift output of the scan driving circuit 10.

[0081] Figure 8 A control timing diagram of a shift register provided in an embodiment of the present invention is applicable to Figure 6 The shift register shown, combined with Figures 6 to 8The working process of the shift register provided in this embodiment at least includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5. The first voltage signal VGL and the second voltage signal VGH are mutually inverse signals. In this embodiment, the first voltage signal VGL is a low level signal, and the second voltage signal VGH is a high level signal.

[0082] In the first stage t1, the start signal SIN input to the reset terminal RE of the shift register 100 is at a low level, the first clock signal SCK1 input to the first clock signal terminal SC1 is at a low level, and the second clock signal SCK2 input to the second clock signal terminal SC2 is at a high level, so the first transistor M1 and the second transistor M2 are turned on, the first voltage signal VGL is transmitted to the gate of the sixth transistor M6 through the first transistor M1, the sixth transistor M6 is turned on, and the second voltage signal VGH is transmitted to the output terminal OUT of the shift register 100, and the output terminal OUT outputs a high level. The signal input to the trigger signal input terminal IN is transmitted to the gate of the seventh transistor M7 through the second transistor M2. When the shift register 100 is a first-stage shift register 100, the start signal SIN is input to the signal input terminal IN, and the seventh transistor M7 is turned on, and the high level of the second clock signal SCK2 (the same as the second voltage signal VGH) is transmitted to the output terminal OUT, and the output terminal OUT outputs a high level. When the shift register 100 is a shift register of other stages except the first stage, the trigger signal input terminal IN inputs the output signal of the previous stage shift register 100. Since the start signal SIN is at a low level, the first transistor M1 is in the on state, and the output terminal OUT of the shift register 100 is at a high level. The seventh transistor M7 is turned off, so the output terminal OUT still outputs a high level.

[0083] It should be noted that the subsequent stages are described by taking the first-stage shift register as an example.

[0084] In this embodiment, since the first transistor M1 of each stage of the shift register 100 is turned on when the start signal SIN is at a low level (i.e., at the first frame moment), the first node N1 (i.e., the gate of the sixth transistor M6) is reset to the first voltage signal VGL to control the output terminal OUT of each stage of the shift register 100 to output the second voltage signal VGH.

[0085] In the second stage t2, the start signal SIN input to the reset terminal RE of the shift register 100 is high, the first clock signal SCK1 input to the first clock signal terminal SC1 is high, and the second clock signal SCK2 input to the second clock signal terminal SC2 is low. Due to the storage function of the second capacitor C2, the second node N2 maintains a low level, and the third node N3 is also low. The third transistor M3 is turned on, and the high-level first clock signal SCK1 is transmitted to the first node N1, and the sixth transistor M6 is turned off. Under the potential control of the second node N2, the seventh transistor M7 is turned on, and the low level of the second clock signal SCK2 is transmitted to the output terminal OUT, so that the output signal potential of the shift register 100 becomes low. Under the bootstrap effect of the second capacitor C2, the potential of the gate of the seventh transistor M7 (i.e., the second node N2) is pulled to a lower level, and the seventh transistor M7 continues to be turned on, so the signal output by the output terminal OUT is low.

[0086] In the third stage t3, the start signal SIN inputted by the reset terminal RE of the shift register 100 is at a high level, the first clock signal SCK1 inputted by the first clock signal terminal SC1 is at a low level, and the second clock signal SCK2 inputted by the second clock signal terminal SC2 is at a high level, so the second transistor M2 and the first transistor M1 are turned on, the potential of the first node N1 becomes a low level (the first voltage signal VGL), and the potential of the second node N2 becomes a high level (the high level of the start signal SIN). Under the potential control of the first node N1, the sixth transistor M6 is turned on, and the second voltage signal VGH is transmitted to the output terminal OUT, and the signal outputted by the output terminal OUT is at a high level. At this time, the seventh transistor M7 is in an off state under the potential control of the second node N2.

[0087] In the fourth stage t4, the start signal SIN inputted by the reset terminal RE of the shift register 100 is at a high level, the first clock signal SCK1 inputted by the first clock signal terminal SC1 is at a high level, the second clock signal SCK2 inputted by the second clock signal terminal SC2 is at a low level, and under the action of the first capacitor C1, the potential of the first node N1 is maintained at a low level, and the fourth transistor M4 and the sixth transistor M6 are turned on. At the same time, under the control of the low-level second clock signal SCK2, the fifth transistor M5 is turned on, the second voltage signal VGH is transmitted to the third node N3 through the fourth transistor M4 and the fifth transistor M5, the seventh transistor M7 is turned off, and the signal outputted by the output terminal OUT is maintained at a high level.

[0088] In the fifth stage t5, the start signal SIN inputted by the reset terminal RE of the shift register 100 is at a high level, the first clock signal SCK1 inputted by the first clock signal terminal SC1 is at a low level, the second clock signal SCK2 inputted by the second clock signal terminal SC2 is at a high level, the first transistor M1 and the second transistor M2 are turned on, and the second node N2 maintains a high level, so the seventh transistor M7 is still in the off state. Since the first transistor M1 is turned on, the potential of the first node N1 is at a low level, the sixth transistor M6 is turned on, and the signal outputted by the output terminal OUT is at a high level.

[0089] After the above five stages, the signal output of the first-stage shift register 100 is realized. It should be noted that, since there are multiple stages of shift registers 100 in the scan drive circuit 10, the output signal of the previous stage shift register 100 can be used as the input signal of the next stage shift register 100, thereby realizing the step-by-step shift transmission of the output signal, and the working process of the other stages of the shift register 100 can refer to the above related description, which will not be repeated here.

[0090] It should be noted that the first clock signal and the second clock signal connected to the odd-numbered shift register 100 are opposite to those connected to the even-numbered shift register 100. The above five stages can be the working stages of the odd-numbered shift register, such as the working stages of the first-level shift register. The five stages of the even-numbered shift register are briefly described below by taking the second-level shift register as an example. The trigger signal input terminal IN of the second-level shift register is connected to the signal output by the output terminal OUT of the first-level shift register, and the signal output by the output terminal OUT of the first-level shift register is, for example, Figure 8 The signal output from the output terminal OUT is shown.

[0091] In the first stage t1, the trigger signal input terminal IN of the shift register is connected to a high level, the first clock signal SCK1 input to the first clock signal terminal SC1 is a high level, and the second clock signal SCK2 input to the second clock signal terminal SC2 is a low level, so the first transistor M1 and the second transistor M2 are disconnected. In addition, the gate of the first transistor M1 is connected to a reset signal, and taking the reset signal as the start signal SIN as an example, the start signal SIN is a low level, so the first transistor M1 and the sixth transistor M6 are in a conducting state, and the output terminal OUT of the shift register is a high level.

[0092] In the second stage t2, the trigger signal input terminal IN of the shift register is connected to a low level, the first clock signal SCK1 inputted by the first clock signal terminal SC1 is a low level, and the second clock signal SCK2 inputted by the second clock signal terminal SC2 is a high level, so the first transistor M1 and the second transistor M2 are turned on, and the first node N1 and the second node N2 are both low levels. The second voltage signal VGH is transmitted to the output terminal OUT of the shift register, and the seventh transistor M7 is turned on, transmitting the high level of the second clock signal SCK2 (the same as the second voltage signal VGH) to the output terminal OUT, and the output terminal OUT outputs a high level.

[0093] In the third stage t3, the trigger signal input terminal IN of the shift register is connected to a high level, the first clock signal SCK1 input by the first clock signal terminal SC1 is a high level, and the second clock signal SCK2 input by the second clock signal terminal SC2 is a low level, so the second transistor M2 and the first transistor M1 are disconnected. Due to the storage effect of the second capacitor C2, the second node N2 maintains a low level, then the third node N3 is a low level, the third transistor M3 is turned on, and the high-level first clock signal SCK1 is transmitted to the first node N1, and the sixth transistor M6 is turned off. Under the potential control of the second node N2, the seventh transistor M7 is turned on, and the low level of the second clock signal SCK2 is transmitted to the output terminal OUT, so that the output signal potential of the shift register 100 becomes low. Under the bootstrap effect of the second capacitor C2, the potential of the gate of the seventh transistor M7 (i.e., the second node N2) is pulled to a lower level, and the seventh transistor M7 continues to be turned on, so the signal output by the output terminal OUT is a low level.

[0094] In the fourth stage t4, the trigger signal input terminal IN of the shift register is connected to a high level, the first clock signal SCK1 input by the first clock signal terminal SC1 is a low level, and the second clock signal SCK2 input by the second clock signal terminal SC2 is a high level, so the second transistor M2 and the first transistor M1 are turned on, the potential of the first node N1 becomes a low level (the first voltage signal VGL), and the potential of the second node N2 becomes a high level (the high level of the start signal SIN). Under the potential control of the first node N1, the sixth transistor M6 is turned on, and the second voltage signal VGH is transmitted to the output terminal OUT, and the signal output by the output terminal OUT is a high level. At this time, the seventh transistor M7 is in an off state under the potential control of the second node N2.

[0095] In the fifth stage t5, the trigger signal input terminal IN of the shift register is connected to a high level, the first clock signal SCK1 input by the first clock signal terminal SC1 is a high level, and the second clock signal SCK2 input by the second clock signal terminal SC2 is a low level. Under the action of the first capacitor C1, the potential of the first node N1 is maintained at a low level, and the fourth transistor M4 and the sixth transistor M6 are turned on.

[0096] At the same time, under the control of the low-level second clock signal SCK2, the fifth transistor M5 is turned on, the second voltage signal VGH is transmitted to the third node N3 through the fourth transistor M4 and the fifth transistor M5, the seventh transistor M7 is turned off, and the signal output by the output terminal OUT maintains a high level.

[0097] After the above five stages, the signal output of the second stage shift register is realized. The signal output of the even-numbered stage shift register is similar to the signal output of the second stage shift register, and will not be repeated here.

[0098] Fig. 9 A schematic diagram of another shift register structure provided by an embodiment of the present invention, referring to Fig. 9 On the basis of the above technical solution, optionally, the shift register 100 further includes a protection module 107 , and the protection module 107 is connected between the output end of the second input module 102 and the control end of the second output module 104 .

[0099] Specifically, the protection module 107 includes an eighth transistor M8, a first electrode of the eighth transistor M8 is connected to the second end of the second input module 102, a second electrode of the eighth transistor M8 is connected to the control end of the second output module 104, and a gate of the eighth transistor M8 inputs the first voltage signal VGL. That is, the eighth transistor M8 is connected between the second node N2 and the third node N3, and the eighth transistor M8 can be in a normally-on state in response to the first voltage signal VGL. By setting the eighth transistor M8, the extremely low potential of the gate of the seventh transistor M7 can be prevented from being transmitted to the third node N3 in the second stage t2, thereby affecting the normal operation of the shift register 100.

[0100] Optionally, the first input module 101 includes two transistors connected in parallel, a gate of one of the two transistors is a first control terminal of the first input module 101 , and a gate of the other transistor is a second control terminal of the first input module 101 .

[0101] Fig.10 It is shown that the first input module 101 has two control terminals by connecting two transistors in parallel. Fig.10 The first input module 101 includes a first transistor M1, which is two transistors connected in parallel. The first electrodes of the two transistors are electrically connected and serve as the first end of the first input module, and the second electrodes of the two transistors are electrically connected and serve as the second end of the first input module.

[0102] Optionally, an embodiment of the present invention further provides a driving method of a scan driving circuit, which is applicable to the scan driving circuit provided by any of the above embodiments. Figure 1 and Figure 2 As shown, the scan drive circuit 10 includes a plurality of cascaded shift registers 100, the plurality of cascaded shift registers 100 include a first shift register 11, the first shift register 11 includes a first input module 101, a second input module 102, a first output module 103 and a second output module 104; a first control end of the first input module 101 is connected to a reset signal VREF, a second control end of the first input module 101 is connected to a first clock signal SCK1, the first input module 101 is used to control the potential of the control end of the first output module 103 according to the reset signal VREF or the first clock signal SCK1; the second input module 102 is used to control the potential of the control end of the second output module 104; the output end of the first output module 103 and the output end of the second output module 104 are both connected to the output end OUT of the first shift register 11, the first output module 103 is used to output a first signal VC1 according to the potential of its control end, and the second output module 104 is used to output a second signal VC2 different from the first signal VC1 according to the potential of its control end.

[0103] The driving method of the scan driving circuit includes:

[0104] In the start-up phase of the scan driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output end of the first shift register.

[0105] The driving method of the scanning driving circuit provided by the embodiment of the present invention controls the first input module in each level of the first shift register to respond to the reset signal when the scanning driving circuit is turned on, so that the first output module is turned on, so as to reset the potential of the output end of the first shift register. Compared with the prior art, the technical solution provided by the embodiment of the present invention can reset the output signal of the signal output end of the first shift register to the first signal during the start-up phase of the scanning driving circuit, so that the second output module will not be mis-conducted, so as to ensure the stability and reliability of the output signal of the scanning driving circuit.

[0106] The scan drive circuit provided in this embodiment can be applied to a display panel to provide a gate drive signal to a pixel circuit in the display panel. In the start-up phase of the scan drive circuit, the gate drive signal is written to the gate of the data write transistor in the pixel circuit by the scan drive circuit, so that the data write transistor is turned off, ensuring that the pixel circuit of the corresponding row will not write the data voltage of other rows, thereby preventing the display brightness of the first frame of the display panel from being abnormal, which is conducive to improving the display effect of the display panel.

[0107] Optionally, an embodiment of the present invention further provides a display panel, Fig.11 A schematic diagram of a display panel according to an embodiment of the present invention is provided. Fig.11 , the display panel includes the scan driving circuit provided by any embodiment of the present invention.

[0108] Furthermore, the display panel may also include a first clock signal line CLK1, a second clock signal line CLK2, a first potential signal line V1, and a second potential signal line V2; the first clock signal line CLK1 is used to transmit a first clock signal SCK1 to an odd-numbered shift register, and to transmit a second clock signal SCK2 to an even-numbered shift register. The second clock signal line CLK2 is used to transmit a second clock signal SCK2 to an odd-numbered shift register, and to transmit a first clock signal SCK1 to an even-numbered shift register. The first potential signal line V1 is used to transmit a first voltage signal VGL to the scan drive circuit 10, and the second potential signal line V2 is used to transmit a second voltage signal VGH to the scan drive circuit 10.

[0109] Furthermore, the display panel may also include a scan line, the signal output terminal OUT of the shift register 100 is connected to the scan line, and the signal (S1, S2...Sn) output by the output terminal OUT of the shift register 100 is used as a scan signal; preferably, the display panel also includes a pixel circuit 200, the pixel circuit 200 includes a driving transistor, a data writing transistor and a light emitting diode, the data writing transistor is used to transmit the data voltage to the gate of the driving transistor, the driving transistor is used to drive the light emitting diode to emit light according to the data voltage, and the gate of the data writing transistor is connected to the scan line. The specific structure of the pixel circuit 200 can refer to the relevant description in the prior art, and this embodiment does not impose any limitation on this.

[0110] When the scanning driving circuit provided by any of the above embodiments is applied to a display panel, a gate driving signal can be provided to the pixel circuit 200 in the display panel. In the first frame stage (i.e., the scanning driving circuit is turned on stage), the gate driving signal is written to the gate of the data writing transistor in the pixel circuit 200 by the scanning driving circuit, so that the data writing transistor is effectively turned off, ensuring that the pixel circuit of the corresponding row will not write the data voltage of other rows, thereby preventing the display brightness of the first frame of the display panel from being abnormal, which is conducive to improving the display effect of the display panel.

[0111] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document is not limited here. The connection described in the present invention can refer to an electrical connection.

[0112] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A scanning driving circuit, comprising a plurality of cascaded shift registers, characterized in that, the plurality of cascaded shift registers include a first shift register, and the first shift register includes a first input module, a second input module, a first output module and a second output module; a first control terminal of the first input module is connected to a reset signal, a second control terminal of the first input module is connected to a first clock signal, and the first input module is configured to control a potential of a control terminal of the first output module according to the reset signal or the first clock signal; the second input module is configured to control a potential of a control terminal of the second output module; output terminals of the first output module and the second output module are both connected to an output terminal of the first shift register, the first output module is configured to output a first signal according to the potential of its control terminal, and the second output module is configured to output a second signal according to the potential of its control terminal; wherein, in an enabling stage of the scanning driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output terminal of the first shift register, and output signals of all the first shift registers are the first signal; the first shift register includes at least some of the shift registers from the second stage to the nth stage in the scanning driving circuit, n represents a total number of stages of the shift registers in the scanning driving circuit, and n is an integer greater than 2; the reset signal is a start signal inputted to a trigger signal input terminal of the first-stage shift register in the scanning driving circuit; the first shift register further includes the first-stage shift register in the scanning driving circuit; first control terminals of the first input modules of the plurality of first shift registers are connected to the same reset signal.

2. The scanning driving circuit according to claim 1, characterized in that, a first terminal of the first input module is connected to a first voltage signal, and a second terminal of the first input module is connected to a control terminal of the first output module; the first input module includes a first transistor, the first transistor is a double-gate transistor, a first gate of the first transistor is the second control terminal of the first input module, a second gate of the first transistor is the first control terminal of the first input module, a first pole of the first transistor is the first terminal of the first input module, and a second pole of the first transistor is the second terminal of the first input module; the first gate of the first transistor is a top gate, and the second gate of the first transistor is a bottom gate.

3. The scanning driving circuit according to claim 1, characterized in that, the first input module includes two transistors connected in parallel, a gate of one of the two transistors is the first control terminal of the first input module, and a gate of the other transistor is the second control terminal of the first input module.

4. The scanning driving circuit according to claim 1, characterized in that, The control terminal of the second input module is connected to the first clock signal, the first terminal of the second input module serves as the trigger signal input terminal of the first shift register, and the second terminal of the second input module is connected to the control terminal of the second output module; The second input module includes a second transistor. The first pole of the second transistor is the first terminal of the second input module, the gate of the second transistor is the control terminal of the second input module, and the second pole of the second transistor is the second terminal of the second input module.

5. The scan driving circuit according to claim 1, characterized in that, The first shift register further includes: a first output control module and a second output control module. The output terminal of the first output control module is connected to the control terminal of the first output module, and the output terminal of the second output control module is connected to the control terminal of the second output module; The first output control module includes a third transistor. The gate of the third transistor is connected to the second terminal of the second input module, the first pole of the third transistor is connected to the first clock signal, and the second pole of the third transistor is the output terminal of the first output control module; The second output control module includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is connected to the control terminal of the first output module, the first pole of the fourth transistor inputs a second voltage signal, the second pole of the fourth transistor is connected to the first pole of the fifth transistor, the second pole of the fifth transistor is the output terminal of the second output control module, and the gate of the fifth transistor is connected to the second clock signal.

6. The scan driving circuit according to claim 1, characterized in that, The first output module includes a sixth transistor and a first capacitor. The gate of the sixth transistor serves as the control terminal of the first output module, the first pole of the sixth transistor inputs a second voltage signal, the second pole of the sixth transistor serves as the output terminal of the first output module, and the first capacitor is connected between the first pole and the gate of the sixth transistor; and / or, The second output module includes a seventh transistor and a second capacitor. The gate of the seventh transistor serves as the control terminal of the second output module, the first pole of the seventh transistor is connected to the second clock signal, the second pole of the seventh transistor serves as the output terminal of the second output module, and the second capacitor is connected between the second pole and the gate of the seventh transistor.

7. The scan driving circuit according to claim 1, characterized in that, In the plurality of cascaded shift registers, the trigger signal accessed by the next-stage shift register is provided by the signal output terminal of the previous-stage shift register, and the trigger signal of the first-stage shift register is provided by the start signal line; In the plurality of cascaded shift registers, the first clock signal accessed by the odd-stage shift registers and the second clock signal accessed by the even-stage shift registers are both provided by the first clock signal line, and the second clock signal accessed by the odd-stage shift registers and the first clock signal accessed by the even-stage shift registers are both provided by the second clock signal line.

8. A driving method for a scanning driving circuit, characterized in that, the driving method is used to drive the scanning driving circuit according to any one of claims 1-7; the driving method of the scanning driving circuit includes: in the opening stage of the scanning driving circuit, the first input module of the first shift register responds to the reset signal, so that the first output module is turned on to reset the potential of the output end of the first shift register.

9. A display panel, characterized in that, it includes the scanning driving circuit according to any one of claims 1-7; the display panel further includes a first clock signal line, a second clock signal line, a first potential signal line and a second potential signal line; the first clock signal line is used to transmit a first clock signal to the odd-stage shift register and a second clock signal to the even-stage shift register; the second clock signal line is used to transmit a second clock signal to the odd-stage shift register and a first clock signal to the even-stage shift register; the first potential signal line is used to transmit a first voltage signal to the scanning driving circuit, and the second potential signal line is used to transmit a second voltage signal to the scanning driving circuit.

Images