Method of manufacturing an inner wall, method of manufacturing a device, device, and apparatus

Abstract

This invention provides a method for fabricating an inner wall, comprising: providing a substrate; forming alternating stacked sacrificial layers and channel layers on the substrate; etching the sacrificial layers, channel layers, and substrate to form a plurality of fin structures arranged along a first direction; forming a plurality of dummy gate structures arranged along a second direction; etching each fin structure to form a plurality of source / drain cavities; etching both ends of the sacrificial layer in each fin structure along the second direction to form an inner wall cavity; selectively growing a dielectric material based on the sacrificial layers to form the inner wall; filling the inner wall cavity with the dielectric material; and epitaxially growing source / drain layers in the source / drain cavities. The technical solution provided by this invention solves the problem of unavoidable etching-related damage by selectively growing a dielectric material on the surface of the sacrificial layer, thereby reducing associated damage.

Description

Technical Field

[0001] This invention relates, and more particularly to a method for manufacturing an inner wall, a method for preparing a device, a device, and an apparatus. Background Technology

[0002] In the fabrication process of gate-around transistor devices, for the advanced process node of inner sidewall technology, the current proposed fabrication of inner sidewalls in gate-around transistor devices requires two steps: depositing dielectric material and etching dielectric material. However, the etching process of dielectric material is prone to causing collateral damage, and the etching thickness of dielectric material is difficult to control accurately.

[0003] Therefore, developing a new manufacturing process for forming the inner sidewall has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0004] This invention provides a method for fabricating an inner wall, a method for preparing a device, a device, and an apparatus to solve the problem of unavoidable damage caused by etching.

[0005] According to a first aspect of the present invention, a method for manufacturing an inner wall is provided, the method comprising:

[0006] A substrate is provided; said substrate having alternately stacked sacrificial layers and channel layers formed thereon;

[0007] The sacrificial layer, the trench layer, and the substrate are etched to form a plurality of fin structures arranged along a first direction; and shallow trench isolation structures are formed between adjacent plurality of fin structures.

[0008] A plurality of dummy gate structures are formed along a second direction; the dummy gate structures are located on the plurality of fin structures, and each dummy gate structure spans each of the plurality of fin structures;

[0009] Etching each of the fin structures forms several source / leak cavities;

[0010] Etch both ends of the sacrificial layer in each of the fin structures along the second direction to form an inner wall cavity;

[0011] A dielectric material is selectively grown based on the sacrificial layer to form an inner wall; the dielectric material fills the cavity of the inner wall.

[0012] An epitaxial source / drain layer is formed in the source / drain cavity.

[0013] Optionally, the thickness of the inner wall along the second direction is controlled by the time for growing the dielectric material.

[0014] Optionally, the dielectric material is made of a precursor material.

[0015] Optionally, the precursor material is a silicon-based, aluminum-based, or hafnium-based material.

[0016] Optionally, the sacrificial layer is made of SiGe.

[0017] Optionally, before growing the dielectric material based on the sacrificial layer, the method further includes: performing a surface treatment on the surface of the sacrificial layer.

[0018] Optionally, the surface treatment may be performed using a dry method, a wet method, an oxidation method, or a reduction method.

[0019] According to a second aspect of the present invention, a method for fabricating a semiconductor device is also provided, including the method for fabricating an inner sidewall as described in the first aspect of the present invention.

[0020] According to a third aspect of the present invention, a semiconductor device is also provided, which is prepared by a method for preparing a semiconductor device according to a second aspect of the present invention.

[0021] According to a fourth aspect of the present invention, an electronic device is also provided, comprising the semiconductor device described in the third aspect of the present invention.

[0022] The present invention provides a method for manufacturing an inner wall, which selectively fills the cavity of the inner wall with a dielectric material, thereby completing the preparation of the inner wall in one step; without the need for an etching process, it solves the problem of unavoidable damage caused by etching, thereby reducing the damage caused by etching.

[0023] Furthermore, since the selective growth time of the dielectric material can be precisely controlled, and the thickness of the inner wall depends on the selective growth time of the dielectric material, the thickness of the inner wall can be precisely controlled, thus solving the problem of the inability to precisely control the thickness of the inner wall. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of an embodiment of the present invention for a method of manufacturing an inner wall;

[0026] Figure 2 This is a schematic diagram of a device structure prepared according to the inner wall fabrication method provided in an embodiment of the present invention. Figure 1 ;

[0027] Figure 3 This is a schematic diagram of a device structure fabricated according to an embodiment of the present invention using an inner wall fabrication method. Figure 2 ;

[0028] Figure 4 This is a schematic diagram of a device structure fabricated according to an embodiment of the present invention using an inner wall fabrication method. Figure 3 ;

[0029] Explanation of reference numerals in the attached figures:

[0030] 101-Substrate;

[0031] 102-channel layer;

[0032] 103 - Sacrificial Layer;

[0033] 104-Dummy gate structure;

[0034] 105-spacer layer;

[0035] 106 - Inner wall;

[0036] 107-Source / Drain Layer. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] The traditional process steps for fabricating the inner wall in a gate-around transistor are as follows:

[0040] 1. After forming the dummy gate, etch the fin structure of the source / drain region to form the source / drain cavity;

[0041] 2. The sacrificial layer of the etched fin structure is close to the source / drain region, forming an inner wall cavity;

[0042] 3. Depositing an isolation layer material on the surface of a gate-around transistor device;

[0043] 4. Etch the isolation layer material outside the inner wall cavity so that the remaining isolation layer material in the inner wall cavity forms an inner wall; thereby isolating the source / drain area and the dummy gate through the inner wall;

[0044] 5. Epitaxially grow source and / or drain electrodes outside the source / drain region; further, isolate the source and / or drain electrodes from the subsequently formed gate electrode through an inner sidewall; thereby reducing parasitic capacitance and protecting the source and / or drain electrodes from etching during the subsequent release of the sacrificial layer.

[0045] As can be seen, the current proposed technique for fabricating inner sidewalls in gate-around transistors uses a non-selective deposition method to grow insulating layers on all surfaces of the device; then, the insulating layers in the non-inner-wall cavities are etched so that the remaining insulating layers in the inner-wall cavities form the inner sidewalls. This specifically includes two steps: depositing the insulating layer material and etching the insulating layer material. However, on the one hand, collateral damage is easily caused during the etching of the insulating layer material in the non-inner-wall cavities; on the other hand, the insulating layer material in the inner-wall cavities is easily lost. Therefore, the thickness and shape of the insulating layer material in the inner-wall cavities are difficult to control accurately, and the thickness of the ultimately etched inner sidewall is difficult to control accurately, making it difficult to produce high-quality inner sidewalls.

[0046] In view of this, after repeated experiments, the inventors discovered that by using a selective precipitation method, taking advantage of the difference in properties between the surface materials of the channel layer and the sacrificial layer, and using silicon-based organic materials as precursors, the insulating layer material can be grown only on the surface of the sacrificial layer. This allows the precipitated dielectric material to fill only the inner wall cavity to form the inner wall. The thickness of the inner wall can be precisely controlled through selective precipitation.

[0047] As can be seen, the technical solution provided in this application has the following advantages: on the one hand, the thickness of the inner wall can be precisely controlled; on the other hand, the inner wall can be formed by selective precipitation in a single step; no etching step is required, thus avoiding collateral damage; therefore, the technical solution proposed in this application can produce devices with high-quality inner walls.

[0048] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0049] Please refer to Figures 1-4According to an embodiment of the present invention, a method for manufacturing an inner wall is provided, the process flow diagram of which is shown below. Figure 1 As shown, the method includes:

[0050] S11: A substrate 101 is provided; an alternately stacked sacrificial layer 103 and a channel layer 102 are formed on the substrate 101; in one specific embodiment, the material of the sacrificial layer 103 is SiGe;

[0051] S12: Etch the sacrificial layer 103, the channel layer 102 and the substrate 101 to form a plurality of fin structures arranged along a first direction; and form shallow trench isolation structures located between adjacent plurality of fin structures;

[0052] S13: A plurality of dummy gate structures 104 are formed along the second direction; the dummy gate structures 104 are located on the plurality of fin structures, and each dummy gate structure 104 spans each of the plurality of fin structures; spacer layers 105 are also provided on the surfaces of the dummy gate structures 104 along both sides of the second direction.

[0053] S14: Etch each of the fin structures to form a plurality of source / drain cavities; the device after forming the plurality of source / drain cavities is as follows: Figure 2 As shown;

[0054] S15: Etch both ends of the sacrificial layer 103 in each of the fin structures along the second direction to form an inner wall cavity;

[0055] S16: Selectively grow a dielectric material based on the sacrificial layer 103 to form an inner sidewall 106; the dielectric material fills the cavity of the inner sidewall; the device after forming the inner sidewall 106 is as follows: Figure 3 As shown;

[0056] S17: Epitaxial source / drain layer 107 is formed in the source / drain cavity. The source / drain layer 107 and the dummy gate structure 104 are isolated by the spacer layer 105. The device after forming the source / drain layer 107 is as follows. Figure 4 As shown;

[0057] On the plane where the substrate 101 is located, the second direction is perpendicular to the first direction; therefore, the plurality of source / drain cavities are located on both sides of the dummy gate structure 104 along the second direction, and thus the sacrificial layer 103 etched in step S15 is located between the dummy gate structure 104 and the source / drain cavities, so that after process step S15, the formed inner wall cavity is located between the dummy gate structure 104 and the source / drain cavity. The sacrificial layer 103 in step S16 is the remaining sacrificial layer 103 after performing step S15; thus, the dielectric material is selectively grown on the surface of the source / drain cavity with the remaining sacrificial layer 103 in contact; so that the dielectric material fills the inner wall cavity to form the inner sidewall 106.

[0058] The present invention provides a method for fabricating an inner sidewall by selectively growing a dielectric material based on a sacrificial layer 103 to fill the inner wall cavity with the dielectric material, thereby completing the fabrication of the sidewall in one step; without the need for an etching process, it solves the problem of unavoidable incidental damage to the device during the etching process of the inner sidewall 106.

[0059] In one embodiment, the thickness of the inner wall 106 along the second direction is controlled by the time for growing the dielectric material.

[0060] Since the thickness of the inner wall 106 can be precisely controlled by the time of growing the dielectric material, the present invention further solves the problem that the thickness of the inner wall 106 cannot be precisely controlled.

[0061] In one embodiment, the dielectric material is made of a precursor material. Specifically, the precursor material may be silicon-based, aluminum-based, or hafnium-based. Of course, the precursor material can also be other precursor materials, and this invention is not limited thereto; any implementation of the precursor material is within the protection scope of this invention.

[0062] The method for selectively growing dielectric materials is a selective precipitation method, and the specific principle is as follows: utilizing the difference in properties between the material surface of the channel layer 102 and the material surface of the sacrificial layer 103; using a precursor material, the dielectric material is grown only on the surface of the sacrificial layer 103; thus, the dielectric material is ultimately grown based on the surface of the sacrificial layer 103; achieving the goal of the precipitated dielectric material filling only the inner wall cavity, so as to ultimately form the inner sidewall 106.

[0063] In order to achieve higher selectivity in the deposition of dielectric materials, as a preferred embodiment, before growing the dielectric material based on the sacrificial layer 103, the surface of the sacrificial layer 103 is further subjected to surface treatment.

[0064] In one embodiment, the surface treatment is performed using a dry method, a wet method, an oxidation method, or a reduction method; of course, the surface treatment method can also be other surface treatment methods, and the present invention is not limited thereto. Any implementation of the surface treatment is within the protection scope of the present invention.

[0065] According to another embodiment of the present invention, a method for fabricating a semiconductor device is provided, comprising: the method for improving the etching morphology of the inner sidewall as described in any of the foregoing embodiments.

[0066] Secondly, according to another embodiment of the present invention, a semiconductor device is provided, which is prepared using the semiconductor device preparation method described in the foregoing embodiments.

[0067] In addition, according to other embodiments of the present invention, an electronic device is provided, including the semiconductor device described in the foregoing embodiments.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing an inner wall, characterized in that, The method includes: A substrate is provided; said substrate having alternately stacked sacrificial layers and channel layers formed thereon; The sacrificial layer, the trench layer, and the substrate are etched to form a plurality of fin structures arranged along a first direction; and shallow trench isolation structures are formed between adjacent plurality of fin structures. A plurality of dummy gate structures are formed along a second direction; the dummy gate structures are located on the plurality of fin structures, and each dummy gate structure spans each of the plurality of fin structures; Etching each of the fin structures forms several source / leak cavities; Etch both ends of the sacrificial layer in each of the fin structures along the second direction to form an inner wall cavity; Selectively growing a dielectric material based on the sacrificial layer to form an inner wall includes: utilizing the property difference between the material surfaces of the channel layer and the sacrificial layer; using a precursor material so that the dielectric material grows only on the surface of the sacrificial layer; thereby ultimately growing the dielectric material based on the surface of the sacrificial layer; achieving the goal of the precipitated dielectric material filling only the inner wall cavity to ultimately form the inner wall; the dielectric material filling the inner wall cavity; An epitaxial source / drain layer is formed in the source / drain cavity.

2. The method for manufacturing the inner wall according to claim 1, characterized in that, The thickness of the inner wall along the second direction is controlled by the time it takes to grow the dielectric material.

3. The method for manufacturing the inner wall according to claim 2, characterized in that, The dielectric material is made of a precursor material.

4. The method for manufacturing the inner wall according to claim 3, characterized in that, The precursor material is silicon-based, aluminum-based, or hafnium-based.

5. The method for manufacturing the inner wall according to claim 4, characterized in that, The material of the sacrificial layer is SiGe.

6. The method for manufacturing the inner wall according to claim 5, characterized in that, Before growing the dielectric material based on the sacrificial layer, the process further includes: performing a surface treatment on the surface of the sacrificial layer.

7. The method for manufacturing the inner wall according to claim 6, characterized in that, The surface treatment method used is a dry method, a wet method, an oxidation method, or a reduction method.

8. A method for fabricating a semiconductor device, characterized in that, include: The method for manufacturing the inner wall according to any one of claims 1 to 7.

9. A semiconductor device, characterized in that, It is prepared using the semiconductor device preparation method described in claim 8.

10. An electronic device comprising the semiconductor device of claim 9.

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