Semiconductor device, electronic device, and manufacturing method

Abstract

The embodiment of the present disclosure discloses a semiconductor device, an electronic device and a preparation method, and relates to the technical field of semiconductors. The semiconductor device comprises a semiconductor substrate, a word line trench, a word line structure, a gate oxide layer and an insulating structure. The insulating structure covers the sidewall of the top of the word line trench, the upper surface of the word line structure away from one side of the set plane, the upper surface of the gate oxide layer and the outer side surface of the top of the gate oxide layer. The upper surface of the word line structure away from one side of the set plane is lower than the upper surface of the semiconductor substrate, the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, and the lower surface of the insulating structure close to one side of the set plane is lower than the upper surface of the word line structure away from one side of the set plane, so that the GIDL effect is improved, the leakage current is reduced and the performance of the transistor is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to semiconductor devices, electronic devices, and methods for their fabrication. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device composed of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to the word line, and its drain or source is connected to the bit line or capacitor. The voltage signal on the word line controls the transistor's on or off state, thereby reading data from the capacitor via the bit line or writing data to the capacitor via the bit line for storage. Typically, to reduce device size, crisscrossing word lines and bit lines are arranged in the active region of the array. With the miniaturization of device dimensions, the GIDL (Gate-induced Drain Leakage) effect has a significant impact on transistor performance. Summary of the Invention

[0003] This disclosure provides semiconductor devices, electronic devices, and fabrication methods to reduce the GIDL effect in semiconductor devices.

[0004] According to some embodiments, a first aspect of this disclosure provides a semiconductor device, including:

[0005] A semiconductor substrate having word line trenches; the word line trenches extending along a first direction;

[0006] A character line structure, wherein the character line structure fills the character line groove;

[0007] A gate oxide layer is located between the word line structure and the word line trench;

[0008] An insulating structure is filled within the word line trench; wherein the insulating structure covers the sidewall at the top of the word line trench, the upper surface of the word line structure away from the set plane, the upper surface of the gate oxide layer, and the outer surface of the top of the gate oxide layer; the set plane is the plane containing the lower surface of the semiconductor substrate;

[0009] In this design, the upper surface of the word line structure on the side away from the setting plane is lower than the upper surface of the semiconductor substrate, the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, and the lower surface of the insulating structure on the side closer to the setting plane is lower than the upper surface of the word line structure on the side away from the setting plane. This allows a portion of the insulating structure to be positioned around the gate oxide layer, creating an overlap between the insulating structure and the gate oxide layer in the second direction. This combination of the insulating structure and the gate oxide layer increases the thickness between the upper surface of the word line structure and the semiconductor substrate. Specifically, the thickness of the insulating material between the upper surface of the word line structure and the semiconductor substrate is D1 + D2 (D1 represents the thickness of the gate oxide layer, and D2 represents the thickness of the insulating structure overlapping with the gate oxide layer in the second direction). The thickness of the insulating material between the lower surface of the insulating structure on the side closer to the setting plane and the setting plane is D1. Therefore, D1 + D2 > D1. This increases the thickness of the insulating material between the upper surface of the word line structure and the source / drain regions in the active region compared to the original gate oxide layer, effectively improving the GIDL effect, reducing transistor leakage current, and improving the overall performance of the transistor.

[0010] In some possible embodiments, the insulating structure includes: a first insulating layer and a second insulating layer; the first insulating layer is located between the second insulating layer and the word line groove;

[0011] The first insulating layer covers the sidewall of the top of the word line trench and the outer side of the top of the gate oxide layer, and the lower surface of the insulating structure near the set plane is the lower surface of the first insulating layer near the set plane.

[0012] The second insulating layer covers the first insulating layer and fills the word line groove.

[0013] In some possible embodiments, the second insulating layer includes an insulating protective layer; wherein the insulating protective layer covers the first insulating layer and fills the word line groove.

[0014] In some possible embodiments, the second insulating layer further includes an insulating dielectric layer; wherein the insulating dielectric layer is located at least between the insulating protective layer and the gate oxide layer.

[0015] In some possible embodiments, the upper surface of the gate oxide layer on the side away from the setting plane is not higher than the upper surface of the word line structure on the side away from the setting plane.

[0016] In some possible embodiments, the semiconductor device further includes a polysilicon material portion; wherein the polysilicon material portion is located between the word line structure and the insulating structure, and the upper surface of the polysilicon material portion on the side away from the setting plane is lower than the upper surface of the semiconductor substrate, and the upper surface of the polysilicon material portion on the side away from the setting plane is higher than the upper surface of the gate oxide layer on the side away from the setting plane.

[0017] In some possible embodiments, the insulating structure further includes: a third insulating layer; the third insulating layer is located between the second insulating layer and the polycrystalline silicon material portion; the third insulating layer covers the outer surface of the polycrystalline silicon material portion.

[0018] In some possible embodiments, the semiconductor substrate further has a channel isolation structure and a plurality of active regions; wherein the channel isolation structure separates adjacent active regions, and the word line trench extends along the first direction and passes through the respective active regions and the trench isolation structure;

[0019] The gate oxide layer at least covers the sidewalls of the word line trench located in the active region;

[0020] The word line structure includes a blocking portion and a conductive portion; wherein the blocking portion is located between the conductive portion and the gate oxide layer; the upper surface of the conductive portion is flush with the upper surface of the blocking portion on the side away from the set plane.

[0021] This disclosure also provides a method for fabricating a semiconductor device, including:

[0022] A word line trench is formed on a semiconductor substrate; wherein the word line trench extends along a first direction;

[0023] A gate oxide layer and a word line structure are formed within the word line trench, and a semiconductor substrate is exposed at the sidewall of the word line trench; wherein the word line structure fills the word line trench, and the upper surface of the word line structure on the side away from the set plane is lower than the upper surface of the semiconductor substrate, and the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate;

[0024] An insulating structure is filled within the word line trench; wherein the insulating structure covers the sidewall of the top of the word line trench, the upper surface of the word line structure away from the setting plane, the upper surface of the gate oxide layer, and the outer surface of the top of the gate oxide layer; and the lower surface of the insulating structure near the setting plane is lower than the upper surface of the word line structure away from the setting plane; the setting plane is the plane containing the lower surface of the semiconductor substrate. This allows a portion of the insulating structure to be positioned around the gate oxide layer, and allows the insulating structure and the gate oxide layer to overlap in the second direction. This allows the insulating structure and the gate oxide layer to combine and increase the thickness between the upper surface of the word line structure and the semiconductor substrate. That is, the thickness of the insulating material between the upper surface of the word line structure and the semiconductor substrate is D1+D2 (D1 represents the thickness of the gate oxide layer, and D2 represents the thickness of the insulating structure overlapping with the gate oxide layer in the second direction). The thickness of the insulating material between the lower surface of the insulating structure near the setting plane and the semiconductor substrate is D1. Therefore, D1+D2>D1. This allows for an increase in the thickness of the insulating material between the top of the word line structure and the source / drain regions in the active region, compared to the original gate oxide layer. This effectively mitigates the GIDL effect, reduces transistor leakage current, and improves the overall performance of the transistor.

[0025] In some possible embodiments, the word line groove is filled with an insulating structure, including:

[0026] A first insulating layer is formed on the semiconductor substrate exposed at the sidewall of the word line trench, and the first insulating layer also covers the outer side surface of the top of the gate oxide layer; wherein, the lower surface of the insulating structure near the set plane is the lower surface of the first insulating layer near the set plane.

[0027] A second insulating layer is filled into the trench in which the first insulating layer is formed, so that the first insulating layer and the second insulating layer form the insulating structure.

[0028] In some possible embodiments, forming a first insulating layer on the semiconductor substrate exposed at the word line trench sidewalls includes:

[0029] The surface of the semiconductor substrate exposed at the sidewall of the word line trench is oxidized to form the first insulating layer.

[0030] In some possible embodiments, forming the gate oxide layer and word line structure within the word line trench includes:

[0031] The surface of the semiconductor substrate at the word line trench is oxidized to form an initial gate oxide layer;

[0032] The word line structure is filled in the word line trench where the initial gate oxide layer is formed, and the initial gate oxide layer formed on the side of the word line trench away from the set plane is exposed.

[0033] The exposed gate oxide initial layer is etched so that the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, thus forming the gate oxide layer.

[0034] In some possible embodiments, after filling the word line structure within the word line trench where the initial gate oxide layer is formed and exposing the initial gate oxide layer formed on the side of the word line trench away from the defined plane, and before etching the exposed initial gate oxide layer, the method further includes:

[0035] Polysilicon material is filled into the word line trenches in which the word line structure is formed, forming a polysilicon initial layer;

[0036] The polysilicon initial layer is etched so that the upper surface of the polysilicon initial layer is lower than the upper surface of the semiconductor substrate, thereby forming the polysilicon material portion.

[0037] In some possible embodiments, while oxidizing the surface of the semiconductor substrate exposed at the word line trench sidewall, the outer surface of the polycrystalline silicon material exposed is also oxidized to form the third insulating layer.

[0038] According to some embodiments, a third aspect of this disclosure provides an electronic device that may include a semiconductor device and a circuit board, wherein the semiconductor device and the circuit board are connected. The semiconductor device is a semiconductor device as described in the first aspect or various embodiments thereof, or the semiconductor device is formed using a fabrication method described in the second aspect or various embodiments thereof. Attached Figure Description

[0039] Figure 1 A top view of the semiconductor device provided in an embodiment of this disclosure;

[0040] Figure 2 for Figure 1 Some cross-sectional views of the structure along the AA' direction are shown in the top view of the structure.

[0041] Figure 3 for Figure 1 Other cross-sectional views along the AA' direction shown in the top view structural diagram;

[0042] Figure 4 for Figure 1The top view of the structure shown includes some cross-sectional views along the AA' direction.

[0043] Figure 5A for Figure 1 The top view of the structure shown includes some cross-sectional views along the AA' direction.

[0044] Figure 5B for Figure 1 The top view of the structure shown includes some cross-sectional views along the AA' direction.

[0045] Figure 6 for Figure 1 The top view of the structure shown includes some cross-sectional views along the AA' direction.

[0046] Figure 7 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0047] Figures 8A to 8G This is a cross-sectional structural schematic diagram of the process for fabricating a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this disclosure clearer, a further detailed description of this disclosure will be provided below in conjunction with the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction as described in this disclosure are illustrative of the accompanying drawings, but changes may be made as needed, and all such changes are included within the scope of protection of this disclosure. The accompanying drawings of this disclosure are for illustrative purposes only and do not represent actual scale.

[0049] It should be noted that specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific embodiments disclosed below. The following descriptions are preferred embodiments for carrying out this disclosure; however, these descriptions are for the purpose of illustrating the general principles of this disclosure and are not intended to limit the scope of this disclosure.

[0050] See Figure 1 and Figure 2The semiconductor device provided in this disclosure may include a semiconductor substrate 100. The semiconductor substrate 100 may have an array region and a peripheral region. The array region may have memory cells, word line structures 130, and bit lines; the memory cells may have transistors and capacitors. The peripheral region may have control circuits, protection circuits (e.g., fuse devices), etc. Exemplarily, the semiconductor substrate 100 may be made of silicon, germanium, or silicon-on-insulator (SOI) substrates, or may include germanium-silicon compounds, silicon carbide, or other known materials, such as gallium arsenide and other Group III or V compounds. Certain dopant ions may be implanted into the semiconductor substrate 100 according to design requirements to change electrical parameters. Exemplarily, the semiconductor substrate 100 may be a silicon substrate.

[0051] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 The array region of the semiconductor substrate 100 may include a channel isolation structure 111 and multiple active regions 120. The channel isolation structure 111 separates adjacent active regions 120, i.e., it defines a plurality of spaced-apart active regions 120. This allows the channel isolation structure 111 to isolate leakage current and reduce electrical coupling. Exemplarily, the channel isolation structure 111 can be configured as a shallow trench isolation structure (STI). For example, shallow trenches can be formed in the semiconductor substrate 100 to define the region containing the active regions 120. The shallow trenches are filled with an insulating material to serve as the shallow trench isolation structure 111. In some examples, the insulating material filled in the shallow trenches can be silicon oxide, silicon nitride, or other materials. Furthermore, the depth of the shallow trenches can be set according to the needs of the actual application to control the degree of isolation between the transistor active regions 120.

[0052] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2The semiconductor device also includes word line trenches 133, word line structures 130, and gate oxide layers 140 located in an array region of the semiconductor substrate 100. One word line trench 133 corresponds to one word line structure 130, and the gate oxide layer 140 is located between the word line structure 130 and the word line trench 133, insulating the word line structure 130 from the semiconductor substrate 100 forming the word line trench 133. Exemplarily, multiple word line trenches 133 and multiple word line structures 130 are provided, with one word line structure 130 disposed in each word line trench 133. Furthermore, each active region 120 extends along a second direction F2, and each word line trench 133 extends along a first direction F1, passing through the corresponding active region 120 and the trench isolation structure. Each word line structure 130 also extends along the first direction F1, passing through the corresponding active region 120 and the trench isolation structure. For example, the angle between the first direction F1 and the second direction F2 can be greater than 0 degrees and less than or equal to 90 degrees, and is not limited here.

[0053] For example, word line structure 130 can serve as the gate of a transistor, and a portion of the active region 120 containing the gate of the transistor can serve as its channel region. The source / drain regions of the transistor can be located within the active regions 120 on both sides of word line structure 130, excluding the channel regions. For example, one source / drain region, such as the active region 120 between two word line structures 130, can serve as the source of the corresponding transistor, and another source / drain region, such as the active region 120 between word line structure 130 and channel isolation structure 111, can serve as the drain of the corresponding transistor, without limitation herein.

[0054] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 The semiconductor device also includes an insulating structure 150 located in the array region of the semiconductor substrate 100, which fills the word line trench 133. The insulating structure 150 covers the sidewalls at the top of the word line trench 133, the upper surface S1 of the word line structure 130 away from the setting plane S01, the upper surface S2 of the gate oxide layer 140 (the upper surface S2 is the upper surface S2 of the gate oxide layer 140), and the outer surface of the top of the gate oxide layer 140 (i.e., a portion of the insulating structure 150 is disposed around the outer surface of the top of the gate oxide layer 140). Furthermore, the upper surface S1 of the word line structure 130 away from the setting plane S01 is lower than the upper surface S02 of the semiconductor substrate, the upper surface S2 of the gate oxide layer 140 is lower than the upper surface S02 of the semiconductor substrate, and the lower surface S3 of the insulating structure 150 near the setting plane S01 is lower than the upper surface S1 of the word line structure 130 away from the setting plane S01. Here, plane S01 is defined as the plane containing the lower surface of semiconductor substrate 100.

[0055] The semiconductor device provided in this embodiment of the disclosure is configured such that the upper surface S1 of the word line structure 130 away from the setting plane S01 is lower than the upper surface S02 of the semiconductor substrate, the upper surface S2 of the gate oxide layer 140 is lower than the upper surface S02 of the semiconductor substrate, and the lower surface S3 of the insulating structure 150 near the setting plane S01 is lower than the upper surface S1 of the word line structure 130 away from the setting plane S01. Furthermore, the insulating structure 150 covers the sidewalls of the word line trench 133, the upper surface S1 of the word line structure 130 away from the setting plane S01, the upper surface S2 of the gate oxide layer 140, and the outer surface of the portion of the gate oxide layer 140 away from the setting plane S01 (i.e., a portion of the insulating structure 150 is disposed around the outer surface of the portion of the gate oxide layer 140 away from the setting plane S01). This allows a portion of the insulating structure 150 to be disposed around the periphery of the gate oxide layer 140, and the insulating structure 150 and the gate oxide layer 140 to have an overlapping area in the second direction F2. This allows the insulating structure 150 to be combined with the gate oxide layer 140, increasing the thickness between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100. Specifically, the thickness of the insulating material between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 is D1 + D2 (D1 represents the thickness of the gate oxide layer 140, and D2 represents the thickness of the insulating structure 150, which overlaps with the gate oxide layer 140 in the second direction F2). The thickness of the insulating material between the lower surface S3 of the insulating structure 150 (closer to the setting plane S01) and the setting plane S01, and the semiconductor substrate 100, is D1. Therefore, D1 + D2 > D1. This increases the thickness of the insulating material between the upper surface S1 of the word line structure 130 and the source / drain region in the active region 120 by D2 compared to the original gate oxide layer 140, effectively improving the GIDL effect, reducing transistor leakage current, and improving the overall performance of the transistor.

[0056] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 The word line structure 130 may include a blocking portion 131 and a conductive portion 132; wherein, the blocking portion 131 is located between the conductive portion 132 and the gate oxide layer 140, the gate oxide layer 140 at least covers the sidewalls of the word line trench located in the channel region of the active region 120, and the upper surface of the conductive portion 132 is flush with the upper surface of the blocking portion 131 on the side away from the setting plane S01. Exemplarily, the upper surface of the conductive portion 132 is the upper surface S1 of the word line structure 130. Exemplarily, the material of the blocking portion 131 may include at least one of TiN, TaN, WN, MoN, TiSiN, and WSiN. The material of the conductive portion 132 may include at least one of W, Mo, Ti, and Ta.

[0057] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 The insulating structure 150 may include a first insulating layer 151 and a second insulating layer 152. The first insulating layer 151 is located between the second insulating layer 152 and the word line trench 133. The first insulating layer 151 covers the top sidewall of the word line trench 133 and the outer surface of the top of the gate oxide layer 140. The second insulating layer 152 covers the first insulating layer 151 and fills the word line trench 133. Furthermore, the lower surface S3 of the insulating structure 150 near the setting plane S01 is the lower surface of the first insulating layer 151 near the setting plane S01. That is, the lower surface of the first insulating layer 151 near the setting plane S01 is lower than the upper surface of the word line structure 130 away from the setting plane S01. This allows the first insulating layer 151 to be disposed around the gate oxide layer 140, and the first insulating layer 151 and the gate oxide layer 140 to have an overlapping area in the second direction F2, thereby increasing the thickness between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 through the combination of the first insulating layer 151 and the gate oxide layer 140. That is, the thickness of the insulating material between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 is D1+D2 (D1 represents the thickness of the gate oxide layer 140, and D2 represents the thickness of the first insulating layer 151). The thickness of the insulating material between the lower surface S3 of the first insulating layer 151, which is closer to the setting plane S01, and the setting plane S01, and the semiconductor substrate 100 is D1. Therefore, D1+D2>D1. This increases the thickness of the insulating material between the upper surface S1 of the word line structure 130 and the source / drain region in the active region 120 by D2 compared to the original gate oxide layer 140. This effectively improves the GIDL effect, reduces the leakage current of the transistor, and improves the overall performance of the transistor. For example, the first insulating layer 151 can be obtained by oxidizing the semiconductor substrate 100 located on the sidewall at the top of the word line trench 133.

[0058] It should be noted that, in combination Figure 2 As shown, the sidewalls at the top of the word line trench 133 covered by the first insulating layer 151 are actually partially covered. That is, only the semiconductor substrate 100 on the sidewalls at the top of the word line trench in the active region 120 is oxidized to the first insulating layer (if the semiconductor substrate is a Si substrate, then only the Si on the sidewalls at the top of the word line trench in the active region 120 is oxidized to the first insulating layer), and the first insulating layer will not be formed in the channel isolation structure.

[0059] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2The second insulating layer 152 may include an insulating protective layer 1522; wherein the insulating protective layer 1522 covers the first insulating layer 151 and fills the word line trench 133. Exemplarily, the material of the insulating protective layer 1522 may include one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxynitride. Thus, after forming the first insulating layer 151, the second insulating layer 152 can be formed using a single film layer, reducing process steps and costs.

[0060] In some embodiments of this disclosure, reference is made to Figure 2 This allows the upper surface S2 of the gate oxide layer 140 to be lower than the upper surface S02 of the semiconductor substrate, and the upper surface S2 of the gate oxide layer 140 to be higher than the upper surface S1 of the word line structure 130 on the side away from the set plane S01. This allows the insulating material between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 to include the first insulating layer 151 and the gate oxide layer 140.

[0061] In other embodiments of this disclosure, reference is made to Figure 3 Alternatively, the upper surface S2 of the gate oxide layer 140 can be lower than the upper surface S02 of the semiconductor substrate, and the upper surface S2 of the gate oxide layer 140 can be equal to the upper surface S1 of the word line structure 130 on the side away from the set plane S01. In this way, the insulating material between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 can include the first insulating layer 151 and the gate oxide layer 140.

[0062] In some embodiments of this disclosure, reference is made to Figure 4 Alternatively, the upper surface S2 of the gate oxide layer 140 can be lower than the upper surface S02 of the semiconductor substrate, and the upper surface S2 of the gate oxide layer 140 can be lower than the upper surface S1 of the word line structure 130 on the side away from the set plane S01. In this way, the insulating material between the upper surface S1 of the word line structure 130 and the semiconductor substrate 100 can also include a first insulating layer 151 and a second insulating layer 152.

[0063] In some embodiments of this disclosure, reference is made to Figure 5A and Figure 5B The semiconductor device may further include a polysilicon material portion 160; wherein the polysilicon material portion 160 is located between the word line structure 130 and the insulating structure 150, and the upper surface S4 of the polysilicon material portion 160 (the upper surface S4 is the upper surface of the polysilicon material portion 160 on the side away from the set plane S01) is lower than the upper surface S02 of the semiconductor substrate, and the upper surface S4 of the polysilicon material portion 160 is higher than the upper surface S2 of the gate oxide layer 140. This can further reduce the leakage current of the transistor.

[0064] In some embodiments of this disclosure, reference is made to Figure 5A and Figure 5BThe second insulating layer 152 may further include an insulating dielectric layer 1521. That is, the second insulating layer 152 may include an insulating dielectric layer 1521 and an insulating protective layer 1522. The insulating dielectric layer 1521 is located at least between the insulating protective layer 1522 and the gate oxide layer 140. This reduces parasitic capacitance through the insulating dielectric layer 1521. For example, refer to... Figure 5A The insulating dielectric layer 1521 is located between the insulating protective layer 1522 and the gate oxide layer 140, that is, the insulating dielectric layer 1521 is disposed in the grooves formed by the first insulating layer 151 on both sides of the polysilicon material portion 160. (Reference) Figure 5B An insulating dielectric layer 1521 covers the surface of the first insulating layer 151, and an insulating protective layer 1522 is located on the insulating dielectric layer 1521 and fills the word line trench 133. Furthermore, the insulating dielectric layer 1521 also covers the upper surface of the semiconductor substrate 100 of the active region 120. Alternatively, the insulating dielectric layer 1521 may only be disposed within the word line trench 133. Exemplarily, the material of the insulating dielectric layer 1521 may include a low dielectric constant material, such as SiOH.

[0065] In some embodiments of this disclosure, reference is made to Figure 6 The insulating structure 150 may further include a third insulating layer 153. That is, the insulating structure 150 may include a first insulating layer 151, a second insulating layer 152, and a third insulating layer 153. The third insulating layer 153 is located between the second insulating layer 152 and the polysilicon material portion 160, and covers the outer surface of the polysilicon material portion 160. This further increases the thickness of the insulating material between the upper surface S4 of the polysilicon material portion 160 and the semiconductor substrate 100, further reducing the leakage current of the transistor. Exemplarily, when the second insulating layer 152 includes an insulating dielectric layer 1521 and an insulating protective layer 1522, the third insulating layer 153 is located between the insulating dielectric layer 1521 and the polysilicon material portion 160. Exemplarily, the third insulating layer 153 may be obtained by oxidizing the outer surface of the polysilicon material portion 160. It should be noted that the outer surface of the polysilicon material portion 160 covered by the third insulating layer 153 includes the upper surface and at least a portion of the outer surface of the polysilicon material portion 160. Furthermore, the arrangement of the first insulating layer 151 and the second insulating layer 152 can refer to the above embodiment, and will not be repeated here.

[0066] It should be noted that in actual processes, due to limitations in process conditions or other factors, the above-mentioned flushing relationship may not be perfectly flush and may have some deviations. Therefore, as long as the above-mentioned flushing relationship roughly meets the above conditions, it is acceptable and falls within the protection scope of this disclosure. For example, the above-mentioned flushing relationship can be within the allowable error range.

[0067] It should be noted that in actual processes, due to limitations in process conditions or other factors, the above-mentioned equality relationships may not be completely equal and may have some deviations. Therefore, as long as the above-mentioned equality relationships roughly meet the above conditions, they are all within the protection scope of this disclosure. For example, the above-mentioned equality relationships can be those that are permissible within the allowable error range.

[0068] refer to Figure 7 The preparation method provided in this disclosure may include the following steps:

[0069] S10. Form word line trenches on a semiconductor substrate.

[0070] Exemplarily, before performing step S10, the process may further include: forming a channel isolation structure 111 in the semiconductor substrate 100, and a plurality of spaced active regions 120 defined by the channel isolation structure 111. For example, firstly, a semiconductor substrate 100 is provided. The material of the semiconductor substrate 100 may include silicon, germanium, or silicon-on-insulator (SOI) semiconductors, or may include germanium-silicon compounds, silicon carbide, or other known materials, such as gallium arsenide and other group III or V compounds. Certain dopant ions may also be implanted into the semiconductor substrate 100 to change the electrical parameters according to design requirements. Exemplarily, the provided semiconductor substrate 100 may be a silicon substrate.

[0071] Subsequently, a channel isolation structure 111 and a plurality of spaced active regions 120 defined by the channel isolation structure 111 are formed in the semiconductor substrate 100. Exemplarily, an STI mask is first formed on the semiconductor substrate 100, and the area of ​​the semiconductor substrate 100 covered by the STI mask is the active region 120. Then, using the STI mask as an etching mask, a vapor phase etching process is employed. The etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar to achieve a certain etching selectivity, etching the exposed semiconductor substrate 100 (i.e., the semiconductor substrate 100 not covered by the STI mask) to form shallow trenches, while retaining the area of ​​the semiconductor substrate 100 where the active regions 120 will be formed. Afterward, the STI mask is removed. Subsequently, SiN is filled into the shallow trench to form a shallow trench isolation structure 111, which serves as a channel isolation structure 111. A plurality of spaced active regions 120 are then formed within the semiconductor substrate 100 by the shallow trench isolation structure 111, thereby forming a... Figure 8A The structure of the semiconductor device shown.

[0072] For example, step 10 may include: forming word line trenches 133 in the semiconductor substrate 100 where the channel isolation structure 111 and the active region 120100 are located using photolithography and etching processes. For example, a word line trench 133 mask is formed using photolithography, which exposes the area in the semiconductor substrate 100 where the word line trenches 133 will be formed, while covering the remaining area. Using the word line trench 133 mask as an etching mask, a vapor phase etching process is used, where the etching gas can be one or more of SF6, CF4, Cl2, CHF3, O2, and Ar, to etch the exposed semiconductor substrate 100 where the channel isolation structure 111 and the active region 120100 are located, so as to form word line trenches 133 extending along the first direction F1 in the semiconductor substrate 100 where the channel isolation structure 111 and the active region 120100 are located. Subsequently, vapor phase etching was used to remove the mask 133 of the word line trenches, thereby forming Figure 8B The structure of the semiconductor device shown.

[0073] S20. A gate oxide layer and a word line structure are formed within a word line trench, and a semiconductor substrate is exposed at the sidewall of the word line trench. The word line structure fills the word line trench, and the upper surface of the word line structure on the side away from the set plane is lower than the upper surface of the semiconductor substrate, and the upper surface of the gate oxide layer on the side away from the set plane is lower than the upper surface of the semiconductor substrate.

[0074] Exemplarily, step S20 includes: firstly, oxidizing the surface of the semiconductor substrate 100 at the word line trench 133 to form an initial gate oxide layer. For example, at least one of in-situ steam generation (ISSG) and thermal oxidation (TO) processes (such as regenerative thermal oxidation (RTO)) is used to oxidize the surface of the semiconductor substrate 100 at the word line trench 133 to form an initial gate oxide layer, thereby forming a gate oxide initial layer. Figure 8C The structure of the semiconductor device shown.

[0075] Subsequently, word line structures 130 are filled into the word line trenches 133 where the initial gate oxide layer has been formed, exposing the initial gate oxide layer formed on the side of the word line trenches 133 away from the set plane S01. For example, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes to deposit a barrier initial layer of TiN on the surface of the word line trenches 133, so that the barrier initial layer covers the surface of the word line trenches 133. Subsequently, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes to deposit W or Mo or W and Mo in the word line trenches 133 covered with the barrier initial layer to form a conductive initial layer. Subsequently, an etching process (e.g., vapor phase etching) is used to etch the barrier initial layer and the conductive initial layer, making the etched barrier initial layer and conductive initial layer flush with the upper surface away from the set plane S01 and lower than the upper surface of the semiconductor substrate, forming a word line structure 130, thereby forming a... Figure 8D The structure of the semiconductor device shown allows for the formation of embedded word lines.

[0076] Subsequently, the exposed initial gate oxide layer is etched, such that the upper surface of the gate oxide layer 140 on the side away from the set plane S01 is lower than the upper surface of the semiconductor substrate, thus forming the gate oxide layer 140. For example, a vapor phase etching process is used to etch the exposed initial gate oxide layer, such that the upper surface of the etched initial gate oxide layer on the side away from the set plane S01 is lower than the upper surface of the semiconductor substrate, and the upper surface of the etched initial gate oxide layer on the side away from the set plane S01 is higher than the upper surface of the word line structure 130 on the side away from the set plane S01, thus forming the gate oxide layer 140, thereby forming a structure as shown in the image. Figure 8E The structure of the semiconductor device shown.

[0077] In some examples, when the semiconductor device also includes a polysilicon material portion 160, after filling the word line structure 130 in the word line trench 133 where the gate oxide initial layer is formed, and exposing the gate oxide initial layer formed on the side of the word line trench 133 away from the set plane S01, and before etching the exposed gate oxide initial layer, the process further includes: First, a deposition process can be selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes to fill the word line trench 133 where the word line structure 130 is formed with polysilicon material, forming a polysilicon initial layer. Then, an etching process (e.g., vapor phase etching) is used to etch the polysilicon initial layer so that the upper surface of the polysilicon initial layer is lower than the upper surface of the semiconductor substrate, forming the polysilicon material portion 160. Subsequently, the exposed initial gate oxide layer is etched, such that the upper surface of the gate oxide layer 140 on the side away from the set plane S01 is lower than the upper surface of the semiconductor substrate, thus forming the gate oxide layer 140. For example, a vapor phase etching process is used to etch the exposed initial gate oxide layer, such that the upper surface of the etched initial gate oxide layer on the side away from the set plane S01 is lower than the upper surface of the semiconductor substrate, and the upper surface of the etched initial gate oxide layer on the side away from the set plane S01 is higher than the upper surface of the word line structure 130 on the side away from the set plane S01, thus forming the gate oxide layer 140, thereby forming a structure as shown in the image. Figure 8F The structure of the semiconductor device shown.

[0078] S30. Fill the word line trench with an insulating structure. The insulating structure covers the top sidewall of the word line trench, the upper surface of the word line structure, the upper surface of the gate oxide layer on the side away from the setting plane, and the outer side of the top of the gate oxide layer; and the lower surface of the insulating structure on the side closer to the setting plane is lower than the upper surface of the word line structure on the side away from the setting plane; the setting plane is the plane where the lower surface of the semiconductor substrate is located.

[0079] Exemplarily, step S30 includes: firstly, forming a first insulating layer 151 on the semiconductor substrate 100 exposed at the sidewall of the word line trench 133, and making the first insulating layer 151 also cover the outer surface of the top of the gate oxide layer 140. The lower surface of the first insulating layer 151 near the setting plane S01 is lower than the upper surface of the word line structure 130 away from the setting plane S01. For example, the surface of the semiconductor substrate 100 exposed at the sidewall of the word line trench 133 is oxidized to form the first insulating layer 151. In some examples, at least one of the ISSG process and the TO process (such as the RTO process) is used to oxidize the surface of the semiconductor substrate 100 exposed at the sidewall of the word line trench 133 to form the first insulating layer 151. Furthermore, while oxidizing the surface of the semiconductor substrate 100 exposed at the sidewall of the word line trench 133, the outer surface of the polysilicon material portion 160 is oxidized to form a third insulating layer 153, thereby forming a... Figure 8G The structure of the semiconductor device shown.

[0080] Subsequently, a second insulating layer 152 is filled into the word line trench 133 where the first insulating layer 151 is formed, so that the formed first insulating layer 151 and the second insulating layer 152 form an insulating structure 150. Exemplarily, when the second insulating layer 152 includes an insulating protective layer 1522 and an insulating dielectric layer 1521, firstly, a deposition process selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes can be used to deposit SiOH in the word line trench 133 to form the insulating dielectric layer 1521. Then, a deposition process selected from chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes can be used to deposit SiN in the word line trench 133 to form the insulating protective layer 1522, thereby forming an insulating structure 150. Figure 6 The structure of the semiconductor device shown.

[0081] This disclosure also provides an electronic device, which includes a circuit board (such as a printed circuit board) and any of the semiconductor devices provided in the above embodiments of this disclosure, wherein the semiconductor device is connected to the circuit board. Since the principle by which this electronic device solves the problem is similar to that of the aforementioned semiconductor device, the implementation of this electronic device can refer to the implementation of the aforementioned semiconductor device, and repeated details will not be described again.

[0082] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate with word line trenches; The word line groove extends along a first direction; A character line structure, wherein the character line structure fills the character line groove; A gate oxide layer is located between the word line structure and the word line trench, and the upper surface of the gate oxide layer is not higher than the upper surface of the word line structure on the side away from the set plane; An insulating structure is filled within the word line trench; wherein the insulating structure covers the sidewall at the top of the word line trench, the upper surface of the word line structure on the side away from the defined plane, the upper surface of the gate oxide layer, and the outer surface of the top of the gate oxide layer; the defined plane is the plane containing the lower surface of the semiconductor substrate; Wherein, the upper surface of the word line structure on the side away from the setting plane is lower than the upper surface of the semiconductor substrate, the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, and the lower surface of the insulating structure on the side close to the setting plane is lower than the upper surface of the word line structure on the side away from the setting plane.

2. The semiconductor device as claimed in claim 1, characterized in that, The insulating structure includes: a first insulating layer and a second insulating layer; the first insulating layer is located between the second insulating layer and the word line groove; The first insulating layer covers the sidewall of the top of the word line trench and the outer side of the top of the gate oxide layer, and the lower surface of the insulating structure near the set plane is the lower surface of the first insulating layer near the set plane. The second insulating layer covers the first insulating layer and fills the word line groove.

3. The semiconductor device as described in claim 2, characterized in that, The second insulating layer includes an insulating protective layer; wherein the insulating protective layer covers the first insulating layer and fills the word line groove.

4. The semiconductor device as described in claim 3, characterized in that, The second insulating layer further includes an insulating dielectric layer; wherein the insulating dielectric layer is located at least between the insulating protective layer and the gate oxide layer.

5. The semiconductor device according to any one of claims 2-4, characterized in that, The semiconductor device further includes a polysilicon material portion; wherein the polysilicon material portion is located between the word line structure and the insulating structure, and the upper surface of the polysilicon material portion is lower than the upper surface of the semiconductor substrate, and the upper surface of the polysilicon material portion is higher than the upper surface of the gate oxide layer.

6. The semiconductor device as claimed in claim 5, characterized in that, The insulating structure further includes: a third insulating layer; the third insulating layer is located between the second insulating layer and the polycrystalline silicon material portion; the third insulating layer covers the outer surface of the polycrystalline silicon material portion.

7. The semiconductor device according to any one of claims 1-4, characterized in that, The semiconductor substrate also has a channel isolation structure and a plurality of active regions; wherein the channel isolation structure separates adjacent active regions, and the word line trench extends along the first direction and passes through the corresponding active region and the trench isolation structure. The gate oxide layer at least covers the sidewalls of the word line trench located in the active region; The word line structure includes a blocking portion and a conductive portion; wherein the blocking portion is located between the conductive portion and the gate oxide layer; the upper surface of the conductive portion is flush with the upper surface of the blocking portion on the side away from the set plane.

8. A method for fabricating a semiconductor device, characterized in that, include: A word line trench is formed on a semiconductor substrate; wherein the word line trench extends along a first direction; A gate oxide layer and a word line structure are formed within the word line trench, and a semiconductor substrate is exposed at the sidewall of the word line trench; wherein the word line structure fills the word line trench, and the upper surface of the word line structure on the side away from the set plane is lower than the upper surface of the semiconductor substrate, the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, and the upper surface of the gate oxide layer is not higher than the upper surface of the word line structure on the side away from the set plane; An insulating structure is filled within the word line trench; wherein the insulating structure covers the sidewall at the top of the word line trench, the upper surface of the word line structure away from the set plane, the upper surface of the gate oxide layer, and the outer surface of the top of the gate oxide layer; and the lower surface of the insulating structure near the set plane is lower than the upper surface of the word line structure away from the set plane; the set plane is the plane containing the lower surface of the semiconductor substrate.

9. The method for fabricating a semiconductor device as described in claim 8, characterized in that, An insulating structure is filled within the groove for the letter lines, including: A first insulating layer is formed on the semiconductor substrate exposed at the sidewall of the word line trench, and the first insulating layer also covers the outer side surface of the top of the gate oxide layer; wherein, the lower surface of the insulating structure near the set plane is the lower surface of the first insulating layer near the set plane. A second insulating layer is filled into the trench in which the first insulating layer is formed, so that the first insulating layer and the second insulating layer form the insulating structure.

10. The method for fabricating a semiconductor device as described in claim 9, characterized in that, The formation of a first insulating layer on the semiconductor substrate exposed at the sidewall of the word line trench includes: The surface of the semiconductor substrate exposed at the sidewall of the word line trench is oxidized to form the first insulating layer.

11. The method for fabricating a semiconductor device as described in claim 10, characterized in that, The formation of the gate oxide layer and word line structure within the word line trench includes: The surface of the semiconductor substrate at the word line trench is oxidized to form an initial gate oxide layer; The word line structure is filled in the word line trench where the initial gate oxide layer is formed, and the initial gate oxide layer formed on the side of the word line trench away from the set plane is exposed. The exposed gate oxide initial layer is etched so that the upper surface of the gate oxide layer is lower than the upper surface of the semiconductor substrate, thereby forming the gate oxide layer.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, After filling the word line structure within the word line trench where the initial gate oxide layer is formed, and exposing the initial gate oxide layer formed on the side of the word line trench away from the defined plane, and before etching the exposed initial gate oxide layer, the method further includes: Polysilicon material is filled into the word line trenches in which the word line structure is formed, forming a polysilicon initial layer; The polysilicon initial layer is etched so that the upper surface of the polysilicon initial layer is lower than the upper surface of the semiconductor substrate, thereby forming a polysilicon material portion.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, While oxidizing the surface of the semiconductor substrate exposed at the word line trench sidewall, the outer surface of the polycrystalline silicon material exposed is also oxidized to form a third insulating layer.

14. An electronic device, characterized in that, Includes a semiconductor device and a circuit board, wherein the semiconductor device and the circuit board are connected; The semiconductor device is the semiconductor device as described in any one of claims 1-7, or the semiconductor device is formed using the preparation method as described in any one of claims 8-13.

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