Super junction insulated gate bipolar transistor

Abstract

The application discloses a super-junction insulated gate bipolar transistor, which comprises a collector, a collector region, a drift region, an epitaxial layer, a well region and an emitter arranged in sequence along a first direction, and a gate and a super-junction region, the gate is arranged in the well region and the epitaxial layer, the drift region has a first region and a second region arranged in sequence along the first direction, the second region is located between the first region and the collector region, wherein the super-junction region is arranged in the first region, the second region is provided with an ion implantation region, the ion implantation region can control the minority carrier lifetime at the bottom of the second region, and the ion implantation region has no direct contact with the super-junction region and the collector region. The super-junction insulated gate bipolar transistor provided by the application reduces current tailing in the off process of the super-junction IGBT and accelerates the off process of the device.

Description

Technical Field

[0001] This invention relates in particular to a superjunction insulated gate bipolar transistor, belonging to the field of transistor technology. Background Technology

[0002] Superjunction IGBTs, as a new generation of high-speed IGBT design technology, have had their superior electrical performance experimentally verified. The inventors of this case provide a device structure for a superjunction IGBT. Figure 1 As shown, 1 is the P-collector region, 2 is the N-drift region, 3 is the P-type superjunction region, 4 is the epitaxial layer, 5 is the gate oxide layer, 6 is the gate, 7 is the P-well region, 8 is the N+ emitter, 9 is the dielectric layer, 10 is the emitter metal, 11 is the P+ collector, and 12 is the collector metal. Due to the conductance modulation effect of bipolar devices, superjunction IGBTs have a current tailing problem during turn-off, and the current tailing will lead to a large turn-off energy loss of the device. Summary of the Invention

[0003] The main objective of this invention is to provide a superjunction insulated gate bipolar transistor, thereby overcoming the shortcomings of the prior art.

[0004] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0005] This invention provides a superjunction insulated-gate bipolar transistor, comprising a collector, a collector region, a drift region, an epitaxial layer, a well region, and an emitter arranged sequentially along a first direction, as well as a gate and a superjunction region, wherein the gate is disposed within the well region and the epitaxial layer.

[0006] The drift region has a first region and a second region arranged sequentially along a first direction. The second region is located between the first region and the collector region. The superjunction region is disposed in the first region, and the second region is provided with an ion implantation region. The ion implantation region can regulate the minority carrier lifetime of the second region, and the ion implantation region has no direct contact with the superjunction region and the collector region.

[0007] Compared with the prior art, the superjunction insulated gate bipolar transistor provided by the present invention uses a hydrogen injection process to regulate the minority carrier lifetime in the region below the superjunction region, thereby reducing the minority carrier storage effect, reducing the current tailing during the turn-off process of the superjunction IGBT, accelerating the turn-off process of the device, and ultimately achieving the goal of reducing turn-off losses. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the structure of an existing superjunction IGBT device provided by the inventor of this case;

[0009] Figure 2 The results of the analysis and testing of the carrier distribution of IGBT turn-off tail in this invention are as follows;

[0010] Figure 3 This is a schematic diagram of the structure of a superjunction insulated gate bipolar transistor provided in Embodiment 1 of the present invention;

[0011] Figure 4 This is a schematic diagram of the structure of a superjunction insulated gate bipolar transistor provided in Embodiment 2 of the present invention;

[0012] Figure 5 This is a schematic diagram of the structure of a superjunction insulated gate bipolar transistor provided in Embodiment 3 of the present invention. Detailed Implementation

[0013] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate the technical solution, its implementation process, and its principles.

[0014] Explanation of terms designed in the embodiments of this invention:

[0015] GTR: Giant Transistor, also known as Power BJT, is a type of bipolar junction transistor that can withstand high voltage and high current. However, its driving circuit is complex and its driving power is large.

[0016] MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor, is a type of field-effect transistor widely used in analog and digital circuits. MOSFETs are classified into two types based on the polarity of their "channel" (working charge carriers): "N-type" and "P-type," commonly referred to as NMOSFET and PMOSFET.

[0017] IGBT: Insulated Gate Bipolar Transistor, is a composite fully controllable voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor) and MOS (Insulated Gate Field Effect Transistor), combining the advantages of high input impedance of MOSFET and low on-state voltage drop of GTR.

[0018] GTRs have a low saturation voltage drop and high current density, but also require a large drive current; MOSFETs have very low drive power and fast switching speed, but also have a large on-state voltage drop and low current density. IGBTs combine the advantages of both devices, offering low drive power and a low saturation voltage drop. They are ideally suited for applications in converter systems with DC voltages of 600V and above, such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives.

[0019] This invention provides a superjunction insulated-gate bipolar transistor, comprising a collector, a collector region, a drift region, an epitaxial layer, a well region, and an emitter arranged sequentially along a first direction, as well as a gate and a superjunction region, wherein the gate is disposed within the well region and the epitaxial layer.

[0020] The drift region has a first region and a second region arranged sequentially along a first direction. The second region is located between the first region and the collector region. The superjunction region is disposed in the first region, and the second region is provided with an ion implantation region. The ion implantation region can regulate the minority carrier lifetime of the second region, and the ion implantation region has no direct contact with the superjunction region and the collector region.

[0021] In one specific embodiment, the ion implantation region is formed by hydrogen ion implantation into the drift region, and the doping concentration of the ion implantation region is greater than the doping concentration of the drift region.

[0022] In one specific embodiment, the hydrogen doping concentration of the ion implantation region is 1E16-1E18. Tests have shown that under this doping concentration, minority carrier lifetime control (i.e., the aforementioned minority carrier lifetime) can be achieved in the region below the superjunction in the drift region. However, if the doping concentration is too high or too low, it is not conducive to minority carrier lifetime control.

[0023] In one specific embodiment, the thickness of the ion implantation region in the first direction is (0.2-0.8)H, where H is the vertical distance between the superjunction region and the collector region in the first direction.

[0024] In one specific embodiment, the vertical distance between the ion implantation region and the superjunction region in the first direction is (0.1-0.4)H, preferably 0.25H.

[0025] In one specific embodiment, a plurality of superjunction regions are provided in the drift region, and the plurality of superjunction regions are spaced apart in a second direction. The ion implantation region is at least corresponding to a first orthographic projection area of ​​the superjunction region in a first direction, and / or the ion implantation region is corresponding to a second orthographic projection area of ​​the gap between the plurality of superjunction regions in a first direction. The second direction is angular to the first direction.

[0026] In one specific embodiment, an ion implantation region is provided within the drift region, and the ion implantation region is continuously disposed in the first orthographic projection region and the second orthographic projection region.

[0027] In one specific embodiment, a plurality of ion implantation regions are provided within the drift region, and the plurality of ion implantation regions are spaced apart along a second direction. The plurality of ion implantation regions are all located in the first orthographic projection region, and each ion implantation region corresponds to a superjunction region. Alternatively, the plurality of ion implantation regions are all located in the second orthographic projection region, and each ion implantation region corresponds to the gap between two adjacent superjunction regions. Or, a portion of the plurality of ion implantation regions is located in the first orthographic projection region, and the remaining portion is located in the second orthographic projection region.

[0028] In one specific embodiment, the minimum spacing between two adjacent ion implantation regions in the second direction is 0.1H, and the maximum spacing is 5H.

[0029] In one specific embodiment, the plurality of ion implantation regions are arranged at equal intervals in the second direction.

[0030] In one specific embodiment, the ion implantation region is completely surrounded by the drift region.

[0031] In one specific embodiment, the collector region, superjunction region, and well region are all of the first conductivity type, and the drift region and emitter are all of the second conductivity type.

[0032] The following will further explain the technical solution, its implementation process and principle in conjunction with the accompanying drawings and specific implementation examples. Unless otherwise specified, the ion implantation process, testing method and testing equipment used in the embodiments of the present invention can all be those known to those skilled in the art, and no specific limitations are made here.

[0033] IGBTs exhibit a significant tail current during turn-off. TCAD simulation and analysis revealed this, as follows: Figure 2 As shown, this is mainly related to the stored charge of minority carriers (holes) in the region below the superjunction. This invention uses hydrogen injection technology to regulate the minority carrier lifetime in the region below the superjunction, thereby reducing the minority carrier storage effect and accelerating the device turn-off process.

[0034] Example 1

[0035] Please see Figure 3 A superjunction insulated-gate bipolar transistor includes a collector metal 12, a P+ collector 11, a P- collector region 1, an N- drift region 2, a secondary epitaxial layer 4, a P-well region 7, and an emitter metal 10 arranged sequentially along a first direction; and...

[0036] The device comprises a P-type superjunction region 3, a gate 6, and an N+ emitter 8. The P-type superjunction region 3 is disposed within the N-drift region 2. The gate 6 is disposed within the P-well region 7 and the secondary epitaxial layer 4. The N+ emitter 8 is disposed within the P-well region 7 and surrounds the gate 6. A gate oxide layer 5 is disposed between the gate 6, the secondary epitaxial layer 4, the P-well region 7, and the N+ emitter 8. A dielectric layer 9 is disposed between the emitter metal 10 and the gate 6. The emitter metal 10 is connected to the N+ emitter 8. The first direction can be the longitudinal direction of the device.

[0037] It should be noted that the materials and dimensions of the collector metal 12, P+ collector 11, P- collector region 1, N- drift region 2, secondary epitaxial layer 4, P-well region 7, emitter metal 10, P-type superjunction region 3, gate 6 and N+ emitter 8 in this embodiment can all be those known to those skilled in the art, and no limitation is imposed on them here.

[0038] In this embodiment, the N-drift region 2 has a first region and a second region arranged sequentially along a first direction. The second region is located between the first region and the P-collector region 1. The P-type superjunction region 3 is disposed in the first region, and the second region is provided with an ion implantation region 13. The ion implantation region 13 can regulate the minority carrier lifetime of the second region, thereby reducing the current tailing during the turn-off process of the superjunction IGBT and ultimately achieving the purpose of reducing turn-off losses.

[0039] In this embodiment, the ion implantation region 13 is formed by hydrogen ion implantation into the N-drift region 2. The doping concentration of the ion implantation region 13 is greater than that of the N-drift region 2, and the hydrogen doping concentration of the ion implantation region 13 is 1E16-1E18.

[0040] It should be noted that when the device is forward-biased, holes from the bottom collector are injected into the N-drift region 2 through ion implantation region 13. Since the doping concentration of ion implantation region 13 is higher than that of N-drift region 2, an electron-rich region is formed. When holes pass through ion implantation region 13, the recombination effect of the holes reduces the hole injection concentration, thereby controlling the minority carrier lifetime. Therefore, to achieve minority carrier lifetime control in the region below the P-type superjunction region by ion implantation region 13, the hydrogen doping concentration of ion implantation region 13 needs to be 1E16-1E18. When the device is turned off from the on-state, holes in N-drift region 2 are removed, resulting in a tail current. Compared to the traditional structure, the introduction of ion implantation region 13 reduces the total number of holes, thus effectively reducing the tail current.

[0041] In this embodiment, the first region of the N-drift region 2 is provided with a plurality of P-type superjunction regions 3, which are spaced apart along a second direction. The second region of the N-drift region 2 is provided with a plurality of ion implantation regions 13, which are spaced apart along a second direction. Each ion implantation region 13 is correspondingly located below a P-type superjunction region 3, that is, each ion implantation region 13 is correspondingly located within the first orthographic projection region of the P-type superjunction region 3 in the first direction. The second direction can be the lateral direction of the device, and the second direction is perpendicular to the first direction.

[0042] In this embodiment, the ion implantation region 13 is not in direct contact with the P-type superjunction region 3 and the P-collector region 1. It can be understood that each of the ion implantation regions 13 is an island structure completely surrounded by the N-drift region 2.

[0043] In this embodiment, the thickness of the ion implantation region 13 in the first direction is (0.2-0.8)H, and the vertical distance between the ion implantation region 13 and the P-type superjunction region 3 in the first direction is 0.1-0.4H, where H is the vertical distance between the P-type superjunction region 3 and the P-collector region 1 in the first direction. By setting it in this way, the minority carrier lifetime in the region below the P-type superjunction region can be better realized.

[0044] In this embodiment, the plurality of ion implantation regions 13 are arranged at equal intervals along the second direction, and the distance between two adjacent ion implantation regions 13 along the second direction is 0.5H.

[0045] Example 2

[0046] Please see Figure 4 The structure of a superjunction insulated gate bipolar transistor in Embodiment 2 is basically the same as that in Embodiment 1, except that the ion implantation region 13 in this embodiment is disposed below the gap between multiple P-type superjunction regions 3, that is, the ion implantation region 13 is disposed in the second orthogonal projection region of the gap between multiple P-type superjunction regions 3 in the first direction.

[0047] Example 3

[0048] Please see Figure 5 The structure of a superjunction insulated gate bipolar transistor in Embodiment 3 is basically the same as that in Embodiment 1 or 2, except that: in this embodiment, some of the multiple ion implantation regions 13 are disposed below the P-type superjunction region 3, and some are disposed below the gap between the multiple P-type superjunction regions 3. That is, some of the multiple ion implantation regions 13 are disposed in the first orthogonal projection area of ​​the P-type superjunction region 3 in the first direction, and some are disposed in the second orthogonal projection area of ​​the gap between the multiple P-type superjunction regions 3 in the first direction.

[0049] Example 4

[0050] The structure of the superjunction insulated gate bipolar transistor in Example 4 is basically the same as that of the device in Example 1, Example 2, or Example 3, except that:

[0051] In this embodiment, the plurality of ion implantation regions 13 are not equally spaced in the second direction, and the minimum spacing between two adjacent ion implantation regions 13 in the second direction is 0.1H and the maximum spacing is 5H.

[0052] Example 5

[0053] The structure of a superjunction insulated gate bipolar transistor in Embodiment 5 is basically the same as that in Embodiment 1, except that: in this embodiment, the second region of the N-drift region 2 is provided with an ion implantation region 13, which extends continuously along the second direction. The ion implantation region 13 is correspondingly located below the gap between the multiple P-type superjunction regions 3.

[0054] The devices in Examples 1-5 were tested respectively. The test results show that Example 1 focuses on controlling the minority carrier concentration directly below the P-type superjunction region 3, which can appropriately improve the tail current characteristics of the device. Example 2 focuses on controlling the minority carrier concentration below the gap between the P-type superjunction regions 3. Since the storage of minority carriers in this part directly affects the tail current, this scheme has a better tail current suppression effect than Example 1. Example 3 adopts uniform control of the minority carrier concentration below the superjunction region. The tail current reduction effect is between that of Example 1 and Example 2, and the device's conduction and switching characteristics have a good trade-off effect. Example 4 optimizes the minority carrier concentration in the characteristic region. The tail current optimization effect of the device is better than that of the device in Example 3, and it can achieve the best trade-off between conduction and switching characteristics. Example 5 performs uniform optimization on the region below the superjunction. It has advantages in the process implementation stage. Its tail current optimization effect is only better than that of Example 1, but weaker than that of the devices in Examples 2-4.

[0055] Comparative Example 1

[0056] Please see Figure 1 A superjunction insulated-gate bipolar transistor includes a collector metal 12, a P+ collector 11, a P- collector region 1, an N- drift region 2, a secondary epitaxial layer 4, a P-well region 7, and an emitter metal 10 arranged sequentially along a first direction; and...

[0057] The device comprises a P-type superjunction region 3, a gate 6, and an N+ emitter 8. The P-type superjunction region 3 is disposed within the N-drift region 2. The gate 6 is disposed within the P-well region 7 and the secondary epitaxial layer 4. The N+ emitter 8 is disposed within the P-well region 7 and surrounds the gate 6. A gate oxide layer 5 is disposed between the gate 6, the secondary epitaxial layer 4, the P-well region 7, and the N+ emitter 8. A dielectric layer 9 is disposed between the emitter metal 10 and the gate 6. The emitter metal 10 is connected to the N+ emitter 8. The first direction can be the longitudinal direction of the device.

[0058] Comparative Example 2

[0059] The structure of a superjunction insulated gate bipolar transistor in Comparative Example 2 is basically the same as that of the device in Example 1. The difference is that the ion implantation region 13 in Comparative Example 2 is connected to the P-type superjunction region 3. It was found through testing that the connection between the ion implantation region 13 and the P-type superjunction region 3 restricts the current path in the device and affects the current carrying capacity of the device.

[0060] Comparative Example 3

[0061] The structure of a superjunction insulated gate bipolar transistor in Comparative Example 3 is basically the same as that of the device in Example 1. The difference is that the ion implantation region 13 in Comparative Example 3 is connected to the P-collector region 1. It was found through testing that the connection between the ion implantation region 13 and the P-collector region 1 restricts the current path in the device and affects the current carrying capacity of the device.

[0062] The devices in Comparative Examples 1-3 were tested respectively. The test results show that Comparative Examples 1-3 have obvious limitations on the current path of the device in the on-state mode. Although it can reduce the tail current to a certain extent, the conduction characteristics of the device are severely degraded.

[0063] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A superjunction insulated-gate bipolar transistor, comprising a collector, a collector region, a drift region, an epitaxial layer, a well region, and an emitter arranged sequentially along a first direction, and a gate and a superjunction region, wherein the gate is disposed within the well region and the epitaxial layer, characterized in that: The drift region has a first region and a second region arranged sequentially along a first direction. The second region is located between the first region and the collector region. The superjunction region is disposed in the first region, and the second region is provided with an ion implantation region. The ion implantation region can regulate the minority carrier lifetime of the second region, and the ion implantation region has no direct contact with the superjunction region and the collector region. The ion implantation region is formed by hydrogen ion implantation into the drift region. The doping concentration of the ion implantation region is greater than the doping concentration of the drift region, and the hydrogen doping concentration of the ion implantation region is 1E16-1E18.

2. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that: The thickness of the ion implantation region in the first direction is (0.2-0.8)H, where H is the vertical distance between the superjunction region and the collector region in the first direction.

3. The superjunction insulated gate bipolar transistor according to claim 2, characterized in that: The vertical distance between the ion implantation region and the superjunction region in the first direction is (0.1-0.4)H.

4. The superjunction insulated-gate bipolar transistor according to any one of claims 1-3, characterized in that: The drift region is provided with multiple superjunction regions, which are spaced apart in a second direction. The ion implantation region is at least corresponding to the first orthographic projection area of ​​the superjunction region in a first direction, and / or the ion implantation region is corresponding to the second orthographic projection area of ​​the gap between the multiple superjunction regions in a first direction. The second direction is set at an angle to the first direction.

5. The superjunction insulated gate bipolar transistor according to claim 4, characterized in that: An ion implantation region is provided within the drift region, and the ion implantation region is continuously disposed in the first orthographic projection region and the second orthographic projection region.

6. The superjunction insulated gate bipolar transistor according to claim 4, characterized in that: The drift region contains multiple ion implantation regions, which are spaced apart along a second direction. Each of the multiple ion implantation regions is located within the first orthographic projection region, and each ion implantation region corresponds to a superjunction region. Alternatively, each of the multiple ion implantation regions is located within the second orthographic projection region, and each ion implantation region corresponds to the gap between two adjacent superjunction regions. Or, a portion of the multiple ion implantation regions is located within the first orthographic projection region, while the remaining portion is located within the second orthographic projection region.

7. The superjunction insulated gate bipolar transistor according to claim 6, characterized in that: The minimum spacing between two adjacent ion implantation regions in the second direction is 0.1H, and the maximum spacing is 5H.

8. The superjunction insulated gate bipolar transistor according to claim 6 or 7, characterized in that: The plurality of ion implantation regions are equally spaced in the second direction.

9. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that: The ion implantation region is completely surrounded by the drift region.

10. The superjunction insulated gate bipolar transistor according to claim 1, characterized in that: The current collector region, superjunction region, and well region are all of the first conductivity type, while the drift region and emitter are of the second conductivity type.

Images