Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure and a memory. The semiconductor structure preparation method comprises the following steps: providing a substrate; sequentially forming a magnetic composite layer and a transfer mask layer on the substrate; performing a plurality of mask etching processes on the transfer mask layer to form a plurality of mask patterns arranged in an array in the transfer mask layer, and the transfer mask layer between at least part of the mask patterns forms a transfer pattern; and etching the magnetic composite layer along the transfer pattern to form a plurality of columnar structures arranged in an array, and the columnar structures form magnetic tunnel junctions. Adjacent columnar structures are isolated by gaps. The application facilitates the preparation of a semiconductor structure with high-density magnetic tunnel junctions, and can effectively adjust the size of the magnetic tunnel junctions and reduce the difficulty of preparing the semiconductor structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] MRAM (Magnetic Random Access Memory) is a type of non-volatile magnetic random access memory. It features high-speed read and write capabilities, high integration density, and can be repeatedly written to an unlimited number of times.

[0003] MRAM comprises an array of multiple magnetic tunnel junctions (MTJs). An MTJ device can change its resistance state based on the magnetic material within it. It consists of two ferromagnetic layers and a thin insulating layer between them. When a voltage is applied across the junction of an MTJ device, the magnetic moments of the two ferromagnetic layers are aligned, allowing electrons to tunnel through the thin insulating layer, thus turning the MTJ device on. In related technologies, arrayed MTJ devices are fabricated using strip mask patterns and photolithography.

[0004] However, the above-mentioned fabrication methods are difficult to use to fabricate high-density MTJ devices, and it is also difficult to adjust the size of MTJ devices, making the fabrication of MTJ devices quite challenging. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory, which facilitates the fabrication of a semiconductor structure with high-density magnetic tunnel junctions and can effectively adjust the size of the magnetic tunnel junctions, thereby reducing the difficulty of fabricating the semiconductor structure.

[0006] To achieve the above objectives, in a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0007] Provide substrate;

[0008] A magnetic composite layer and a transfer mask layer are sequentially formed on the substrate;

[0009] Multiple mask etching processes are performed on the transfer mask layer to form multiple mask patterns arranged in an array in the transfer mask layer, and at least some of the mask patterns are transferred between the mask layers to form transfer patterns.

[0010] A magnetic composite layer is etched along a transfer pattern to form multiple columnar structures arranged in an array, which form magnetic tunnel junctions; adjacent columnar structures are separated by gaps.

[0011] In the above-mentioned method for fabricating semiconductor structures, it is optional that the mask pattern used in multiple mask etching processes has the same shape, and the shape of the mask pattern includes dot-like shapes.

[0012] In the above-mentioned method for fabricating semiconductor structures, optionally, the process of performing multiple mask etching processes on the transfer mask layer includes:

[0013] A first composite mask layer and a first initial mask layer are sequentially formed on the transfer mask layer;

[0014] The first composite mask layer and the transfer mask layer are etched along the first initial mask layer to form a first mask pattern in the transfer mask layer;

[0015] A second composite mask layer and a second initial mask layer are sequentially formed on the transfer mask layer, with the second composite mask layer covering the first mask pattern;

[0016] The second composite mask layer and the transfer mask layer are etched along the second initial mask layer to form a second mask pattern in the transfer mask layer.

[0017] In the above-described method for fabricating a semiconductor structure, optionally, the first mask pattern includes a plurality of first holes arranged in an array, and the second mask pattern includes a plurality of second holes arranged in an array.

[0018] The first and second holes do not overlap in the transfer mask layer, and the transfer mask layer located between the first and second holes forms a transfer pattern.

[0019] In the above-mentioned method for fabricating semiconductor structures, optionally, the first hole and a portion of the second hole are located in the same row, and the first hole and the second hole located in the same row are arranged alternately along the row direction;

[0020] The other part of the second holes is located between the first holes in two adjacent rows, and is set in a corresponding manner to the first holes in the two adjacent rows, and is set in a staggered manner to the second holes in the two adjacent rows.

[0021] In the above-mentioned method for fabricating semiconductor structures, optionally, the first hole and the second hole are located in different rows, and the first hole and the second hole are arranged alternately along a diagonal direction.

[0022] In the above-described method for fabricating a semiconductor structure, optionally, the first composite mask layer includes a first hard mask layer and a first filling mask layer, wherein the first filling mask layer is located on the side of the first hard mask layer away from the substrate.

[0023] Forming a first composite mask layer on a transfer mask layer includes: forming a first hard mask layer on the transfer mask layer; and forming a first filler mask layer on the first hard mask layer.

[0024] Etching the first composite mask layer along the first initial mask layer includes: etching the first filling mask layer along the first initial mask layer; and etching the first hard mask layer along the first initial mask layer.

[0025] In the above-mentioned method for fabricating a semiconductor structure, optionally, the first initial mask layer includes a plurality of first initial mask patterns arranged in an array;

[0026] Etching the first composite mask layer along the first initial mask layer includes: etching the first filling mask layer along the first initial mask pattern; and etching the first hard mask layer along the first initial mask pattern.

[0027] In the above-described method for fabricating a semiconductor structure, optionally, the second composite mask layer includes a second hard mask layer and a second filler mask layer, wherein the second filler mask layer is located on the side of the second hard mask layer away from the substrate;

[0028] Forming a second composite mask layer on a transfer mask layer includes: forming a second hard mask layer on the transfer mask layer; and forming a second filler mask layer on the second hard mask layer.

[0029] Etching the second composite mask layer along the second initial mask layer includes: etching the second filling mask layer along the second initial mask layer; and etching the second hard mask layer along the second initial mask layer.

[0030] In the above-described method for fabricating a semiconductor structure, optionally, the second initial mask layer includes a plurality of second initial mask patterns arranged in an array;

[0031] Etching the second composite mask layer along the second initial mask layer includes: etching the second filling mask layer along the second initial mask pattern; and etching the second hard mask layer along the second initial mask pattern.

[0032] In the above-described method for fabricating the semiconductor structure, optionally, after forming the magnetic composite layer on the substrate and before forming the transfer mask layer, the following steps are also included:

[0033] A pattern transfer layer is formed, which is located between the magnetic composite layer and the transfer mask layer;

[0034] Before etching the magnetic composite layer along the transfer pattern, the following steps are also included:

[0035] The pattern transfer layer is etched along the transfer pattern.

[0036] In the above-described method for fabricating a semiconductor structure, optionally, the magnetic composite layer includes a second magnetic layer, an insulating layer, and a first magnetic layer stacked sequentially; the first magnetic layer is located on the side of the second magnetic layer away from the substrate.

[0037] Forming a magnetic composite layer on a substrate includes: forming a second magnetic layer on the substrate; forming an insulating layer on the second magnetic layer; and forming a first magnetic layer on the insulating layer.

[0038] Etching the magnetic composite layer along the transfer pattern includes: sequentially etching the first magnetic layer, the insulating layer, and the second magnetic layer along the transfer pattern.

[0039] In the above-described method for fabricating a semiconductor structure, optionally, the first mask pattern has the same shape and size as the first initial mask pattern, and the second mask pattern has the same shape and size as the second initial mask pattern.

[0040] In the above-described method for fabricating a semiconductor structure, optionally, the shapes of both the first initial mask pattern and the second initial mask pattern include dots, and the diameter of the dots in the first initial mask pattern is equal to the diameter of the dots in the second initial mask pattern.

[0041] Secondly, this application provides a semiconductor structure, which is prepared by the above-described semiconductor structure preparation method.

[0042] Thirdly, this application provides a memory including the semiconductor structure described above.

[0043] In the aforementioned memory, optionally, there are multiple semiconductor structures arranged in an array, and an isolation structure is provided between the magnetic tunnel junctions of two adjacent semiconductor structures.

[0044] The semiconductor structure fabrication method, semiconductor structure, and memory provided in this application involve forming a magnetic composite layer and a transfer mask layer on a substrate. Multiple mask etching processes are performed on the transfer mask layer to form multiple mask patterns. Transfer patterns are formed between the mask patterns, and the magnetic composite layer is etched using these transfer patterns to form a columnar structure, which in turn forms a magnetic tunnel junction. Gaps are formed between adjacent columnar structures to improve the stability of the magnetic tunnel junction. Multiple mask etching processes effectively increase the density of magnetic tunnel junction formation. The size of the magnetic tunnel junction can be adjusted by modifying the size of the mask etching patterns, thus effectively reducing the fabrication difficulty of semiconductor structures with magnetic tunnel junctions.

[0045] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0048] Figure 2 A top view of the semiconductor structure forming the first initial mask layer provided in an embodiment of this application;

[0049] Figure 3 for Figure 2 Cross-sectional view of line A-A';

[0050] Figure 4 for Figure 2 Cross-sectional view of B-B';

[0051] Figure 5 This is a schematic diagram of the magnetic composite layer of the semiconductor structure provided in the embodiments of this application;

[0052] Figure 6 A top view of the semiconductor structure forming the first mask pattern provided in the embodiments of this application;

[0053] Figure 7 for Figure 6 Cross-sectional view of C-C';

[0054] Figure 8 for Figure 6 Cross-sectional view of D-D';

[0055] Figure 9 A top view of the semiconductor structure forming the second initial mask layer provided in an embodiment of this application;

[0056] Figure 10 for Figure 9 Cross-sectional view of E-E';

[0057] Figure 11 for Figure 9 Cross-sectional view of F-F';

[0058] Figure 12 A top view of the semiconductor structure forming the second mask pattern provided in an embodiment of this application;

[0059] Figure 13 for Figure 12 Cross-sectional view of G-G';

[0060] Figure 14 for Figure 12 Cross-sectional view of H-H';

[0061] Figure 15 A top view of the formation and transfer pattern of the semiconductor structure provided in the embodiments of this application;

[0062] Figure 16 A top view of the etching pattern transfer layer of the semiconductor structure provided in the embodiments of this application;

[0063] Figure 17 for Figure 16 Cross-sectional view of I-I';

[0064] Figure 18 for Figure 16 Cross-sectional view of J-J';

[0065] Figure 19 This is a schematic diagram of the formation of a columnar structure in the semiconductor structure provided in the embodiments of this application;

[0066] Figure 20 A cross-sectional view of the formation of a columnar structure in the semiconductor structure provided in the embodiments of this application;

[0067] Figure 21 A top view of another second initial mask layer for forming a semiconductor structure provided in the embodiments of this application;

[0068] Figure 22 for Figure 21 A cross-sectional view of K-K' in the diagram;

[0069] Figure 23 for Figure 21 A cross-sectional view of L-L' in the diagram;

[0070] Figure 24 A top view of another second mask pattern for forming a semiconductor structure provided in an embodiment of this application;

[0071] Figure 25 for Figure 24 Cross-sectional view of M-M' in the diagram;

[0072] Figure 26 for Figure 24 A cross-sectional view of N-N' in the diagram;

[0073] Figure 27 A top view of another transfer pattern for forming a semiconductor structure provided in an embodiment of this application;

[0074] Figure 28 A top view of another columnar structure for forming the semiconductor structure provided in the embodiments of this application;

[0075] Figure 29 for Figure 28 A cross-sectional view of O-O' in the diagram;

[0076] Figure 30 for Figure 28 A cross-sectional view of P-P' in the diagram;

[0077] Figure 31 This is a schematic diagram of another columnar structure for forming the semiconductor structure provided in the embodiments of this application.

[0078] Explanation of reference numerals in the attached figures:

[0079] 100, Substrate; 200, Magnetic composite layer; 200a, Columnar structure; 201, First magnetic layer; 202, Insulating layer; 203, Second magnetic layer; 203a, Magnetic base layer; 203b, First composite layer; 203c, First magnetic intermediate layer; 203d, Second composite layer; 203e, Second magnetic intermediate layer; 203f, Magnetic body layer; 300, Transfer mask layer; 301, First mask pattern; 302, Second mask pattern; 303, Transfer pattern; 400, First composite mask layer; 400a, First hard mask layer; 400b, First filling mask layer; 401, First initial mask layer; 500, Second composite mask layer; 500a, Second hard mask layer; 500b, Second filling mask layer; 501, Second initial mask layer; 600, Pattern transfer layer; 700, Gap isolation. Detailed Implementation

[0080] The inventors of this application discovered during their research that MRAM comprises multiple memory cells arranged in an array, each memory cell containing an MTJ and a transistor. Therefore, in MRAM, the multiple magnetic tunnel junctions of the multiple memory cells are also arranged in an array. The MTJ can change its resistance state according to the magnetic material within the device. It comprises two ferromagnetic layers and a thin insulating layer between the two ferromagnetic layers, which are a reference layer and a free layer, respectively. The MTJ is connected to an external circuit via a transistor. When the transistor is turned on, a voltage signal from the external circuit is applied across the junction of the MTJ device through the transistor. This reverses the magnetic moment direction of the free layer. When the magnetic moments of the free layer and the reference layer are in the same direction, electrons can tunnel through the thin insulating layer, and the MTJ device becomes conductive.

[0081] In related technologies, arrayed MTJ devices are fabricated using strip mask patterns and photolithography. The strip mask pattern can consist of two layers, stacked together with their extension directions intersecting. At the intersection, a mask pattern for etching the MTJs is formed. This mask pattern is then transferred to the MTJ prefabrication layer via photolithography, thereby forming an array of multiple MTJs within the MTJ prefabrication layer.

[0082] In the above-described methods, the density of the fabricated MTJ is increased by increasing the density of the strip mask pattern. Alternatively, the size of the fabricated MTJ is adjusted by adjusting the size of the strip mask pattern. However, increasing the density or adjusting the size of the strip mask pattern will cause diffraction during photolithography, resulting in lower imaging accuracy during strip mask pattern transfer. This makes it difficult to fabricate high-density MTJs or to adjust the size of the MTJ, thus making MTJ fabrication quite challenging.

[0083] In view of this, the semiconductor structure fabrication method, semiconductor structure, and memory provided in this application form a magnetic composite layer and a transfer mask layer on a substrate. Multiple mask patterns are formed in the transfer mask layer through multiple mask etching processes. A transfer pattern is formed between the mask patterns, and the magnetic composite layer is etched using the transfer pattern to form a columnar structure, which in turn forms a magnetic tunnel junction. The stability of the magnetic tunnel junction is improved by forming gaps between adjacent columnar structures. Through multiple mask etching processes, the density of magnetic tunnel junctions can be effectively increased. By adjusting the size of the mask etching pattern, the size of the magnetic tunnel junction can be adjusted, thus effectively reducing the fabrication difficulty of semiconductor structures with magnetic tunnel junctions.

[0084] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0085] Figure 1 This is a schematic flowchart of the method for fabricating the semiconductor structure provided in the embodiments of this application, with reference to... Figure 1 As shown, in a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure, comprising:

[0086] S100: Providing a substrate. The substrate 100 provides a structural basis for subsequent structures and processes. The material of the substrate 100 may include any or more of silicon, germanium, silicon-germanium, silicon carbide, silicon-on-insulator substrate, and germanium-on-insulator substrate. In this embodiment, at least a portion of the substrate 100 is a silicon substrate, and the silicon material may be single-crystal silicon. The substrate 100 can be prepared by chemical vapor deposition (CVD).

[0087] S200: A magnetic composite layer and a transfer mask layer are sequentially formed on the substrate.

[0088] Figure 2 This is a top view of the semiconductor structure forming the first initial mask layer provided in an embodiment of this application. Figure 3 for Figure 2 Cross-sectional view of line A-A' Figure 4 for Figure 2 Cross-sectional view of B-B' Figure 5 This is a schematic diagram of the magnetic composite layer of the semiconductor structure provided in an embodiment of this application. (Combined with...) Figures 2 to 5 As shown, the transfer mask layer 300 is located on the side of the magnetic composite layer 200 away from the substrate 100. Both the magnetic composite layer 200 and the transfer mask layer 300 can be formed by deposition.

[0089] The material of the transfer mask layer 300 can be polycrystalline silicon.

[0090] Reference Figure 5 As shown, the magnetic composite layer 200 includes a second magnetic layer 203, an insulating layer 202, and a first magnetic layer 201 stacked sequentially; the first magnetic layer 201 is located on the side of the second magnetic layer 203 away from the substrate 100. Forming the magnetic composite layer 200 on the substrate 100 includes: forming the second magnetic layer 203 on the substrate 100; forming the insulating layer 202 on the second magnetic layer 203; and forming the first magnetic layer 201 on the insulating layer 202. The first magnetic layer 201 can serve as a free layer, and the second magnetic layer 203 can serve as a pinned layer. Along the direction away from the substrate 100, the second magnetic layer 203 may include a magnetic base layer 203a (seed layer), a first composite layer 203b, a first magnetic intermediate layer 203c, a second composite layer 203d, a second magnetic intermediate layer 203e, and a magnetic body layer 203f stacked sequentially.

[0091] Wherein, the first composite layer 203b and the second composite layer 203d can both be Co and Pt composite layers ([Co(x) / Pt(y))). m(Multilayer). The material of the first magnetic intermediate layer 203c may include, but is not limited to, Ru or Ir, and the material of the second magnetic intermediate layer 203e may include, but is not limited to, Ta. The materials of the magnetic body layer 203f and the first magnetic layer 201 may include, but are not limited to, a CoFeB composite layer. The insulating layer 202 may serve as a tunnel barrier to isolate the first magnetic layer 201 and the second magnetic layer 203, and its material may include, but is not limited to, MgO.

[0092] As one feasible implementation method, combined with Figure 2 and Figure 3 As shown, after forming the magnetic composite layer 200 on the substrate 100 and before forming the transfer mask layer 300, a pattern transfer layer 600 is formed, located between the magnetic composite layer 200 and the transfer mask layer 300. This pattern transfer layer 600 serves as a transition layer during the etching process of the magnetic composite layer 200. It not only protects the magnetic composite layer 200 from damage during the etching of the transfer mask layer 300, but also allows the mask pattern transferred from multiple mask etching processes to the transfer mask layer 300 to be transferred entirely to the magnetic composite layer 200 in a single etching process, reducing the difficulty of etching the magnetic composite layer 200 along the mask pattern formed during multiple mask etching processes.

[0093] The pattern transfer layer 600 can be a mask layer including oxides, which can be formed by deposition. The oxide material can be, but is not limited to, silicon oxide, germanium oxide, or silicon-germanium oxide.

[0094] S300: Multiple mask etching processes are performed on the transfer mask layer to form multiple mask patterns arranged in an array in the transfer mask layer, and at least some of the mask patterns are transferred between the mask layers to form transfer patterns.

[0095] In this process, the mask pattern used in multiple mask etchings is the same shape, and the shape of the mask pattern includes dots.

[0096] It should be noted that in this embodiment, the multiple mask etching process is illustrated using a two-stage mask etching process as an example. In some embodiments, to increase the density of the magnetic tunnel junction, the number of mask etching processes can be three or more, and this embodiment does not impose any limitations on this.

[0097] In this embodiment, the first mask etching process may include: sequentially forming a first composite mask layer 400 and a first initial mask layer 401 on the transfer mask layer 300. (Refer to...) Figure 3 and Figure 4 As shown, the first initial mask layer 401 is located on the side of the first composite mask layer 400 away from the substrate 100.

[0098] The first composite mask layer 400 includes a first hard mask layer 400a and a first filler mask layer 400b, with the first filler mask layer 400b located on the side of the first hard mask layer 400a away from the substrate 100. Both the first hard mask layer 400a and the first filler mask layer 400b can be formed by deposition. The material of the first hard mask layer 400a can be a spin-on hard mask (SOH), and the material of the first filler mask layer 400b can be SiON.

[0099] Forming a first composite mask layer 400 on the transfer mask layer 300 includes: forming a first hard mask layer 400a on the transfer mask layer 300; and forming a first filler mask layer 400b on the first hard mask layer 400a. Etching the first composite mask layer 400 along the first initial mask layer 401 includes: etching the first filler mask layer 400b along the first initial mask layer 401; and etching the first hard mask layer 400a along the first initial mask layer 401.

[0100] Specifically, the first initial mask layer 401 includes a plurality of first initial mask patterns arranged in an array. Etching the first composite mask layer 400 along the first initial mask layer 401 includes: etching a first filling mask layer 400b along the first initial mask patterns; and etching a first hard mask layer 400a along the first initial mask patterns. (Refer to...) Figure 2 As shown, the pattern of the first initial mask layer 401 may include multiple dot-shaped patterns arranged in an array. The first initial mask layer 401 may be a photoresist, and its material may be an organic compound sensitive to light (e.g., ultraviolet light), such as polyvinyl cinnamate.

[0101] Figure 6 This is a top view of the semiconductor structure formed by the first mask pattern according to an embodiment of this application. Figure 7 for Figure 6 Cross-sectional view of C-C' Figure 8 for Figure 6 A cross-sectional view of D-D'. Combined with... Figures 6 to 8 As shown, after forming the first composite mask layer 400 and the first initial mask layer 401, the method further includes etching the first composite mask layer 400 and the transfer mask layer 300 along the first initial mask layer 401 to form a first mask pattern 301 in the transfer mask layer 300.

[0102] It should be noted that the above etching can be photolithography, and ultraviolet light can be used to sequentially transfer the pattern of the first initial mask layer 401 to the first composite mask layer 400 and the transfer mask layer 300. (Refer to...) Figure 6 As shown, the pattern of the first initial mask layer 401 is transferred to the transfer mask layer 300 to form the first mask pattern 301.

[0103] In this embodiment, the second mask etching process may include: sequentially forming a second composite mask layer 500 and a second initial mask layer 501 on the transfer mask layer 300, wherein the second composite mask layer 500 covers the first mask pattern 301.

[0104] Figure 9 This is a top view of the semiconductor structure forming the second initial mask layer provided in an embodiment of this application. Figure 10 for Figure 9 Cross-sectional view of E-E' Figure 11 for Figure 9 Cross-sectional view of F-F'. Combined with... Figures 9 to 11 As shown, the second initial mask layer 501 is located on the side of the second composite mask layer 500 away from the substrate 100.

[0105] The second composite mask layer 500 includes a second hard mask layer 500a and a second filler mask layer 500b, with the second filler mask layer 500b located on the side of the second hard mask layer 500a away from the substrate 100. Both the second hard mask layer 500a and the second filler mask layer 500b can be formed by deposition. The material of the second hard mask layer 500a can be spin-coated hard mask SiO2, and the material of the second filler mask layer 500b can be SiON.

[0106] Forming a second composite mask layer 500 on the transfer mask layer 300 includes: forming a second hard mask layer 500a on the transfer mask layer 300; and forming a second filler mask layer 500b on the second hard mask layer 500a. Etching the second composite mask layer 500 along the second initial mask layer 501 includes: etching the second filler mask layer 500b along the second initial mask layer 501; and etching the second hard mask layer 500a along the second initial mask layer 501.

[0107] Specifically, the second initial mask layer 501 includes a plurality of second initial mask patterns arranged in an array. Etching the second composite mask layer 500 along the second initial mask layer 501 includes: etching a second filling mask layer 500b along the second initial mask pattern; and etching a second hard mask layer 500a along the second initial mask pattern. (Refer to...) Figure 9 As shown, the pattern of the second initial mask layer 501 may include multiple dot-shaped patterns arranged in an array. It should be noted that the orthographic projections of the pattern of the second initial mask layer 501 and the pattern of the first initial mask layer 401 onto the substrate 100 are offset from each other. This ensures that the subsequently formed first mask pattern 301 and second mask pattern 302 can form the transfer pattern 303.

[0108] Figure 12 This is a top view of the semiconductor structure forming the second mask pattern provided in an embodiment of this application. Figure 13 for Figure 12 Cross-sectional view of G-G' Figure 14 for Figure 12 A cross-sectional view of H-H'. Combined with... Figures 12 to 14 As shown, the second composite mask layer 500 and the transfer mask layer 300 are etched along the second initial mask layer 501 to form a second mask pattern 302 in the transfer mask layer 300.

[0109] It should be noted that the etching described above can also be photolithography, transferring the pattern of the second initial mask layer 501 sequentially to the second composite mask layer 500 and the transfer mask layer 300. (Refer to...) Figure 12 As shown, the pattern of the second initial mask layer 501 is transferred to the transfer mask layer 300 to form the second mask pattern 302.

[0110] Specifically, at the H-H' section line, only the second mask pattern 302 exists, therefore the H-H' section view shows the second mask patterns 302 arranged at intervals. At the G-G' section line, the first mask pattern 301 and the second mask pattern 302 coexist and are connected to each other, therefore at the G-G' section view, there is no transfer mask layer 300.

[0111] Figure 15 A top view of the formation and transfer pattern of the semiconductor structure provided in the embodiments of this application, with reference to... Figure 15 As shown, a first mask pattern 301 and a second mask pattern 302 form a mask pattern, and a transfer pattern 303 is formed between some of the mask patterns. Specifically, the first mask pattern 301 includes a plurality of first holes arranged in an array, and the second mask pattern 302 includes a plurality of second holes arranged in an array. The first holes and the second holes do not overlap in the transfer mask layer 300, and the transfer mask layer 300 located between the first holes and the second holes forms a transfer pattern.

[0112] In this embodiment, the first hole and a portion of the second holes are located in the same row, and the first and second holes in the same row are arranged alternately along the row direction;

[0113] The other part of the second holes is located between the first holes in two adjacent rows, and is set in a corresponding manner to the first holes in the two adjacent rows, and is set in a staggered manner to the second holes in the two adjacent rows.

[0114] It should be noted that the column direction can be... Figure 15 The direction indicated by y in the text can be the row direction. Figure 15The x-axis indicates the direction. The first row of mask patterns along the -y direction includes both the first hole of the first mask pattern 301 and the second hole of the second mask pattern 302, which can be interconnected. The second row of mask patterns contains only the second hole of the second mask pattern 302.

[0115] In one feasible implementation, both the first and second initial mask patterns include dots in their shapes, with the diameter of the dots in the first and second initial mask patterns being equal. This improves the structural regularity of the subsequently formed columnar structure 200a and reduces the fabrication difficulty.

[0116] Of course, in some embodiments, the dot diameters of the first initial mask pattern and the second initial mask pattern may be unequal. During the fabrication process, the sizes of the first holes in the first mask pattern 301 and the second holes in the second mask pattern 302 can be adjusted by adjusting the dot diameters of the first and second initial mask patterns, thereby adjusting the size of the transfer pattern 303 and ultimately the size of the magnetic tunnel junction. This reduces the difficulty of adjusting the size of the magnetic tunnel junction and lowers the fabrication difficulty of the semiconductor structure.

[0117] After forming the transfer pattern 303, the process further includes: S400: etching a magnetic composite layer along the transfer pattern to form multiple columnar structures arranged in an array, the columnar structures forming a magnetic tunnel junction; adjacent columnar structures are separated by gaps.

[0118] Figure 16 This is a top view of the etching pattern transfer layer of the semiconductor structure provided in an embodiment of this application. Figure 17 for Figure 16 Cross-sectional view of I-I' Figure 18 for Figure 16 Cross-sectional view of J-J'. (Refer to...) Figures 16 to 18 As shown, before etching the magnetic composite layer 200 along the transfer pattern 303, the process further includes etching the pattern transfer layer 600 along the transfer pattern 303. This etching process can be photolithography, etching along the transfer pattern 303 to remove the portion of the pattern transfer layer 600 not covered by the transfer pattern 303, while retaining the portion covered by the transfer pattern 303. Then, the pattern transfer layer 600 is removed by wet etching, thus forming... Figure 17 and Figure 18 The structure.

[0119] Figure 19 This is a schematic diagram of the formation of a columnar structure in the semiconductor structure provided in an embodiment of this application. Figure 20 A cross-sectional view showing the formation of a columnar structure in a semiconductor structure provided in an embodiment of this application. (In conjunction with...) Figure 19 and Figure 20 As shown, specifically, etching the magnetic composite layer 200 along the transfer pattern 303 includes: sequentially etching the first magnetic layer 201, the insulating layer 202, and the second magnetic layer 203 along the transfer pattern 303.

[0120] In this embodiment, refer to Figure 19 As shown, the resulting columnar structure 200a can be arranged in a square shape. Figure 19 (The part outlined by the dashed line) This can improve the regularity of the columnar structure 200a and enhance the structural stability of the magnetic tunnel structure.

[0121] It should be noted that the gap isolation 700 between adjacent columnar structures 200a can be formed by spacing adjacent columnar structures 200a apart, with a gap between them. Alternatively, an insulating material can be filled between adjacent columnar structures 200a, forming the gap isolation 700. This embodiment does not limit the specific structure of the gap isolation 700. The gap isolation 700 can effectively block the transmission of electrical signals between adjacent columnar structures 200a, thereby ensuring the stability of electrical signal transmission within the columnar structures 200a and improving the performance stability of the semiconductor structure. Furthermore, when the gap isolation 700 is formed of an insulating material, the gap material can provide supporting force for the columnar structures 200a, preventing them from tilting or collapsing, thereby improving the structural stability of the columnar structures 200a and the semiconductor structure.

[0122] The following describes another mask pattern structure provided by the embodiments of this application. Compared with the mask pattern in the above embodiments, the arrangement of the second mask pattern 302 is different.

[0123] The first mask etching process in this embodiment is the same as the first mask etching process in the above embodiment, and will not be described again here. In particular, the second mask etching process in this embodiment is different. Specifically, Figure 21 A top view of another second initial mask layer for forming a semiconductor structure provided in this application embodiment. Figure 22 for Figure 21 The cross-sectional view of K-K' in the middle. Figure 23 for Figure 21 The cross-sectional view of L-L' in the diagram. (Refer to...) Figures 21 to 23 As shown, the dot pattern of the second initial mask layer 501 and the dot pattern of the first initial mask layer 401 are also offset from each other on the substrate 100. However, in this embodiment, the dot pattern of the second initial mask layer 501 and the dot pattern of the first initial mask layer 401 are located in different rows on the substrate 100 and are offset from each other.

[0124] In this embodiment, the dot patterns of the first initial mask layer 401 and the second initial mask layer 501 are transferred to the transfer mask layer 300 to form a mask pattern. Figure 24 A top view of another second mask pattern for forming a semiconductor structure provided in this application embodiment. Figure 25 for Figure 24 The cross-sectional view of M-M' in the middle. Figure 26 for Figure 24 The cross-sectional view of N-N' in the diagram. Combined with... Figures 24 to 26 As shown, the first hole of the first mask pattern 301 and the second hole of the second mask pattern 302 are located in different rows, and the first hole and the second hole are arranged alternately along the diagonal direction.

[0125] Figure 27 A top view of another transfer pattern for forming a semiconductor structure provided in this application embodiment, referring to... Figure 27 As shown, the column direction is Figure 27 The direction indicated by y is the row direction. Figure 27 The direction indicated by x in the middle is the diagonal direction. Figure 27 The direction indicated by q, the x-direction, and the y-direction are all located in the same plane, with the q-direction being the diagonal direction of the array formed by the x-direction and the y-direction. In the first row of mask patterns along the -y direction, only the first hole of the first mask pattern 301 exists. In the mask patterns located in the second row, only the second hole of the second mask pattern 302 exists, and the first holes of the first mask pattern 301 and the second holes of the second mask pattern 302 in different rows are staggered.

[0126] The first hole of the first mask pattern 301 and the second hole of the second mask pattern 302 are arranged alternately along a diagonal q direction or a direction parallel to the q direction.

[0127] Figure 28 This is a top view of another columnar structure formed for the semiconductor structure provided in the embodiments of this application. Figure 29 for Figure 28 Cross-sectional view of O-O' in the middle. Figure 30 for Figure 28 The cross-sectional view of P-P' in the diagram. After the transfer pattern 303 is formed, the pattern transfer layer 600 and the magnetic composite layer 200 can be etched along the etch hole. This step is the same as in the first embodiment described above, and will not be repeated here.

[0128] Figure 31 This is a schematic diagram illustrating another columnar structure for forming the semiconductor structure provided in this application embodiment. (Refer to...) Figure 31 As shown, the resulting columnar structure 200a can be arranged in a hexagonal shape. Figure 31(The part outlined by the dashed line) This can increase the density of the columnar structure 200a and the area utilization on the substrate 100, thereby increasing the density of the magnetic tunnel junction.

[0129] Secondly, embodiments of this application provide a semiconductor structure, which is fabricated using the above-described fabrication method. This semiconductor structure can be a magnetic tunnel junction.

[0130] Thirdly, embodiments of this application provide a memory including the aforementioned semiconductor structure. This memory can be an MRAM memory, which may include multiple memory cells arranged in an array. Each memory cell may include a transistor and the aforementioned magnetic tunnel junction. The magnetic tunnel junction is connected to an external circuit via the transistor. When the transistor is turned on, a voltage signal from the external circuit is applied across the junction of the magnetic tunnel junction. This reverses the magnetic moment direction of the free layer in the magnetic tunnel junction. When the magnetic moment directions of the free layer and the reference layer are the same, electrons can tunnel through the thin insulating layer 202, the magnetic tunnel junction becomes active, and the voltage signal from the external circuit is stored in the memory cell.

[0131] As one feasible implementation, multiple semiconductor structures are arranged in an array, with an isolation structure between the magnetic tunnel junctions of adjacent semiconductor structures. Since the memory cells are arranged in an array, the magnetic tunnel junctions in each memory cell are also arranged in an array. The isolation structure between adjacent magnetic tunnel junctions can be made of an insulating material, effectively blocking the transmission of electrical signals between adjacent magnetic tunnel junctions, thereby ensuring the performance stability of each memory cell. Unlike the gap isolation 700 described above, this isolation structure can be a shallow trench isolation (STI) formed in the substrate 100, which can be formed before the magnetic tunnel junction fabrication and is mainly used to block signal interference between adjacent memory cells.

[0132] Other technical features in the semiconductor structure and memory of this application are the same as those in the embodiments of the above-described semiconductor structure preparation method, and can achieve the same technical effects, and will not be described in detail here.

[0133] In the above description, it should be understood that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection or an indirect connection through an intermediate medium, or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. The terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "multiple" means two or more, unless otherwise precisely specified.

[0134] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0135] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A magnetic composite layer and a transfer mask layer are sequentially formed on the substrate; Multiple mask etching processes are performed on the transfer mask layer to form multiple mask patterns arranged in an array within the transfer mask layer, wherein at least a portion of the mask patterns form transfer patterns on the transfer mask layer, specifically including: A first composite mask layer and a first initial mask layer are sequentially formed on the transfer mask layer; The first composite mask layer and the transfer mask layer are etched along the first initial mask layer to form a first mask pattern in the transfer mask layer; A second composite mask layer and a second initial mask layer are sequentially formed on the transfer mask layer, wherein the second composite mask layer covers the first mask pattern; The second composite mask layer and the transfer mask layer are etched along the second initial mask layer to form a second mask pattern in the transfer mask layer; wherein the first mask pattern includes a plurality of first holes arranged in an array, the second mask pattern includes a plurality of second holes arranged in an array, the first holes and the second holes do not overlap in the transfer mask layer, the transfer mask layer located between the first holes and the second holes forms the transfer pattern, the first holes and a portion of the second holes are located in the same row, the first holes and the second holes located in the same row are alternately arranged along the row direction, and another portion of the second holes are located between two adjacent rows of first holes and are corresponding to the first holes in the two adjacent rows, and are offset from the second holes in the two adjacent rows; The magnetic composite layer is etched along the transfer pattern to form a plurality of columnar structures arranged in an array, the columnar structures forming magnetic tunnel junctions; adjacent columnar structures are separated by gaps.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The mask pattern used in multiple mask etching processes is the same shape, and the shape of the mask pattern includes dots.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first composite mask layer includes a first hard mask layer and a first filler mask layer, wherein the first filler mask layer is located on the side of the first hard mask layer away from the substrate; Forming a first composite mask layer on the transfer mask layer includes: forming a first hard mask layer on the transfer mask layer; and forming a first filler mask layer on the first hard mask layer. Etching the first composite mask layer along the first initial mask layer includes: etching the first filling mask layer along the first initial mask layer; and etching the first hard mask layer along the first initial mask layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first initial mask layer includes a plurality of first initial mask patterns arranged in an array; Etching the first composite mask layer along the first initial mask layer includes: etching the first filling mask layer along the first initial mask pattern; The first hard mask layer is etched along the first initial mask pattern.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The second composite mask layer includes a second hard mask layer and a second filler mask layer, wherein the second filler mask layer is located on the side of the second hard mask layer away from the substrate; Forming a second composite mask layer on the transfer mask layer includes: forming a second hard mask layer on the transfer mask layer; and forming a second filler mask layer on the second hard mask layer. Etching the second composite mask layer along the second initial mask layer includes: etching the second filling mask layer along the second initial mask layer; and etching the second hard mask layer along the second initial mask layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The second initial mask layer includes a plurality of second initial mask patterns arranged in an array; Etching the second composite mask layer along the second initial mask layer includes: etching the second filling mask layer along the second initial mask pattern; The second hard mask layer is etched along the second initial mask pattern.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the magnetic composite layer on the substrate and before forming the transfer mask layer, the process further includes: A pattern transfer layer is formed, the pattern transfer layer being located between the magnetic composite layer and the transfer mask layer; Before etching the magnetic composite layer along the transfer pattern, the process further includes: The pattern transfer layer is etched along the transfer pattern.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The magnetic composite layer includes a second magnetic layer, an insulating layer, and a first magnetic layer stacked sequentially. Forming the magnetic composite layer on the substrate includes: forming a second magnetic layer on the substrate; forming the insulating layer on the second magnetic layer; and forming the first magnetic layer on the insulating layer. Etching the magnetic composite layer along the transfer pattern includes: sequentially etching the first magnetic layer, the insulating layer, and the second magnetic layer along the transfer pattern.

9. The method for preparing a semiconductor structure according to claim 6, characterized in that, The first mask pattern has the same shape and size as the first initial mask pattern, and the second mask pattern has the same shape and size as the second initial mask pattern.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, Both the first initial mask pattern and the second initial mask pattern include dots in their shapes, and the diameter of the dots in the first initial mask pattern is equal to the diameter of the dots in the second initial mask pattern.

11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the semiconductor structure preparation method according to any one of claims 1-10.

12. A memory, characterized in that, Includes the semiconductor structure described in claim 11.

13. The memory according to claim 12, characterized in that, The semiconductor structure is multiple, and the multiple semiconductor structures are arranged in an array. An isolation structure is provided between the magnetic tunnel junctions of two adjacent semiconductor structures.

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