An operational amplifier structure using dynamic compensation in a switched capacitor integrator of a ΣΔ modulator

Abstract

The present invention discloses an operational amplifier structure using dynamic compensation in a ΣΔ modulator switched capacitor integrator, comprising a reference voltage input terminal, a feedback DAC capacitor, a sampling capacitor, a signal input terminal, an integrating capacitor, a fully differential folded cascode two-stage operational amplifier, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control switch. The structure has low power consumption.

Description

Technical Field

[0001] The present invention relates to a single-ended structure of a switched capacitor integrator, and in particular to an operational amplifier structure using dynamic compensation in a ΣΔ modulator switched capacitor integrator. Background Art

[0002] ΣΔ analog-to-digital converters (ADCs), one of the most significant innovations in analog integrated circuit design in recent decades, have been widely adopted in low-frequency applications such as battery management systems (BMS), temperature sensors, and digital audio signal processing. The performance of the ΣΔ modulator is crucial for these applications. A ΣΔ modulator primarily consists of a switched capacitor integrator, a quantizer, and a corresponding analog-to-digital converter (DAC). The operational amplifier (op amp) in the switched capacitor integrator accounts for a significant portion of the modulator's power consumption. Therefore, designing a low-power switched capacitor integrator is crucial for minimizing the power consumption of the ΣΔ ADC. Summary of the Invention

[0003] The object of the present invention is to overcome the above-mentioned shortcomings of the prior art and to provide an operational amplifier structure using dynamic compensation in a switched capacitor integrator of a ΣΔ modulator, which has low power consumption.

[0004] To achieve the above-mentioned object, the operational amplifier structure using dynamic compensation in the ΣΔ modulator switched capacitor integrator of the present invention includes a reference voltage input terminal, a feedback DAC capacitor, a sampling capacitor, a signal input terminal, an integrating capacitor, a fully differential folded cascode two-stage operational amplifier, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, and a seventh control switch;

[0005] The reference voltage input terminal is connected to one end of the second control switch and one end of the feedback DAC capacitor via the first control switch; the other end of the feedback DAC capacitor is connected to one end of the third control switch, one end of the fourth control switch, one end of the fifth control switch, and one end of the sampling capacitor; the other end of the sampling capacitor is connected to one end of the sixth control switch and one end of the seventh control switch; the other end of the seventh control switch is connected to the signal input terminal; the other end of the fourth control switch is connected to one end of the integrating capacitor and the inverting input terminal of the fully differential folded cascode two-stage operational amplifier; the other end of the integrating capacitor is connected to the output terminal of the fully differential folded cascode two-stage operational amplifier and one end of the output capacitor;

[0006] The other end of the second control switch, the other end of the third control switch, the other end of the fifth control switch, the other end of the sixth control switch, the non-inverting input end of the fully differential folded cascode two-stage operational amplifier and the other end of the output capacitor are all grounded.

[0007] The phases of the control signals of the first control switch, the third control switch, the fifth control switch, and the seventh control switch are all the same.

[0008] The phases of the control signals of the second control switch, the fourth control switch, and the sixth control switch are all the same.

[0009] The fully differential folded cascode two-stage operational amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth PMOS transistor, a sixteenth NMOS transistor, a seventeenth PMOS transistor, an eighth PMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first resistor, a second resistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, a twenty-first PMOS transistor, a twenty-second PMOS transistor, a fifth capacitor, a sixth capacitor, a third resistor, a fourth resistor, a negative input terminal, a positive input terminal, a first bias voltage node, a second bias voltage node, a third bias voltage node, a fourth bias voltage node, a power supply, a common-mode feedback voltage node, a positive output terminal, a negative output terminal, and a reference voltage terminal;

[0010] The gate of the first NMOS transistor is connected to the positive input terminal, the source of the first NMOS transistor is connected to the drain of the sixth NMOS transistor, and the drain of the first NMOS transistor is connected to the source of the eighth PMOS transistor;

[0011] The gate of the second NMOS transistor is connected to the negative input terminal, the source of the second NMOS transistor is connected to the drain of the sixth NMOS transistor, and the drain of the second NMOS transistor is connected to the source of the ninth PMOS transistor;

[0012] The gate of the third NMOS transistor and the gate of the fourth NMOS transistor are connected to the third bias voltage node; the drain of the third NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the third NMOS transistor is connected to the drain of the fifth NMOS transistor;

[0013] The drain of the fourth NMOS transistor is connected to the drain of the ninth PMOS transistor, and the source of the fourth NMOS transistor is connected to the drain of the seventh NMOS transistor; the gate of the fifth NMOS transistor, the gate of the sixth NMOS transistor, the gate of the seventh NMOS transistor, and the gate of the eighteenth NMOS transistor are connected to the fourth bias voltage node; the source of the fifth NMOS transistor, the source of the sixth NMOS transistor, the source of the seventh MOS transistor, and the source of the eighteenth NMOS transistor are grounded;

[0014] The gate of the eighth PMOS transistor and the gate of the ninth PMOS transistor are connected to the second bias voltage node;

[0015] The gate of the tenth PMOS transistor and the gate of the eleventh PMOS transistor are connected to the first bias voltage node; the source of the tenth PMOS transistor, the source of the eleventh PMOS transistor, the source of the twelfth PMOS transistor, the source of the thirteenth PMOS transistor, the source of the fifteenth PMOS transistor, and the source of the seventeenth PMOS transistor are connected to the power supply;

[0016] The gate of the twelfth PMOS transistor, the gate of the thirteenth PMOS transistor, the gate of the twenty-first PMOS transistor, and the gate of the twenty-second PMOS transistor are connected to the common-mode feedback voltage node;

[0017] The drain of the tenth PMOS transistor and the drain of the twelfth PMOS transistor are connected to the source of the eighth PMOS transistor;

[0018] The drain of the eleventh PMOS transistor and the drain of the thirteenth PMOS transistor are connected to the source of the ninth PMOS transistor;

[0019] The gate of the fourteenth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the fourteenth NMOS transistor is grounded, and the drain of the fourteenth NMOS transistor and the drain of the fifteenth PMOS transistor are connected to the positive output terminal;

[0020] The gate of the sixteenth NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the sixteenth NMOS transistor is grounded, and the drain of the sixteenth NMOS transistor and the drain of the seventeenth PMOS transistor are connected to the negative output terminal;

[0021] The positive terminal of the first capacitor is connected to the positive output terminal Vout+, and the negative terminal of the first capacitor is connected to one end of the first switch;

[0022] The positive end of the second capacitor is connected to the positive output terminal, and the other end of the first switch and the negative end of the second capacitor are connected to one end of the first resistor;

[0023] The other end of the first resistor is connected to the gate of the fourteenth NMOS transistor;

[0024] The positive terminal of the third capacitor is connected to the negative output terminal, and the negative terminal of the third capacitor is connected to the second switch;

[0025] The positive terminal of the fourth capacitor is connected to the negative output terminal, and the negative terminal of the fourth capacitor is connected to one end of the second resistor;

[0026] The other end of the second resistor is connected to the gate of the sixteenth NMOS transistor;

[0027] The drain of the eighteenth NMOS transistor is connected to the sources of the nineteenth NMOS transistor and the twentieth NMOS transistor;

[0028] A gate of the nineteenth NMOS transistor is connected to the reference voltage terminal, and a drain of the nineteenth NMOS transistor is connected to the drain of the twenty-first PMOS transistor;

[0029] a gate of the twentieth NMOS transistor is connected to the positive terminal of the fifth capacitor and the positive terminal of the sixth capacitor, and a drain of the twentieth NMOS transistor is connected to the drain of the twenty-second PMOS transistor;

[0030] The drain of the twenty-first PMOS transistor is connected to the gate of the twenty-first PMOS transistor;

[0031] The drain of the twenty-second PMOS transistor is connected to the gate of the twenty-second PMOS transistor;

[0032] The negative terminal of the fifth capacitor is connected to the positive output terminal;

[0033] The negative terminal of the sixth capacitor is connected to the negative output terminal;

[0034] One end of the third resistor is connected to the positive output terminal, and the other end of the third resistor is connected to the positive terminal of the fifth capacitor;

[0035] One end of the fourth resistor is connected to the negative output terminal, and the other end of the fourth resistor is connected to the positive terminal of the fifth capacitor.

[0036] The present invention has the following beneficial effects:

[0037] The operational amplifier structure using dynamic compensation in the switched capacitor integrator of the ΣΔ modulator described in the present invention adopts a fully differential folded cascode two-stage operational amplifier during specific operation. Under the premise of ensuring the stability of the operational amplifier loop, only the operational amplifier Miller compensation capacitor is dynamically adjusted, so that the operational amplifier can obtain sufficient bandwidth in both the sampling phase and the integration phase, and the phase margin has no redundancy. Compared with traditional design methods, the power consumption of the ΣΔ modulator is saved, the structure is simple, the operation is convenient, and the practicality is extremely strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a circuit schematic diagram of a fully differential folded cascode two-stage operational amplifier of the present invention;

[0039] Figure 2a It is a structural diagram of the present invention;

[0040] Figure 2b This is the clock timing diagram when the Φ1 phase and the Φ2 phase do not overlap;

[0041] Figure 3 This is an equivalent model diagram of a two-stage operational amplifier in the switched capacitor integrator of the present invention;

[0042] Figure 4 The closed-loop frequency response and loop phase response diagram of the operational amplifier in the switched capacitor integrator of the present invention under two phases;

[0043] Figure 5 This is a diagram of an equivalent model of a two-stage operational amplifier for dynamically adjusting the Miller capacitance in the present invention;

[0044] Figure 6 The closed-loop frequency response and loop phase response diagram of the operation amplifier in two phases in the present invention are shown. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only embodiments of a part of the present invention, not all embodiments, and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts disclosed in the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0046] The accompanying drawings illustrate schematic diagrams of the structures of the disclosed embodiments of the present invention. These figures are not drawn to scale; for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0047] refer to Figure 2a and Figure 2b The operational amplifier structure using dynamic compensation in the ΣΔ modulator switched capacitor integrator of the present invention includes a reference voltage input terminal Vref, a feedback DAC capacitor C ref , sampling capacitor Cs, signal input terminal Vin, integration capacitor C i , a fully differential folded cascode two-stage operational amplifier, a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, a sixth control switch K6 and a seventh control switch K7;

[0048] The reference voltage input terminal Vref is connected to the first control switch K1 and one end of the second control switch K2 and the feedback DAC capacitor C ref One end of the feedback DAC capacitor C ref The other end of the sampling capacitor Cs is connected to one end of the third control switch K3, one end of the fourth control switch K4, one end of the fifth control switch K5 and one end of the sampling capacitor Cs. The other end of the sampling capacitor Cs is connected to one end of the sixth control switch K6 and one end of the seventh control switch K7. The other end of the seventh control switch K7 is connected to the signal input terminal Vin. The other end of the fourth control switch K4 is connected to the integration capacitor Cs. i One end of the fully differential folded cascode two-stage operational amplifier is connected to the inverting input terminal, and the integrating capacitor C i The other end is connected to the output of the fully differential folded common source and common gate two-stage op amp and the output capacitor C L One end of the

[0049] The other end of the second control switch K2, the other end of the third control switch K3, the other end of the fifth control switch K5, the other end of the sixth control switch K6, the non-inverting input end of the fully differential folded cascode two-stage operational amplifier, and the output capacitor C L The other ends are grounded.

[0050] The control signals of the first control switch K1, the third control switch K3, the fifth control switch K5 and the seventh control switch K7 all have a phase of Φ1, and the control signals of the second control switch K2, the fourth control switch K4 and the sixth control switch K6 all have a phase of Φ2.

[0051] refer to Figure 1 The fully differential folded cascode two-stage operational amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth NMOS transistor M14, a fifteenth PMOS transistor M15, a sixteenth NMOS transistor M16, a seventeenth PMOS transistor M17, an eighth PMOS transistor M8, and a first capacitor C C1 , the second capacitor C C2 , the third capacitor C C3 , the fourth capacitor C C4 , a first resistor R1, a second resistor R2, an eighteenth NMOS transistor M18, a nineteenth NMOS transistor M19, a twentieth NMOS transistor M20, a twenty-first PMOS transistor M21, a twenty-second PMOS transistor M22, a fifth capacitor C5, a sixth capacitor C6, a third resistor R3, a fourth resistor R4, a negative input terminal Vin-, a positive input terminal Vin+, a first bias voltage node VB1, a second bias voltage node VB2, a third bias voltage node VB3, a fourth bias voltage node VB4, a power supply, a common-mode feedback voltage node VCMFB, a positive output terminal Vout+, a negative output terminal Vout-, and a reference voltage terminal V REF ;

[0052] The gate of the first NMOS transistor M1 is connected to the positive input terminal Vin+, the source of the first NMOS transistor M1 is connected to the drain of the sixth NMOS transistor M6, and the drain of the first NMOS transistor M1 is connected to the source of the eighth PMOS transistor M9;

[0053] The gate of the second NMOS transistor M2 is connected to the negative input terminal Vin-, the source of the second NMOS transistor M2 is connected to the drain of the sixth NMOS transistor M6, and the drain of the second NMOS transistor M2 is connected to the source of the ninth PMOS transistor M9;

[0054] The gate of the third NMOS transistor M3 and the gate of the fourth NMOS transistor M4 are connected to the third bias voltage node VB3; the drain of the third NMOS transistor M3 is connected to the drain of the eighth PMOS transistor M8, and the source of the third NMOS transistor M3 is connected to the drain of the fifth NMOS transistor M5;

[0055] The drain of the fourth NMOS transistor M4 is connected to the drain of the ninth PMOS transistor M9, and the source of the fourth NMOS transistor M4 is connected to the drain of the seventh NMOS transistor M7; the gate of the fifth NMOS transistor M5, the gate of the sixth NMOS transistor M6, the gate of the seventh NMOS transistor M7, and the gate of the eighteenth NMOS transistor M18 are connected to the fourth bias voltage node VB4; the source of the fifth NMOS transistor M5, the source of the sixth NMOS transistor M6, the source of the seventh MOS transistor M7, and the source of the eighteenth NMOS transistor M18 are grounded;

[0056] The gate of the eighth PMOS transistor M8 and the gate of the ninth PMOS transistor M9 are connected to the second bias voltage node VB2;

[0057] The gate of the tenth PMOS transistor M10 and the gate of the eleventh PMOS transistor M11 are connected to the first bias voltage node VB1; the source of the tenth PMOS transistor M10, the source of the eleventh PMOS transistor M11, the source of the twelfth PMOS transistor M12, the source of the thirteenth PMOS transistor M13, the source of the fifteenth PMOS transistor M15, and the source of the seventeenth PMOS transistor M17 are connected to the power supply;

[0058] The gate of the twelfth PMOS transistor M12, the gate of the thirteenth PMOS transistor M13, the gate of the twenty-first PMOS transistor M21, and the gate of the twenty-second PMOS transistor M22 are connected to the common-mode feedback voltage node VCMFB;

[0059] The drain of the tenth PMOS transistor M10 and the drain of the twelfth PMOS transistor M12 are connected to the source of the eighth PMOS transistor M8;

[0060] The drain of the eleventh PMOS transistor M11 and the drain of the thirteenth PMOS transistor M13 are connected to the source of the ninth PMOS transistor M9;

[0061] The gate of the fourteenth NMOS transistor M14 is connected to the drain of the third NMOS transistor M3, the source of the fourteenth NMOS transistor M14 is grounded, and the drain of the fourteenth NMOS transistor M14 and the drain of the fifteenth PMOS transistor M15 are connected to the positive output terminal Vout+;

[0062] The gate of the sixteenth NMOS transistor M16 is connected to the drain of the fourth NMOS transistor M4, the source of the sixteenth NMOS transistor M16 is grounded, and the drain of the sixteenth NMOS transistor M16 and the drain of the seventeenth PMOS transistor M17 are connected to the negative output terminal Vout-;

[0063] The first capacitor C C1 The positive terminal of the first capacitor C is connected to the positive output terminal Vout+. C1 The negative terminal is connected to one end of the first switch S1;

[0064] The second capacitor C C2 The positive end of the first switch S1 is connected to the positive output terminal Vout+, and the other end of the first switch S1 and the second capacitor C C2 The negative end of is connected to one end of the first resistor R1;

[0065] The other end of the first resistor R1 is connected to the gate of the fourteenth NMOS transistor M14;

[0066] The third capacitor C C3 The positive terminal is connected to the negative output terminal Vout-, and the third capacitor C C3 The negative terminal is connected to the second switch S2;

[0067] The fourth capacitor C C4 The positive terminal of the fourth capacitor C is connected to the negative output terminal Vout-. C4 The negative end of is connected to one end of the second resistor R2;

[0068] The other end of the second resistor R2 is connected to the gate of the sixteenth NMOS transistor M14;

[0069] The drain of the eighteenth NMOS transistor M18 is connected to the sources of the nineteenth NMOS transistor M19 and the twentieth NMOS transistor M20;

[0070] The gate of the nineteenth NMOS transistor M19 is connected to the reference voltage terminal V REF The drain of the nineteenth NMOS transistor M19 is connected to the drain of the twenty-first PMOS transistor M21;

[0071] The gate of the twentieth NMOS transistor M20 is connected to the positive terminal of the fifth capacitor C5 and the positive terminal of the sixth capacitor C6, and the drain of the twentieth NMOS transistor M20 is connected to the drain of the twenty-second PMOS transistor M22;

[0072] The drain of the twenty-first PMOS transistor M21 is connected to the gate of the twenty-first PMOS transistor M21;

[0073] The drain of the twenty-second PMOS transistor M22 is connected to the gate of the twenty-second PMOS transistor M22;

[0074] The negative terminal of the fifth capacitor C5 is connected to the positive output terminal Vout+;

[0075] The negative terminal of the sixth capacitor C6 is connected to the negative output terminal Vout-;

[0076] One end of the third resistor R3 is connected to the positive output terminal Vout+, and the other end of the third resistor R3 is connected to the positive end of the fifth capacitor C5;

[0077] One end of the fourth resistor R4 is connected to the negative output terminal Vout−, and the other end of the fourth resistor R4 is connected to the positive end of the fifth capacitor C5.

[0078] refer to Figure 1 Under the same conditions, NMOS transistors have higher mobility than PMOS transistors. Therefore, the first stage of the fully differential folded cascode two-stage op amp of the present invention uses NMOS transistors as differential pair inputs to increase the speed of the op amp. The folded cascode structure of the first stage op amp not only improves gain but also enhances the noise suppression capability of the power supply. The second stage op amp is used to achieve a larger output swing. Since the fully differential op amp cannot determine the output voltage value, the present invention also designs a common-mode feedback circuit to stabilize the output voltage. Assuming the output resistance of the MOS transistor is r o , the transconductance is g m , the DC gain of the two-stage operational amplifier proposed in the present invention is:

[0079] Av=g m1 ·(g m3 r o3 r o5 ) / / [g m8 r o8 (r o1 / / r o10 / / r o12 )]·g m16 (r o16 / / r o17 )

[0080] refer to Figure 3 A detailed analysis of the closed-loop characteristics of the two-stage op amp in the switched capacitor integrator is given below:

[0081] G m1 and G m2 are the transconductance of the first and second stages of the op amp, β is the loop feedback coefficient, and C C is the Miller compensation capacitor, C eq is the equivalent load capacitance. The main pole of the two-stage op amp is located at the output node of the first stage. The equivalent output capacitance here is:

[0082] C=G m2 ·(r o2 / / ro15 )·C c ,

[0083] The equivalent output resistance is:

[0084] R=1 / G m =1 / β·G m1 ·G m2 ·(r o2 / / ro15 ),

[0085] Then the main pole frequency, that is, the bandwidth of the op amp, is:

[0086] BW=1 / RC=β·G m1 / C c .

[0087] In the traditional design process of the switched capacitor integrator, in order to improve the bandwidth, it is generally chosen to make the first-stage input transconductance G of the op amp as large as possible. m1 Designed to be as large as possible, and g m ∝I, so a larger current will be allocated during the op amp design process, which will increase the overall power consumption.

[0088] The present invention reduces the design difficulty of the operational amplifier and m1 Under the premise of reference Figure 4 , dynamically adjust the Miller compensation capacitance as the switching capacitor phase changes to cope with the change of the feedback coefficient β, and reduce the Miller capacitance value in the phase where β decreases to maintain the stability of the closed-loop bandwidth and avoid increasing g m1 In order to cope with the reduction of closed-loop bandwidth caused by the reduction of β, the present invention uses the Miller compensation capacitor C C Divided into the first capacitor C C1 and the second capacitor C C2 Two parts, the first capacitor C C1 It is controlled by a control switch with a timing of Φ1, such as Figure 5 As shown. In the Φ1 phase, the integrator is in the hold state and the feedback coefficient β Φ1 Close to 1, at this time, closing the switch can provide sufficient compensation for unity gain stability; in the Φ2 phase, the integrator is in the integrating state, and the feedback coefficient is:

[0089] β Φ2 ≈Ci / (C S +C ref +C i ),

[0090] At this time, the switch is disconnected, the Miller compensation capacitance is reduced, and the Miller capacitance is reduced, which increases the unity gain bandwidth product of the op amp and reduces the reduction in the op amp closed loop bandwidth caused by the reduction in the feedback coefficient. The op amp closed loop frequency response at this time is as follows: Figure 6As shown, due to the reduction in Miller compensation capacitance, the pole separation effect caused by the compensation capacitance is weakened, the main pole of the op amp shifts to the right, the gain-bandwidth product increases, the closed-loop bandwidth remains almost unchanged, and the phase margin of the op amp is approximately equal in the two phases. Compared with the traditional structure where the closed-loop bandwidth and phase margin of the two phases change significantly, the present invention achieves the same closed-loop bandwidth and phase margin for the Φ1 phase and the Φ2 phase. Therefore, there is no need to over-design the bandwidth of the Φ1 phase op amp or over-design the phase margin of the Φ2 phase to simultaneously meet the stability and speed of the two phases. The power consumption of the op amp and modulator is reduced while ensuring the stability of the op amp loop in the integrator. It is suitable for ΣΔ modulation systems with large feedback coefficients.

Claims

1. An operational amplifier structure using dynamic compensation in a ΣΔ modulator switched capacitor integrator, characterized in that: Including reference voltage input (Vref), feedback DAC capacitor (C ref ), sampling capacitor (Cs), signal input terminal (Vin), integration capacitor (C i ), a fully differential folded cascode two-stage operational amplifier, a first control switch (K1), a second control switch (K2), a third control switch (K3), a fourth control switch (K4), a fifth control switch (K5), a sixth control switch (K6) and a seventh control switch (K7); The reference voltage input terminal (Vref) is connected to the first control switch (K1), one end of the second control switch (K2) and the feedback DAC capacitor (C ref ) is connected to one end of the feedback DAC capacitor (C ref ) is connected to one end of the third control switch (K3), one end of the fourth control switch (K4), one end of the fifth control switch (K5) and one end of the sampling capacitor (Cs); the other end of the sampling capacitor (Cs) is connected to one end of the sixth control switch (K6) and one end of the seventh control switch (K7); the other end of the seventh control switch (K7) is connected to the signal input terminal (Vin); the other end of the fourth control switch (K4) is connected to the integration capacitor (Cs); i ) and the inverting input of the fully differential folded cascode two-stage op amp, the integrating capacitor (C i ) and the output of the fully differential folded cascode two-stage op amp and the output capacitor (C L ) is connected to one end of the The other end of the second control switch (K2), the other end of the third control switch (K3), the other end of the fifth control switch (K5), the other end of the sixth control switch (K6), the non-inverting input end of the fully differential folded common source and common gate two-stage operational amplifier and the output capacitor (C L ) are grounded; The fully differential folded common-source common-gate two-stage operational amplifier comprises a first NMOS transistor (M1), a second NMOS transistor (M2), a third NMOS transistor (M3), a fourth NMOS transistor (M4), a fifth NMOS transistor (M5), a sixth NMOS transistor (M6), a seventh NMOS transistor (M7), an eighth PMOS transistor (M8), a ninth PMOS transistor (M9), a tenth PMOS transistor (M10), an eleventh PMOS transistor (M11), a twelfth PMOS transistor (M12), a thirteenth PMOS transistor (M13), a fourteenth NMOS transistor (M14), a fifteenth PMOS transistor (M15), a sixteenth NMOS transistor (M16), a seventeenth PMOS transistor (M17), an eighth PMOS transistor (M8), a first capacitor (C C1 ), the second capacitor (C C2 ), the third capacitor (C C3 ), the fourth capacitor (C C4 ), a first resistor (R1), a second resistor (R2), an eighteenth NMOS transistor (M18), a nineteenth NMOS transistor (M19), a twentieth NMOS transistor (M20), a twenty-first PMOS transistor (M21), a twenty-second PMOS transistor (M22), a fifth capacitor (C5), a sixth capacitor (C6), a third resistor (R3), a fourth resistor (R4), a negative input terminal (Vin-), a positive input terminal (Vin+), a first bias voltage node (VB1), a second bias voltage node (VB2), a third bias voltage node (VB3), a fourth bias voltage node (VB4), a power supply, a common-mode feedback voltage node (VCMFB), a positive output terminal Vout+, a negative output terminal (Vout-) and a reference voltage terminal (V REF ); The gate of the first NMOS transistor (M1) is connected to the positive input terminal (Vin+), the source of the first NMOS transistor (M1) is connected to the drain of the sixth NMOS transistor (M6), and the drain of the first NMOS transistor (M1) is connected to the source of the eighth PMOS transistor (M8); The gate of the second NMOS transistor (M2) is connected to the negative input terminal (Vin-), the source of the second NMOS transistor (M2) is connected to the drain of the sixth NMOS transistor (M6), and the drain of the second NMOS transistor (M2) is connected to the source of the ninth PMOS transistor (M9); The gate of the third NMOS transistor (M3) and the gate of the fourth NMOS transistor (M4) are connected to the third bias voltage node (VB3); the drain of the third NMOS transistor (M3) is connected to the drain of the eighth PMOS transistor (M8); and the source of the third NMOS transistor (M3) is connected to the drain of the fifth NMOS transistor (M5); The drain of the fourth NMOS transistor (M4) is connected to the drain of the ninth PMOS transistor (M9), and the source of the fourth NMOS transistor (M4) is connected to the drain of the seventh NMOS transistor (M7); the gate of the fifth NMOS transistor (M5), the gate of the sixth NMOS transistor (M6), the gate of the seventh NMOS transistor (M7), and the gate of the eighteenth NMOS transistor (M18) are connected to a fourth bias voltage node (VB4); the source of the fifth NMOS transistor (M5), the source of the sixth NMOS transistor (M6), the source of the seventh NMOS transistor (M7), and the source of the eighteenth NMOS transistor (M18) are grounded; The gate of the eighth PMOS transistor (M8) and the gate of the ninth PMOS transistor (M9) are connected to the second bias voltage node (VB2); The gate of the tenth PMOS transistor (M10) and the gate of the eleventh PMOS transistor (M11) are connected to the first bias voltage node (VB1); the source of the tenth PMOS transistor (M10), the source of the eleventh PMOS transistor (M11), the source of the twelfth PMOS transistor (M12), the source of the thirteenth PMOS transistor (M13), the source of the fifteenth PMOS transistor (M15), and the source of the seventeenth PMOS transistor (M17) are connected to a power supply; The gate of the twelfth PMOS transistor (M12), the gate of the thirteenth PMOS transistor (M13), the gate of the twenty-first PMOS transistor (M21), and the gate of the twenty-second PMOS transistor (M22) are connected to the common-mode feedback voltage node (VCMFB); The drain of the tenth PMOS transistor (M10) and the drain of the twelfth PMOS transistor (M12) are connected to the source of the eighth PMOS transistor (M8); The drain of the eleventh PMOS transistor (M11) and the drain of the thirteenth PMOS transistor (M13) are connected to the source of the ninth PMOS transistor (M9); a gate of a fourteenth NMOS transistor (M14) connected to a drain of the third NMOS transistor (M3), a source of the fourteenth NMOS transistor (M14) connected to ground, and a drain of the fourteenth NMOS transistor (M14) and a drain of the fifteenth PMOS transistor (M15) connected to a positive output terminal (Vout+); a gate of a sixteenth NMOS transistor (M16) connected to a drain of the fourth NMOS transistor (M4), a source of the sixteenth NMOS transistor (M16) connected to ground, and a drain of the sixteenth NMOS transistor (M16) and a drain of the seventeenth PMOS transistor (M17) connected to a negative output terminal (Vout-); The first capacitor (C C1 ) is connected to the positive output terminal (Vout+), the first capacitor (C C1 ) is connected to one end of the first switch (S1); The second capacitor (C C2 ) is connected to the positive output terminal (Vout+), the other end of the first switch (S1) and the second capacitor (C C2 ) is connected to one end of a first resistor (R1); The other end of the first resistor (R1) is connected to the gate of the fourteenth NMOS transistor (M14); The third capacitor (C C3 ) is connected to the negative output terminal (Vout-), and the third capacitor (C C3 ) is connected to the negative terminal of the second switch (S2); The fourth capacitor (C C4 ) is connected to the negative output terminal (Vout-), and the fourth capacitor (C C4 ) is connected to one end of a second resistor (R2); The other end of the second resistor (R2) is connected to the gate of the sixteenth NMOS transistor (M16); The drain of the eighteenth NMOS transistor (M18) is connected to the sources of the nineteenth NMOS transistor (M19) and the twentieth NMOS transistor (M20); The gate of the nineteenth NMOS transistor (M19) is connected to the reference voltage terminal (V REF ), the drain of the nineteenth NMOS transistor (M19) is connected to the drain of the twenty-first PMOS transistor (M21); a gate of the twentieth NMOS transistor (M20) connected to the positive terminal of the fifth capacitor (C5) and the positive terminal of the sixth capacitor (C6), and a drain of the twentieth NMOS transistor (M20) connected to the drain of the twenty-second PMOS transistor (M22); The drain of the twenty-first PMOS transistor (M21) is connected to the gate of the twenty-first PMOS transistor (M21); The drain of the twenty-second PMOS transistor (M22) is connected to the gate of the twenty-second PMOS transistor (M22); The negative terminal of the fifth capacitor (C5) is connected to the positive output terminal (Vout+); The negative terminal of the sixth capacitor (C6) is connected to the negative output terminal (Vout-); One end of the third resistor (R3) is connected to the positive output terminal (Vout+), and the other end of the third resistor (R3) is connected to the positive terminal of the fifth capacitor (C5); One end of the fourth resistor (R4) is connected to the negative output terminal (Vout-), and the other end of the fourth resistor (R4) is connected to the positive terminal of the fifth capacitor (C5).

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