Method and apparatus for reducing transmission of rendering information

Abstract

This disclosure relates to methods and apparatus for graphics processing. Aspects of this disclosure can define a portion of a display area, wherein this portion of the display area is determined based on the display content of the display area. Furthermore, aspects of this disclosure can communicate display information corresponding to the defined portion of the display area. Additionally, aspects of this disclosure can update the display information corresponding to the defined portion of the display area. Aspects of this disclosure can also communicate updated display information corresponding to the defined portion of the display area. Aspects of this disclosure can also render at least some display content of the display area corresponding to the defined portion of the display area. In some aspects, updating display information can be based on the rendered display content of the display area.

Description

[0001] Priority is claimed under Section 119 of 35U.SC.

[0002] This application claims priority and benefit to U.S. nonprovisional application No. 16 / 673,564, filed November 4, 2019, which is expressly incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to processing systems, and more specifically to one or more techniques for graphics processing. Background Technology

[0004] Computing devices typically utilize graphics processing units (GPUs) to accelerate the rendering of graphics data used for display. Such devices can include, for example, computer workstations, mobile phones such as so-called smartphones, embedded systems, personal computers, tablet computers, and video game consoles. A GPU executes a graphics processing pipeline comprising one or more processing classes that work together to execute graphics processing commands and output frames. A central processing unit (CPU) controls the operation of the GPU by issuing one or more graphics processing commands to it. Modern CPUs are typically capable of executing multiple applications simultaneously, each of which may require the GPU during execution. Devices that provide content for visual presentation on a display typically include a GPU.

[0005] Typically, a device's GPU is configured to perform processing within the graphics processing pipeline. However, with the advent of wireless communication and smaller handheld devices, the need for improved graphics processing continues to grow. Summary of the Invention

[0006] The following is a simplified overview of one or more aspects to provide a basic understanding of such aspects. This overview is not a comprehensive overview of all anticipated aspects, and is neither intended to identify the key elements of all aspects nor to depict the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0007] In one aspect of this disclosure, a method, computer-readable medium, and apparatus are provided. The apparatus may be a central processing unit (CPU), a graphics processing unit (GPU), or any apparatus capable of performing graphics processing. The apparatus may determine a portion of a display area or an intermediate rendering target buffer, wherein the portion of the display area may be determined based on the display content of the display area or the intermediate rendering target buffer. The apparatus may also communicate display information corresponding to the determined portion of the display area or the intermediate rendering target buffer. Additionally, the apparatus may update the display information corresponding to the determined portion of the display area. The apparatus may also communicate updated display information corresponding to the determined portion of the display area or the intermediate rendering target buffer. The apparatus may also render at least some display content of the display area corresponding to the determined portion of the display area or the intermediate rendering target buffer. Furthermore, the apparatus may determine the display information corresponding to the determined portion of the display area or the intermediate rendering target buffer. The apparatus may also copy the display information corresponding to the determined portion of the display area from system memory to GPU internal memory (GMEM). The apparatus may also store the updated display information corresponding to the determined portion of the display area or the intermediate rendering target buffer in the GMEM. The apparatus may also copy the updated display information corresponding to the determined portion of the display area to the GMEM. The device can also store updated display information corresponding to a specific portion of the display area in system memory or dynamic random access memory (DRAM). The device can also copy the updated display information corresponding to a specific portion of the display area into system memory or DRAM. The device can also identify a specific portion of the display area based on the displayed content of the display area.

[0008] Details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will be apparent from the description and drawings, as well as from the claims. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating an example content generation system according to one or more techniques of this disclosure.

[0010] Figure 2 An example GPU according to one or more technologies disclosed herein is shown.

[0011] Figure 3 Example images or surfaces are shown according to one or more techniques in accordance with this disclosure.

[0012] Figure 4 Example diagrams of a system memory and GMEM according to one or more technologies of this disclosure are shown.

[0013] Figure 5Example diagrams of a system memory and GMEM according to one or more technologies of this disclosure are shown.

[0014] Figure 6 An example flowchart of an example method according to one or more techniques of this disclosure is shown. Detailed Implementation

[0015] Even if an entire tile or bin is not rendered, some GPUs can still perform de-parse and parsing operations on the entire tile or bin. By doing so, these GPUs are transferring an unnecessary amount of data corresponding to that tile from system memory to GMEM and back. Furthermore, de-parse and parsing the entire tile or bin while a portion of the tile is being rendered wastes memory bandwidth and system power. Reducing the amount of data copied or transferred between system memory and GPU memory can improve GPU performance and / or reduce GPU power consumption. Aspects of this disclosure can reduce the amount of unnecessary de-parse and parsing operations by transferring data corresponding to the rendering area of ​​the tile. Therefore, aspects of this disclosure may not transfer all data or information for each tile. To reduce unnecessary de-parse and parsing operations, aspects of this disclosure can determine or communicate data corresponding to the rendering area of ​​the tile. In some aspects, this can be referred to as a conditional de-parse and parsing mechanism, which can improve GPU performance and / or reduce GPU power consumption.

[0016] The various aspects of the systems, apparatus, computer program products, and methods will be described more fully below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the systems, apparatus, computer program products, and methods disclosed herein, whether implemented independently of or in combination with other aspects of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice a method. Additionally, the scope of this disclosure is intended to cover an apparatus or method that is practiced using structures, functions, or structures and functions other than those set forth herein. Any aspect disclosed herein may be embodied by one or more elements of the claims.

[0017] While various aspects are described herein, numerous variations and substitutions of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of the aspects of this disclosure have been mentioned, the scope of this disclosure is not intended to be limited to a particular benefit, use, or objective. Rather, the aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transport protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and accompanying drawings are merely illustrative and not limiting of this disclosure, the scope of which is defined by the appended claims and their equivalents.

[0018] Various apparatuses and methods are presented with reference to several aspects. These apparatuses and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms and / or the like (collectively, “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. The implementation of these elements as hardware or software depends on the specific application and the design constraints imposed on the system as a whole.

[0019] For example, an element, any part of an element, or any combination of elements can be implemented as a “processing system” comprising one or more processors (also referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, system-on-a-chip (SoCs), baseband processors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Software can be interpreted broadly as instructions, instruction sets, code, code segments, program code, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether or not referred to as software, firmware, middleware, microcode, hardware description languages, or others. The terminology may be used to refer to software. As described herein, one or more technologies can refer to an application (i.e., software) configured to perform one or more functions. In these examples, the application may be stored on memory (e.g., on-chip memory of a processor, system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute the application. For example, an application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access code from memory and execute the code accessed from memory to perform one or more technologies described herein. In some examples, components in this disclosure are identified. In these examples, the components may be hardware, software, or a combination thereof. These components may be separate components or subcomponents of a single component.

[0020] Therefore, in one or more examples described herein, the described functionality can be implemented in hardware, software, or any combination thereof. If implemented in software, the functionality can be stored on a computer-readable medium or encoded on a computer-readable medium as one or more instructions or code. A computer-readable medium includes a computer storage medium. A storage medium can be any available medium that can be accessed by a computer. By way of example, and not limitation, such a computer-readable medium can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of computer-readable media of the types described above, or any other medium that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0021] In general, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, improving the rendering of graphics content, and / or reducing the load on processing units (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for utilizing graphics processing in any device. Other exemplary benefits are described throughout this disclosure.

[0022] As used herein, instances of the term "content" can refer to "graphic content," "image," or vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" can refer to content produced by one or more processes in the graphics processing pipeline. In some examples, as used herein, the term "graphic content" can refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" can refer to content produced by a graphics processing unit.

[0023] In some examples, as used herein, the term "display content" can refer to content generated by a processing unit configured to perform display processing. Graphical content can be processed into display content. For example, a graphics processing unit can output graphical content, such as frames, to a buffer (which may be referred to as a frame buffer). A display processing unit can read graphical content (such as one or more frames) from the buffer and perform one or more display processing techniques on it to generate display content. For example, a display processing unit can be configured to perform compositing on one or more rendering layers to generate frames. As another example, a display processing unit can be configured to composite, blend, or otherwise combine two or more layers into a single frame. A display processing unit can be configured to perform scaling on frames, such as zooming in or out. In some examples, a frame can refer to a layer. In other examples, a frame can refer to two or more layers that have been blended together to form a frame, i.e., a frame comprises two or more layers, and frames comprising two or more layers can be subsequently blended.

[0024] Figure 1This is a block diagram illustrating an example content generation system 100 configured to implement one or more technologies of the present disclosure. The content generation system 100 includes a device 104. Device 104 may include one or more components or circuitry for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a System-on-a-Chip (SOC). Device 104 may include one or more components configured to perform one or more technologies of the present disclosure. In the illustrated example, device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some aspects, device 104 may include multiple optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. Reference to display 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for rendering thereon. In other examples, the first and second displays may receive the same frames to render on them. In further examples, the results of graphics processing may not be displayed on the device; for example, the first and second displays may not receive any frames to render on them. Instead, the frames or graphics processing results may be transferred to another device. In some respects, this can be called split rendering.

[0025] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor, such as display processor 127, to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being rendered by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise render the frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: liquid crystal display (LCD), plasma display, organic light-emitting diode (OLED) display, projection display device, augmented reality display device, virtual reality display device, head-mounted display, or any other type of display device.

[0026] Memory (such as system memory 124) external to processing unit 120 and content encoder / decoder 122 may be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 may be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 and content encoder / decoder 122 may be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 may be communicatively coupled to each other via a bus or a different connection.

[0027] Content encoder / decoder 122 can be configured to receive graphical content from any source, such as system memory 124 and / or communication interface 126. System memory 124 can be configured to store received encoded or decoded graphical content. Content encoder / decoder 122 can be configured to receive, for example, encoded or decoded graphical content from system memory 124 and / or communication interface 126 in the form of encoded pixel data. Content encoder / decoder 122 can be configured to encode or decode any graphical content.

[0028] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media or optical storage media or any other type of memory.

[0029] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may mean that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be construed as meaning that internal memory 121 or system memory 124 is immovable or that its contents are static. As one example, system memory 124 may be removed from device 104 and moved to another device. As another example, system memory 124 may not be removed from device 104.

[0030] Processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, processing unit 120 may be integrated into the motherboard of device 104. In some examples, processing unit 120 may reside on a graphics card mounted in a port on the motherboard of device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with device 104. Processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are implemented in part in software, processing unit 120 may store software instructions in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., may be considered as one or more processors.

[0031] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the motherboard of device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If these techniques are implemented in part in software, the content encoder / decoder 122 may store software instructions in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute the instructions in hardware to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, combinations of hardware and software, etc., can be considered as one or more processors.

[0032] In some aspects, the content generation system 100 may include an optional communication interface 126. Communication interface 126 may include a receiver 128 and a transmitter 130. Receiver 128 may be configured to perform any of the receiving functions described herein with respect to device 104. Furthermore, receiver 128 may be configured to receive information from another device, such as eye or head positioning information, rendering commands, or location information. Transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to device 104. For example, transmitter 130 may be configured to transmit information to another device, which may include a request for content. Receiver 128 and transmitter 130 may be combined to form transceiver 132. In such an example, transceiver 132 may be configured to perform any of the receiving and / or transmitting functions described herein with respect to device 104.

[0033] Refer again Figure 1 In some aspects, the graphics processing pipeline 107 may include a determining component 198 configured to determine a portion of a display area or intermediate rendering target buffer, wherein the determination of this portion of the display area may be based on the display content of the display area or intermediate rendering target buffer. The determining component 198 may also be configured to communicate display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The determining component 198 may also be configured to update the display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The determining component 198 may also be configured to communicate updated display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The determining component 198 may also be configured to render at least some display content of the display area corresponding to the determined portion of the display area or intermediate rendering target buffer. The determining component 198 may also be configured to determine the display information corresponding to the determined portion of the display area. The determining component 198 may also be configured to copy the display information corresponding to the determined portion of the display area from system memory to GMEM. The determining component 198 can also be configured to store updated display information corresponding to a determined portion of the display area in GPU internal memory (GMEM). The determining component 198 can also be configured to copy the updated display information corresponding to the determined portion of the display area to GMEM. The determining component 198 can also be configured to store the updated display information corresponding to the determined portion of the display area in system memory or dynamic random access memory (DRAM). The determining component 198 can also be configured to copy the updated display information corresponding to the determined portion of the display area to system memory or DRAM. The determining component 198 can also be configured to identify the determined portion of the display area based on the display content of the display area.

[0034] As described herein, a device such as device 104 can refer to any device, apparatus, or system configured to perform one or more of the technologies described herein. For example, a device can be a server, base station, user equipment, client device, station, access point, computer (e.g., personal computer, desktop computer, laptop computer, tablet computer, computer workstation, or mainframe computer), terminal product, apparatus, telephone, smartphone, server, video game platform or console, handheld device (e.g., portable video game device or personal digital assistant (PDA)), wearable computing device (e.g., smartwatch), augmented reality device or virtual reality device, non-wearable device, display or display device, television, set-top box, intermediate network device, digital media player, video streaming device, content streaming device, in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the technologies described herein. The processes described herein may be described as being performed by a specific component (e.g., GPU), but in further embodiments, other components (e.g., CPU) consistent with the disclosed embodiments may be used for execution.

[0035] GPUs can process various types of data or data packets within the GPU pipeline. For example, in some aspects, a GPU can process two types of data or data packets, such as context register packets and draw call data. Context register packets can be collections of global state information (e.g., information about global registers, shaders, or constant data) that can specify how the graphics context will be processed. For example, a context register packet may include information about the color format. In some aspects of a context register packet, there may be a bit indicating which workload belongs to the context register. Furthermore, multiple functions or programs can run concurrently and / or in parallel. For example, a function or program can describe a specific operation, such as a color mode or color format. Therefore, context registers can define multiple states of the GPU.

[0036] Context states can be used to determine how individual processing units (such as vertex extractors (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate, and / or in what modes they operate. For this purpose, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in the pipeline based on the context register definitions of modes or states. Certain processing units (such as VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states can change, the GPU may need to modify the corresponding context. Furthermore, workloads corresponding to modes or states can follow changing modes or states.

[0037] Figure 2 An example GPU 200 according to one or more technologies disclosed herein is shown. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z-processing engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, an L2 cache (UCHE) 238, and system memory 240. Although Figure 2 The GPU 200 includes processing units 220-238, but the GPU 200 may include many additional processing units. Furthermore, processing units 220-238 are merely an example, and any combination or order of processing units can be used by the GPU according to this disclosure. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0038] like Figure 2 As shown, the GPU can use a CP (e.g., CP 210) or a hardware accelerator to resolve the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then send context register packet 260 or draw call data packet 212 to processing units or blocks in the GPU via separate paths. Furthermore, the command buffer 250 can alternate between context registers and draw calls of different states. For example, the command buffer can be constructed as follows: context register of context N, multiple draw calls of context N, context register of context N+1, and multiple draw calls of context N+1.

[0039] GPUs can render images in various ways. In some cases, GPUs can use either binning or tiled rendering to render images. In a tiled rendering GPU, an image can be divided or separated into different segments or tiles. After the image is divided, each segment or tile can be rendered separately. A tiled rendering GPU can divide a computer graphics image into a grid format, so that each part of the grid (i.e., a tile) is rendered separately. In some aspects, during the binning pass, the image can be divided into different grids or tiles. In some aspects, during the binning pass, a visibility flow can be constructed if visible primitives or draw calls can be identified.

[0040] In some respects, the GPU can apply the drawing or rendering process to different grids or tiles. For example, the GPU can render to a grid and perform all drawing for the primitives or pixels in that grid. During the process of rendering to a grid, the render target can reside in GMEM. In some cases, after rendering to a grid, the contents of the render target can be moved to system memory, and GMEM can be freed for rendering the next grid. Furthermore, the GPU can render to another grid and perform drawing for the primitives or pixels in that grid. Therefore, in some respects, a small number of grids (e.g., four grids) may cover all drawing on a surface. Additionally, the GPU can loop through all drawing within a grid, but perform drawing only for visible drawing calls (i.e., drawing calls that include visible geometry). In some respects, a visibility stream can be generated, for example, during the grid stage to determine the visibility information of each primitive in the image or scene. For example, this visibility stream can identify whether a primitive is visible. In some respects, this information can be used to remove, for example, primitives that are not visible during the rendering stage. Furthermore, at least some primitives identified as visible can be rendered during the rendering stage.

[0041] In some aspects of tile rendering, there may be multiple processing segments or stages. For example, rendering can be performed in two stages, such as a visibility or tile visibility stage, and a rendering or tile rendering stage. During the visibility stage, the GPU can input a rendering workload, record the positions of primitives or triangles, and then determine which primitives or triangles fall into which tile or region. In some aspects of the visibility stage, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering stage, the GPU can input a visibility stream and process one tile or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or primitive vertices are visible or invisible. In this way, visible primitives or primitive vertices can be processed. By doing so, the GPU can reduce the unnecessary workload of processing or rendering invisible primitives or triangles.

[0042] In some aspects, certain types of primitive geometry can be processed during the visibility phase, such as positioning geometry only. Furthermore, depending on the positioning or location of primitives or triangles, primitives can be classified into different cells or regions. In some cases, primitives or triangles can be classified into different cells by determining their visibility information. For example, the GPU can determine or write visibility information for each primitive in each cell or region, for instance, in system memory. This visibility information can be used to determine or generate a visibility stream. During the rendering phase, primitives in each cell can be rendered separately. In these cases, the visibility stream can be retrieved from memory used to discard primitives that are not visible for that cell.

[0043] GPUs, or certain aspects of GPU architecture, can offer many different rendering options, such as software rendering and hardware rendering. In software rendering, the driver or CPU can rewrite the entire frame geometry by processing each view at a time. Furthermore, certain different states may change depending on the view. Thus, in software rendering, software can rewrite the entire workload by changing some states that are available for rendering for each viewpoint in the image. In some respects, this can increase overhead because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for rewriting or processing the geometry for each viewpoint in the image. Therefore, the hardware can manage the rewriting or processing of primitives or triangles for each viewpoint in the image.

[0044] Figure 3 An image or surface 300 is shown, comprising multiple primitives divided into multiple subdivisions. For example... Figure 3 As shown, the image or surface 300 includes region 302, which includes primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided or placed into different grids, such as grids 310, 311, 312, 313, 314, and 315. Figure 3 An example of tile rendering using primitives 321-324 from multiple viewpoints is shown. For example, primitives 321-324 are located in a first viewpoint 350 and a second viewpoint 351. In this way, a GPU that processes or renders an image or surface 300 including region 302 can utilize multiple viewpoints or multi-view rendering.

[0045] As noted in this paper, GPUs or graphics processing units can use tile rendering architectures to reduce power consumption or save memory bandwidth. As further described above, this rendering method can divide the scene into multiple grids and include a visibility phase that identifies the visible triangles in each grid. Therefore, in tile rendering, the entire screen can be divided into multiple grids or tiles. The scene can then be rendered multiple times, for example, once or more for each grid.

[0046] In graphics rendering, some graphics applications may render to a single target (i.e., the rendering target) once or multiple times. For example, in graphics rendering, a frame buffer on system memory can be updated multiple times. A frame buffer can be a portion of memory or random access memory (RAM), for example, containing bitmaps or storage to help store the GPU's display data. A frame buffer can also be a storage buffer containing a complete frame of data. Furthermore, a frame buffer can be a logical buffer. In some aspects, updating the frame buffer can be performed in grid or tile rendering, where, as described above, the surface is divided into multiple grids or tiles, and each grid or tile can then be rendered separately. Furthermore, in tile rendering, the frame buffer can be divided into multiple grids or tiles.

[0047] A graphics application may build or include multiple buffers, such as a depth buffer and / or a color buffer with diffuse color. Furthermore, a graphics application may build or include, for example, a shadow map for light at the depth or color buffer. For instance, an application may run a renderer on one buffer (e.g., for diffuse color) and then move to another buffer, for example, to create shadows for different lights. A graphics application may also combine other information with information previously stored in the buffers (e.g., specular color and / or shadows from a previous color buffer).

[0048] As indicated in this article, in a grid or tile rendering architecture, such as when rendering from different types of memory, frame buffers can have data that is repeatedly stored or written. This can be referred to as resolving and de-resolving frame buffers or system memory. For example, when storing or writing to one frame buffer and then switching to another, the data or information on the frame buffer can be resolved from GPU Internal Memory (GMEM) at the GPU to system memory, i.e., memory in Dual Data Rate (DDR) RAM or Dynamic RAM (DRAM).

[0049] In some respects, system memory can also be system-on-chip (SoC) memory or another type of chip-based memory, used to store data or information, for example, on a device or smartphone. System memory can also be physical data storage shared by the CPU and / or GPU. In some respects, system memory can be, for example, a DRAM chip on a device or smartphone. Therefore, SoC memory can be used to store data in a chip-based manner.

[0050] In some respects, GMEM can be on-chip memory at the GPU, which can be implemented by static RAM (SRAM). Alternatively, GMEM can be stored on the device (e.g., a smartphone). As indicated herein, data or information can be transferred between system memory or DRAM and GMEM, for example, at the device. In some respects, system memory or DRAM can be at the CPU or GPU. Furthermore, data can be stored at DDR or DRAM. In grid or tile rendering, a small portion of the memory can be stored at the GPU, for example, at GMEM. In some cases, storing data at GMEM can utilize a larger processing workload and / or consume less power compared to storing data at the frame buffer or system memory.

[0051] As noted in this paper, in grid or tile rendering, different types of memory storage (e.g., system or SoC memory and GMEM or on-chip memory) can be used to store different data or information (e.g., the color or depth of a specific tile). In some respects, the rendering data for each tile or grid can be transferred during de-parse or the parsing process. During the de-parse process, data or information can be moved from system memory to GMEM. Similarly, during the parsing process, data or information can be moved from GMEM to system memory. This process can then be repeated for the next grid or tile.

[0052] In some respects, the GMEM or on-chip memory can have a limited data size. Therefore, the process of transferring rendering information from the GMEM to system memory or the frame buffer can be performed tile-by-tile. For example, the GMEM can have a size that stores 256×256 pixels of color, which can correspond to the size of a tile. Compared to the size of the GMEM, the frame buffer or system memory can have a larger data size, for example, it can store 1920×1080 pixels of color. In some respects, when the frame buffer is segmented (e.g., 1920×1080 pixels), this can be performed in multiple steps based on the size of each tile (e.g., 256×256 pixels).

[0053] As described above, when data or information is stored or written to system memory or frame buffer, or when data or information is moved from system memory to GMEM, tiles or frames can be de-parsed. Furthermore, when data or information is moved from GMEM to system memory, tiles or frames can be parsed. For example, the parsing process can transfer data or information of, for example, a tile size of 256×256 pixels to system memory. Aspects of this disclosure can then move to another tile and continue the de-parse / parsing process, such as by de-parseing the tile from system memory to GMEM, rendering the tile, and then parsing the tile from GMEM to system memory. This process can continue until the entire frame buffer is filled.

[0054] As indicated in this document, the data for each tile can be moved from system memory to GMEM (i.e., the de-parse process), and then, after rendering, the data can be moved back from GMEM to system memory (i.e., the parsing process). Therefore, the de-parse process can be the reverse of the data movement compared to the parsing process. This de-parse / parsing process can be performed because GPU memory or GMEM can store less information than system memory. Thus, once rendered, tile data can be moved from GMEM back to the frame buffer and stored in system memory. In this way, the tile's rendering data can be transferred to the frame buffer in system memory. Furthermore, in some aspects, during the de-parse process, when tiles need to be rendered at the GPU, data stored in the frame buffer can be transferred to GMEM. Therefore, a portion of the frame buffer data can be transferred from system memory to GMEM, and after rendering based on that data, the data can be transferred back to the frame buffer in system memory. This process can be performed on each cell or tile until the entire surface is rendered.

[0055] Additionally, in some aspects, each tile can be rendered multiple times, resulting in only portions of the tile being rendered. Therefore, during the de-parse / resolve process, rendering data can be transferred back and forth between system memory and GMEM multiple times. For example, the GPU can render one aspect of a surface or tile (e.g., the background), and that data can be stored in system memory while other aspects of the surface or tile are rendered. Then, when rendering another part of the scene (e.g., a character), that data can be transferred back to the GPU. This process can also be called multipath rendering.

[0056] Furthermore, the GPU can render different aspects of a scene at different times. For example, it can render the diffuse colors of the scene, then the spectral colors, and then the shadows. Therefore, the frame buffer can incrementally store data when rendering tiles or grids in multiple paths. Additionally, data can be transferred back and forth between system memory and GPU memory multiple times during the rendering of each grid or tile.

[0057] In a tiled rendering GPU, switching back to a previously rendered surface may involve many different operations for each tile. For example, some data used for a tile (e.g., color and depth data) may be moved from a buffer (e.g., a color and depth buffer in system memory) to the GPU's internal memory for color and depth. As described above, this process can be referred to as a de-parsing process. The tile or tile can then be rendered based on the data (e.g., color and depth data). The data (e.g., color and depth data) may then be moved from the GPU's internal memory for color and depth to a buffer in system memory (e.g., a color and depth buffer). As described above, this process can be referred to as a parsing process.

[0058] In some cases, when de-parses or re-parses a tile, the entire tile can be transferred from system memory to GMEM before rendering the tile. After rendering, the entire tile can be resolved from GMEM to system memory. Therefore, when transferring certain data for a tile to and / or from system memory and GMEM in order to render that tile, the entire tile's data can be transferred. As indicated in this document, for de-parse and re-parse processes, transferring data from system memory to GMEM may require both GPU power and performance, and vice versa.

[0059] Figure 4 Example Figure 400 illustrates one or more technologies according to this disclosure, including system memory and GMEM. (See Figure 400 for an example.) Figure 4 As shown in Figure 400, system memory 410, system memory 420, system memory 430, system memory 440, GMEM 412, GMEM 422, GMEM 432, display content 428, deparse process 414, rendering 424, and parsing process 434. The system memory at 410 / 420 / 430 / 440 can represent the system memory at the GPU or CPU during different times of the deparse / parsing process. The GMEM at 412 / 422 / 432 can represent the GMEM at the GPU during different times of the deparse / parsing process.

[0060] like Figure 4As shown, during the unparsing process 414, tile data or information can be moved from system memory 410 to GMEM 412. During rendering 424, display content 428 (e.g., the sun) can be rendered for the tile. After rendering, the data or information of display content 428 can be written to or stored in GMEM 422. After the data or information of display content 428 has been copied and / or stored in GMEM 432, during the parsing process 434, the data or information of display content 428 can be moved from GMEM 432 to system memory 430. The data or information of display content 428 can be copied to or stored in system memory 440.

[0061] Figure 4 In some aspects, it's possible to update only a portion of a tile (e.g., the sun), but the entire tile's data can be transferred from system memory to GMEM and back. Transferring the entire tile's data wastes significant memory bandwidth. When a portion of a tile is rendered, the entire area of ​​the tile is not rendered. This can also apply to certain rendering operations, such as when rendering color and depth memories. In some aspects, during framed rendering, large portions of the data or information for a frame or tile may not be written to or updated after rendering. For example, certain parts of GMEM may not need to be updated during rendering. Figure 4 As shown, the sun is rendered at position 424, so other parts of the grid or tile may not need to be rendered.

[0062] As indicated in this article, unrendered tiles or regions may not require unparse and resolve operations. For example, when rendering a portion of a tile, a portion of the frame buffer is updated, so the entire tile's data may not need to be transferred to the frame buffer or system memory. Furthermore, blindly unparse and resolve the entire tile or tile while a portion of it is being rendered wastes memory bandwidth and system power. Therefore, the unparse and resolve process, by moving the entire tile's data from system memory to GMEM and then back, can waste significant bandwidth. By reducing the amount of data or memory copied or transferred between system memory and GPU memory, GPU performance can be improved and / or GPU power consumption reduced.

[0063] Various aspects of this disclosure can reduce the amount of unnecessary de-parsing and parsing operations by transmitting data or information corresponding to the areas to be rendered for a grid or tile. Therefore, various aspects of this disclosure may not transmit all data or information for each tile. To reduce unnecessary de-parsing and parsing operations, various aspects of this disclosure can (e.g., when rendering color and depth memory) determine or detect the rendering areas of a grid or tile. Therefore, a GPU according to this disclosure can de-parse and parse the rendering areas of a grid or tile. In some aspects, this can be referred to as a conditional de-parsing and parsing mechanism.

[0064] Various aspects of this disclosure can detect the region being rendered, causing data or information corresponding to the rendered region of the tile to be transmitted. Similarly, data for necessary regions of the tile from the frame buffer (e.g., a small portion of the frame buffer) can be transmitted to and / or from system memory and GMEM. In some cases, various aspects of this disclosure can also transmit the entire tile, but update only portions of the tile. This can be a conditional update, where potentially updated portions of the tile are actually updated, allowing various aspects of this disclosure to not update or render unnecessary portions of the tile that do not require updating or rendering.

[0065] As described above, aspects of this disclosure can de-parse portions of grids or tiles updated or rendered by the GPU, i.e., a conditional de-parse process. Furthermore, after rendering display content or updating information about the rendered display content, aspects of this disclosure can parse necessary portions of grids or tiles, i.e., a conditional parsing process. By conditionally de-parseing and parsing information about the rendered portions of tiles, aspects of this disclosure can allocate GPU bandwidth and power to portions of tile rendering or updating. Additionally, aspects of this disclosure can identify rendering areas of tiles, enabling data for that specific rendering area to be transferred between system memory and GMEM, and vice versa.

[0066] This disclosure can also utilize previously rendered portions of tiles, allowing data corresponding to these previously rendered portions of the tiles to be transferred back and forth between system memory and GMEM, and vice versa. Furthermore, according to this disclosure, the GPU can determine the portion of the tiles or data to be rendered, and then transfer that information back and forth between system memory and GPU memory. By doing so, this disclosure can avoid transferring all data or memory for each cell or tile, thereby saving GPU performance and power consumption.

[0067] In some aspects, this disclosure allows the location of a tile's rendering area to be determined simultaneously with rendering or updating the area. By determining the location of the rendering area, data for that area can be moved from system memory to GMEM, and then the data for that specific area can be updated. Therefore, this disclosure can determine or identify areas of a tile being rendered, such that data corresponding to the rendering area can be transferred based on this determination. Thus, this disclosure can process portions of a tile or grid, and once the rendering area of ​​the tile is determined, data for that portion of the tile can be transferred from system memory to GMEM during the unparsing process. After updating or rendering that area of ​​the tile, data for that portion of the tile can be transferred from GMEM to system memory during the parsing process.

[0068] In some aspects, this disclosure allows determining when to update a frame buffer based on the data or information transmitted to and from the frame buffer. For example, an application can determine when to update the frame buffer and notify the GPU driver when to transmit data to / from the frame buffer. Furthermore, the GPU driver can notify the GPU when to unparse data from system memory to GPU memory and when to parse data from GPU memory to system memory. In some aspects, the GPU driver can also translate application commands into GPU commands.

[0069] In some cases, unparse / parse operations can be performed tile-by-tile, allowing the driver to notify the GPU that the rendering process will continue and the frame buffer will continue to be updated. Therefore, the GPU can transfer data for a specific tile, update the frame buffer during a draw call, and then transfer the data from GMEM to system memory.

[0070] As indicated herein, aspects of this disclosure can deparse portions of tile data on demand and as necessary. This disclosure can determine the location of updates, and during a draw call, the GPU can update the frame buffer with data from the tile's rendering region. In some aspects, this disclosure can generate the location of the tile region (e.g., xy-coordinate data in a frame) before performing any other functions on that region. For example, the GPU of this disclosure can determine the xy-coordinate data of the updated region and then perform shading and / or color updates on that updated region and the xy-coordinate data. Thus, once the location is known, frame buffer data can be transferred from system memory to GMEM, and then the data for that region can be updated. After rendering, the data for that region can be updated, and this disclosure can transfer the updated data for that region. Therefore, this disclosure can move the updated data of the tile's rendering region, rather than moving the entire tile data. As indicated herein, this process can be referred to as on-demand updating.

[0071] The aspects of this disclosure can perform multiple steps for the aforementioned conditional unparse / parse process. For example, the GPU described herein can determine the data of the region of a tile to be rendered and transfer it from system memory to GMEM; that is, the GPU can unparse the data of the tile region. The GPU can then render the region of the tile corresponding to the data transferred to GMEM. For example, the GPU can render a new object in the tile. After rendering, the data of the rendered region can be updated. The updated data of the rendered region can then be stored and / or copied to GMEM. The updated data of the rendered region can then be transferred from GMEM to system memory. Finally, the data of the rendered region can be stored and / or copied to system memory.

[0072] As described above, aspects of this disclosure can determine the portion of a tile to be rendered. Data for this tile region can be transferred or communicated from system memory to GMEM. In some aspects, such data transfer can occur simultaneously with rendering. This disclosure can then render that region of the tile and / or update the data in that rendered region. Data updates can be performed incrementally. The data in the rendered region can then be stored or copied at GMEM before being transferred or communicated to system memory. The data in the rendered region can then be stored or copied at system memory or DRAM. In some aspects, the data in the rendered region can also be stored or copied in a frame buffer.

[0073] Figure 5 Example Figure 500 illustrates one or more technologies according to this disclosure, including system memory and GMEM. (See Figure 500 for details.) Figure 5 As shown in Figure 500, system memory 510, system memory 520, system memory 530, system memory 540, GMEM 512, GMEM 522, GMEM 532, GMEM 542, region 516, display content 528, deparse process 514, rendering 524, and parsing process 534. The system memory at 510 / 520 / 530 / 540 can represent the system memory at the GPU or CPU during different times of the deparse / parsing process. GMEM 512 / 522 / 532 / 534 can represent the GMEM at the GPU during different times of the deparse / parsing process.

[0074] like Figure 5As shown, region 516 is the portion of the tile to be rendered, which can be determined based on the display content. Region 516 may include a smaller area than the entire tile. During the de-resolution process 514, data or information of region 516 can be moved or communicated from system memory 510 to GMEM 512. During rendering 524, the display content 528 of region 516 (e.g., the sun) can be rendered. After rendering, the data or information of the display content 528 of region 516 can be updated based on the rendering. The data or information of the display content 528 of region 516 can be written, copied, or stored to GMEM 532. After the data or information of the display content 528 of region 516 has been copied and / or stored at GMEM 532, during the resolution process 534, the data or information of the display content 528 of region 516 can be moved from GMEM 532 to system memory 530. The data or information of the display content 528 of region 516 can then be copied or stored to system memory 540. Figure 5 As shown, the data or information of the display content 528 in area 516 can be stored in GMEM 542 and system memory 540.

[0075] Figure 5 In some aspects, regions of a tile (e.g., the sun) can be rendered or updated, and data for these regions can be transferred from system memory to GMEM and back. By transferring data for the rendered tile regions, this disclosure can save significant GPU power and / or memory bandwidth. When rendering only a portion of a tile, it is not necessary to transfer data for the entire tile region. This can also be applied to certain rendering operations, such as when rendering color and depth memory. In some aspects, large portions of the data or information for a grid or tile may not be updated or rendered after rendering. Figure 5 As shown, the sun in region 516 is being rendered at position 524, and other parts of the tile may not need to be rendered, so that the data corresponding to these other parts of the tile may not need to be communicated or transmitted.

[0076] Figure 5 The display content (e.g., the sun) of the rendered area 516 of the display tile is rendered, and data for a specific area 516 of the tile (e.g., data corresponding to the sun) is transferred back and forth from system memory to GMEM. As described above, by transferring data corresponding to the rendered area of ​​the tile (e.g., area 516), significant GPU power and / or memory bandwidth can be saved. After the display content of area 516 is rendered, this disclosure can update the data corresponding to area 516, which will be transferred back from GMEM to system memory. In some aspects, rendering the display content at area 516 can occur simultaneously with transferring the data of area 516 from system memory to GMEM.

[0077] Figure 5 An example of the above process for communicating tile information during the de-parsing and parsing processes is shown. For example... Figure 5 As shown, various aspects of this disclosure (e.g., the CPU and GPU described herein) can perform multiple different steps or processes to communicate portions of data or information of a block during the decryption and parsing process. For example, the GPU described herein can determine a portion of a display area (e.g., area 516 or an intermediate render target buffer), wherein this portion of the display area can be determined based on the display content of the display area or the intermediate render target buffer. In some aspects, this portion of the display area (e.g., area 516) can be determined by the CPU or the GPU. The GPU described herein can also identify the determined portion of the display area based on the display content of the display area (e.g., area 516) or the intermediate render target buffer.

[0078] Additionally, the GPU described herein can determine display information corresponding to a defined portion of a display area (e.g., area 516) or an intermediate rendering target buffer. The GPU described herein can also copy the display information corresponding to the defined portion of the display area (e.g., area 516) from system memory (e.g., system memory 510) to GMEM (e.g., GMEM 532). The GPU described herein can also (e.g., during deparse process 514) communicate the display information corresponding to the defined portion of the display area (e.g., area 516) or the intermediate rendering target buffer. In some aspects, the GPU described herein can (e.g., during deparse process 514) send the display information corresponding to the defined portion of the display area (e.g., area 516) to GMEM (e.g., GMEM 512).

[0079] The GPU described herein can also (e.g., at rendering 524) render at least some display content (e.g., display content 528) of a display area corresponding to a defined portion of a display area (e.g., area 516) or an intermediate rendering target buffer. The GPU described herein can also update display information corresponding to a defined portion of a display area (e.g., area 516) or an intermediate rendering target buffer. In some aspects, the updated display information corresponding to a defined portion of a display area (e.g., area 516) can be based on (e.g., at rendering 524) at least some of the rendered display content (e.g., display content 528) of the display area. In some aspects, the updated display information corresponding to a defined portion of a display area (e.g., area 516) can be updated incrementally, such that at least some information of the updated display information is updated separately from at least some other information of the updated display information.

[0080] Furthermore, the GPU described herein can copy updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of region 516) to the GMEM (e.g., GMEM 532). The GPU described herein can also store updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of region 516) in the GMEM (e.g., GMEM 532).

[0081] The GPU described herein can also (e.g., during the parsing process 534) communicate updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of area 516). In some aspects, the GPU described herein can (e.g., during the parsing process 534) send the updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of area 516) to system memory or DRAM (e.g., system memory 530). Furthermore, the GPU described herein can copy the updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of area 516) to system memory or DRAM (e.g., system memory 540). The GPU described herein can also store the updated display information corresponding to a defined portion of the display area (e.g., information corresponding to display content 528 of area 516) in system memory or DRAM (e.g., system memory 540).

[0082] In some aspects, the GPU's rasterizer can inform the parsing engine which regions of the tile to render. Additionally, in other aspects, the parsing engine can load color and / or depth information for these rendered regions from system memory into GMEM or GPU internal memory. Furthermore, the rendering backend can, for example, record which regions of the tile have been updated based on the rendering process. Moreover, the parsing engine can move the color and depth of the updated regions from GPU internal memory or GMEM to system memory.

[0083] The foregoing aspects of this disclosure may include numerous advantages. For example, the conditional unparsing and parsing mechanisms described herein can reduce GPU memory workload, improve GPU performance, and / or reduce power consumption. Furthermore, since aspects of this disclosure can avoid transmitting entire tile data, the amount of data transmitted corresponding to the rendering region can be reduced. For example, since this disclosure can avoid transmitting entire tile data, aspects of this disclosure can improve GPU performance and / or reduce power consumption.

[0084] Figure 6An example flowchart 600 is shown, illustrating an example method according to one or more techniques of this disclosure. This method can be performed by a device such as a CPU, GPU, or a graphics processing apparatus. At 602, the device can determine a portion of a display area or intermediate rendering target buffer, wherein this portion of the display area can be determined based on the display content of the display area or intermediate rendering target buffer, such as in conjunction with... Figure 3 , 4 As described in example 5. In some respects, this portion of the display area can be determined by the Central Processing Unit (CPU) or the Graphics Processing Unit (GPU), such as in combination. Figure 3 , 4 As described in example 5. In 604, the device can identify a specific portion of the display area based on the display content of the display area or the intermediate rendering target buffer, such as in combination with... Figure 3 , 4 As described in example 5.

[0085] At 606, the device can determine display information corresponding to a defined portion of the display area or intermediate rendering target buffer, such as in combination with Figure 3 , 4 And as described in example 5. In 608, the device can copy display information corresponding to a defined portion of the display area from system memory to GMEM, as in conjunction with... Figure 3 , 4 And as described in example 5. In 610, the device can communicate display information corresponding to a defined portion of the display area or intermediate rendering target buffer, such as in combination with... Figure 3 , 4 As described in example 5. In some aspects, the device can send display information corresponding to a defined portion of the display area to the GPU internal memory (GMEM), such as in conjunction with... Figure 3 , 4 As described in example 5.

[0086] In 612, the device can render at least some display content of a display area corresponding to a defined portion of the display area or intermediate rendering target buffer, such as in combination with Figure 3 , 4 As described in example 5. In 614, the device can update display information corresponding to a defined portion of the display area, such as in conjunction with... Figure 3 , 4 As described in example 5. In some aspects, the updated display information corresponding to a defined portion of the display area can be based on at least some of the display content rendered by the display area, such as in combination with... Figure 3 , 4As described in example 5. In some aspects, the updated display information corresponding to a defined portion of the display area can be updated incrementally, such that at least some information of the updated display information is updated separately from at least some other information of the updated display information, such as in combination. Figure 3 , 4 As described in example 5.

[0087] In 616, the device can copy updated display information corresponding to a defined portion of the display area to the GMEM, such as in combination with... Figure 3 , 4 And as described in example 5. In 618, the device can store updated display information corresponding to a defined portion of the display area in GMEM, as in conjunction with... Figure 3 , 4 As described in example 5.

[0088] In 620, the device can communicate updated display information corresponding to a defined portion of the display area or intermediate rendering target buffer, such as in combination with Figure 3 , 4 As described in example 5. In some aspects, the device can send updated display information corresponding to a defined portion of the display area to the system memory or dynamic random access memory (DRAM), such as in conjunction with... Figure 3 , 4 And as described in example 5. In 622, the device can copy updated display information corresponding to a defined portion of the display area to system memory or DRAM, as in combination with... Figure 3 , 4 And as described in example 5. In 624, the device can also store updated display information corresponding to a defined portion of the display area in system memory or DRAM, as in combination with... Figure 3 , 4 As described in example 5.

[0089] In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be a CPU, a GPU, or some other processor capable of performing graphics processing. In one aspect, the apparatus may be a processing unit 120 within device 104, or some other hardware within device 104 or another device. The apparatus may include components for determining a portion of a display area or intermediate rendering target buffer, wherein the portion of the display area may be determined based on display content of the display area or intermediate rendering target buffer. The apparatus may include components for communicating display information corresponding to the determined portion of the display area or intermediate rendering target buffer. Additionally, the apparatus may include components for updating the display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The apparatus may also include components for communicating updated display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The apparatus may also include components for rendering at least some display content of the display area corresponding to the determined portion of the display area or intermediate rendering target buffer. The apparatus may also include components for determining the display information corresponding to the determined portion of the display area or intermediate rendering target buffer. The apparatus may also include components for copying the display information corresponding to the determined portion of the display area from system memory to GMEM. The apparatus may further include components for storing updated display information corresponding to a defined portion of the display area or intermediate rendering target buffer in the GMEM. The apparatus may also include components for copying the updated display information corresponding to a defined portion of the display area or intermediate rendering target buffer into the GMEM. The apparatus may further include components for storing the updated display information corresponding to a defined portion of the display area in system memory or dynamic random access memory (DRAM). The apparatus may further include components for copying the updated display information corresponding to a defined portion of the display area into system memory or DRAM. The apparatus may further include components for identifying a defined portion of the display area based on the display content of the display area.

[0090] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, CPU, or some other processor capable of performing graphics processing to implement the parsing and deparsing techniques described herein. This can also be accomplished at a lower cost compared to other graphics processing techniques. Furthermore, the graphics processing techniques of this invention can improve or accelerate data processing or execution. Additionally, the graphics processing techniques of this invention can improve resource or data utilization and / or resource efficiency. Furthermore, aspects of this disclosure can utilize conditional information transmission, which can reduce the time and money consumed during the parsing and deparsing processes.

[0091] According to this disclosure, the term "or" may be interpreted as "and / or" unless the context otherwise indicates. Furthermore, while phrases such as "one or more" or "at least one" may be used for some features disclosed herein but not others, features not using such language may be interpreted as having this implied meaning unless the context otherwise indicates.

[0092] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used in this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, then the functionality, processing unit, technique, or other module described herein may be stored on or transmitted through a computer-readable medium as one or more instructions or code. A computer-readable medium may include a computer data storage medium or a communication medium, including any medium that facilitates communication of a computer program from one place to another. In this way, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium accessible by one or more computers or one or more processors to retrieve instructions, code, and / or data structures to implement the techniques described herein. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. The optical discs and disks used in this document include compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media. Computer program products may include computer-readable media.

[0093] The code can be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuit systems. Therefore, the term "processor" as used herein can refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Similarly, these techniques can be implemented entirely within one or more circuit or logic elements.

[0094] The techniques disclosed herein can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs), or collections of ICs, such as chipsets. Various components, modules, or units are described in this disclosure to emphasize functional aspects of a device configured to perform the disclosed techniques, but they do not necessarily need to be implemented through different hardware units. Rather, as described above, various units can be combined in any hardware unit or provided by a batch of interoperable hardware units including one or more processors as described above, combined with suitable software and / or firmware.

[0095] Various examples have been described. These and other examples are within the scope of the appended claims.

Claims

1. A graphics processing method, comprising: A portion of a display area is defined, wherein the portion of the display area is determined based on the display content of the display area, wherein the portion of the display area corresponds to the display content to be rendered, and wherein the portion of the display area is less than the area of ​​the display area. Display information corresponding only to the portion of the tile is communicated from system memory to the graphics processing unit's internal memory (GMEM). Update the display information of the tile that corresponds only to the portion thereof, wherein the updated display information corresponds to the rendered display content; as well as The GMEM communicates updated display information of the tile corresponding only to the portion thereof to the system memory.

2. The method according to claim 1, further comprising: Render at least some display content in the display area corresponding to the portion of the tile.

3. The method of claim 2, wherein the updated display information corresponding only to the portion of the tile is based on at least some of the rendered display content of the display area.

4. The method according to claim 1, further comprising: Determine the display information corresponding to the portion of the tile.

5. The method according to claim 1, further comprising: The display information corresponding only to the portion of the tile is copied from the system memory to the GMEM.

6. The method of claim 1, wherein the display information corresponding only to the portion of the communication tile includes: Send the display information corresponding only to the portion of the tile to the GMEM.

7. The method of claim 1, wherein the updated display information corresponding only to the portion of the tile is updated incrementally, such that at least some information in the updated display information is updated separately from at least some other information in the updated display information.

8. The method according to claim 1, further comprising: The updated display information corresponding only to the portion of the tile is stored in the GMEM.

9. The method according to claim 8, further comprising: The updated display information corresponding only to the portion of the tile is copied to the GMEM.

10. The method of claim 1, wherein the updated display information corresponding only to the portion of the communication of the tile further comprises: The updated display information corresponding only to the portion of the tile is sent to the system memory or dynamic random access memory (DRAM).

11. The method according to claim 1, further comprising: The updated display information corresponding only to the portion of the tile is stored in the system memory or DRAM.

12. The method of claim 11, further comprising: The updated display information corresponding only to the portion of the tile is copied to the system memory or the DRAM.

13. The method according to claim 1, further comprising: The portion of the tile is identified based on the content displayed in the display area.

14. The method of claim 1, wherein the portion of the tile is determined by a central processing unit (CPU) or a graphics processing unit (GPU).

15. An apparatus for graphics processing, comprising: At least one processor is configured as follows: A portion of a display area is defined, wherein the portion of the display area is determined based on the display content of the display area, wherein the portion of the display area corresponds to the display content to be rendered, and wherein the portion of the display area is less than the area of ​​the display area. Display information corresponding only to the portion of the tile is communicated from system memory to the graphics processing unit's internal memory (GMEM). Update the display information of the tile that corresponds only to the portion thereof, wherein the updated display information corresponds to the rendered display content; as well as The GMEM communicates updated display information of the tile corresponding only to the portion thereof to the system memory.

16. The apparatus of claim 15, wherein the at least one processor is further configured to: Render at least some display content in the display area corresponding to the portion of the tile.

17. The apparatus of claim 16, wherein the updated display information corresponding only to the portion of the tile is based on at least some of the display content rendered in the display area.

18. The apparatus of claim 15, wherein the at least one processor is further configured to: Determine the display information corresponding to the portion of the tile.

19. The apparatus of claim 15, wherein the at least one processor is further configured to: The display information corresponding only to the portion of the tile is copied from the system memory to the GMEM.

20. The apparatus of claim 15, wherein, In order to communicate the display information corresponding only to the portion of the tile, the at least one processor is configured to: Send the display information corresponding only to the portion of the tile to the GMEM.

21. The apparatus of claim 15, wherein, In order to update the display information corresponding only to the portion of the tile, the at least one processor is configured to: The display information corresponding only to the portion of the tile is updated incrementally, such that at least some of the updated display information is updated separately from at least some other information in the updated display information.

22. The apparatus of claim 15, wherein the at least one processor is further configured to: The updated display information corresponding only to the portion of the tile is stored in the GMEM.

23. The apparatus of claim 22, wherein the at least one processor is further configured to: The updated display information corresponding only to the portion of the tile is copied to the GMEM.

24. The apparatus of claim 15, wherein, In order to communicate the updated display information corresponding only to the portion of the tile, the at least one processor is configured to: The updated display information corresponding only to the portion of the tile is sent to the system memory or dynamic random access memory (DRAM).

25. The apparatus of claim 15, wherein the at least one processor is further configured to: The updated display information corresponding only to the portion of the tile is stored in the system memory or DRAM.

26. The apparatus of claim 25, wherein the at least one processor is further configured to: The updated display information corresponding only to the portion of the tile is copied to the system memory or the DRAM.

27. The apparatus of claim 15, wherein the at least one processor is further configured to: The portion of the tile is identified based on the content displayed in the display area.

28. The apparatus of claim 15, wherein the at least one processor comprises a central processing unit (CPU) or a graphics processing unit (GPU).

29. An apparatus for graphics processing, comprising: A component for determining a portion of a tile in a display area, wherein the portion of the tile is determined based on the display content of the display area, wherein the portion of the tile corresponds to the display content to be rendered, and wherein the portion of the tile is less than the area of ​​the tile; A component for communicating display information corresponding only to the portion of the tile from system memory to the graphics processing unit internal memory (GMEM); A component for updating the display information of the tile that corresponds only to the portion thereof, wherein the updated display information corresponds to the rendered display content; as well as A component for communicating update display information corresponding only to the portion of the tile from the GMEM to the system memory.

30. The apparatus of claim 29, further comprising: A component for rendering at least some display content corresponding to the portion of the tile in the display area.

31. The apparatus of claim 30, wherein the updated display information corresponding only to the portion of the tile is based on at least some of the display content rendered in the display area.

32. The apparatus of claim 29, further comprising: A component for determining the display information corresponding to the portion of the tile.

33. The apparatus of claim 29, further comprising: A component for copying the display information corresponding only to the portion of the tile from the system memory to the GMEM.

34. The apparatus of claim 29, wherein the component for communicating the display information corresponding only to the portion of the tile is further configured to: Send the display information corresponding only to the portion of the tile to the GMEM.

35. The apparatus of claim 29, wherein the component for updating the display information is configured to: The updated display information corresponding only to the portion of the tile is incrementally updated, such that at least some information in the updated display information is updated separately from at least some other information in the updated display information.

36. The apparatus of claim 29, further comprising: A component for storing the updated display information of the tile that corresponds only to the portion in the GMEM.

37. The apparatus of claim 36, further comprising: A component for copying the updated display information corresponding only to the portion of the tile to the GMEM.

38. The apparatus of claim 29, wherein the component for communicating the updated display information corresponding only to the portion of the tile is further configured to: The updated display information corresponding only to the portion of the tile is sent to the system memory or dynamic random access memory (DRAM).

39. The apparatus of claim 29, further comprising: A component for storing the updated display information of the tile, corresponding only to the portion thereof, in the system memory or DRAM.

40. The apparatus of claim 39, further comprising: A component for copying the updated display information corresponding only to the portion of the tile to the system memory or the DRAM.

41. The apparatus of claim 29, further comprising: A component for identifying the portion of the tile based on the displayed content of the display area.

42. The apparatus of claim 29, wherein the component for determining the portion of the tile includes a central processing unit (CPU) or a graphics processing unit (GPU).

43. A computer-readable medium storing computer-executable code for graphics processing, the computer-executable code comprising code that performs the following: A portion of a display area is defined, wherein the portion of the display area is determined based on the display content of the display area, wherein the portion of the display area corresponds to the display content to be rendered, and wherein the portion of the display area is less than the area of ​​the display area. Display information corresponding only to the portion of the tile is communicated from system memory to the graphics processing unit's internal memory (GMEM). Update the display information of the tile that corresponds only to the portion thereof, wherein the updated display information corresponds to the rendered display content; as well as The GMEM communicates updated display information of the tile corresponding only to the portion thereof to the system memory.

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