Phase change memory using multiple stacks of PCM material

Abstract

A method for improving the linearity of phase-change memory (PCM) cell structures is proposed. The method includes: forming a bottom electrode (12) over a substrate (10); constructing a PCM stack (20) comprising multiple PCM layers, each having a different crystallization temperature, over the bottom electrode (12); and forming a top electrode (32) over the PCM stack (20). The crystallization temperature varies in ascending order from the bottom electrode (12) to the top electrode (32).

Description

Background Technology

[0001] The present invention relates generally to semiconductor devices, and more specifically to a phase-change memory (PCM) cell employing multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures and / or resistivities to improve device linearity.

[0002] Phase-change memory (PCM) is one of the next-generation non-volatile memory devices expected to meet the growing demand for high-performance and low-power semiconductor memory devices. In PCM devices, data can be stored or erased by heating or cooling the phase-change layer. PCM devices can also be used in analog computing applications due to the possibility of multiple states existing within a cell. Weights can be stored in PCM cells during the training or inference of a neutral network. However, the linearity of PCM states is one of the problems associated with deploying PCM in artificial intelligence (AI) applications. Summary of the Invention

[0003] According to one embodiment, a method for improving the linearity of a phase-change memory (PCM) cell structure is provided. The method includes: forming a bottom electrode over a substrate; constructing a PCM stack comprising a plurality of PCM layers, each of the PCM layers having a different crystallization temperature, over the bottom electrode; and forming a top electrode over the PCM stack. The crystallization temperature varies in ascending order from the bottom electrode to the top electrode.

[0004] According to another embodiment, a method for improving the linearity of a phase-change memory (PCM) cell structure is provided. The method includes: forming a bottom electrode over a substrate; constructing a PCM stack comprising a plurality of PCM layers, each of the PCM layers having a different crystallization temperature, over the bottom electrode; and forming a top electrode over the PCM stack. The crystallization temperature is low in the central region of the PCM stack, and high in the topmost and bottommost regions of the PCM stack.

[0005] According to another embodiment, a semiconductor device is provided for improving the linearity of a phase-change memory (PCM) cell structure. The semiconductor device includes: a bottom electrode disposed above a substrate; a PCM stack disposed above the bottom electrode, comprising a plurality of PCM layers, each PCM layer having a different crystallization temperature; and a top electrode disposed above the PCM stack. The crystallization temperatures vary in descending order within a portion or entirely of the PCM stack.

[0006] According to another embodiment, a semiconductor structure is provided, the semiconductor structure comprising: a bottom electrode disposed above a substrate; a PCM stack disposed above the bottom electrode, the PCM stack comprising a plurality of PCM layers, each PCM layer having a different crystallization temperature; and a top electrode disposed above the PCM stack, wherein the crystallization temperature in the central region of the PCM stack is at a low point, and the crystallization temperature in the topmost and bottommost regions of the PCM stack is at a high point.

[0007] It should be noted that these exemplary embodiments have been described with reference to different subjects. Specifically, some embodiments are described with reference to method type claims, while others are described with reference to apparatus type claims. However, those skilled in the art will conclude from the above and below description that, unless otherwise indicated, any combination of features relating to different subjects (specifically, between features of method type claims and features of apparatus type claims) is also considered to be described in this document, except for any combination of features belonging to one type of subject matter.

[0008] These and other features and advantages will become clear from the following detailed description of its illustrative embodiments, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0009] The present invention will be provided in detail in the following description of preferred embodiments with reference to the following drawings, in which:

[0010] Figure 1 This is a cross-sectional view of a semiconductor structure including a bottom electrode formed above a substrate, according to an embodiment of the present invention;

[0011] Figure 2 This is an embodiment of the present invention. Figure 1 A cross-sectional view of a semiconductor structure in which heater elements are deposited and patterned;

[0012] Figure 3 This is according to an embodiment of the present invention. Figure 2 A cross-sectional view of a semiconductor structure in which resistive pads are deposited;

[0013] Figure 4 This is an embodiment of the present invention. Figure 3 A cross-sectional view of a semiconductor structure in which a Ge-Sb-Te (germanium-antimony-tellurium or "GST") stack is formed;

[0014] Figure 5 The top electrode is formed according to an embodiment of the present invention. Figure 4 A cross-sectional view of the semiconductor structure;

[0015] Figure 6 This is a cross-sectional view of a semiconductor structure including a bottom electrode formed above a substrate, according to another embodiment of the present invention;

[0016] Figure 7 This is an embodiment of the present invention. Figure 6 A cross-sectional view of a semiconductor structure, wherein a GST stack is formed above the bottom electrode;

[0017] Figure 8 This is an embodiment of the present invention. Figure 7 A cross-sectional view of a semiconductor structure in which a stack of phase change materials is patterned;

[0018] Figure 9 This is an embodiment of the present invention. Figure 8 A cross-sectional view of a semiconductor structure in which resistive pads are deposited on top of a patterned stack of phase change material;

[0019] Figure 10 This is an embodiment of the present invention. Figure 9 A cross-sectional view of a semiconductor structure in which the interlayer dielectric (ILD) is deposited and planarized;

[0020] Figure 11 This is an embodiment of the present invention. Figure 10 A cross-sectional view of a semiconductor structure, wherein the top electrode is formed above a patterned stack of phase change materials;

[0021] Figure 12 A block / flowchart of an exemplary neuromorphic and synaptic network according to an embodiment of the present invention, comprising crossbars of electronic synapses interconnecting electronic neurons and axons; and

[0022] Figure 13 A block diagram depicts the components of a computing system including a computing device and a neuromorphic chip according to an embodiment of the present invention.

[0023] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements. Detailed Implementation

[0024] According to embodiments of the present invention, methods and apparatus are provided for constructing phase change memory structures or phase change memory (PCM) cells having multiple stacks of Ge-Sb-Te (germanium-antimony-tellurium or "GST") materials with different crystallization temperatures and / or resistivities to improve device linearity. Mushroom GST structures and confined cell GST structures are introduced, wherein the crystallization temperatures vary in ascending, descending, or a combination of ascending and descending orders.

[0025] Embodiments of the present invention provide a method and apparatus for forming a single PCM device using multilayer phase change materials with different crystallization temperatures to achieve better linearity. No diffusion barrier layer or passivation layer is used between the phase change material layers.

[0026] Embodiments of the present invention provide methods and apparatus for employing phase-change-based materials in PCM cells. By applying a current level suitable for implementation in integrated circuits, a phase-change material (e.g., a chalcogenide) can be caused to change phase between an amorphous and a crystalline state. The substantially amorphous state is characterized by a higher resistivity than the substantially crystalline state, which can be easily sensed to indicate data.

[0027] Phase change materials (PCMs) can switch between a first structural state and a second structural state. In the first structural state, the material is in a generally amorphous solid phase, while in the second structural state, the material is in a generally crystalline solid phase within the active region of the unit. The term "amorphous" refers to a relatively disordered structure, more disordered than a single crystal, possessing detectable characteristics such as higher resistivity than a crystalline phase. The term "crystalline" refers to a relatively more ordered structure, more ordered than an amorphous structure, possessing detectable characteristics such as lower resistivity than an amorphous phase. Other material properties affected by the transition between amorphous and crystalline phases include atomic order, free electron density, and activation energy. Materials can be transformed into different solid phases or mixtures of two or more solid phases, thus providing grayscale values ​​between completely amorphous and completely crystalline states.

[0028] The transition from an amorphous to a crystalline state is typically a low-current operation, requiring a current sufficient to raise the phase change material to a level between the phase change temperature and the melting temperature. The transition from a crystalline to an amorphous state (referred to as "reset") is typically a high-current operation, involving short, high-current-density pulses to melt or break down the crystalline structure. After this, the phase change material is rapidly cooled, quenching the phase change process and allowing at least a portion of the phase change structure to stabilize in the amorphous state.

[0029] It should be understood that the invention will be described based on the given illustrative framework; however, other frameworks, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the invention. It should be noted that, for clarity, certain features may not be shown in all the figures. This is not intended to be construed as limiting the scope of any particular embodiment, illustration, or claims.

[0030] Figure 1 This is a cross-sectional view of a semiconductor structure including a bottom electrode formed above a substrate, according to an embodiment of the present invention.

[0031] The semiconductor structure 5 includes a bottom electrode 12 formed above the substrate 10. The bottom electrode 12 may be formed within the substrate 10.

[0032] The substrate 10 may be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 may be substantially (e.g., except for contaminants) a single element (e.g., silicon), predominantly (e.g., with doping) a single element, such as silicon (Si) or germanium (Ge), or the substrate 10 may include compounds such as GaAs, SiC, or SiGe. The substrate 10 may also have multiple material layers. In some embodiments, the substrate 10 includes a semiconductor material, which includes, but is not limited to, silicon (Si), silicon-germanium (SiGe), silicon carbide (SiC), Si:C (carbon-doped silicon), silicon-germanium carbide (SiGeC), carbon-doped silicon-germanium (SiGe:C), III-V group (e.g., GaAs, AlGaAs, InAs, InP, etc.), II-V group compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.) or other similar semiconductors. Furthermore, multilayer semiconductor materials may be used as the semiconductor material of the substrate 10. In some embodiments, the substrate 10 includes both a semiconductor material and a dielectric material. The semiconductor substrate 10 may also include organic semiconductors or layered semiconductors, such as Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. A portion or all of the semiconductor substrate 10 may be amorphous, polycrystalline, or monocrystalline. In addition to the types of semiconductor substrates described above, the semiconductor substrate 10 used in this invention may also include a mixed-orientation (HOT) semiconductor substrate, wherein the HOT substrate has surface regions with different crystal orientations.

[0033] The bottom electrode 12 may be formed, for example, from Ta, Ti / TiN, W, WN, TaN, polycrystalline silicon, doped polycrystalline silicon, amorphous silicon, doped amorphous silicon, or any other suitable material or any other conductive material. Alternatively, the bottom electrode 12 may be, for example, any suitable one or more conductive materials, such as Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W, or any other suitable material, and may be deposited or formed in any suitable manner.

[0034] Figure 2 This is an embodiment of the present invention. Figure 1 A cross-sectional view of a semiconductor structure in which heater elements are deposited and patterned.

[0035] In each exemplary embodiment, heater element 14 is deposited and patterned.

[0036] Heater element 14 is present on one side of dielectric layer 16. Heater element 14 comprises a thin layer of refractory material with a thickness between about 5 nanometers (nm) and about 100 nm, having a relatively high resistivity between about 100 ohm-cm (Ωcm) and about 10000 Ωcm (e.g., between about 500 Ωcm and about 3000 Ωcm). Suitable refractory materials include, but are not limited to, tantalum nitride (TaN) and materials having the chemical formula Ta. x Si y N z Metals in which x, y, and z are each between 0 and approximately 1.

[0037] Heater element 14 may include a conductive material that is chemically inert when in contact with materials used for the PCM stack and the top electrode. Examples of such conductive but chemically inert materials include carbon, TiN, and TaN. Titanium nitride and tantalum nitride both exhibit low diffusion rates for metallic elements. Therefore, forming heater element 14 from these materials prevents metallic elements contained in the top electrode from diffusing into the PCM stack.

[0038] The dielectric material of layer 16 may include, but is not limited to, ultra-low k (ULK) materials, such as porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and their porous variants, silsesquioxanes, siloxanes, or other dielectric materials having a dielectric constant, for example, in the range of about 2 to about 4. Dielectric layer 16 may have the same thickness as heater element 14.

[0039] Figure 3 This is an embodiment of the present invention. Figure 2 A cross-sectional view of a semiconductor structure in which resistive pads are deposited.

[0040] In various exemplary embodiments, a resistive pad 18 is deposited. The resistive pad 18 may be a metal nitride layer, such as titanium nitride (TiN). The resistive pad 18 is used for resistance drift correction.

[0041] In another embodiment, the resistive pad 18 may be, for example, TaN with different types of deposition (such as PVD, CVD, ALD) and different resistance values. This material is not limited to other metal types such as TiN, W, or amorphous carbon (aC), or dielectrics such as Al2O3, HfO2, SiN, ZrO2, etc.

[0042] Figure 4 This is an embodiment of the present invention. Figure 3 A cross-sectional view of a semiconductor structure in which a Ge-Sb-Te (germanium-antimony-tellurium or "GST") stack is formed.

[0043] In various exemplary embodiments, a phase change material stack 20 is deposited. The phase change material stack 20 may be a GST stack. The GST stack 20 may include a first layer 22, a second layer 24, a third layer 26, and a fourth layer 28.

[0044] In one example, the first layer 22 may be, for example, a low-Ge concentration GST (less than 20% Ge content). The second layer 24 may be, for example, a medium to low Ge concentration GST (between 20% and 40% Ge content). The third layer 26 may be, for example, a medium Ge concentration GST (between 40% and 70% Ge content). The fourth layer 28 may be, for example, a high Ge concentration GST (greater than 60% Ge content). No diffusion barrier or passivation layer is used between layers 22, 24, 26, and 28. Therefore, for better linearity, a single PCM device 30 is formed from multilayer phase change materials (e.g., GST) with different crystallization temperatures.

[0045] GST stack 20 can have different Ge / Te concentrations to have melting T gradients, where regions closer to heater 14 require lower melting T and different N concentrations to have different Rs, where N can be implanted or co-sputtered.

[0046] Figure 5 The top electrode is formed according to an embodiment of the present invention. Figure 4 A cross-sectional view of the semiconductor structure.

[0047] In various exemplary embodiments, an ILD 34 is deposited and a top electrode 32 is formed within the ILD 34. The GST stack 20 can be patterned to form a GST stack 30. Thus, the top electrode 32 directly contacts the patterned GST stack 30.

[0048] Structure 35 illustrates a GST stack 30 formed between the top electrode 32 and the bottom electrode 12. Therefore, structure 35 employs multiple GST materials with different crystallization temperatures and / or resistivities to improve device linearity. Structure 35 can be referred to as a mushroom structure, where the higher crystallization temperature is at the top of the GST stack 30 and the lower crystallization temperature is at the bottom of the GST stack 30. In other words, the crystallization temperature increases with each layer added. Therefore, moving from the bottom to the top of structure 35, the crystallization temperature increases. The crystallization temperature changes in ascending order from the bottom electrode to the top electrode, or alternatively, in descending order from the top electrode to the bottom electrode. Different crystallization temperatures can be achieved through doping and / or different material contents.

[0049] The top electrode 32 may be formed, for example, from Ta, Ti / TiN, W, WN, TaN, polycrystalline silicon, doped polycrystalline silicon, amorphous silicon, doped amorphous silicon, or any other suitable material or any other conductive material. Alternatively, the top electrode 32 may be, for example, any suitable one or more conductive materials, such as Ag, Al, Cu, Ta, TaN, Ti, TiN, Al, W, or any other suitable material, and may be deposited or formed in any suitable manner.

[0050] ILD 34 may comprise any material known in the art, such as porous silicates, carbon-doped oxides, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials. ILD 34 may be formed using any method known in the art, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. ILD 34 may have a thickness ranging from about 25 nm to about 200 nm.

[0051] Phase change materials (PCMs) can be changed from one phase state to another by applying electrical pulses. Shorter, higher amplitude pulses tend to change PCMs to a generally amorphous state and are called reset pulses. Longer, lower amplitude pulses tend to change PCMs to a generally crystalline state and are called program pulses. Shorter, higher amplitude pulses have enough energy to melt the material in the active volume and are short enough to allow the material to solidify in the amorphous state.

[0052] Phase change materials can include chalcogenide-based materials and other materials. Chalcogenides include any one of the four elements that make up Group VI of the periodic table: oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). Chalcogenides also include compounds of chalcogen elements that have a more positive charge or are radicals. Chalcogenide alloys include combinations of chalcogenides with other materials such as transition metals. Chalcogenide alloys typically include one or more elements from column VI of the periodic table, such as germanium (Ge) and tin (Sn). Typically, chalcogenide alloys include combinations of one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Phase-change based memory materials can include the following alloys: Ga / Sb, In / Sb, In / Se, Sb / Te, Ge / Te, Ge / Sb / Te, In / Sb / Te, Ga / Se / Te, Sn / Sb / Te, In / Sb / Ge, Ag / In / Sb / Te, Ge / Sn / Sb / Te, Ge / Sb / Se / Te, and Te / Ge / Sb / S. Within the Ge / Sb / Te alloy family, a wide range of alloy compositions can be used.

[0053] In some embodiments, chalcogenides and other phase change materials are doped with impurities to modify the conductivity, transition temperature, melting temperature, and other properties of memory elements using the doped chalcogenides. Representative impurities used for doping chalcogenides include nitrogen, silicon, oxygen, silicon dioxide, silicon nitride, copper, silver, gold, aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum nitride, titanium, and titanium oxide.

[0054] In this example, the phase change material stack 30 preferably comprises a Ge-Sb-Te (germanium-antimony-tellurium or "GST") alloy. Alternatively, other suitable materials for the phase change material stack 30 may include Si-Sb-Te alloys, Ga-Sb-Te alloys, As-Sb-Te alloys, Ag-In-Sb-Te alloys, Ge-In-Sb-Te alloys, Ge-Sb alloys, Sb-Te alloys, Si-Sb alloys, and combinations thereof.

[0055] Figure 6 This is a cross-sectional view of a semiconductor structure including a bottom electrode formed above a substrate, according to another embodiment of the present invention.

[0056] The semiconductor structure 5' includes a bottom electrode 12 formed above the substrate 10. The bottom electrode 12 may be formed within the substrate 10.

[0057] Figure 7 This is an embodiment of the present invention. Figure 6 A cross-sectional view of the semiconductor structure, in which a GST stack is formed above the bottom electrode.

[0058] In various exemplary embodiments, a phase change material stack 40 is deposited. The phase change material stack 40 may be a GST stack. The GST stack 40 may include a first layer 42, a second layer 44, a third layer 46, a fourth layer 48, a fifth layer 50, a sixth layer 52, and a seventh layer 54.

[0059] In one example, the first layer 42 can be, for example, a high-germanium (Ge) concentration GST (greater than 60% Ge content). The second layer 44 can be, for example, a medium-Ge concentration GST (between 40% and 70% Ge content). The third layer 46 can be, for example, a low-to-medium Ge concentration GST (between 20% and 40% Ge content). The fourth layer 48 can be, for example, a low-Ge concentration GST (less than 20% Ge content). The fifth layer 50 can be, for example, a low-to-medium Ge concentration GST (between 20% and 40% Ge content). The sixth layer 52 can be, for example, a medium-Ge concentration GST (between 40% and 70% Ge content). The seventh layer 54 can be, for example, a high-germanium (Ge) concentration GST (greater than 60% Ge content). No diffusion barrier layers are used between layers 42, 44, 46, 48, 50, 52, and 54. Therefore, for better linearity, multilayer phase change materials (e.g., GST) with different crystallization temperatures are formed into a single PCM device 40. In structure 40, the central or intermediate region has the lowest crystallization temperature.

[0060] Figure 8 This is an embodiment of the present invention. Figure 7 A cross-sectional view of a semiconductor structure in which the phase change material stack is patterned.

[0061] In various exemplary embodiments, the phase change material stack 40 is patterned to form a GST stack 40'.

[0062] Figure 9 This is an embodiment of the present invention. Figure 8 A cross-sectional view of a semiconductor structure, in which a resistive pad is deposited on top of a patterned stack of phase change material.

[0063] In various exemplary embodiments, a resistive pad 60 is deposited over a patterned phase change material stack 40'. The resistive pad 60 is used for resistance drift correction.

[0064] The resistive pad 60 can be a metal nitride layer, such as titanium nitride (TiN).

[0065] In another embodiment, the resistive pad 60 may be, for example, TaN with different types of deposition (such as PVD, CVD, ALD) and different resistance values. This material is not limited to other metal types such as TiN, W or amorphous carbon (aC) and dielectrics such as Al2O3, HfO2, SiN, ZrO2, etc.

[0066] Figure 10 This is an embodiment of the present invention. Figure 9 A cross-sectional view of a semiconductor structure in which the interlayer dielectric (ILD) is deposited and planarized.

[0067] In various exemplary embodiments, the ILD 62 is deposited and planarized, for example, by chemical mechanical polishing (CMP), thereby exposing the top surface of the seventh layer 54.

[0068] Figure 11 This is an embodiment of the present invention. Figure 10 A cross-sectional view of a semiconductor structure, wherein the top electrode is formed above a patterned stack of phase change material.

[0069] In various exemplary embodiments, a top electrode 64 is formed over a patterned phase change material stack body 40'. The top electrode 64 may be formed within a dielectric layer 66. In one example, the dielectric layer 66 may be an ILD layer. Structure 70 illustrates a GST stack body 40' formed between the top electrode 64 and the bottom electrode 12. The top electrode 64 and the bottom electrode 12 are in direct contact with the GST stack body 40'. The top electrode 64 is also in direct contact with the resistive pad 60.

[0070] Structure 70 uses multiple GST materials with different crystallization temperatures and / or resistivities to improve the linearity of the device. Structure 70 can be referred to as a confined-unit GST structure, where higher crystallization temperatures are at the top of the GST stack 30 and lower crystallization temperatures are in the middle or center of the GST stack 30. In other words, with each layer added, the crystallization temperature decreases to a specific point and then increases. Thus, moving from the bottom to the middle of structure 70, the crystallization temperature decreases to the midpoint. At the midpoint, moving from the middle to the top of structure 70, the crystallization temperature increases to the highest level. The crystallization temperature changes in descending order from the bottom electrode to the middle and in ascending order from the middle electrode to the top electrode. Different crystallization temperatures can be achieved through doping and / or different material contents.

[0071] In summary, the structure of an exemplary embodiment of the present invention can be a mushroom-shaped GST structure with multiple GST stacks having different crystallization temperatures, wherein the crystallization temperatures are ordered from high to low from top to bottom, and wherein different crystallization temperatures can be achieved by doping and / or different material contents. The method of an exemplary embodiment of the present invention includes a confined unit GST structure with multiple GST stacks having different crystallization temperatures, wherein the crystallization temperatures are ordered from high to low from top and bottom to center, and furthermore, these different crystallization temperatures can be achieved by doping and / or different material contents. Therefore, exemplary embodiments of the present invention generate multiple stakes or continuous stacks of PCM films with different G characteristics relative to a set pulse by chemical doping of the same material and / or gradual changes in the material composition. G differs from low to high and from top to bottom. Improved G linearity relative to a set number of pulses can be achieved by manipulating the layer composition gradient and / or thickness. Furthermore, the same pulse is used throughout the stack.

[0072] Furthermore, exemplary embodiments of the present invention employ PCM, which can be used in neuromorphic computing applications, as described below. Figure 12 and 13 As described herein, the linearity of conductivity is valuable for weight updates for neuromorphic computation purposes. Therefore, the improved linearity of the mushroom and constrained unit devices described herein can be beneficial for neuromorphic computation applications.

[0073] Figure 12 This is a block / flowchart of an exemplary neuromorphic and synaptic network according to an embodiment of the present invention, which includes cross-sections of electronic synapses that interconnect electronic neurons and axons.

[0074] Example tile circuit 100 has cross-body 112 according to an embodiment of the invention. In one example, the entire circuit may include a “hyper-dense cross-body array” having a spacing in the range of about 0.1 nm to 10 μm. Neuromorphological and synaptic circuit 100 includes cross-body 112 interconnecting multiple digital neurons 111 including neurons 114, 116, 118, and 120. These neurons 111 are also referred to herein as “electronic neurons.” For illustrative purposes, example circuit 100 provides symmetrical connections between two pairs of neurons (e.g., N1 and N3). However, embodiments of the invention are useful not only for such symmetrical connections of neurons but also for asymmetrical connections of neurons (neurons N1 and N3 do not need to be connected by the same connections). The cross-body in the tile is adapted to an appropriate ratio of synapses to neurons and therefore does not need to be square.

[0075] In example circuit 100, neuron 111 is connected to crossbody 112 via dendritic pathways / wires (dendrites) 113 (such as dendrites 126 and 128). Neuron 111 is also connected to crossbody 112 via axonal pathways / wires (axons) 115 (e.g., axons 134 and 136). Neurons 114 and 116 are dendritic neurons, and neurons 118 and 120 are axonal neurons connected to axon 113. Specifically, neurons 114 and 116 are shown having outputs 122 and 124 respectively connected to dendrites (e.g., bit lines) 126 and 128. Axonal neurons 118 and 120 are shown having outputs 130 and 132 respectively connected to axons (e.g., word lines or access lines) 134 and 136.

[0076] When any of neurons 114, 116, 118, and 120 is fired, it will pulse to its axon and to its dendritic connections. Each synapse provides contact between the axon of one neuron and the dendrites of another neuron, and the two neurons are referred to as the presynapse and postsynapse, respectively, relative to that synapse.

[0077] The connections between dendrites 126, 128 and axons 134, 136 are achieved via digital synaptic devices 131 (synapses). The node where the synaptic device is located may be referred to herein as a "crossover node". Typically, according to embodiments of the invention, neurons 114 and 116 will "fire" (emit pulses) in response to inputs received from their axonal input connections (not shown) exceeding a threshold. Neurons 118 and 120 will "fire" (emit pulses) in response to inputs received from their external input connections (not shown) (typically from other neurons) exceeding a threshold. In one embodiment, when neurons 114 and 116 fire, they maintain decaying post-synaptic STDP (post-STDP) variables. For example, in one embodiment, the decay period may be 50 ms. The post-STDP variable is used to implement STDP by encoding the time of the last firing of the associated neuron. This STDP is used to control long-term enhancement or "enhancement," in which context, long-term enhancement or "enhancement" is defined as an increase in synaptic conductance. When neurons 118 and 120 are fired, they maintain the presynaptic STDP (presynaptic STDP) variable, which decays in a similar manner to neurons 114 and 116.

[0078] For example, the pre-STDP and post-STDP variables can decay according to exponential, linear, polynomial, or quadratic functions. In another embodiment of the invention, these variables can increase rather than decrease over time. In any case, this variable can be used to implement STDP by encoding the time of the last firing of the associated neuron. STDP is used to control long-term inhibition, or “repression,” which is defined in this context as a reduction in synaptic conduction rate. Note that the effects of the pre-STDP and post-STDP variables can be opposite to those of pre-STDP achieving enhancement and post-STDP achieving inhibition.

[0079] An external bidirectional communication environment can provide sensory input and consume motor output. Digital neurons 111, implemented using complementary metal-oxide-semiconductor (CMOS) logic gates, receive and integrate spike inputs. In one embodiment, neuron 111 includes comparator circuitry that generates a spike when the integrated input exceeds a threshold. In one embodiment, binary synapses are implemented using transposeable 1-bit static random access memory (SRAM) cells, where each neuron 111 can be an excitatory or inhibitory neuron (or both). Each learning rule on the axon and dendrites of each neuron can be reconfigured as described below. This assumes transposeable access to the cross-body memory array. Neurons that select spikes one at a time send spike events to the corresponding axons, where the axons may reside on a core or elsewhere in a larger system with many cores.

[0080] As used herein, the term "electronic neuron" refers to an architecture configured to mimic biological neurons. Electronic neurons create connections between processing elements that are substantially functionally equivalent to neurons in a biological brain. Thus, a neuromorphic and synaptic system including electronic neurons according to embodiments of the invention may include different electronic circuits modeled after biological neurons. Furthermore, a neuromorphic and synaptic system including electronic neurons according to embodiments of the invention may include different processing elements (including computer simulations) modeled after biological neurons. While certain illustrative embodiments of the invention have been described herein using the term "electronic neuron including electronic circuits," the invention is not limited to electronic circuits. A neuromorphic and synaptic system according to embodiments of the invention may be implemented as including circuitry and additionally as a computer-simulated neuromorphic and synaptic architecture. In practice, embodiments of the invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment including both hardware and software elements.

[0081] Figure 13 A block diagram depicts the components of a computing system including a computing device and a neuromorphic chip according to an embodiment of the present invention.

[0082] Figure 13A block diagram depicts the components of a system 200, including a computing device 205. It should be understood that... Figure 13 This illustration provides only one possible implementation and does not imply any limitation regarding the environment in which different embodiments may be implemented. Many modifications can be made to the depicted environment.

[0083] The computing device 205 includes a communication structure 202 that provides communication between the computer processor 204, memory 206, permanent memory 208, communication unit 210, and input / output (I / O) interface 212. The communication structure 202 can be implemented using any architecture designed to transfer data and / or control information between processors (such as microprocessors, communication and network processors, etc.), system memory, peripheral devices, and any other hardware components within the system. For example, the communication structure 202 can be implemented using one or more buses.

[0084] Memory 206, cache memory 216, and permanent memory 208 are computer-readable storage media. In this embodiment, memory 206 includes random access memory (RAM) 214. Memory 214 may also be a phase-change memory as exemplified in this embodiment of the invention. Typically, memory 206 may include any suitable volatile or non-volatile computer-readable storage medium.

[0085] In some embodiments of the invention, the deep learning program 225 is included in and operated by the neuromorphic chip 222 as a component of the computing device 205. In other embodiments, the deep learning program 225 is stored in permanent storage 208 for execution by the neuromorphic chip 222 in conjunction with one or more memory units in memory 206 and one or more computer processor units in corresponding computer processors 204. In this embodiment, the permanent storage 208 includes a magnetic hard disk drive. Alternatively, or in addition to a magnetic hard disk drive, the permanent storage 208 may include a solid-state hard disk drive, a semiconductor storage device, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0086] The media used in the persistent storage device 208 can also be removable. For example, a removable hard disk drive can be used for the persistent storage device 208. Other examples include optical discs and disks, thumb drives and smart cards, which are inserted into the drive to be transferred to another computer-readable storage medium that is also part of the persistent storage device 208.

[0087] In some embodiments of the invention, a neuromorphic chip 222 is included in a computing device 205 and connected to a communication structure 202. The neuromorphic chip 222 includes electronic logic for providing a stacked Restricted Boltzmann machine and a feedforward neural network including deep learning algorithm components that are trainable and perform machine learning. In other embodiments, logistical and algorithmic component operations are performed by a dedicated data structure included within the computing device 205 and the feedforward neural network, which performs the deep learning functions of the stacked Restricted Boltzmann machine.

[0088] In these examples, communication unit 210 provides communication with other data processing systems or devices, including resources of a distributed data processing environment. In these examples, communication unit 210 includes one or more network interface cards. Communication unit 210 can provide communication using either or both physical and wireless communication links. Deep learning program 225 can be downloaded to permanent storage 208 via communication unit 210.

[0089] I / O interface 212 allows data input and output to other devices that can be connected to computing system 200. For example, I / O interface 212 can provide connectivity to external device 218 (such as a keyboard, keypad, touchscreen, and / or other suitable input devices). External device 218 may also include portable computer-readable storage media, such as thumb drives, portable optical discs or disks, and memory cards.

[0090] Display 220 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

[0091] about Figure 1-11Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD). As used herein, “deposition” can include any now-known or later-developed technique suitable for the material to be deposited, including, but not limited to, chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmospheric CVD (SACVD), and high-density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), finite reaction process CVD (LRPCVD), metal-organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitriding, spin coating, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), electroplating, and evaporation.

[0092] It should be understood that the invention will be described based on the given illustrative architecture; however, other architectures, structures, substrate materials, and process features and steps / blocks may vary within the scope of the invention.

[0093] It will also be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, the element may be directly on the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly on" or "directly above" another element, no intermediate elements are present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0094] This embodiment may include a design for an integrated circuit chip, which can be created using a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk, or virtual hard disk, such as in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the obtained design directly or indirectly to such an entity via physical mechanisms (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing a photomask, which includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer to be etched or processed.

[0095] The methods described herein can be used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in a package. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with one or both surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0096] It should also be understood that the material compounds will be described based on the listed elements (e.g., SiGe). These compounds include elements in different proportions within the compound; for example, SiGe includes Si. x Ge 1-x Where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and still function according to embodiments of the invention. Compounds having additional elements will be referred to herein as alloys. References to "one embodiment" or "embodiment" and other variations thereof in the specification mean that a particular feature, structure, property, etc., described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0097] It should be understood that, for example, in the cases of “A / B,” “A and / or B,” and “at least one of A and B,” the use of any one of the following “ / ,” “and / or,” and “at least one” is intended to cover the selection of only the first listed option (A), or only the selection of the second listed option (B), or the selection of both options (A and B). As another example, in the cases of “A, B, and / or C” and “at least one of A, B, and C,” this wording is intended to cover only the selection of the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed items (A and C), or only the second and third listed items (B and C), or all three options (A, B, and C). It will be apparent to those skilled in the art that this can be extended for many of the listed items.

[0098] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to also include the plural forms. It should be further understood that, when used herein, the terms “comprising,” “including,” and / or “having” specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0099] To facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein. It will be understood that spatial relative terms are intended to cover different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features would be oriented “above” other elements or features. Thus, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as “between” two layers, the layer may be the only layer between the two layers, or one or more intermediate layers may exist.

[0100] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0101] Preferred embodiments of PCM cells employing multiple stacks of GST materials with different crystallization temperatures and / or resistivities to improve device linearity have been described (these are intended to be illustrative and not restrictive). It should be noted that modifications and variations can be made by those skilled in the art based on the above teachings. Therefore, it should be understood that changes may be made to the specific embodiments described within the scope of the invention as outlined in the appended claims. Aspects of the invention have thus been described, along with the details and specificities required by patent law, and the claims and desired aspects protected by patent certificates are enumerated in the appended claims.

Claims

1. A method for improving the linearity of a phase-change memory (PCM) cell structure, the method comprising: A bottom electrode is formed above the substrate; A heating element is formed on the upper surface of the bottom electrode, which is in contact with the upper surface of the bottom electrode; A resistive pad with a flat surface is formed on the upper surface of the heating element, and the resistive pad contacts only the upper surface of the heating element; A PCM stack comprising multiple PCM layers is constructed above the flat surface of the resistive pad, each PCM layer having a different crystallization temperature. as well as A top electrode is formed above the PCM stack. One of the following is true: the crystallization temperature changes in ascending order from the bottom electrode to the top electrode; The crystallization temperature in the central region of the PCM stack is low, while the crystallization temperature in the top and bottom regions of the PCM stack is high.

2. The method according to claim 1, wherein, Each of the plurality of PCM layers comprises a Ge-Sb-Te alloy.

3. The method according to claim 1, wherein, The crystallization temperature changes in ascending order from the bottom electrode to the top electrode, and the plurality of PCM layers comprises four layers.

4. The method according to claim 3, wherein, The first layer contains less than 20% germanium (Ge), the second layer contains between 20% and 40% Ge, the third layer contains between 40% and 70% Ge, and the fourth layer contains more than 60% Ge.

5. The method according to claim 1, wherein, The crystallization temperature changes in ascending order from the bottom electrode to the top electrode.

6. The method according to claim 1, wherein, The different crystallization temperatures are achieved by doping and / or varying material contents.

7. The method according to claim 1, wherein, The crystallization temperature in the central region of the PCM stack is low, while the crystallization temperature in the top and bottom regions of the PCM stack is high, and the plurality of PCM layers comprises seven layers.

8. The method according to claim 7, wherein, The first layer contains more than 60% germanium (Ge), the second layer contains between 40% and 70% Ge, the third layer contains between 20% and 40% Ge, the fourth layer contains less than 20% Ge, the fifth layer contains between 20% and 40% Ge, the sixth layer contains between 40% and 70% Ge, and the seventh layer contains more than 60% Ge.

9. The method according to claim 1, wherein, The crystallization temperature in the central region of the PCM stack is low, while the crystallization temperature in the top and bottom regions of the PCM stack is high, and the resistive pad is disposed near the sidewall of the PCM stack.

10. The method according to claim 1, wherein, The crystallization temperature is low in the central region of the PCM stack and high in the top and bottom regions of the PCM stack, and the crystallization temperature changes in ascending order in a portion of the PCM stack.

11. The method according to claim 1, wherein, The crystallization temperature is low in the central region of the PCM stack, and high in the top and bottom regions of the PCM stack, with the crystallization temperature changing in descending order within a portion of the PCM stack.

12. A semiconductor structure, comprising: The bottom electrode is disposed above the substrate; A heating element disposed on the upper surface of the bottom electrode and in contact with the upper surface of the bottom electrode; A resistive pad with a flat surface is disposed on the upper surface of the heating element, and the resistive pad contacts only the upper surface of the heating element; A PCM stack disposed above the flat surface of the resistive pad, the PCM stack comprising multiple PCM layers, each PCM layer having a different crystallization temperature; and The top electrode is disposed above the PCM stack. One of the following is true: the crystallization temperature changes in descending order within at least a portion of the PCM stack; or the crystallization temperature changes in ascending order from the bottom electrode to the top electrode. The crystallization temperature is low in the central region of the PCM stack, and high in the top and bottom regions of the PCM stack.

13. The semiconductor structure according to claim 12, wherein, Each of the plurality of PCM layers comprises a Ge-Sb-Te alloy.

14. The semiconductor structure according to claim 13, wherein, The different crystallization temperatures are achieved by doping and / or varying material contents.

15. The semiconductor structure according to claim 12, wherein, The crystallization temperature changes in descending order within at least a portion of the PCM stack, and the first layer of the PCM stack contains less than 20% germanium (Ge), the second layer of the PCM stack contains between 20% and 40% Ge content, the third layer of the PCM stack contains between 40% and 70% Ge content, and the fourth layer of the PCM stack contains more than 60% Ge content.

16. The semiconductor structure according to claim 12, wherein, The crystallization temperature varies in descending order within at least a portion of the PCM stack, and the descending order is from the top electrode to the bottom electrode.

17. The semiconductor structure according to claim 12, wherein, The crystallization temperature in the central region of the PCM stack is low, and the crystallization temperature in the top and bottom regions of the PCM stack is high. The plurality of PCM layers comprises seven layers, wherein the first layer comprises a germanium (Ge) content greater than 60%, the second layer comprises a Ge content between 40% and 70%, the third layer comprises a Ge content between 20% and 40%, the fourth layer comprises a Ge content less than 20%, the fifth layer comprises a Ge content between 20% and 40%, the sixth layer comprises a Ge content between 40% and 70%, and the seventh layer comprises a Ge content greater than 60%.

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