Semiconductor device and method for manufacturing the same

Abstract

Suitable for manufacturing semiconductor devices that include both elements using polysilicon and elements using oxide semiconductors in electronic circuits. A first semiconductor region formed of a polysilicon film 54 is formed on an insulating substrate 50, and insulating films 55 and 58 are stacked on the first semiconductor region. After forming contact holes 63 in the insulating films 55 and 58, an oxide semiconductor film 82 is formed on the surface of the insulating film 58b. An etching mask 84 is formed on the surface of the oxide semiconductor film 82. The oxide semiconductor film 82 is etched using this etching mask 84, removing the oxide semiconductor film 82 from the contact hole 63 and forming a second semiconductor region formed of the oxide semiconductor film 60. A conductive material is embedded in the contact hole 63 to form contact electrodes 62s and 62d electrically connected to the first semiconductor region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a semiconductor region formed of polysilicon and a semiconductor region formed of a metal oxide semiconductor (hereinafter referred to as an oxide semiconductor) and a method for manufacturing the same. Background Art

[0002] In recent years, display devices using thin-film transistors (TFTs) on insulating substrates to form pixel circuits have become practical. Examples of display devices include organic EL displays using organic electroluminescence (EL) elements and liquid crystal displays.

[0003] A typical TFT includes a semiconductor layer made of amorphous silicon, polycrystalline silicon, or the like. For example, low-temperature polycrystalline silicon (LTPS), formed at low temperatures, is used as the semiconductor layer. Recently, pixel circuits are also using TFTs that include an oxide semiconductor layer, typified by indium gallium zinc oxide (IGZO).

[0004] For example, TFTs using LTPS (hereinafter referred to as LTPS-TFTs) have the advantages of high reliability and high electron mobility, while TFTs using oxide semiconductors (hereinafter referred to as OS-TFTs) have the advantage of low leakage current. To take advantage of the advantages of these respective device characteristics and manufacturing processes, devices such as hybrid display devices combining the two TFTs have been proposed.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-173505 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] In the case of a device in which two TFTs are mixed, the manufacturing process becomes complicated, and research has been conducted to reduce the process load and cost. As one of them, when connecting a signal line to a source / drain portion formed of LTPS in an LTPS-TFT, an operation of removing the surface oxide film of LTPS with hydrofluoric acid (hereinafter referred to as hydrofluoric acid (original Japanese: フッ酸)) is performed. When this process is carried out after forming the oxide semiconductor region of an OS-TFT, it is necessary to protect the oxide semiconductor region using a photoresist. However, due to pinholes, pattern defects, etc. in the photoresist, disappearance of the oxide semiconductor layer can easily occur.

[0010] Figure 8 FIG. is a process flow diagram for explaining this conventional process. In Figure 8 In the state shown in (a) of, on the LTPS layer 2 formed on the insulating substrate 1, insulating films 3 to 5 and the gate electrode 6 of the LTPS-TFT are formed, and further, an oxide semiconductor layer 7 is formed on its surface. A photoresist film 8 ( Figure 8 in (b) of) is formed on this surface, and by dry etching or the like, the insulating films 3 to 5 in the opening 9 portion of the photoresist film 8 are removed to form a contact hole 10 reaching the LPTS layer 2 ( Figure 8 in (c) of). Then, after removing the photoresist film 8 ( Figure 8 in (c) of), a signal line formed of metal or the like is formed in the contact hole 10 ( Figure 8 in (d) of).

[0011] In this process, after forming the contact hole 10 and before removing the photoresist film 8, the above-mentioned surface oxide film of LTPS is removed by hydrofluoric acid cleaning. Figure 9 FIG. is a schematic vertical cross-sectional view near the oxide semiconductor layer 7 when hydrofluoric acid cleaning is performed. The photoresist film 8 exists at the position shown by the dotted line 8b all the time in the state of (b) of Figure 8 , that is, at the moment when the photoresist film 8 is patterned to form the opening 9, but is eroded during subsequent processes such as dry etching for forming the contact hole 10. The covering property of the photoresist film 8 can be different between the flat portion and the stepped portion, and at the stepped portion at the end of the oxide semiconductor layer 7, the photoresist film 8 can become thinner or pinholes can occur. Combining this with the above-mentioned erosion, hydrofluoric acid passes through the photoresist film 8 at this stepped portion, and disappearance of the above-mentioned oxide semiconductor layer easily occurs.

[0012] The present invention solves the above problems and can suitably manufacture a semiconductor device including both an element using polysilicon and an element using an oxide semiconductor in an electronic circuit.

[0013] Means for Solving the Problems

[0014] (1) The method for manufacturing a semiconductor device according to the present invention comprises: a step of forming a first semiconductor region formed of a polysilicon film on an insulating substrate; a step of stacking an insulating film on the first semiconductor region; a step of forming a contact hole in the insulating film that reaches the first semiconductor region; a step of forming an oxide semiconductor film on the surface of the insulating film in which the contact hole is formed; a step of forming an etching mask on the surface of the oxide semiconductor film; a step of etching the oxide semiconductor film using the etching mask to remove the oxide semiconductor film from the contact hole and form a second semiconductor region formed of the oxide semiconductor film; and a step of burying a conductive material in the contact hole to form a contact electrode electrically connected to the first semiconductor region.

[0015] (2) The semiconductor device according to the present invention comprises: an insulating substrate; a first semiconductor region formed of polycrystalline silicon formed on the insulating substrate; an insulating film stacked on the first semiconductor region; a contact hole formed in the insulating film and reaching the first semiconductor region; a second semiconductor region formed of an oxide semiconductor formed on the insulating film; and a contact electrode formed of a conductive material embedded in the contact hole and electrically connected to the first semiconductor region, wherein the insulating film contains a metal element constituting the oxide semiconductor at the boundary surface with the contact hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] [ Figure 1 ] is a schematic stereoscopic diagram showing an organic EL display device involved in an embodiment of the present invention.

[0017] [ Figure 2 ] is a schematic top view showing the general structure of the organic EL display device involved in an embodiment of the present invention.

[0018] [ Figure 3 ] is a circuit diagram of each pixel of the organic EL display device involved in an embodiment of the present invention.

[0019] [ Figure 4 ] is a schematic vertical cross-sectional view of the organic EL display device involved in this embodiment.

[0020] [ Figure 5 ] is a process flow chart illustrating the features of the manufacturing method of the array substrate involved in the present invention.

[0021] [ Figure 6 ] is a process flow chart illustrating the features of the manufacturing method of the array substrate involved in the present invention.

[0022] [ Figure 7 ] is a schematic vertical cross-sectional view of a portion of the driving transistor DRT in the array substrate according to the present invention.

[0023] [ Figure 8 ] is a process flow chart illustrating the existing process.

[0024] [ Figure 9 ] is a schematic vertical cross-sectional view showing the vicinity of the oxide semiconductor layer during hydrofluoric acid cleaning. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention can be implemented in various forms within the scope of the present invention and is not to be construed as being limited to the following exemplary embodiments.

[0026] To clarify the description, the drawings may sometimes schematically illustrate the width, thickness, shape, etc. of various parts compared to actual embodiments. However, these are merely examples and do not limit the interpretation of the present invention. In this specification and the drawings, elements having the same functions as those described in the accompanying drawings are denoted by the same reference numerals, and duplicate descriptions may be omitted.

[0027] Furthermore, in the detailed description of the present invention, when specifying the positional relationship between a certain structure and other structures, the so-called "upper" and "lower" not only refer to the situation where they are located directly above or below a certain structure, but also include the situation where there are other structures in between unless otherwise specified.

[0028] The following describes a pixel circuit in an organic EL display device as an embodiment of a semiconductor device according to the present invention. The organic EL display device has a plurality of pixels arranged two-dimensionally in an image display area, and each pixel includes an OLED (organic light emitting diode) as an organic EL element.

[0029] Figure 1A schematic three-dimensional diagram of an organic EL display device 20 according to an embodiment of the present invention is shown. The organic EL display device 20 has an array substrate 22 on which a display area 21 having a plurality of pixels arranged in a two-dimensional manner is formed. Here, the array substrate 22 is equivalent to the semiconductor device of the embodiment, and the array substrate 22 is formed with a stacked structure such as TFT and OLED on a base material (insulating substrate) formed by a glass substrate, a flexible resin film, etc. On the array substrate 22, in addition to forming an OLED and a pixel circuit for each pixel, a driving circuit (not shown) for controlling a plurality of pixels may also be formed. In addition, signals and power for controlling a plurality of pixels are input via a flexible printed circuit (Flexible Print Circuit: FPC) 24. The FPC 24 is crimped onto a terminal (not shown) formed on the array substrate 22 for electrical connection. In order to protect the display area 21, a display surface protective film 25 or an opposing substrate may also be provided.

[0030] Figure 2 1 is a schematic plan view showing a schematic configuration of an organic EL display device 20 according to an embodiment of the present invention. Figure 3 This is a circuit diagram of each pixel of the organic EL display device 20 according to an embodiment of the present invention. The organic EL display device 20 controls the light emission of the OLED provided in each pixel by a control device 31, a scanning line driving circuit 32, and an image line driving circuit 33 to display an image.

[0031] The scanning line driving circuit 32 is connected to scanning signal lines 34 provided for the horizontal arrangement of pixels (pixel rows), and the image line driving circuit 33 is connected to image signal lines 35 provided for the vertical arrangement of pixels (pixel columns).

[0032] Each pixel's circuit includes a pixel transistor SST, a drive transistor DRT, and a holding capacitor Cs. These are connected to a scanning signal line 34 and an image signal line 35, and control the light emission of the OLED in that pixel based on the signals supplied from these signal lines. The pixel transistor SST and the drive transistor DRT are TFTs formed on the array substrate 22.

[0033] The gate of the pixel transistor SST is electrically connected to the scanning signal line 34. The scanning signal line 34 of each pixel row is commonly connected to the gates of multiple SSTs arranged along the pixel row. One of the source or drain of the SST is electrically connected to the image signal line 35, and the other is electrically connected to the gate of the driving transistor DRT. The image signal line 35 of each pixel column is commonly connected to the multiple SSTs arranged along the pixel column. The driving transistor DRT is, for example, a field effect transistor with an n-type channel, the source is electrically connected to the anode of the OLED, and the drain is electrically connected to the power line 36. The cathode of the OLED is fixed to a ground potential or a negative potential, and a potential that generates a positive voltage between the cathode potential of the OLED is supplied to the power line 36.

[0034] The scanning line driving circuit 32 sequentially selects the scanning signal lines 34 based on a timing signal input from the control device 31 , and applies a voltage for turning on the pixel transistor SST to the selected scanning signal line 34 .

[0035] The image line drive circuit 33 receives image signals from the control device 31 and, based on the selection of the scanning signal line 34 by the scanning line drive circuit 32, outputs a voltage corresponding to the image signal for the selected pixel row to each image signal line 35. This voltage is written to the holding capacitor Cs via the pixel transistor SST in the selected pixel row. The drive transistor DRT supplies a current corresponding to the written voltage to the OLED, thereby causing the OLED of the pixel corresponding to the selected scanning signal line 34 to emit light.

[0036] Here, the pixel transistor SST and the driving transistor DRT are disclosed as transistors constituting the pixel, but transistors having other functions may also be included.

[0037] It should be noted that Figure 2 In the figure, the scanning line driving circuit 32 and the image line driving circuit 33 are shown as separate blocks, but they can be assembled into one IC (Integrated Circuit) or formed separately in three or more places. When assembled into an IC, it can be mounted on the array substrate 22 or on the array substrate 22. Figure 1 shown on the FPC.

[0038] In this embodiment, Figure 3The pixel transistor SST of the two TFTs shown is a transistor having an oxide semiconductor layer. Specifically, the pixel transistor SST is a TFT (OS-TFT) whose channel layer is formed of a transparent amorphous oxide semiconductor (TAOS), for example, IGZO is used as TAOS. As mentioned above, the luminous intensity of the OLED is determined by the current value supplied by the driving transistor DRT, so it is preferable that the gate potential of the DRT remains constant throughout the luminous period. Therefore, in order to suppress the leakage of charge from the gate of the DRT, an OS-TFT with a small leakage current is used in the transistor connected to the gate of the DRT, that is, the SST.

[0039] On the other hand, the driving transistor DRT among the two TFTs is a transistor for controlling conduction between the pixel electrode and the power supply line 36 , and may be an LTPS-TFT.

[0040] Figure 4 : is a schematic vertical cross-sectional view of the organic EL display device 20 according to this embodiment. Specifically, Figure 4 The cross-sectional view of the portion corresponding to one pixel in the array substrate 22 shows the pixel transistor SST, the driving transistor DRT and the OLED. The array substrate 22 is manufactured using a semiconductor device manufacturing process and basically has Figure 4 The stacked structure is formed in sequence from the lower side.

[0041] The substrate 50 is formed from a flexible film such as polyimide or polyethylene terephthalate. Alternatively, the substrate 50 may be formed from other resins or glass. A primer layer 51 is provided on the upper surface of the substrate 50, serving as a barrier layer against impurities contained in the substrate 50. The primer layer 51 may be formed from a silicon oxide film, a silicon nitride film, or the like, and may also have a laminated structure thereof. For example, in this embodiment, the primer layer 51 has a three-layer structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are laminated in this order.

[0042] An additional film 52 may be provided on the undercoat layer 51 corresponding to the location of the drive transistor DRT. The additional film 52 can suppress changes in transistor characteristics caused by light intrusion from the back of the channel, or, for example, can be formed of a conductive material and impart a back-gate effect to the drive transistor by applying a predetermined potential. For example, the additional film 52 can be formed of molybdenum (Mo), tungsten (W), or alloys thereof (MoW).

[0043] On the additional film 52, an LTPS layer 54 is disposed, via an insulating layer 53, to form the semiconductor region (first semiconductor region) of the drive transistor DRT. In this embodiment, the LTPS layer 54 forms the channel region, source region, and drain region of the drive transistor DRT. It should be noted that the insulating layer 53 may be, for example, a silicon nitride film, a silicon oxide film, or a stacked film thereof.

[0044] After forming the LTPS layer 54, a gate insulating film 55 is formed from silicon oxide or the like, and a metal film stacked thereon is patterned to form a gate electrode 56 of the drive transistor DRT, a signal line 57 connected to the additional film 52, and the like. This metal film is formed, for example, of a MoW alloy with a three-layer structure (Ti / Al / Ti) of titanium (Ti), aluminum (Al), and titanium stacked in this order.

[0045] An inorganic film is stacked to cover the gate electrode 56 and the like as an interlayer insulating film 58. In this embodiment, the interlayer insulating film 58 has a stacked structure including a silicon nitride film 58a and a silicon oxide film 58b.

[0046] Pixel transistors SST and signal lines are formed on the interlayer insulating film 58. Specifically, a TAOS layer 60, which will become the semiconductor region (second semiconductor region) of the pixel transistor SST, is first formed on the surface of the silicon oxide film 58b. In this embodiment, the TAOS layer 60 constitutes the channel region, source region, and drain region of the pixel transistor SST.

[0047] After forming the TAOS layer 60, a conductive material is formed and patterned to form signal lines that serve as the source / drain electrodes (S / D electrodes) of the drive transistor DRT and the pixel transistor SST. It should be noted that the conductive material here is, for example, a metal. In this embodiment, a Ti / Al / Ti film is used.

[0048] The S / D electrodes 61 of the pixel transistor SST overlap with and are electrically connected to the end surface of the TAOS layer 60. The S / D electrodes 62 (62s, 62d) of the drive transistor are connected to the LTPS layer 54 via contact holes 63 that penetrate the interlayer insulating film 58 and the gate insulating film 55. Here, a portion of the LTPS layer 54, including the portion connected to the S / D electrode 62s, serves as a source region, and a portion of the LTPS layer 54, including the portion connected to the S / D electrode 62d, serves as a drain region.

[0049] After forming the S / D electrodes 61 and 62, the metal film stacked thereon via the gate insulating film 65 is patterned to form the gate electrode 64 of the pixel transistor SST. That is, the pixel transistor SST is a top-gate TFT having a gate electrode 64 on the channel region (TAOS layer 60). In addition, the gate insulating film 65 can form a recessed portion between the S / D electrodes 61 on the TAOS layer 60, and the gate electrode 64 can be arranged in the recessed portion. In this case, a horizontal gap can be generated between the gate electrode 64 and the S / D electrode 61. The area in the TAOS layer 60 corresponding to the gap between the S / D electrode 61 and the gate electrode 64 is treated by ion implantation or the like through the gap to reduce resistance.

[0050] A passivation layer 66 and a planarization layer 67 are stacked as layers on the gate electrode 64. Pixel electrodes 68, which serve as the anode electrodes of the OLED, and banks 69, formed of an insulating material and separating the pixel electrodes 68, are arranged on the surface of the planarization layer 67. It should be noted that vertical wiring 71 for connecting the S / D electrodes 62s and the pixel electrodes 68 is provided in contact holes 70 extending from the surface of the passivation layer 66 to the S / D electrodes 62s. The pixel electrodes 68 are connected to the vertical wiring 71 via contact holes 72 provided in the planarization layer 67. The pixel electrodes 68 may be structured to reflect light emitted by the OLED toward the display surface. For example, they may be a stacked structure of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) and a reflective material such as silver (Ag).

[0051] The bank 69 is arranged along the periphery of the pixel, and the area forming the light-emitting surface of the OLED becomes the opening of the bank 69. The bank 69 covers the ends of the pixel electrode 68. On the other hand, the top surface of the pixel electrode 68 is exposed at the bottom of the opening, and an organic material layer 75, which serves as an organic layer including a light-emitting layer, is laminated on this surface. The bank 69 is formed of polyimide, acrylic resin, or the like.

[0052] A common electrode 76, which serves as the cathode electrode of the OLED, is formed on the organic material layer 75. It should be noted that the common electrode 76 is formed of a material that transmits light emitted from the organic material layer 75. Specifically, the common electrode 76 is formed of a metal with a low work function and is formed into a semi-transparent thin film to enable efficient electron injection into the organic material layer 75. For example, the common electrode 76 is formed of an MgAg alloy.

[0053] The OLED formed by the pixel electrode 68, the organic material layer 75 and the common electrode 76 is provided with a sealing film etc. to seal the upper surface of the OLED and prevent the OLED from being degraded by moisture. Figure 4In the figure, the structure on the OLED is omitted.

[0054] Figure 5 and Figure 6 For manufacturing Figure 4 The process flow chart of the array substrate 22 is used to illustrate the features of the present invention, and is shown with Figure 4 A schematic vertical cross-section of the array substrate 22 at the corresponding position.

[0055] exist Figure 5 In the array substrate 22 shown in (a), there is formed Figure 4 The stacked structure shown is from the substrate 50 to the interlayer insulating film 58. For the array substrate 22, a photoresist is applied to the surface of the interlayer insulating film 58 (silicon oxide film 58b) and patterned using a photolithography process to form a photoresist film 80 having an opening 80h at the location where the contact hole 63 is to be formed.

[0056] Dry etching or the like is performed using the photoresist film 80 as an etching mask to remove the insulating film below the opening 80 h , specifically, the interlayer insulating film 58 and the gate insulating film 55 , thereby forming a contact hole 63 reaching the LPTS layer 54 . Figure 5 (b) shows a state where the photoresist film 80 is removed after the contact hole 63 is formed.

[0057] By sputtering, a TAOS film 82 is formed to cover the surface of the interlayer insulating film 58 where the contact hole 63 is formed with the oxide semiconductor. Figure 5 (c)). For example, in this embodiment, as described above, IGZO is used as the oxide semiconductor. Here, the TAOS film 82 is also formed inside the contact hole 63.

[0058] The TAOS film 82 is patterned to form a TAOS layer 60 of a semiconductor region to be a pixel transistor SST. Specifically, a photoresist coated on the surface of the TAOS film 82 is patterned by a photolithography process to form a photoresist film 84 ( Figure 6 (a)). The photoresist film 84 is used as a mask to perform etching, and the TAOS film 82 outside the masked area is selectively removed, thereby forming a TAOS layer 60 ( Figure 6 (b)). This etching process is, for example, wet etching using acid as an etching solution.

[0059] exist Figure 6 (a) to Figure 6During step (b), the TAOS film 82 within the contact hole 63 is also removed. Furthermore, during this process, in preparation for the subsequent formation of the S / D electrodes 62, any oxide film that may be present on the surface of the LTPS layer 54 is also removed, exposing the LTPS layer 54 at the bottom of the contact hole 63. The etching of the TAOS film 82 and the etching of the surface oxide film of the LTPS layer 54 can be performed using the same etching solution or different etching solutions. For example, an etching solution containing hydrofluoric acid can be used to remove both the TAOS film 82 and the surface oxide film.

[0060] After the TAOS layer 60 is formed and the surface oxide film is removed, the photoresist film 84 used as an etching mask is removed from the surface of the array substrate 22 ( Figure 6 (c)), a metal film is formed on its surface, and the metal film is patterned using photolithography technology to form S / D electrodes 61 and 62 ( Figure 6 (d)). Here, the S / D electrode 62 is a contact electrode with the LTPS layer 54, and contacts the LTPS layer 54 at the bottom surface of the contact hole 63. Since the surface oxide film is removed in advance, the S / D electrode 62 and the LTPS layer 54 are properly electrically connected. Then, a Figure 4 The upper structure shown completes the array substrate 22.

[0061] Figure 7 FIG. 1 is a schematic vertical cross-sectional view of a portion of the driving transistor DRT in the array substrate 22. Figure 5 When the TAOS film 82 shown in (c) is formed, the component elements of the oxide semiconductor are injected into the surface of the array substrate 22 exposed to sputtering. As a result, a layer 90 containing metal elements constituting the oxide semiconductor is formed on the upper surface of the silicon oxide film 58b and the interface between the gate insulating film 55 and the interlayer insulating film 58 and the contact hole 63 (i.e., the surface of the insulating films 55 and 58 exposed on the side of the contact hole 63). In this embodiment, as described above, IGZO is used as the oxide semiconductor. Accordingly, a layer 90 containing at least one of indium, gallium, and zinc as a metal element can be present at the interface between the insulating film and the contact hole.

[0062] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, the configurations described in the embodiments may be replaced with substantially the same configurations, configurations having the same effects, or configurations capable of achieving the same purpose.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a first semiconductor region formed of a polysilicon film on an insulating substrate; a step of stacking an insulating film on the first semiconductor region; forming a contact hole in the insulating film that reaches the first semiconductor region; forming an oxide semiconductor film on the surface of the insulating film in which the contact hole is formed; forming an etching mask on a surface of the oxide semiconductor film; an etching step of etching the oxide semiconductor film using the etching mask to remove the oxide semiconductor film from the contact hole and to form a second semiconductor region formed of the oxide semiconductor film; and a step of embedding a conductive material in the contact hole to form a contact electrode electrically connected to the first semiconductor region; In the etching step, the oxide semiconductor film is etched using an etching solution containing hydrofluoric acid and the oxide semiconductor film is removed from the contact hole.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The oxide semiconductor film is formed of indium gallium zinc composite oxide (IGZO).

3. A semiconductor device, characterized in that have: insulating substrate; a first semiconductor region formed of polycrystalline silicon and formed on the insulating substrate; an insulating film stacked on the first semiconductor region; a contact hole formed in the insulating film and reaching the first semiconductor region; a second semiconductor region formed of an oxide semiconductor and formed on the insulating film; and a contact electrode formed of a conductive material embedded in the contact hole and electrically connected to the first semiconductor region; The second semiconductor region is formed by etching the oxide semiconductor using an etching solution containing hydrofluoric acid. The insulating film contains a metal element constituting the oxide semiconductor at a boundary surface with the contact hole.

4. The semiconductor device according to claim 3, wherein have: a first transistor having a channel region formed in the first semiconductor region; and A top-gate second transistor has a channel region formed in the second semiconductor region.

5. The semiconductor device according to claim 3, wherein The oxide semiconductor is indium gallium zinc composite oxide (IGZO), A layer containing at least any one of indium, gallium, and zinc as the metal element exists on the boundary surface between the insulating film and the contact hole.

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