Memory peripheral circuit having recessed channel transistors and method of forming the same

Abstract

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recessed channel transistor. The recessed channel transistor includes a well having a recess, a recessed gate structure protruding into the recess of the well and including a gate dielectric and a gate electrode on the gate dielectric, and a source and a drain spaced apart by the recessed gate structure. At least one of the source or the drain includes a first region in contact with the gate dielectric, and a second region having a higher doping concentration than the first region.

Description

Background Art

[0001] The present disclosure relates to semiconductor devices and methods of manufacturing the same.

[0002] Memory peripheral circuits (e.g., page buffer circuits, driver circuits, and input / output (I / O) circuits) are used to facilitate the operation of memory cells in memory devices such as NAND and NOR flash memory devices, phase change memory (PCM) devices, and ferroelectric memory devices. Transistors (e.g., metal oxide semiconductor (MOS) transistors) are used to form peripheral circuits. Therefore, in order to shrink memory chips, continuous shrinking of MOS transistors is required. Summary of the Invention

[0003] In one aspect, a memory device includes a memory cell array and a plurality of peripheral circuits coupled to the memory cell array. The peripheral circuits include a first peripheral circuit, which includes a recessed channel transistor. The recessed channel transistor includes: a well having a recess; a recessed gate structure protruding into the recess of the well and including a gate dielectric and a gate electrode on the gate dielectric; and a source and a drain separated by the recessed gate structure. At least one of the source or drain includes a first region in contact with the gate dielectric and a second region having a higher doping concentration than the first region.

[0004] In some embodiments, the difference in doping concentration between the first region and the second region is at least 10 times.

[0005] In some embodiments, the doping concentration of the first region is between 10 18 / cm 3 with 10 19 / cm 3 and the doping concentration of the second region is at least 10 20 / cm 3 .

[0006] In some embodiments, the thickness of the first region is greater than the thickness of the second region.

[0007] In some embodiments, the thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm.

[0008] In some embodiments, the recessed channel transistor further includes source / drain contacts contacting the second region.

[0009] In some embodiments, the well is a P-well, and at least one of the source or the drain is a drain doped with an N-type dopant.

[0010] In some embodiments, the recessed channel transistor further comprises a spacer structure on a sidewall of the gate electrode. In some embodiments, the source and drain are separated by the spacer structure and each comprises a raised portion above a bottom surface of the spacer structure and in contact with a sidewall of the spacer structure.

[0011] In some embodiments, the second region is at least in the elevated portion.

[0012] In some embodiments, the peripheral circuit further includes a second peripheral circuit, the second peripheral circuit including a planar transistor. In some embodiments, the planar transistor includes a well and a planar gate structure on the well, and the planar gate structure includes a gate dielectric and a gate electrode on the gate dielectric.

[0013] In some embodiments, the thickness of the gate dielectric of the recessed channel transistor is greater than the thickness of the gate dielectric of the planar transistor.

[0014] In some embodiments, the first peripheral circuit includes a driving circuit.

[0015] In some implementations, the first peripheral circuit is coupled to a voltage source greater than 3.3V.

[0016] In some embodiments, the voltage source is between 5V and 30V.

[0017] In another aspect, a semiconductor device includes a substrate, a first transistor, and a second transistor. The first transistor includes: a first well in the substrate and having a recess; a recessed gate structure protruding into the recess of the first well and including a first gate dielectric and a first gate electrode on the first gate dielectric; and a source and a drain separated by the recessed gate structure. At least one of the first source or the first drain includes a first region in contact with the first gate dielectric and a second region at the top surface of the substrate and having a higher doping concentration than the first region. The second transistor includes: a second well in the substrate; and a flat gate structure on the second well, and the flat gate structure includes a second gate dielectric and a second gate electrode on the second gate dielectric.

[0018] In some embodiments, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

[0019] In some embodiments, the difference in doping concentration between the first region and the second region is at least 10 times.

[0020] In some embodiments, the doping concentration of the first region is between 10 18 / cm 3 with 10 19 / cm 3and the doping concentration of the second region is at least 10 20 / cm 3 .

[0021] In some embodiments, the thickness of the first region is greater than the thickness of the second region.

[0022] In some embodiments, the thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm.

[0023] In some embodiments, the recessed channel transistor further includes source / drain contacts contacting the second region.

[0024] In another aspect, a method for forming a semiconductor device is provided. A recess is formed in a substrate. A first gate dielectric is formed on the sidewalls and bottom surface of the recess, and a second gate dielectric is formed on the substrate. A first gate electrode is formed on the first gate dielectric, and a second gate electrode is formed on the second gate dielectric. A first source and a first drain are formed, separated by the first gate dielectric and the first gate electrode. At least one of the first source or the first drain includes a first region in contact with the first gate dielectric, and a second region at the top surface of the substrate having a higher doping concentration than the first region.

[0025] In some embodiments, to form the first source and the first drain, dopants are implanted into the second region, and the dopants are locally annealed to dope the first region.

[0026] In some embodiments, the local annealing includes laser spike annealing.

[0027] In some embodiments, the difference in doping concentration between the first region and the second region is at least 10 times.

[0028] In some embodiments, the doping concentration of the first region is between 10 18 / cm 3 with 10 19 / cm 3 and the doping concentration of the second region is at least 10 20 / cm 3 .

[0029] In some embodiments, the thickness of the first region is greater than the thickness of the second region.

[0030] In some embodiments, the thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm.

[0031] In some embodiments, source / drain contacts are formed in contact with the second region.

[0032] In some embodiments, a first well and a second well are formed in the substrate such that the recess is in the first well and the second gate dielectric is on the second well. In some embodiments, a second source and a second drain are formed in the second well. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure.

[0034] Figure 1 A schematic diagram of an exemplary memory device having a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0035] Figure 2 shows some aspects of the present disclosure Figure 1 A block diagram of exemplary peripheral circuits of a memory device in FIG.

[0036] Figure 3 Block diagram showing peripheral circuits supplied with various voltages according to some aspects of the present disclosure

[0037] Figure 4 Shown are plan and side views of a cross-section of an exemplary planar transistor according to aspects of the present disclosure.

[0038] Figure 5 Plan and side views of a cross-section of an exemplary recessed channel transistor according to aspects of the present disclosure are shown.

[0039] Figure 6A A side view of a cross section of an exemplary recessed channel transistor according to aspects of the present disclosure is shown.

[0040] Figure 6B A side view of a cross section of another exemplary recessed channel transistor according to aspects of the present disclosure is shown.

[0041] Figure 6C A side view of a cross section of yet another exemplary recessed channel transistor according to aspects of the present disclosure is shown.

[0042] Figure 7A shows some aspects of the present disclosure Figure 6B Example source / drain junction profiles of a recessed channel transistor in FIG.

[0043] Figure 7B shows some aspects of the present disclosure Figure 6CAnother exemplary source / drain junction profile for a recessed channel transistor in FIG.

[0044] Figure 8 A side view of a cross section of an exemplary semiconductor device having a recessed channel transistor and a planar transistor according to aspects of the present disclosure is shown.

[0045] Figures 9A-9K A fabrication process for forming an exemplary semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure is shown.

[0046] Figure 10 A flow chart illustrating an exemplary method for forming a semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure is shown.

[0047] Figure 11 A flow chart illustrating another exemplary method for forming a semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure is shown.

[0048] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0049] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Thus, other configurations and arrangements may be used without departing from the scope of this disclosure. In addition, this disclosure may also be used for various other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified with one another, and in a manner not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0050] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can also be understood to convey singular usage or to convey plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0051] It should be readily understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers therebetween, and “on” or “over” means not only “on something” or “over something,” but also includes “on something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0052] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein for ease of description to describe the relationship of one element or feature to another element or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0053] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0054] As used herein, the term "layer" refers to a material portion comprising an area having a thickness. A layer may extend over the entire underlying structure or superstructure, or may have a range that is less than the range of the underlying structure or superstructure. In addition, a layer may be a region of a homogeneous or non-homogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and a contact layer (wherein interconnect lines and / or vertical interconnect path (via) contacts are formed) and one or more dielectric layers.

[0055] With the development of memory devices such as NAND and NOR flash memory devices, PCM devices, and ferroelectric memory devices, more memory cells require more peripheral circuits (and components forming the peripheral circuits, such as transistors) to operate the memory devices. For example, the number and / or size of page buffer circuits need to be increased to match the increased number of memory cells. In another example, the number of driver circuits in a word line driver or a bit line driver is proportional to the number of word lines or bit lines in some memory devices. In addition, in some 3D memory devices in which the memory cell array and the peripheral circuits are fabricated on different substrates and bonded together, the continuous increase in the peripheral circuit area makes it a bottleneck for reducing the total chip size because the memory cell array can be vertically increased by increasing the number of levels rather than increasing the planar size.

[0056] Therefore, it is desirable to reduce the planar area occupied by the peripheral circuits of a memory device as the number of peripheral circuits and their transistors increases. However, following the trend of advanced complementary metal oxide semiconductor (CMOS) technology nodes for logic devices, shrinking the transistor size of the peripheral circuits will result in a significant cost increase and higher leakage current (also known as off-state current I) due to device channel leakage and hot carrier injection (HCI) reliability limitations. off ), which is undesirable for memory devices.

[0057] Furthermore, because some memory devices (e.g., NAND and NOR flash memory devices) require relatively high voltages (e.g., higher than 5V) for certain memory operations (e.g., writing and erasing), unlike logic devices (whose operating voltage can be reduced as CMOS technology nodes advance), the voltage supplied to the memory peripheral circuits cannot be reduced. Consequently, it becomes unfeasible to reduce the size of the memory peripheral circuits by following the trend of advancing CMOS technology nodes (as with conventional logic devices).

[0058] One approach to reducing the size of peripheral circuitry is to shrink transistor area by reducing gate width and length. However, this can lead to channel leakage degradation, limiting the percentage of device area reduction. Consequently, reducing peripheral circuitry in memory devices without sacrificing performance has become increasingly challenging.

[0059] To address one or more of the above-mentioned problems, the present disclosure introduces a solution in which recessed channel transistors (RCTs) replace planar transistors when forming some of the peripheral circuits in a memory device. That is, the peripheral circuits can have hybrid transistors (both recessed channel transistors and planar transistors), which can balance device size reduction and performance degradation. In some embodiments, transistors operating at relatively high voltages (e.g., higher than 3.3V) in some peripheral circuits (e.g., driver circuits in word line drivers or bit line drivers) are recessed channel transistors to reduce transistor size while using less advanced technology nodes (e.g., 55nm and above).

[0060] One disadvantage of recessed gate transistors is the large gate-induced drain leakage (GIDL) current from the larger gate to the source / drain overlap and depletion region (also known as the extended gate-controlled diode) caused by the recessed gate structure protruding into the well in the substrate. Furthermore, GIDL leakage current increases with increasing gate voltage of the recessed gate transistor, becoming a more serious problem for recessed gate transistors operating at relatively high voltages (e.g., above 3.3V) in certain peripheral circuits (e.g., driver circuits). The present disclosure also introduces various solutions to further address the increased GIDL current associated with recessed gate transistors in memory peripheral circuits.

[0061] Consistent with the scope of the present disclosure, in some embodiments, the top surfaces of the source / drain of a recessed gate transistor are elevated from the top surface of the substrate (i.e., the bottom surface of the spacer structure) to reduce the depletion region (i.e., the gate-to-source / drain overlap region) and the electric field in the source / drain and well junctions, thereby mitigating the GIDL effect. Due to the shallow junction depth below the top surface of the substrate, the elevated portions of the source / drain can further reduce transistor dimensions, such as channel length.

[0062] Consistent with the scope of the present disclosure, in some embodiments, a high-low source / drain doping scheme is applied to minimize GIDL current generation while maintaining an acceptable drive current of the memory cell. The high-low source / drain doping scheme can form two regions in the source / drain: a first region with a deep junction profile and a lower doping concentration for reducing the electric field in the source / drain and well diode regions; and a second region with a shallow junction profile and a higher doping concentration for improving contact resistance and series resistance in order to maintain drive current and breakdown voltage.

[0063] Figure 1A schematic diagram of an exemplary memory device 100 having a memory cell array 101 and peripheral circuitry 102 according to some aspects of the present disclosure is shown. The memory device 100 may include the memory cell array 101 and the peripheral circuitry 102 coupled to the memory cell array 101. The memory cell array 101 may be any suitable memory cell array, wherein each memory cell 108 may be a NAND flash memory cell, a NOR flash memory cell, a PCM cell, a ferroelectric memory cell, a dynamic random-access memory (DRAM) cell, a static random access memory (SRAM) cell, a resistive memory cell, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, to name a few examples, or any combination thereof. Figure 1 As shown, the memory cells 108 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 100 may include word lines 104 that couple the peripheral circuit 102 to the memory cell array 101 for controlling the memory cells 108 located in the same row, and bit lines 106 that couple the peripheral circuit 102 to the memory cell array 101 for controlling the memory cells 108 located in the same column. That is, each word line 104 is coupled to the memory cells 108 of a corresponding row, and each bit line is coupled to the memory cells 108 of a corresponding column.

[0064] Peripheral circuitry 102 (also referred to as control and readout circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory cell array 101. For example, peripheral circuitry 102 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver or a bit line driver), an I / O circuit, a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). Peripheral circuitry 102 may include various types of peripheral circuitry formed using MOS technology. For example, Figure 2 Some exemplary peripheral circuits 102 are shown, including a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, registers 214, an interface (I / F) 216, and a data bus 218. It should be understood that in some examples, additional peripheral circuits 102 may also be included.

[0065] The page buffer 204 may be configured to buffer data read from or written to the memory cell array 101 according to a control signal from the control logic 212. The row decoder / word line driver 208 may be configured to drive the memory cell array 101. For example, the row decoder / word line driver 208 may drive the memory cells 108 coupled to the selected word line 104 using a word line voltage generated from the voltage generator 210. The column decoder / bit line driver 206 may be configured to be controlled by the control logic 212 and to select one or more columns of memory cells 108 by applying a bit line voltage generated from the voltage generator 210. For example, the column decoder / bit line driver 206 may apply a column signal for selecting a set of multiple pieces of data to be output from the page buffer 204 in a read operation.

[0066] The control logic 212 may be coupled to each peripheral circuit 102 and configured to control the operation of the peripheral circuit 102. The registers 214 may be coupled to the control logic 212 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit 102.

[0067] The interface 216 can be coupled to the control logic 212 and configured to interface the memory cell array 101 with a memory controller (not shown). In some embodiments, the interface 216 acts as a control buffer to buffer and relay control commands received from the memory controller and / or host (not shown) to the control logic 212, and to buffer and relay status information received from the control logic 212 to the memory controller and / or host. The interface 216 can also be coupled to the page buffer 204 and the column decoder / bit line driver 206 via the data bus 218 and act as an I / O interface and data buffer to buffer and relay write data received from the memory controller and / or host to the page buffer 204, and to buffer and relay read data from the page buffer 204 to the memory controller and / or host. In some embodiments, the interface 216 and the data bus 218 are part of the I / O circuitry of the peripheral circuit 102.

[0068] The voltage generator 210 can be configured to be controlled by the control logic 212 and to generate wordline voltages (e.g., read voltages, write voltages, etc.) and bitline voltages to be supplied to the memory cell array 101. In some embodiments, the voltage generator 210 is part of a voltage source that provides voltages at various levels to various peripheral circuits 102, as described in detail below. Consistent with the scope of the present disclosure, in some embodiments, the voltages provided by the voltage generator 210 to, for example, the row decoder / wordline driver 208, the column decoder / bitline driver 206, and the page buffer 204 are higher than certain levels sufficient to perform memory operations. For example, the voltage provided to the page buffer circuitry in the page buffer 204 and / or the logic circuitry in the control logic 212 can be between 1.3V and 5V, such as 3.3V, and the voltage provided to the driver circuitry in the row decoder / wordline driver 208 and / or the column decoder / bitline driver 206 can be between 5V and 30V.

[0069] Unlike logic devices (e.g., microprocessors), memory devices (e.g., NAND or NOR flash memories) require a wide range of voltages to be supplied to various memory peripheral circuits. For example, Figure 3 A block diagram of peripheral circuits provided with various voltages according to some aspects of the present disclosure is shown. In some embodiments, a memory device (e.g., memory device 100) includes a low-low voltage (LLV) source 301, a low voltage (LV) source 303, and a high voltage (HV) source 305, each of which is configured to provide a voltage at a corresponding level (Vdd1, Vdd2, or Vdd3). For example, Vdd3>Vdd2>Vdd1. Each voltage source 301, 303, or 305 can receive a voltage input at a suitable level from an external power source (e.g., a battery). Each voltage source 301, 303, or 305 can also include a voltage converter and / or a voltage regulator to convert the external voltage input to a corresponding level (Vdd1, Vdd2, or Vdd3) and maintain and output the voltage at the corresponding level (Vdd1, Vdd2, or Vdd3) through a corresponding power rail. In some implementations, the voltage generator 210 of the memory device 100 is part of the voltage sources 301 , 303 , and 305 .

[0070] In some embodiments, the LLV source 301 is configured to provide a voltage lower than 1.3 V, such as a voltage between 0.9 V and 1.2 V (e.g., 0.9 V, 0.95 V, 1 V, 1.05 V, 1.1 V, 1.15 V, 1.2 V, any range bounded by any one of these values ​​as a lower limit, or any range bounded by any two of these values). In one example, the voltage is 1.2 V. In some embodiments, the LV source 303 is configured to provide a voltage between 1.3V and 3.3V (e.g., 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2V, 2.1V, 2.2V, 2.3V, 2.4V, 2.5V, 2.6V, 2.7V, 2.8V, 2.9V, 3V, 3.1V, 3.2V, 3.3V, any range bounded by any one of these values ​​as a lower limit, or any range bounded by any two of these values). In one example, the voltage is 3.3V. In some embodiments, the HV source 305 is configured to provide a voltage greater than 3.3 V, such as a voltage between 5 V and 30 V (e.g., 5 V, 6 V, 7 V, 8 V, 9 V, 10 V, 11 V, 12 V, 13 V, 14 V, 15 V, 16 V, 17 V, 18 V, 19 V, 20 V, 21 V, 22 V, 23 V, 24 V, 25 V, 26 V, 27 V, 28 V, 29 V, 30 V, any range bounded by any one of these values ​​as the lower limit, or any range bounded by any two of these values). It should be understood that the voltage ranges described above with respect to the HV source 305, the LV source 303, and the LLV source 301 are for illustrative purposes and not limiting, and that the HV source 305, the LV source 303, and the LLV source 301 can provide any other suitable voltage ranges.

[0071] Based on their appropriate voltage levels (Vdd1, Vdd2, or Vdd3), memory peripheral circuits (e.g., peripheral circuit 102) can be categorized into LLV circuits 302, LV circuits 304, and HV circuits 306, which can be coupled to LLV source 301, LV source 303, and HV source 305, respectively. In some embodiments, HV circuit 306 includes one or more driver circuits that are coupled to memory cell array 101 via word lines 104 and bit lines 106 and are configured to drive memory cell array 101 by applying voltages at appropriate levels to word lines 104 and bit lines 106 when performing a memory operation (e.g., read, write, or erase). In one example, HV circuit 306 can include a word line driver circuit (e.g., in row decoder / word line driver 208) that is coupled to word line 104 and applies a write voltage in the range of, for example, 5V to 30V to word line 104 during a write operation. In another example, HV circuit 306 may include a bitline driver circuit (e.g., in column decoder / bitline driver 206) that is coupled to bitline 106 and applies an erase voltage, for example, between 5V and 30V, to bitline 106 during an erase operation. In some embodiments, LV circuit 304 includes a page buffer circuit (e.g., in a latch of page buffer 204) and is configured to buffer data read from or written to memory cell array 101. For example, page buffer 204 may be supplied with a voltage, for example, 3.3V, by LV source 303. LV circuit 304 may also include logic circuitry (e.g., in control logic 212). In some embodiments, LLV circuit 302 includes I / O circuitry (e.g., in interface 216 and / or data bus 218) configured to interface memory cell array 101 with a memory controller. For example, the I / O circuitry may be supplied with a voltage, for example, 1.2V, by LLV source 301.

[0072] Consistent with the scope of the present disclosure, in some embodiments, the HV circuits 306 (e.g., the driver circuits in the row decoder / word line driver 208 and the column decoder / bit line driver 206) have recessed channel transistors rather than planar transistors to reduce device size while maintaining comparable or even better device leakage performance. The LLV circuits 302 (e.g., the I / O circuits in the interface 216 and the data bus 218) can still have planar transistors because planar transistors can provide higher operating speeds than recessed channel transistors, which is a desirable feature for I / O circuits that need to frequently communicate with external devices. The LV circuits 304 (e.g., the page buffer circuits in the page buffer 204 and the logic circuits in the control logic 212) can have recessed channel transistors, planar transistors, or a combination thereof. For example, Figure 4shows a plan view and a side view of a cross section of an exemplary planar transistor according to some aspects of the present disclosure, and Figure 5 Plan and side views of a cross-section of an exemplary recessed channel transistor according to aspects of the present disclosure are shown.

[0073] like Figure 4 As shown, for a planar transistor, the effective channel length Leff is the same as the gate length L, while in Figure 5 , for a recessed channel transistor, the effective channel length Leff = Lb + 2Ld - 2xj, where Lb represents the gate length protruding into the substrate at the bottom of the gate structure, Ld represents the depth of the gate structure protruding into the substrate (if the slope is not 90 degrees, the slope is taken into account for better accuracy), and xj represents the junction depth of the source / drain. For planar transistors, a reduction in device area can be achieved by reducing the gate length L (and in some cases the gate width W), which in turn reduces the effective channel length. As a result, channel leakage may be reduced. In contrast, for a recessed channel transistor, a reduction in device area (for example, by reducing the gate length L) may not reduce the effective channel length Leff due to an increase in Ld. In addition, due to the protruding shape of the recessed gate structure and the resulting U-shaped channel, better gate control can be achieved. Therefore, the device area can be reduced while maintaining comparable or even better device leakage performance.

[0074] However, comparison Figure 4 and Figure 5 , the protruding shape of the recessed gate structure into the substrate in the recessed gate transistor may result in the formation of an extended gate-controlled diode D (i.e., a junction between the source / drain and the well having different types of dopants) under the gate structure. That is, a depletion region may be formed at the gate to source / drain overlap region where the source / drain contacts the curved gate dielectric of the recessed gate structure. A high electric field may be formed in the depletion region, thereby generating a high GIDL leakage current, which is the main component of the leakage current of the recessed channel transistor in the HV circuit 306. In order to weaken the GIDL effect at the extended gate-controlled diode D of the recessed channel transistor in particular in the HV circuit 306, and to reduce the resulting GIDL leakage current, in the following Figures 6A-6C Various recessed channel transistors 601, 603, and 605 having improved designs are provided and described in detail.

[0075] like Figure 6AAs shown, the semiconductor device 600 may include a recessed channel transistor 601 on a substrate 602, and the substrate 602 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. The semiconductor device 600 may also include isolation 606 (e.g., shallow trench isolation (STI)) in the substrate 602 and between adjacent recessed channel transistors 601 to reduce current leakage. Figure 6A As shown, the top surface of isolation 606 can be coplanar with the top surface of substrate 602. Isolation 606 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) dielectric (e.g., aluminum oxide, hafnium oxide, zirconium oxide, etc.). In some embodiments, high-k dielectric material includes any dielectric having a dielectric constant or k value higher than that of silicon nitride (k>7). In some embodiments, isolation 606 includes silicon oxide.

[0076] Note that in Figure 6A The x-axis and y-axis are added to further illustrate the spatial relationship of the components in the semiconductor device 600. The substrate 602 includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (lateral direction or width direction). As used herein, when the substrate (e.g., substrate 602) is positioned in the lowest plane of the semiconductor device (e.g., semiconductor device 600) in the y-direction, whether a component (e.g., a layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., a layer or device) is determined relative to the substrate of the semiconductor device in the y-direction (vertical direction or thickness direction). The same concept for describing spatial relationships is applied throughout this disclosure.

[0077] like Figure 6A As shown, in some embodiments, a recessed channel transistor 601 may include a well 604 in a substrate 602 and having a recess. The well 604 may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)), or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). It should be understood that Figure 6A The well 604 in FIG. 6 is for illustrative purposes only. Depending on the doping type of the substrate 602 , the well 604 may be omitted or have different extents and limits in the substrate 602 . The recessed channel transistor 601 may further include a recessed gate structure 608 that protrudes into the recess of the well 604 in the substrate 602 . That is, the recessed gate structure 608 may have two parts in a side view: a protruding portion below the top surface of the substrate 602 and a flat portion above the top surface of the substrate 602 . As described above with reference to FIG. Figure 5 As described above, the depth and slope of the protruding portion of the recessed gate structure 608 determine Ld, which in turn affects the effective channel length Leff of the recessed channel transistor 601. In some embodiments, the depth of the protruding portion of the recessed gate structure 608 (i.e., the depth to which the recessed gate structure 608 protrudes into the substrate 602) is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by any one of these values ​​as the lower limit, or any range bounded by any two of these values).

[0078] In some embodiments, the recessed gate structure 608 includes a curved gate dielectric 610 and a recessed gate electrode 612 on the curved gate dielectric 610. Figure 6A As shown, according to some embodiments, a recess is formed in the region of the substrate 602 where the recessed channel transistor 601 is formed. The recess may be surrounded by a well 604. That is, the portion of the substrate 602 where the well 604 is formed may be removed from the top surface to form the recess, as described in detail below with respect to the manufacturing process. In some embodiments, the depth of the recess is the same as the depth of the protruding portion of the recessed gate structure 608 and is between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by any one of these values ​​as the lower limit, or any range bounded by any two of these values).

[0079] The curved gate dielectric 610 can be formed on the sidewalls and bottom surface of the recess. As a result, according to some embodiments, the curved gate dielectric 610 has a curved shape in a side view that follows the shape of the sidewalls and bottom of the recess. The curved gate dielectric 610 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the curved gate dielectric 610 includes silicon oxide, i.e., a curved gate oxide. According to some embodiments, the recessed gate electrode 612 is above and in contact with the curved gate dielectric 610. Figure 6AAs shown, the recessed gate electrode 612 may also include two parts in a side view: a protruding portion below the top surface of the substrate 602 and a flat portion above the top surface of the substrate 602. That is, the recess in the substrate 602 may be filled with the curved gate dielectric 610 and the protruding portion of the recessed gate electrode 612. The recessed gate electrode 612 may include any suitable conductive material, such as doped polysilicon, a metal (e.g., tungsten, copper, aluminum, etc.), a metal compound (e.g., titanium nitride, tantalum nitride, etc.), or a silicide. In some embodiments, the recessed gate electrode 612 includes doped polysilicon, i.e., recessed gate polysilicon.

[0080] In some embodiments, the recessed channel transistor 601 further includes a spacer structure 614 on the sidewalls of the flat portion of the recessed gate electrode 612 (i.e., on the sidewalls of the portion above the substrate 602). That is, the sidewalls of the spacer structure 614 may be in contact with the sidewalls of the recessed gate electrode 612. Figure 6A As shown, in some embodiments, a spacer structure 614 is also formed on the top surface of the substrate 602. That is, the bottom surface of the spacer structure 614 can be coplanar with the top surface of the substrate 602 and the top surface of the isolation 606. Therefore, the bottom surface of the spacer structure 614, the top surface of the isolation 606, and the top surface of the substrate 602 can refer to the same plane in this article. In some embodiments, the spacer structure 614 includes an inner spacer 616 that contacts the sidewalls of the recessed gate electrode 612, and an outer spacer 618 that contacts the sidewalls of the inner spacer 616. That is, the spacer structure 614 can include multiple spacers (e.g., inner spacers 616 and outer spacers 618) arranged laterally. The spacers 616 and 618 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the outer spacer 618 has a different material from the inner spacer 616. In one example, the inner spacer 616 includes silicon oxide and the outer spacer 618 includes silicon nitride. In another example, the inner spacer 616 includes silicon nitride and the outer spacer 618 includes silicon oxide. It should be understood that in some examples, the spacer structure 614 can include a single spacer or more than two spacers.

[0081] The recessed channel transistor 601 may further include a pair of source and drain electrodes 620 (also referred to herein as source / drain electrodes 620) separated by a spacer structure 614 and a recessed gate structure 608. The source and drain electrodes 620 may be doped with any suitable P-type dopant (e.g., B or Ga) or any suitable N-type dopant (e.g., P or Ar). The dopant type of the source / drain electrodes 620 may be different from the dopant type of the well 604. Figure 6AAs shown, the top surface of the source / drain 620 is elevated from the bottom surface of the spacer structure 614 (i.e., the top surface of the substrate 602). That is, unlike conventional flat source / drain, according to some embodiments, the source / drain 620 of the recessed channel transistor 601 is an elevated source / drain having an elevated portion 622 above the bottom surface of the spacer structure 614 (i.e., the top surface of the substrate 602) and a flat portion 624 below the bottom surface of the spacer structure 614 (i.e., the top surface of the substrate 602). For example, the elevated portion 622 of the source / drain 620 can be above the bottom surface of the spacer structure 614 and in contact with the sidewalls of the spacer structure 614. However, as Figure 6A As shown, according to some embodiments, the elevated portion 622 of the source / drain 620 does not extend to cover the isolation 606. That is, the elevated portion 622 can be self-aligned between the isolation 606 and the spacer structure 614 using selective epitaxial growth, as described in detail below with respect to the fabrication process.

[0082] In some embodiments, the raised portion 622 has the same material as the substrate 602, such as single crystal silicon when the substrate 602 is a silicon substrate. As part of the source / drain 620, the raised portion 622 and the flat portion 624 can be doped with the same type of dopant at the same or different doping concentrations. The depth of the raised portion 622 (i.e., the depth between the top surface of the source / drain 620 and the bottom surface of the spacer structure 614) is not less than 100 nm. In some embodiments, the depth is between 100 nm and 150 nm (e.g., 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, any range bounded by any one of these values ​​as the lower limit, or in any range bounded by any two of these values). Figure 6A As shown, in some embodiments, the recessed gate structure 608 protrudes below the source / drain 620. That is, the lower end of the recessed gate structure 608 can be lower than the lower end of the flat portion 624 of the source / drain 620.

[0083] By raising the top surface of the source / drain 620 above the top surface of the substrate 602, the gate to source / drain overlap area (ie, extended gated diode) can be reduced (compared to Figure 5 ), which in turn reduces the electric field in the depletion region. As a result, by forming the raised portion 622 of the raised source / drain 620 in the recessed channel transistor 601, the GIDL leakage current can be reduced without reducing the drive current (Ids). In addition, by raising the top surface of the source / drain 620 above the top surface of the substrate 602, the gate length Lb of the recessed gate structure 608 can be further reduced while maintaining the same reference length as above. Figure 5The recessed channel transistors 601 have the same effective channel length Leff.

[0084] It should be understood that the recessed channel transistor 601 may include Figure 6A Additional features not shown in the drawings may be present or coupled thereto, such as additional dielectric layers or contacts (eg, source and drain contacts).

[0085] Another way to reduce the electric field at the depletion region (which causes GIDL leakage current) is to reduce the doping concentration of the portion of the source / drain that overlaps the gate structure (e.g., gate dielectric). Figure 6B Another recessed channel transistor 603 is shown. Figure 6A The recessed channel transistor 601 in FIG. Figure 6B The recessed channel transistor 603 in FIG. 6 includes a planar source / drain 626, each of which includes two regions 628 and 630 having different doping concentrations. For ease of description, the same components of the recessed channel transistors 603 and 601 will not be described again below.

[0086] The recessed channel transistor 603 may include a source 626 and a drain 626 (also referred to herein as source / drain 626) separated by a recessed gate structure 608. According to some embodiments, the source / drain 626 is a planar source / drain, i.e., its top surface is coplanar with the bottom surface of the spacer structure 614 (the top surface of the substrate 602). Figure 6B As shown, the source / drain 626 may include a low-doped region 628 in contact with the curved gate dielectric 610 of the recessed gate structure 608, and a high-doped region 630 having a higher doping concentration than the low-doped region 628. According to some embodiments, the doping concentration difference between the high-doped region 630 and the low-doped region 628 of the source / drain 626 is at least 10 times. In some embodiments, the doping concentration of the low-doped region 628 is between 10 and 10. 18 / cm 3 and 10 19 / cm 3 Between (for example, 10 18 / cm 3 , 2×10 18 / cm 3 , 3×10 18 / cm 3 , 4×10 18 / cm 3 , 5×10 18 / cm 3 , 6×10 18 / cm 3 , 7×10 18 / cm 3 , 8×1018 / cm 3 , 9×10 18 / cm 3 , 10 19 / cm 3 , any range bounded by any one of these values ​​as a lower limit, or any range bounded by any two of these values). In some embodiments, the doping concentration of the highly doped region 630 is at least 10 20 / cm 3 , for example, in 10 20 / cm 3 with 10 21 / cm 3 Between (for example, 10 20 / cm 3 , 2×10 20 / cm 3 , 3×10 20 / cm 3 , 4×10 20 / cm 3 , 5×10 20 / cm 3 , 6×10 20 / cm 3 , 7×10 20 / cm 3 , 8×10 20 / cm 3 , 9×10 20 / cm 3 , 10 21 / cm 3 , any range bounded by the lower limit of any one of these values, or in any range bounded by any two of these values).

[0087] like Figure 6B As shown, in addition to different doping concentrations, the highly doped region 630 and the lowly doped region 628 of the source / drain 626 may also have different junction profiles. For example, Figure 7A shows some aspects of the present disclosure Figure 6B6. Example source / drain junction profile of a recessed channel transistor 603 in FIG. In some embodiments, the low-doped region 628 has a deep junction profile, while the highly doped region 630 has a shallow junction profile. For example, the thickness of the low-doped region 628 (measured from the top surface of the substrate 602) is greater than the thickness of the highly doped region 630. In some embodiments, the thickness of the low-doped region 628 is greater than 200 nm. For example, the thickness of the low-doped region 628 can be between 200 nm and 400 nm (e.g., 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, any range bounded by any one of these values ​​as a lower limit, or any range bounded by any two of these values). In some embodiments, the thickness of the highly doped region 630 is less than 100 nm. For example, the thickness of the highly doped region 630 can be between 50 nm and 100 nm (e.g., 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by any one of these values ​​as the lower limit, or in any range bounded by any two of these values).

[0088] like Figure 6B and 7AAs shown, the deep junction profile of the low-doped region 628 can ensure that the low-doped region 628 of the source / drain 626 with a relatively low doping concentration is in contact with the curved gate dielectric 610, so that the doping concentration at the depletion region of the extended gate-controlled diode is relatively low. As a result, the electric field and the resulting GIDL leakage current can be reduced. On the other side, the shallow junction profile of the high-doped region 630 can ensure that the high-doped region 630 of the source / drain 626 with a relatively high doping concentration is spaced apart from the curved gate dielectric 610 to minimize the effect of the high doping concentration on the electric field at the depletion region. In addition, the high-doped region 630 can be formed at the top surface of the substrate 602 so that the source / drain contacts (not shown) of the recessed channel transistor 603 can be in contact with the high-doped region 630 instead of the low-doped region 628. As a result, the contact resistance between the source / drain contacts and the source / drain 626 and the series resistance of the source / drain 626 can be maintained while reducing the doping concentration of the depletion region of the extended gate-controlled diode. Therefore, the drive current and breakdown voltage of the recessed channel transistor 603 can be maintained while reducing the GIDL leakage current. As described in detail below with respect to the manufacturing process, the formation of the highly doped region 630 and the lowly doped region 628 in the source / drain 626 can be achieved through a high-low doping scheme.

[0089] It should be understood that in some examples, the raised source / drain of the recessed channel transistor may also have high doping regions and low doping regions to further reduce the GIDL effect at the extended gate-controlled diode. Figure 6C A recessed channel transistor 605 is shown with raised source / drain electrodes 632, each of which includes a raised portion 622 and a flat portion 634. Figure 6A The elevated source / drain 620 of the recessed channel transistor 601 in FIG. 6 (which has the same doping concentration in the elevated portion 622 and the flat portion 624 ) is different. Figure 6C The flat portion 634 of the raised source / drain 632 of the recessed channel transistor 605 in contact with the curved gate dielectric 610 of the recessed gate structure 608 may have a relatively low doping concentration (similar to Figure 6B The low-doped region 628 in the gate-controlled diode is further reduced to further reduce the GIDL effect at the depletion region of the extended gate-controlled diode. For ease of description, the same components of the recessed channel transistors 605, 603 and 601 are not described below.

[0090] In some embodiments, the doping concentration of the elevated portion 622 is higher than the doping concentration of the flat portion 634 of the source / drain 632. It should be understood that the highly doped region 630 and the lowly doped region 628 may not precisely match the elevated portion 622 and the flat portion 634, respectively. Figure 7BAs shown, the highly doped region 630 may extend beyond the elevated portion 622 into the flat portion 634. That is, the elevated portion 622 may be completely filled with the highly doped region 630, and the flat portion 634 may include the low-doped region 628 and a portion of the highly doped region 630. Although not shown, it should also be understood that in some examples, the highly doped region 630 may not completely fill the elevated portion 622, such that the elevated portion 622 may include the highly doped region 630 and a portion of the low-doped region 628, while the flat portion 634 may be completely filled with the low-doped region 628. However, according to some embodiments, the highly doped region 630 is at least in the elevated portion 622 of the source / drain 632.

[0091] Consistent with the scope of the present disclosure, recessed channel transistors and planar transistors may be used together in memory peripheral circuits, for example, in different peripheral circuits operating at different voltages (e.g., HV circuit 306, LV circuit 304, and LLV circuit 302). Figure 8 A side view of a cross-section of an exemplary semiconductor device 800 having a recessed channel transistor 802 and a planar transistor 804 according to some aspects of the present disclosure is shown. The semiconductor device 800 can include memory peripheral circuits (e.g., peripheral circuits 102) disclosed herein. In some embodiments, the recessed channel transistor 802 is part of the HV circuit 306 (e.g., a driver circuit) and the planar transistor 804 is part of the LLV circuit 302 (e.g., an I / O circuit). It should be understood that the LV circuit 304 (e.g., a page buffer circuit and a logic circuit) can include the recessed channel transistor 802, the planar transistor 804, or any combination thereof. It should also be understood that the semiconductor device 800 is not limited to peripheral circuits of a memory device and can include any semiconductor device having a hybrid recessed channel transistor 802 and a planar transistor 804.

[0092] Each recessed channel transistor 802 or planar transistor 804 may be a MOS field effect transistor (MOSFET) on a substrate 801, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The semiconductor device 800 may include isolation 803 (e.g., STI) in the substrate 801 and between adjacent recessed channel transistors 802 and planar transistors 804 to reduce current leakage. Figure 8 As shown, in some embodiments, the recessed channel transistor 802 and the planar transistor 804 are formed using complementary MOS (CMOS) technology and include pairs of adjacent P-type transistors (eg, PMOS) and N-type transistors (NMOS).

[0093] The P-type recessed channel transistor 806 may be included in the substrate 801 and have an N-well 814 with a recess, and the N-type recessed channel transistor 807 may be included in the substrate 801 and have a P-well 815 with a recess. The P-well 815 may be doped with any suitable P-type dopant, such as B or Ga, and the N-well 814 may be doped with any suitable N-type dopant, such as P or As. It should be understood that Figure 8 The wells 814 and 815 in the substrate 801 are for illustrative purposes only. Depending on the doping type of the substrate 801, the N-well 814 or the P-well 815 may be omitted or have different scopes and limitations in the substrate 801. Each recessed channel transistor 802 may also include a recessed gate structure 819 that protrudes into a recess of the well 814 or 815 in the substrate 801. For example, the recessed gate structure 819 of the P-type recessed channel transistor 806 may protrude into the recess of the N-well 814, and the recessed gate structure 819 of the N-type recessed channel transistor 807 may protrude into the recess of the P-well 815.

[0094] In some embodiments, the recessed gate structure 819 includes a curved gate dielectric 818 and a recessed gate electrode 816 on the curved gate dielectric 818. Figure 8 As shown, according to some embodiments, grooves are formed in the region of the substrate 801 where the grooved channel transistor 802 is formed. Each groove may be surrounded by an N-well 814 or a P-well 815. A curved gate dielectric 818 may be formed on the sidewalls and bottom surface of each groove. As a result, according to some embodiments, the curved gate dielectric 818 has a curved shape in a side view that follows the shape of the sidewalls and bottom of the groove. In some embodiments, the curved gate dielectric 818 includes silicon oxide, i.e., a curved gate oxide. According to some embodiments, the groove gate electrode 816 is above and in contact with the curved gate dielectric 818. Figure 8 As shown, the recessed gate electrode 816 may also include two parts in a side view: a protruding portion below the top surface of the substrate 801 and a flat portion above the top surface of the substrate 801. In some embodiments, the recessed gate electrode 816 includes doped polysilicon, i.e., recessed gate polysilicon.

[0095] In some embodiments, each recessed channel transistor 802 further includes a spacer structure 820 on the sidewalls of the flat portion of the recessed gate electrode 816 (i.e., on the sidewalls of the portion above the substrate 801). The spacer structure 820 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, each spacer structure 820 includes multiple spacers, such as an inner spacer and an outer spacer having different dielectric materials.

[0096] like Figure 8 As shown, each recessed channel transistor 802 may further include a pair of source and drain separated by a recessed gate structure 819 and a spacer structure 820. For example, the P-type recessed channel transistor 806 may include a P-type source 832 and a P-type drain 832 in the N-well 814. Similarly, the N-type recessed channel transistor 807 may include an N-type source 833 and an N-type drain 833 in the P-well 815. The P-type source and drain 832 may be doped with any suitable P-type dopant (e.g., B or Ga), and the N-type source and drain 833 may be doped with any suitable N-type dopant (e.g., P or Ar). Consistent with the scope of the present disclosure, the source / drain 832 or 833 of the recessed channel transistor 802 may be an elevated source / drain 620, a flat source / drain 626 having a high doping region and a low doping region, an elevated source / drain 632 having a high doping region and a low doping region, or any combination thereof, as described above with respect to FIG. Figures 6A-6C As a result, the GILD leakage current of the recessed channel transistor 802 can be reduced while maintaining the drive current and breakdown voltage.

[0097] It should be understood that the above can be used with respect to Figures 6A-6C Additional details of the recessed channel transistor 802 are described with reference to the corresponding recessed channel transistors 601, 603, and 605 in FIG. 1 and are therefore not repeated for ease of description. It should also be understood that each recessed channel transistor 802 may include Figure 8 Additional features not shown may be provided or coupled thereto, such as additional dielectric layers or contacts (eg, source and drain contacts).

[0098] like Figure 8 As shown, the P-type planar transistor 808 may include an N-well 822 in the substrate 801, and the N-type planar transistor 809 may include a P-well 823 in the substrate 801. The N-well 822 may be doped with any suitable N-type dopant, such as P or Ar, and the P-well 823 may be doped with any suitable P-type dopant, such as B or Ga. It should be understood that Figure 8 The wells 822 and 823 in the substrate 801 are for illustrative purposes only. Depending on the doping type of the substrate 801, the N-well 822 or P-well 823 may be omitted or have different scopes and limitations in the substrate 801. Each planar transistor 804 may also include a planar gate structure 827. According to some embodiments, unlike the recessed gate structure 819, the planar gate structure 827 does not protrude into the substrate 801. In some embodiments, due to the presence of the protruding portion of the recessed gate structure 819, the depth of the well 814 or 815 in the recessed channel transistor 802 is greater than the depth of the well 822 or 823 in the planar transistor 804.

[0099] In some embodiments, the planar gate structure 827 includes a planar gate dielectric 826 and a planar gate electrode 824 on the planar gate dielectric 826. According to some embodiments, unlike the recessed channel transistor 802, a recess is not formed in the region of the substrate 801 where the planar transistor 804 is formed. Therefore, the planar gate dielectric 826 can be formed on the top surface of the substrate 801. Therefore, according to some embodiments, the planar gate dielectric 826 has a straight shape in a side view. The planar gate dielectric 826 can include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the planar gate dielectric 826 includes silicon oxide, i.e., a planar gate oxide. According to some embodiments, the planar gate electrode 824 is above and in contact with the planar gate dielectric 826. Unlike the recessed channel transistor 802, the entire planar gate electrode 824 can be above the top surface of the substrate 801. The planar gate electrode 824 can include any suitable conductive material, such as polysilicon, a metal, a metal compound, or a silicide. In some embodiments, the planar gate electrode 824 includes doped polysilicon, ie, planar gate polysilicon.

[0100] like Figure 8 As shown, each planar transistor 804 may further include a pair of sources and drains in a well 822 or 823. For example, the P-type planar transistor 808 may include a P-type source 830 and a P-type drain 830 in the N-well 822, and the N-type planar transistor 809 may include an N-type source 831 and an N-type drain 831 in the P-well 823. The P-type source and drain 830 may be doped with any suitable P-type dopant, such as B or Ga, and the N-type source and drain 831 may be doped with any suitable N-type dopant, such as P or Ar. In some embodiments, the doping concentration of the source / drain 832 or 833 in the recessed channel transistor 802 is different from the doping concentration of the source / drain 830 or 831 in the planar transistor 804, such that the threshold voltage of the recessed channel transistor 802 is different from the threshold voltage of the planar transistor 804. For example, the doping concentration of the source / drain 832 or 833 in the recessed channel transistor 802 and the doping concentration of the source / drain 830 or 831 in the planar transistor 804 can be controlled in such a manner that the threshold voltage of the planar transistor 804 is greater than the threshold voltage of the recessed channel transistor 802. In some embodiments, the source / drain 830 of the planar transistor 804 is a planar source / drain such that the top surface of the source / drain 830 is coplanar with the top surface of the substrate 801.

[0101] In some embodiments, each planar transistor 804 further includes a spacer structure 828 on the sidewalls of the planar gate electrode 824. The spacer structure 828 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the spacer structure 828 includes silicon nitride. It should be understood that each planar transistor 804 may include Figure 8 Additional features not shown in the drawings may be present or coupled thereto, such as additional dielectric layers or contacts (eg, source and drain contacts).

[0102] As described above, the recessed channel transistor 802 and the planar transistor 804 can be used to form different peripheral circuits operating at different voltages. In some embodiments, the recessed channel transistor 802 is coupled to a voltage source greater than 3.3V (e.g., between 5V and 30V). In some embodiments, the planar transistor 804 is coupled to a voltage source no greater than 3.3V (e.g., between 1.2V and 3.3V). Due to the different operating voltages, in addition to different gate structures, other designs of the recessed channel transistor 802 and the planar transistor 804 may also vary. In some embodiments, the thickness of the curved gate dielectric 818 of the recessed channel transistor 802 is greater than the thickness of the flat gate dielectric 826 of the planar transistor 804 to maintain a higher gate voltage. In some embodiments, the lateral dimensions (e.g., in the x-direction) of the spacer structure 820 of the recessed channel transistor 802 are greater than the lateral dimensions of the spacer structure 828 of the planar transistor 804 to prevent source / drain breakdown, leakage, and reliability issues at higher gate voltages. For example, the spacer structure 820 of the recessed channel transistor 802 may include a plurality of spacers (eg, Figures 6A-6C 802 ), while the spacer structure 828 of the planar transistor 804 may include a single spacer (e.g., only the inner spacer 616 without the outer spacer 618). As described in detail below with respect to the manufacturing process, in some embodiments, the spacer structure 828 of the planar transistor 804 includes an inner spacer having the same material as the inner spacer of the spacer structure 820 of the recessed channel transistor 802, but does not include an outer spacer (the outer spacer is included in the spacer structure 820).

[0103] Figures 9A-9K A fabrication process for forming an exemplary semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure is shown. Figure 10 A flow chart illustrating an exemplary method 1000 for forming a semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure is shown. Figure 11A flow chart is shown of another exemplary method 1100 for forming a semiconductor device having recessed channel transistors and planar transistors according to aspects of the present disclosure. Figures 9A-9K 、 Figure 10 and Figure 11 Examples of semiconductor devices shown in include Figures 6A-6C and Figure 8 The semiconductor devices 600 and 800 shown in FIG. will be described together. Figures 9A-9K 、 Figure 10 and Figure 11 It should be understood that the operations shown in methods 1000 and 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. In addition, some operations may be performed simultaneously or in parallel. Figure 10 and Figure 11 The different orders shown are executed.

[0104] refer to Figure 10 , method 1000 begins at operation 1002, where a first well is formed in a substrate. The substrate may be a silicon substrate. Figure 9A As shown, multiple isolations 902, such as STIs, are formed in a silicon substrate 900 using, for example, wet / dry etching and thin film deposition of silicon oxide. The isolations 902 can divide the silicon substrate 900 into multiple regions, in which multiple transistors can be formed. Figure 9A As shown, an N-well 904 and a P-well 906 are then formed in the silicon substrate 900. In some embodiments, the N-well 904 and the P-well 906 are formed in regions for forming planar transistors. The N-well 904 and the P-well 906 can be patterned using photolithography and aligned between the isolation 902, followed by ion implantation of corresponding N-type dopants and P-type dopants.

[0105] Method 1000 proceeds to operation 1004, as shown in FIG. Figure 10 As shown, a second well is formed in the substrate. In some embodiments, the depth of the second well is greater than the depth of the first well. Figure 9BAs shown, an N-well 910 is formed in a silicon substrate 900. The N-well 910 can be part of a P-type recessed channel transistor and can therefore be formed in a region for forming the P-type recessed channel transistor. To form the N-well 910, in some embodiments, a mask layer 908 is formed on the silicon substrate 900 and then patterned to expose the region where the N-well 910 is to be formed. The mask layer 908 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 908 can be patterned using photolithography and wet / dry etching and aligned between the isolations 902. Ion implantation of an N-type dopant such as P or As can be performed using the mask layer 908 to form the N-well 910 in the desired region between the isolations 902. In some embodiments, ion implantation conditions of the N-well 904 , the P-well 906 , and the N-well 910 are controlled such that the depth of the N-well 910 is greater than the depths of the N-well 904 and the P-well 906 .

[0106] like Figure 9C As shown, a P-well 912 is formed in a silicon substrate 900. The P-well 912 can be part of an N-type recessed channel transistor and can therefore be formed in an area for forming the N-type recessed channel transistor. To form the P-well 912, in some embodiments, a mask layer 909 is formed on the silicon substrate 900 and then patterned to expose the area where the P-well 912 is to be formed. The mask layer 909 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 909 can be patterned using photolithography and wet / dry etching and aligned between the isolations 902. Ion implantation of a P-type dopant such as B or Ga can be performed using the mask layer 909 to form the P-well 912 in the desired area between the isolations 902. In some embodiments, ion implantation conditions of the N-well 904 , the P-well 906 , and the P-well 912 are controlled such that the depth of the P-well 912 is greater than the depths of the N-well 904 and the P-well 906 .

[0107] Method 1000 proceeds to operation 1006, as shown in FIG. Figure 10 As shown, a groove is formed in the first well in the substrate so that the groove is surrounded by the first well. In some embodiments, the depth of the groove is between 50nm and 100nm. Figure 9DAs shown, recesses 914 are formed in the N-well 910 and the P-well 912, respectively, using, for example, the same etching process. In some embodiments, a mask layer 911 is formed on the silicon substrate 900, and then patterned to expose regions in the N-well 910 and the P-well 912 where recesses 914 are to be formed. The mask layer 911 may include a soft mask layer, such as a photoresist layer, and / or a hard mask layer, such as a silicon oxide layer. The mask layer 911 may be patterned using photolithography and wet / dry etching. The silicon substrate 900 may then be etched using the mask layer 911 to form recesses 914 in the wells 910 and 912. The etching process may include dry etching and / or wet etching. In some embodiments, the etching process is a dry etching process, such as reactive ion etching (RIE). Etching conditions (e.g., etching rate and etching duration) may be controlled to control the depth of the recesses 914. In some embodiments, the depth of the groove 914 is between 50 nm and 100 nm. Figure 9D As shown, recesses 914 are formed only in wells 910 and 912 of the recessed channel transistors, and not in wells 904 and 906 of the planar transistors.

[0108] Method 1000 proceeds to operation 1008, as shown in FIG. Figure 10 , wherein a curved gate dielectric is formed on the sidewalls and bottom surface of the recess, and a flat gate dielectric is formed on the substrate. In some embodiments, to form the curved gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewalls and bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewalls and bottom surface of the recess, and the gate dielectric layer is patterned.

[0109] like Figure 9J As shown, in each groove 914 (as Figure 9D A curved gate dielectric 931 is formed on the sidewall and bottom surface of the silicon substrate 900, and a flat gate dielectric 925 is formed on the silicon substrate 900. In order to form the curved gate dielectric 931 and the flat gate dielectric 925, as shown in FIG. Figure 9EAs shown, a gate dielectric layer 916 can be formed on the sidewalls and bottom surface of each groove 914 and on the top surface of the silicon substrate 900 (e.g., wells 904 and 906) by the same deposition process. In some embodiments, a dielectric material layer such as silicon oxide is deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, in situ steam generation (ISSG) can be used to deposit a silicon oxide layer to form the gate dielectric layer 916. In some embodiments, before forming the gate dielectric layer 916, a sacrificial dielectric layer (not shown) is formed on the sidewalls and bottom surface of the groove 914, for example, using thermal oxidation, to remove defects on the sidewalls and bottom surface of the groove 914 caused by the etching process. Then, before forming the gate dielectric layer 916, the sacrificial dielectric layer can be removed, for example, using wet etching. As shown Figure 9I and Figure 9J As shown, the gate dielectric layer 916 can be patterned using photolithography and etching processes in subsequent steps or the same steps to form a flat gate dielectric 925 and a curved gate dielectric 931.

[0110] Method 1000 proceeds to operation 1010, as shown in FIG. Figure 10 As shown, a recessed gate electrode is formed on a curved gate dielectric and a flat gate electrode is formed on a flat gate dielectric. In some embodiments, to form the recessed gate electrode and the flat gate electrode, a gate electrode layer is formed on the curved gate dielectric to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

[0111] like Figure 9J As shown, a recessed gate electrode 920 is formed on the curved gate dielectric 931, and a flat gate electrode 922 is formed on the flat gate dielectric 925. In order to form the recessed gate electrode 920 and the flat gate electrode 922, as shown in FIG. Figure 9F As shown, a gate electrode layer 918 is formed on the gate dielectric layer 916. The recess 914 (eg, Figure 9EAs shown). In some embodiments, a conductive material layer 918 such as polysilicon is deposited on the gate dielectric layer 916 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Depending on the surface flatness of the gate electrode layer 918 affected by the depth of the recess 914, a planarization process such as chemical mechanical polishing (CMP) may be performed to planarize the top surface of the gate electrode layer 918. Figure 9G As shown, the gate electrode layer 918 is patterned using photolithography and etching processes in the same step to form a recessed gate electrode 920 and a flat gate electrode 922. In some embodiments, the recessed gate electrode 920 and the flat gate electrode 922 are doped using ion implantation to increase their conductivity.

[0112] Method 1000 proceeds to operation 1012, as shown in FIG. Figure 10 As shown, a first spacer structure is formed on the sidewall of the recessed gate electrode above the substrate, and a second spacer structure is formed on the sidewall of the flat gate electrode. The lateral dimensions of the first spacer structure may be greater than the lateral dimensions of the second spacer structure. In some embodiments, to form the first spacer structure and the second spacer structure, a first inner spacer in contact with the sidewall of the first gate dielectric and a second inner spacer in contact with the sidewall of the second gate electrode are formed, a first outer spacer in contact with the sidewall of the first inner spacer and a second outer spacer in contact with the sidewall of the second inner spacer are formed, and the second outer spacer is removed.

[0113] like Figure 9HAs shown, inner spacers 924 are formed on the sidewalls of the planar gate electrode 922 and the sidewalls of the portion of the recessed gate electrode 920 located above the silicon substrate 900. Outer spacers 955 are then formed on the sidewalls of the inner spacers 924. In some embodiments, to form the inner spacers 924, a dielectric material layer (e.g., silicon nitride or silicon oxide) (not shown) is deposited on the sidewalls and top surfaces of the recessed gate electrode 920 and the planar gate electrode 922, and on the gate dielectric layer 916 using one or more thin film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). The deposited dielectric material layer can then be patterned using photolithography and etching processes in the same step to remove portions of the recessed gate electrode 920, the planar gate electrode 922, and the top surface of the gate dielectric layer 916, leaving portions on the sidewalls of the recessed gate electrode 920 and the planar gate electrode 922 to form the inner spacers 924. In some embodiments, to form the outer spacer 955, another different dielectric material layer (e.g., silicon oxide or silicon nitride) (not shown) is deposited on the sidewalls of the inner spacer 924 and on the top surfaces of the inner spacer 924, the recessed gate electrode 920, and the flat gate electrode 922 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof), and on the gate dielectric layer 916. The deposited other dielectric material layer can then be patterned using photolithography and etching processes to form the outer spacer 955.

[0114] like Figure 9I As shown, a mask layer 951 is formed on a silicon substrate 900, and then the mask layer 951 is patterned to expose regions of the N-well 904 and the P-well 906. The mask layer 951 may include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 951 may be patterned using photolithography and wet / dry etching. The outer spacers 955 not covered by the mask layer 951 may then be selectively etched, leaving only the inner spacers 924 on the sidewalls of the planar gate electrode 922. Depending on the dielectric material used to form the inner spacers 924 and the outer spacers 955, a wet etch may be performed using an etchant that is selective for the outer spacers 955 relative to the inner spacers 924. As a result, according to some embodiments, the spacer structure having the inner spacers 924 and the outer spacers 955 on the sidewalls of the recessed gate electrode 920 has a larger lateral dimension than the spacer structure having only the inner spacers 924 on the sidewalls of the planar gate electrode 922 .

[0115] Method 1000 proceeds to operation 1014, as shown in FIG. Figure 10, wherein the elevated portion is formed above the substrate and contacts the sidewalls of the first spacer structure. In some embodiments, single crystal silicon is epitaxially grown from the substrate to form the elevated portion. In some embodiments, the depth of the elevated portion is no less than 100 nm, for example, between 100 nm and 150 nm.

[0116] like Figure 9J As shown, the raised portion 952 is formed above the N well 910 in the silicon substrate 900 and contacts the sidewalls of the outer spacer 955. Figure 9K As shown, the raised portion 954 is formed above the P-well 912 in the silicon substrate 900 and contacts the sidewalls of the outer spacer 955. To form the raised portions 952 and 954, single crystal silicon can be selectively epitaxially grown from the exposed area of ​​the silicon substrate 900 between the isolation 902 and the outer spacer 925. The manufacturing process for epitaxially growing the raised portions 952 and 954 can include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MBE), or any combination thereof. The depth of the raised portions 952 and 954 can be controlled by controlling the growth rate and / or duration of the epitaxial process.

[0117] Method 1000 proceeds to operation 1016, as shown in FIG. Figure 10 As shown, a first source and a first drain are formed at least in the elevated portion. In some embodiments, to form the first source and the first drain, at least the elevated portion is doped. In some embodiments, the first source and the first drain are formed in the elevated portion and the first well.

[0118] like Figure 9JAs shown, a P-type source 932 and a P-type drain 932 are formed in the raised portion 952 and the N-well 910, and are separated by spacers 924 and 955, a curved gate dielectric 931, and a recessed gate electrode 920. To form the P-type source and drain 932, in some embodiments, a mask layer 930 is formed on the silicon substrate 900, and then the mask layer 930 is patterned to expose the areas where the P-type source and drain 932 are to be formed. The mask layer 930 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 930 can be patterned using photolithography and wet / dry etching and aligned with the N-well 910. Ion implantation of a P-type dopant such as B or Ga can be performed using the mask layer 930 to form the P-type source and drain 932 in at least the raised portion 952. In some embodiments, the P-type dopant is further diffused from the elevated portion 952 into the N-well 910 , for example, by an annealing process, so that P-type source and drain 932 are formed in the elevated portion 952 and the N-well 910 .

[0119] Similarly, if Figure 9K As shown, an N-type source 934 and an N-type drain 934 are formed in the elevated portion 954 and the P-well 912, and are separated by spacers 924 and 955, as well as the curved gate dielectric 931 and the recessed gate electrode 920. To form the N-type source and drain 934, in some embodiments, a mask layer 933 is formed on the silicon substrate 900 and then patterned to expose the areas where the N-type source and drain 934 are to be formed. The mask layer 933 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 933 can be patterned using photolithography and wet / dry etching and aligned with the P-well 912. Ion implantation of an N-type dopant, such as P or As, can be performed using the mask layer 933 to form the N-type source and drain 934 at least in the elevated portion 954. In some embodiments, N-type dopants are further diffused from the elevated portion 954 into the P-well 912 , such as by an annealing process, so that N-type source and drain 934 are formed in the elevated portion 954 and the N-well 912 .

[0120] Method 1000 proceeds to operation 1018, as shown in FIG. Figure 10 As shown, a second source and a second drain are formed in the second well. Figure 9JAs shown, photolithography is then used to form P-type source and drain 926 and N-type source and drain 928 in the N-well 904 and P-well 906 of the planar transistor, respectively, followed by ion implantation of corresponding P-type and N-type dopants. In some embodiments, the conditions for the ion implantation of P-type source and drain 926, N-type source and drain 928, P-type source and drain 932, and N-type source and drain 934, for example, the doping concentration of the P-type source and drain 932 and N-type source and drain 934 of the recessed channel transistor is different from that of the P-type source and drain 926 and N-type source and drain 928 of the planar channel transistor.

[0121] refer to Figure 11 , method 1100 begins at operation 1102, where a first well is formed in a substrate. The substrate may be a silicon substrate. Figure 9A As shown, multiple isolations 902, such as STIs, are formed in a silicon substrate 900 using, for example, wet / dry etching and thin film deposition of silicon oxide. The isolations 902 can divide the silicon substrate 900 into multiple regions, in which multiple transistors can be formed. Figure 9A As shown, an N-well 904 and a P-well 906 are then formed in the silicon substrate 900. In some embodiments, the N-well 904 and the P-well 906 are formed in regions for forming planar transistors. The N-well 904 and the P-well 906 can be patterned using photolithography and aligned between the isolation 902, followed by ion implantation of corresponding N-type dopants and P-type dopants.

[0122] Method 1100 proceeds to operation 1104, as shown in FIG. Figure 11 As shown, a second well is formed in the substrate. In some embodiments, the depth of the second well is greater than the depth of the first well. Figure 9B As shown, an N-well 910 is formed in a silicon substrate 900. The N-well 910 can be part of a P-type recessed channel transistor and can therefore be formed in a region for forming the P-type recessed channel transistor. To form the N-well 910, in some embodiments, a mask layer 908 is formed on the silicon substrate 900 and then patterned to expose the region where the N-well 910 is to be formed. The mask layer 908 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 908 can be patterned using photolithography and wet / dry etching and aligned between the isolations 902. Ion implantation of an N-type dopant such as P or As can be performed using the mask layer 908 to form the N-well 910 in the desired region between the isolations 902. In some embodiments, ion implantation conditions of the N-well 904 , the P-well 906 , and the N-well 910 are controlled such that the depth of the N-well 910 is greater than the depths of the N-well 904 and the P-well 906 .

[0123] like Figure 9C As shown, a P-well 912 is formed in a silicon substrate 900. The P-well 912 can be part of an N-type recessed channel transistor and can therefore be formed in an area for forming the N-type recessed channel transistor. To form the P-well 912, in some embodiments, a mask layer 909 is formed on the silicon substrate 900 and then patterned to expose the area where the P-well 912 is to be formed. The mask layer 909 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 909 can be patterned using photolithography and wet / dry etching and aligned between the isolations 902. Ion implantation of a P-type dopant such as B or Ga can be performed using the mask layer 909 to form the P-well 912 in the desired area between the isolations 902. In some embodiments, ion implantation conditions of the N-well 904 , the P-well 906 , and the P-well 912 are controlled such that the depth of the P-well 912 is greater than the depths of the N-well 904 and the P-well 906 .

[0124] Method 1100 proceeds to operation 1106, as shown in FIG. Figure 11 As shown, a groove is formed in the first well in the substrate so that the groove is surrounded by the first well. In some embodiments, the depth of the groove is between 50nm and 100nm. Figure 9D As shown, recesses 914 are formed in the N-well 910 and the P-well 912, respectively, using, for example, the same etching process. In some embodiments, a mask layer 911 is formed on the silicon substrate 900, and then the mask layer 911 is patterned to expose the regions in the N-well 910 and the P-well 912 where recesses 914 are to be formed. The mask layer 911 may include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 911 may be patterned using photolithography and wet / dry etching. The silicon substrate 900 may then be etched using the mask layer 911 to form recesses 914 in the wells 910 and 912. The etching process may include dry etching and / or wet etching. In some embodiments, the etching process is a dry etching process, such as reactive ion etching (RIE). The etching conditions (e.g., etching rate and etching duration) may be controlled to control the depth of the recesses 914. In some embodiments, the depth of the groove 914 is between 50 nm and 100 nm. Figure 9D As shown, recesses 914 are formed only in wells 910 and 912 of the recessed channel transistors, and not in wells 904 and 906 of the planar transistors.

[0125] Method 1100 proceeds to operation 1108, as Figure 11, wherein a curved gate dielectric is formed on the sidewalls and bottom surface of the recess, and a flat gate dielectric is formed on the substrate. In some embodiments, to form the curved gate dielectric and the flat gate dielectric, a sacrificial dielectric layer is formed on the sidewalls and bottom surface of the recess, the sacrificial dielectric layer is removed, a gate dielectric layer is formed on the sidewalls and bottom surface of the recess, and the gate dielectric layer is patterned.

[0126] like Figure 9J As shown, in each groove 914 (as Figure 9D A curved gate dielectric 931 is formed on the sidewall and bottom surface of the silicon substrate 900, and a flat gate dielectric 925 is formed on the silicon substrate 900. In order to form the curved gate dielectric 931 and the flat gate dielectric 925, as shown in FIG. Figure 9E As shown, a gate dielectric layer 916 can be formed on the sidewalls and bottom surface of each groove 914 and on the top surface of the silicon substrate 900 (e.g., wells 904 and 906) by the same deposition process. In some embodiments, a dielectric material layer such as silicon oxide is deposited using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For example, ISSG can be used to deposit a silicon oxide layer to form the gate dielectric layer 916. In some embodiments, before forming the gate dielectric layer 916, a sacrificial dielectric layer (not shown) is formed on the sidewalls and bottom surface of the groove 914, for example using thermal oxidation, to remove defects on the sidewalls and bottom surface of the groove 914 caused by the etching process. Then, before forming the gate dielectric layer 916, the sacrificial dielectric layer can be removed, for example using wet etching. As shown Figure 9I and 9J As shown, the gate dielectric layer 916 can be patterned using photolithography and etching processes in subsequent steps or the same steps to form a flat gate dielectric 925 and a curved gate dielectric 931.

[0127] Method 1100 proceeds to operation 1110, as shown in FIG. Figure 11 As shown, a recessed gate electrode is formed on a curved gate dielectric and a flat gate electrode is formed on a flat gate dielectric. In some embodiments, to form the recessed gate electrode and the flat gate electrode, a gate electrode layer is formed on the curved gate dielectric to fill the recess, the gate electrode layer is planarized, and the planarized gate electrode layer is patterned.

[0128] like Figure 9J As shown, a recessed gate electrode 920 is formed on the curved gate dielectric 931, and a flat gate electrode 922 is formed on the flat gate dielectric 925. In order to form the recessed gate electrode 920 and the flat gate electrode 922, as shown in FIG. Figure 9FAs shown, a gate electrode layer 918 is formed on the gate dielectric layer 916. The recess 914 (eg, Figure 9E As shown). In some embodiments, a conductive material layer 918 such as polysilicon is deposited on the gate dielectric layer 916 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Depending on the surface flatness of the gate electrode layer 918 affected by the depth of the recess 914, a planarization process such as chemical mechanical polishing (CMP) may be performed to planarize the top surface of the gate electrode layer 918. Figure 9G As shown, the gate electrode layer 918 is patterned using photolithography and etching processes in the same step to form a recessed gate electrode 920 and a flat gate electrode 922. In some embodiments, the recessed gate electrode 920 and the flat gate electrode 922 are doped using ion implantation to increase their conductivity.

[0129] Method 1100 proceeds to operation 1112, as shown in FIG. Figure 11 , wherein a first source and a first drain are formed, separated by a first gate dielectric and a first gate electrode. At least one of the first source or the first drain may include a first region in contact with the first gate dielectric, and a second region at the top surface of the substrate having a higher doping concentration than the first region. In some embodiments, to form the first source and the first drain, a dopant is doped into the second region, and the dopant is locally annealed, for example using laser spike annealing, to dope the first region. In some embodiments, a source / drain contact is formed in contact with the second region.

[0130] like Figure 9JAs shown, a P-type source 932 and a P-type drain 932 are formed in the N-type well 910 and are separated by a curved gate dielectric layer 931 and a recessed gate electrode 920. To form the P-type source and drain 932, in some embodiments, a mask layer 930 is formed on the silicon substrate 900, and then the mask layer 930 is patterned to expose the areas where the P-type source and drain 932 are to be formed. The mask layer 930 may include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 930 may be patterned using photolithography and wet / dry etching and aligned with the N-well 910. In some embodiments, a high-low doping scheme is performed to form the P-type source and drain 932 having high-doped regions and low-doped regions. For example, ion implantation of a P-type dopant such as B or Ga may be first performed using a mask layer 930 to form a shallow junction (as a high-doped region), for example, with a thickness of less than 100 nm, at the top surface of the N-well 910 in the silicon substrate 900. A local annealing process, such as laser spike annealing, may then be performed at the shallow junction to diffuse the P-type dopant into a deep junction (for example, with a thickness of more than 200 nm) (as a low-doped region). After the local annealing, the doping concentration of the low-doped region may be within 10 18 / cm 3 and 10 19 / cm 3 and the doping concentration of the high-doped region may be at least 10 20 / cm 3 .

[0131] Similarly, if Figure 9KAs shown, an N-type source 934 and an N-type drain 934 are formed in the P-well 912 and separated by a curved gate dielectric 931 and a recessed gate electrode 920. To form the N-type source and drain 934, in some embodiments, a mask layer 933 is formed on the silicon substrate 900, and then the mask layer 933 is patterned to expose the areas where the N-type source and drain 934 are to be formed. The mask layer 933 can include a soft mask layer such as a photoresist layer and / or a hard mask layer such as a silicon oxide layer. The mask layer 933 can be patterned using photolithography and wet / dry etching and aligned with the P-well 912. In some embodiments, a high-low doping scheme is implemented to form the N-type source and drain 934 having high-doped regions and low-doped regions. For example, ion implantation of an N-type dopant such as P or As may be performed first using a mask layer 933 to form a shallow junction (as a high-doped region) at the top surface of the P-well 912 in the silicon substrate 900, for example, with a thickness of less than 100 nm. A local annealing process, such as laser spike annealing, may then be performed at the shallow junction to diffuse the N-type dopant into a deep junction (for example, with a thickness of more than 200 nm) (as a low-doped region). After the local annealing, the doping concentration of the low-doped region may be within 10 18 / cm 3 and 10 19 / cm 3 and the doping concentration of the high-doped region may be at least 10 20 / cm 3 .

[0132] Method 1100 proceeds to operation 1114, as shown in FIG. Figure 11 As shown, a second source and a second drain are formed in the second well. Figure 9J As shown, photolithography is then used to form P-type source and drain 926 and N-type source and drain 928 in the N-well 904 and P-well 906 of the planar transistor, respectively, followed by ion implantation of corresponding P-type and N-type dopants. In some embodiments, the conditions for the ion implantation of P-type source and drain 926, N-type source and drain 928, P-type source and drain 932, and N-type source and drain 934, for example, the doping concentration of the P-type source and drain 932 and N-type source and drain 934 of the recessed channel transistor is different from that of the P-type source and drain 926 and N-type source and drain 928 of the planar channel transistor.

[0133] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0134] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device comprising: memory cell array; as well as A plurality of peripheral circuits are coupled to the memory cell array, the peripheral circuits including a first peripheral circuit, the first peripheral circuit including a recessed channel transistor, the recessed channel transistor including: a well having a groove; a recessed gate structure protruding into the recess of the well and comprising a curved gate dielectric and a gate electrode on the gate dielectric, wherein the gate dielectric comprises a side portion and a bottom portion; a spacer structure on a sidewall of the gate electrode; and A source and a drain, the source and the drain being separated by the recessed gate structure, wherein at least one of the source or the drain comprises a first region in contact with the side portion of the gate dielectric, and a second region having a higher doping concentration than the first region, wherein the second region comprises as a first portion an elevated portion above the bottom surface of the spacer structure and in contact with the sidewalls of the spacer structure, and a second portion below the bottom surface of the spacer structure and not in contact with the gate dielectric.

2. The memory device according to claim 1, wherein The doping concentration difference between the first region and the second region is at least 10 times.

3. The memory device according to claim 2, wherein The doping concentration of the first region is 10 18 / cm 3 with 10 19 / cm 3 and the doping concentration of the second region is at least 10 20 / cm 3 .

4. The memory device according to claim 1, wherein The thickness of the first region is greater than the thickness of the second region.

5. The memory device according to claim 4, wherein The thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm. The memory device according to claim 1 , wherein: The recessed channel transistor further includes source / drain contacts in contact with the second region.

7. The memory device according to any one of claims 1 to 6, wherein: The well is a P-well, and the at least one of the source or the drain is a drain doped with an N-type dopant.

8. The memory device according to any one of claims 1 to 6, wherein The source and the drain are separated by the spacer structure.

9. The memory device according to any one of claims 1 to 6, wherein: The peripheral circuit further includes a second peripheral circuit including a planar transistor including a well and a planar gate structure on the well, and the planar gate structure including a gate dielectric and a gate electrode on the gate dielectric.

10. The memory device according to claim 9, wherein The gate dielectric of the recessed channel transistor has a thickness greater than a thickness of the gate dielectric of the planar transistor.

11. The memory device according to any one of claims 1 to 6 and 10, wherein: The first peripheral circuit includes a driving circuit.

12. The memory device according to any one of claims 1 to 6 and 10, wherein: The first peripheral circuit is coupled to a voltage source greater than 3.3V.

13. The memory device according to claim 12, wherein: The voltage source is between 5V and 30V.

14. A semiconductor device comprising: substrate; A first transistor, the first transistor comprising: a first well in the substrate and having a groove; a recessed gate structure protruding into the recess of the first well and comprising a curved first gate dielectric and a first gate electrode on the first gate dielectric, wherein the first gate dielectric comprises a side portion and a bottom portion; a spacer structure on a sidewall of the first gate electrode; and a first source and a first drain, the first source and the first drain being separated by the recessed gate structure, wherein at least one of the first source or the first drain includes a first region contacting the side of the first gate dielectric, and a second region having a higher doping concentration than the first region, wherein the second region includes a first portion that is a raised portion above a bottom surface of the spacer structure and in contact with a sidewall of the spacer structure, and a second portion that is below the bottom surface of the spacer structure and not in contact with the gate dielectric; and A second transistor, the second transistor comprising: a second well in the substrate; and A planar gate structure is on the second well and includes a second gate dielectric and a second gate electrode on the second gate dielectric.

15. The semiconductor device according to claim 14, wherein The thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

16. The semiconductor device according to claim 14, wherein The doping concentration difference between the first region and the second region is at least 10 times.

17. The semiconductor device according to claim 16, wherein The doping concentration of the first region is 10 18 / cm 3 with 10 19 / cm 3 and the doping concentration of the second region is at least 10 20 / cm 3 .

18. The semiconductor device according to any one of claims 14 to 17, wherein: The thickness of the first region is greater than the thickness of the second region.

19. The semiconductor device according to claim 18, wherein The thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm.

20. The semiconductor device according to any one of claims 14 to 17, and 19, wherein: The first transistor also includes source / drain contacts in contact with the second region.

21. A method for forming a semiconductor device, comprising: forming a groove in the substrate; forming a curved first gate dielectric on sidewalls and a bottom surface of the recess, and forming a second gate dielectric on the substrate, wherein the first gate dielectric includes a side portion and a bottom portion; forming a first gate electrode on the first gate dielectric and forming a second gate electrode on the second gate dielectric; forming a first spacer structure on sidewalls of the first gate electrode over the substrate; and A first source and a first drain are formed separated by the first gate dielectric and the first gate electrode, wherein at least one of the first source or the first drain includes a first region in contact with the side portion of the first gate dielectric, and a second region having a higher doping concentration than the first region, wherein the second region includes a raised portion as a first portion above the bottom surface of the spacer structure and in contact with the sidewall of the spacer structure, and a second portion below the bottom surface of the spacer structure and not in contact with the gate dielectric.

22. The method according to claim 21, wherein Forming the first source and the first drain includes: implanting a dopant into the second region; and The dopant is locally annealed to dope the first region.

23. The method according to claim 22, wherein Local annealing includes laser spike annealing.

24. The method according to claim 21, wherein The doping concentration difference between the first region and the second region is at least 10 times.

25. The method according to claim 24, wherein The doping concentration of the first region is 10 18 / cm 3 with 10 19 / cm 3 and the doping concentration of the second region is at least 10 20 / cm 3 .

26. The method according to any one of claims 21 to 25, wherein The thickness of the first region is greater than the thickness of the second region.

27. The method according to claim 26, wherein The thickness of the first region is greater than 200 nm, and the thickness of the second region is less than 100 nm.

28. The method of any one of claims 21 to 25 and 27, further comprising forming source / drain contacts in contact with the second region.

29. The method according to any one of claims 21 to 25, and 27, further comprising: forming a first well and a second well in the substrate, wherein the recess is in the first well and the second gate dielectric is on the second well; and A second source and a second drain are formed in the second well.

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