Multi-mode antenna tuner circuit and related device

Abstract

A multi-mode antenna tuner circuit and related apparatus are provided. The multi-mode antenna tuner circuit can be configured to operate in a low-current mode or a high-power mode. When operating in the high-power mode, the multi-mode antenna tuner circuit can provide full-featured functionality and consume a higher amount of current. In contrast, in the low-current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication device employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some of the multi-mode antenna tuner circuits to operate in the low-current mode based on the operating environment (e.g., frequency band, location, etc.) and the internal state of the wireless communication device (e.g., battery level, signal strength, etc.). As a result, power consumption and heat dissipation can be reduced without degrading the performance of the wireless communication device.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 62 / 961,738, filed on January 16, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The technology of the present disclosure generally relates to antenna tuner circuits in wireless communication devices. Background Art

[0004] Wireless communication devices have become increasingly common in today's society. The popularity of these wireless communication devices is partly driven by the many functions now enabled on such devices. The improvement in processing power in such devices means that wireless communication devices have evolved from mere communication tools into complex mobile multimedia centers capable of enhancing the user experience.

[0005] The re - defined user experience requires various radio access technologies (RATs) to provide higher data rates, such as Wi - Fi, Long - Term Evolution (LTE), and Fifth - Generation New Radio (5G - NR). Thus, a wireless communication device may include different transceiver circuits and multiple antennas for transmitting wireless communication signals at different RATs and / or radio frequencies. Each of the antennas may be coupled to one or more antenna tuner circuits, which are configured to improve the impedance matching, frequency tuning, power handling, and / or linearization of the antenna.

[0006] Notably, a wireless communication device may require a dozen antenna tuner circuits, and each antenna tuner circuit may consume approximately 50 μA of current to operate. In this regard, the antenna tuner circuits alone can consume more than 600 μA of current, which can lead to an increase in power consumption and heat dissipation in the wireless communication device. Summary of the Invention

[0007] Aspects disclosed in the detailed description include a multi-mode antenna tuner circuit and related apparatus. In the embodiments disclosed herein, the multi-mode antenna tuner circuit may be configured to operate in a low current mode or a high power mode. When operating in the high power mode, the multi-mode antenna tuner circuit may provide full-featured functionality and consume a higher amount of current. In contrast, in the low current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication device employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some of the multi-mode antenna tuner circuits to operate in the low current mode based on the operating environment (e.g., frequency band, location, etc.) and the internal state of the wireless communication device (e.g., battery level, signal strength, etc.). As a result, power consumption and heat dissipation can be reduced without degrading the performance of the wireless communication device.

[0008] In one aspect, a multi-mode antenna tuner circuit is provided. The multi-mode antenna tuner circuit includes a voltage input terminal coupled to a voltage source to receive a power supply voltage. The multi-mode antenna tuner circuit further includes a signal output terminal coupled to an antenna port to output a radio frequency (RF) signal. The multi-mode antenna tuner circuit further includes a first set of circuits that together consume a first amount of current. The multi-mode antenna tuner circuit further includes a second set of circuits that together consume a second amount of current greater than the first amount of current. The multi-mode antenna tuner circuit further includes a control circuit. The control circuit is configured to receive an instruction indicating a low current mode or a high power mode. The control circuit is further configured to activate the first set of circuits and deactivate the second set of circuits when the instruction indicates the low current mode. The control circuit is further configured to deactivate the first set of circuits and activate the second set of circuits when the instruction indicates the high power mode.

[0009] In another aspect, a wireless communication device is provided. The wireless communication device includes one or more antenna front-end circuits. Each antenna front-end circuit of the antenna front-end circuits includes an antenna port coupled to an antenna. Each antenna front-end circuit of the antenna front-end circuits further includes a plurality of multi-mode antenna tuner circuits coupled to the antenna port. The wireless communication device further includes a main control circuit coupled to the one or more antenna front-end circuits. The main control circuit is configured to determine that at least one of the plurality of multi-mode antenna tuner circuits in at least one of the one or more antenna front-end circuits is capable of operating in a low current mode. The main control circuit is further configured to cause the at least one multi-mode antenna tuner circuit to operate in the low current mode.

[0010] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of the present disclosure and recognize its additional aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings incorporated in and forming a part of this specification illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0012] Figure 1 is a schematic diagram of an exemplary conventional wireless communication device;

[0013] Figure 2A is a schematic diagram of an exemplary wireless communication device 22 configured in accordance with an embodiment of the present disclosure to achieve an opportunistic reduction in current consumption;

[0014] Figure 2B is provided in Figure 2A is a schematic diagram of an exemplary illustration of one or more SuBUS telegrams transmitted on a single-wire bus in a wireless communication device;

[0015] Figure 3A is a schematic diagram of an exemplary multi-mode antenna tuner circuit configured in accordance with an embodiment of the present disclosure;

[0016] Figure 3B is a schematic diagram of an exemplary negative voltage multiplexer configured in accordance with an embodiment of the present disclosure;

[0017] Figure 4A is a schematic diagram of an exemplary multi-mode antenna tuner circuit configured in accordance with another embodiment of the present disclosure; and

[0018] Figure 4B is a schematic diagram of an exemplary multi-mode antenna tuner circuit configured in accordance with another embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The embodiments set forth below represent the information necessary for those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. When reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts that are not specifically recited herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0020] It should be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] It should be understood that when an element such as a layer, region, or substrate is referred to as "on" or "extending onto" another element, it can be directly on or directly extend onto the other element, or there may also be intervening elements. In contrast, when an element is referred to as "directly on" or "directly extending onto" another element, there are no intervening elements. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as "above" or "extending above" another element, it can be directly above or directly extend above the other element, or there may also be intervening elements. In contrast, when an element is referred to as "directly above" or "directly extending above" another element, there are no intervening elements. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0022] Relative terms such as "below" or "above" or "on" or "under" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms and those discussed above are intended to include different orientations of the device in addition to the orientations depicted in the figures.

[0023] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" are also intended to include the plural forms. It should also be understood that when used herein, the terms "comprises / comprising / includes / including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense.

[0025] Aspects disclosed in the detailed description include a multimode antenna tuner circuit and related apparatus. In embodiments disclosed herein, the multimode antenna tuner circuit may be configured to operate in a low current mode or a high power mode. When operating in the high power mode, the multimode antenna tuner circuit may provide full functionality and consume a higher amount of current. In contrast, in the low current mode, the multimode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication device employing multiple multimode antenna tuner circuits, it is possible to opportunistically configure some of the multimode antenna tuner circuits to operate in the low current mode based on the operating environment (e.g., frequency band, location, etc.) and the internal state of the wireless communication device (e.g., battery level, signal strength, etc.). As a result, power consumption and heat dissipation can be reduced without degrading the performance of the wireless communication device.

[0026] Before discussing the multimode antenna tuner circuit of the present disclosure Figure 2A starting from Figure 1 a brief overview of a conventional wireless communication device is first provided to assist in understanding the current consumption issues associated with conventional antenna tuner circuits.

[0027] In this regard, Figure 1 is a schematic diagram of an exemplary conventional wireless communication device 10. The conventional wireless communication device 10 includes a transceiver circuit 12 and a plurality of antenna front-end circuits 14(1)-14(N). The antenna front-end circuits 14(1)-14(N) include a plurality of antenna ports 16(1)-16(N), each of which is coupled to a corresponding one of a plurality of antennas 18(1)-18(N). Each of the antenna front-end circuits 14(1)-14(N) includes one or more antenna tuner circuits 20(1)-20(M), which are coupled to a corresponding one of the antenna ports 16(1)-16(N).

[0028] It should be noted that each antenna tuner circuit in the antenna tuner circuits 20(1)-20(M) can be configured to perform specific functionality for a corresponding one of the antennas 18(1)-18(N). In this regard, all the antenna tuner circuits 20(1)-20(M) will be required to operate simultaneously in order to perform full-fledged functionality for a corresponding one of the antennas 18(1)-18(N).

[0029] The antenna tuner circuits 20(1)-20(N) in any one of the antenna front-end circuits 14(1)-14(N) can be configured by the transceiver circuit 12 to operate simultaneously in a high-power mode, in which all the antenna tuner circuits 20(1)-20(M) are activated and operate simultaneously. In this regard, each antenna tuner circuit in the antenna tuner circuits 20(1)-20(M) can consume a current of approximately 50 μA.

[0030] The antenna tuner circuits 20(1)-20(N) in any one of the antenna front-end circuits 14(1)-14(N) can also be configured by the transceiver circuit 12 to operate simultaneously in a low-power mode. In this regard, all the antenna tuner circuits 20(1)-20(M) are deactivated and consume very little current.

[0031] The conventional wireless communication device 10 can be configured to support multiple radio access technologies (RATs) and / or operate in multiple radio frequency (RF) bands. Accordingly, the conventional wireless communication device 10 can include multiple antennas, each of which is supported by multiple antenna tuner circuits. For example, if the conventional wireless communication device 10 is configured to support four-by-four (4x4) multiple-input multiple-output (MIMO) communication with four antennas, and each antenna is supported by three (3) antenna tuner circuits, then the conventional wireless communication device 10 will ultimately have twelve (12) antenna tuner circuits. Thus, when operating simultaneously in the high-power mode, the twelve (12) antenna tuner circuits will consume approximately 600 μA of current. The large amount of current drawn by the antenna tuner circuits can significantly shorten the battery life of the conventional wireless communication device 10, thereby degrading the end-user experience. Accordingly, it may be desirable to reduce the current consumption of the antenna tuner circuits to help extend the battery life of the conventional wireless communication device 10.

[0032] In this regard, Figure 2AFIG. 0 is a schematic diagram of an exemplary wireless communication device 22 configured to achieve an opportunistic reduction in current consumption in accordance with an embodiment of the present disclosure. In a non-limiting example, the wireless communication device 22 may be a device with wireless capabilities, such as a smartphone, a tablet computer, a laptop computer, a smart appliance, etc. In another non-limiting example, the wireless communication device 22 may also be a network node, such as a cellular base station, a wireless access point, a low-power radio head, etc.

[0033] The wireless communication device 22 includes one or more antenna front-end circuits 24(1)-24(N). The antenna front-end circuits 24(1)-24(N) include a plurality of antenna ports 26(1)-26(N), each of which is coupled to a respective one of a number of antennas 28(1)-28(N). Each of the antenna front-end circuits 24(1)-24(N) includes a number of multi-mode antenna tuner circuits 30(1)-30(M) (referred to as "M tuner circuits") coupled to a respective one of the antenna ports 26(1)-26(N). The antenna front-end circuits 24(1)-24(N) are configured to receive one or more radio frequency (RF) signals 32(1)-32(N) and output the RF signals 32(1)-32(N) to the antenna ports 26(1)-26(N).

[0034] In a non-limiting example, each of the multi-mode antenna tuner circuits 30(1)-30(M) may be configured to perform a specific function (e.g., load detection, impedance tuning, aperture impedance tuning, etc.) for a respective one of the antennas 28(1)-28(N) coupled to a respective one of the antenna ports 26(1)-26(N). For example, in the antenna front-end circuit 24(1), the multi-mode antenna tuner circuit 30(1) may be configured to perform load detection, and the multi-mode antenna tuner circuit 30(M) may be configured to perform impedance tuning for the antenna 28(1) coupled to the antenna port 26(1).

[0035] As discussed in detail below, each of the multimode antenna tuner circuits 30(1)-30(M) in the antenna front-end circuits 24(1)-24(N) can be individually configured to operate in a low current mode or a high power mode. When operating in the high power mode, each of the multimode antenna tuner circuits 30(1)-30(M) will consume a relatively high amount of current (e.g., 50 μA). In contrast, when operating in the low current mode, each of the multimode antenna tuner circuits 30(1)-30(M) will consume a relatively low amount of current (e.g., 10 μA to 12 μA). Thus, it is possible to configure some or all of the multimode antenna tuner circuits 30(1)-30(M) to operate in the low current mode based on factors such as the operating environment (e.g., frequency band, location, etc.) and the internal state of the wireless communication device 22 (e.g., battery level, signal strength, etc.). As a result, power consumption and heat dissipation can be reduced without degrading the performance of the wireless communication device 22.

[0036] As an example, the wireless communication device 22 includes a main control circuit 34, which may be a transceiver circuit. The wireless communication device 22 may also include a bus control circuit 36 coupled to the main control circuit 34. The bus control circuit 36 is coupled to each of the multimode antenna tuner circuits 30(1)-30(M) in the antenna front-end circuits 24(1)-24(N) via one or more single-wire buses 38(1)-38(L) (referred to as "SuBUS"), each of the single-wire buses including one wire.

[0037] In a non-limiting example, each of the multimode antenna tuner circuits 30(1)-30(M) in each of the antenna front-end circuits 24(1)-24(N) can function as a slave circuit of the bus control circuit 36. In this regard, each of the multimode antenna tuner circuits 30(1)-30(M) is uniquely identified by a corresponding unique slave identifier (USID). Thus, the bus control circuit 36, which functions as the master circuit, can communicate with each of the multimode antenna tuner circuits 30(1)-30(M) in the antenna front-end circuits 24(1)-24(N) based on the USID.

[0038] The bus control circuit 36 and each of the multimode antenna tuner circuits 30(1)-30(M) in the antenna front-end circuits 24(1)-24(N) are configured to communicate based on SuBUS telegrams, as Figure 2B illustrated. In this regard, Figure 2B is provided in Figure 2ASchematic diagram of an exemplary illustration of one or more SuBUS telegrams 40, 42 transmitted on the single-wire buses 38(1)-38(L) in the wireless communication device 22.

[0039] Each of the SuBUS telegrams 40, 42 includes a sequence start (SoS) sequence 44 and a SuBUS command sequence 46 immediately following the SOS sequence 44. The SuBUS command sequence 46 can correspond to a predefined SuBUS operation (e.g., register read or register write). The SOS sequence 44 is always before the SuBUS command sequence 46 and is always transmitted from the bus control circuit 36 to Figure 2A each of the multimode antenna tuner circuits 30(1)-30(M) in each of the antenna front-end circuits 24(1)-24(N). Thus, each of the SuBUS telegrams 40, 42 represents a communication period during which the bus control circuit 36 can communicate with any one of the multimode antenna tuner circuits 30(1)-30(M) in each of the antenna front-end circuits 24(1)-24(N).

[0040] The SuBUS telegram 42 following the SuBUS telegram 40 can have a fast charging period 48 that starts at time T1 and ends at time T2 (T2 > T1) and an idle period 50 that starts at time T2 and ends at time T3 (T3 > T2). The fast charging period 48 is configured to allow each of the multimode antenna tuner circuits 30(1)-30(M) to draw a fast charging current I 充电 (as Figure 2A shown). As discussed later in Figure 3A , the fast charging current I 充电 allows each of the multimode antenna tuner circuits 30(1)-30(M) to generate a power supply voltage to power the corresponding antenna tuning operation.

[0041] In this regard, each of the single-wire buses 38(1)-38(L) is said to be in a fast charging state during the fast charging period 48. The idle period 50 can be a period of inactivity during which the bus control circuit 36 and each of the multimode antenna tuner circuits 30(1)-30(M) in each of the antenna front-end circuits 24(1)-24(N) can be inactive to help save power. Thus, each of the single-wire buses 38(1)-38(L) is said to be in an idle state during the idle period 50.

[0042] The bus control circuit 36 is configured to suspend the SuBUS telegram communication on the single-wire buses 38(1)-38(L) during the fast charging period 48 and the idle period 50. Accordingly, the multi-mode antenna tuner circuits 30(1)-30(M) in each of the bus control circuit 36 and the antenna front-end circuits 24(1)-24(N) are configured to suppress the transmission of SuBUS telegrams and data payloads from time T1 to T3. In this regard, the single-wire buses 38(1)-38(L) can be said to be in a suspended mode between time T1 and T3.

[0043] Return reference Figure 2A , the main control circuit 34 is configured to determine that at least one of the multi-mode antenna tuner circuits 30(1)-30(M) in at least one of the antenna front-end circuits 24(1)-24(N) can operate in a low current mode. Accordingly, the main control circuit 34 can generate an instruction 52 to cause at least one of the multi-mode antenna tuner circuits 30(1)-30(M) to operate in a low current mode. For example, the main control circuit 34 can determine that the multi-mode antenna tuner circuit 30(1) in the antenna front-end circuit 24(1) and the multi-mode antenna tuner circuit 30(M) in the antenna front-end circuit 24(N) can operate in a low current mode. Accordingly, the main control circuit 34 can generate an instruction 52 to cause the multi-mode antenna tuner circuit 30(1) in the antenna front-end circuit 24(1) and the multi-mode antenna tuner circuit 30(M) in the antenna front-end circuit 24(N) to operate in a low current mode.

[0044] The main control circuit 34 can also determine that at least one other of the multi-mode antenna tuner circuits 30(1)-30(M) in at least one of the antenna front-end circuits 24(1)-24(N) can operate in a high power mode. Accordingly, the main control circuit 34 can generate an instruction 52 to cause at least one other of the multi-mode antenna tuner circuits 30(1)-30(M) to operate in a high power mode. For example, the main control circuit 34 can determine that the multi-mode antenna tuner circuit 30(M) in the antenna front-end circuit 24(1) and the multi-mode antenna tuner circuit 30(1) in the antenna front-end circuit 24(N) can operate in a high power mode. Accordingly, the main control circuit 34 can generate an instruction 52 to cause the multi-mode antenna tuner circuit 30(M) in the antenna front-end circuit 24(1) and the multi-mode antenna tuner circuit 30(1) in the antenna front-end circuit 24(N) to operate in a high power mode.

[0045] The main control circuit 34 can determine which one of the multimode antenna tuner circuits 30(1)-30(M) should operate in the low current mode and / or which one of the multimode antenna tuner circuits 30(1)-30(M) should operate in the high power mode based on various factors. In a non-limiting example, the main control circuit 34 can determine the low current mode and / or the high power mode based on factors such as environmental conditions (e.g., distance to the RF transmitter / receiver, indoor / outdoor, obstacles, user density, etc.), RF conditions (e.g., RF band / spectrum, transmit power, receive sensitivity, interference, attenuation, etc.), antenna impedance measurement, and / or battery conditions.

[0046] The bus control circuit 36 receives the instruction 52 from the main control circuit 34. Accordingly, the bus control circuit 36 can encode the instruction 52 into the SuBUS telegrams 40, 42 (also referred to as "bus telegrams"), as Figure 2A shown, and provide the SuBUS telegrams 40, 42 to any one of the multimode antenna tuner circuits 30(1)-30(M) in any one of the antenna front-end circuits 24(1)-24(N).

[0047] The multimode antenna tuner circuits 30(1)-30(M) in the antenna front-end circuits 24(1)-24(N) can be implemented based on different configurations, as described below in Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B discussed. Figure 2A 、 Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B The common elements between

[0048] Figure 3A are shown with common element numbers therein and are not described again here.

[0049] Figure 2B ​​as shown), and draws a fast charging current Icharge from the bus control circuit 36 during the fast charging period 48.

[0050] The multi-mode antenna tuner circuit 54A includes a control circuit 58, which can be, for example, a microprocessor or a field programmable gate array (FPGA). The control circuit 58 can be separate from or integrated with the bus interface circuit 56. The control circuit 58 is configured to decode the SuBUS telegrams 40, 42 to extract the instructions 52. The control circuit 58 can include a register 60 (denoted as "REGMAP") configured to store the instructions 52. In a non-limiting example, the instructions 52 can be stored as a binary bitmap, where the binary value "0" (also referred to as "the first value") and the binary value "1" (also referred to as "the second value") can represent the low current mode and the high power mode, respectively. Thus, by setting the register 60 to the first value or the second value, the control circuit 58 can cause the multi-mode antenna tuner circuit 54A to operate in the low current mode or the high power mode.

[0051] Upon receiving an instruction 52 indicating the low current mode, the control circuit 58 can first determine whether the register 60 is currently set to the second value. If it is determined that the register 60 has the second value, it indicates that the multi-mode antenna tuner circuit 54A is currently operating in the high power mode. In other words, Figure 2A the main control circuit 34 in is intended to switch the multi-mode antenna tuner circuit 54A from the high power mode to the low current mode. In this regard, the control circuit 58 can set the register 60 to the first value after a delay period (e.g., about 50 μs) from the receipt of the instruction 52 indicating the low current mode. In this way, the high power mode is maintained during the delay period, making it possible to maintain the thermal switching performance in the presence of signals 32(1)-32(N).

[0052] The multi-mode antenna tuner circuit 54A includes a voltage input terminal 62 and a voltage source 64 coupled between the bus interface circuit 56 and the voltage input terminal 62. In a non-limiting example, the voltage source 64 includes a capacitor C coupled between the voltage input terminal 62 and ground (GND) V . During the fast charging period 48, the fast charging current I received from the bus control circuit 36 充电 charges the capacitor C V to provide a supply voltage V at the voltage input terminal 62 SUP . Thus, the supply voltage V SUP powers the multi-mode antenna tuner circuit 54A to operate in the low current mode or the high power mode during the communication period 47. In this regard, the capacitor C V is repeatedly charged during the fast charging period 48 and discharged during the communication period 47, asFigure 2B as shown. At this point, when the capacitor C V is fully charged, the supply voltage V SUP will be relatively high (e.g., 1.95 V), and when the capacitor C V starts to discharge, the supply voltage VSUP becomes relatively low (e.g., 1.65 V).

[0053] The multi-mode antenna tuner circuit 54A includes a positive low-dropout (LDO) regulator 66 (denoted as "P-LDO"), a negative LDO regulator 68 (denoted as "N-LDO"), and a bandgap reference circuit 70 (denoted as "bandgap"). The positive LDO regulator 66 and the negative LDO regulator 68 are coupled to the voltage input terminal 62 and are configured to filter the supply voltage V SUP to generate a positive supply voltage V SUP that is independent of the supply voltage V PSUP (e.g., 1.5 V) and a negative supply voltage V NSUP (e.g., -1.5 V). The bandgap reference circuit 70 is also coupled to the voltage input terminal 62 and is configured to generate a clock reference voltage V SUP based on the supply voltage V CLK .

[0054] The multi-mode antenna tuner circuit 54A includes a positive voltage multiplexer 72 (denoted as "PCP MUX") and a negative voltage multiplexer 74 (denoted as "NCP MUX"). The positive voltage multiplexer 72 includes a first voltage input terminal 76, a second voltage input terminal 78, and a first voltage output terminal 80. The first voltage input terminal 76 is coupled to the voltage input terminal 62, and the second voltage input terminal 78 is coupled to the positive LDO regulator 66. The positive voltage multiplexer 72 can be controlled to selectively output the supply voltage V SUP or the positive supply voltage V PSUP at the first voltage output terminal 80. The negative voltage multiplexer 74 includes a third voltage input terminal 82, a fourth voltage input terminal 84, and a second voltage output terminal 86. The third voltage input terminal 82 is coupled to the voltage input terminal 62, and the fourth voltage input terminal 84 is coupled to the negative LDO regulator 68. The negative voltage multiplexer 74 can be controlled to selectively output the supply voltage V SUP or the negative supply voltage V NSUP at the second voltage output terminal 86.

[0055] The multi-mode antenna tuner circuit 54A includes a linearization circuit 88, a bias voltage circuit 90, a positive charge pump 92, a negative charge pump 94, a tuner driver circuit 96, and a tuner circuit 98. The linearization circuit 88 is coupled between a first voltage output terminal 80 and the tuner circuit 98. The bias voltage circuit 90 and the positive charge pump 92 are each coupled between the first voltage output terminal 80 and the tuner driver circuit 96. The negative charge pump 94 is coupled between a second voltage output terminal 86 and the tuner driver circuit 96. The tuner driver circuit 96 is coupled to a voltage input terminal 62. The tuner circuit 98 is coupled between the tuner driver circuit 96 and a signal output terminal 100, and the signal output terminal can be coupled to Figure 2A a corresponding one of the antenna ports 26(1)-26(N) in

[0056] . The positive charge pump 92 is configured to generate a positive reference voltage V SUP or a positive supply voltage V PSUP based on the supply voltage V at the first voltage output terminal 80 PREF (e.g., 3V or 500 mV). The negative charge pump 94 is configured to generate a negative reference voltage V SUP or a negative supply voltage V NSUP based on the supply voltage V at the second voltage output terminal 86 NREF (e.g., -2.5V). The positive reference voltage V PREF and / or the negative reference voltage V NREF are used to bias an RF switch (not shown) in the tuner driver circuit 96 to obtain optimal performance (e.g., on-resistance, off-capacitance, linearity, and / or voltage handling).

[0057] The linearization circuit 88 may include a digital-to-analog converter (DAC) (not shown), and the digital-to-analog converter is configured to generate a programmable bias voltage V BIA to turn on / off the state linear function in the tuner circuit 98 to obtain optimal performance. The bias voltage circuit 90 is coupled to the first voltage output terminal 80 and is configured to generate a body reference voltage V BON to minimize the threshold voltage of the tuner driver circuit 96.

[0058] The multi-mode antenna tuner circuit 54A includes an oscillator 102 and a clock multiplexer 104 (denoted as "CLK"). The oscillator 102 is coupled to a bandgap reference circuit 70 and is configured to generate a reference frequency f REFand supply it to the negative charge pump 94. The clock multiplexer 104 includes a first clock input terminal 106, a second clock input terminal 108, and a first clock output terminal 110. The first clock input terminal 106 is coupled to the oscillator 102 and the negative charge pump 94. The second clock input terminal 108 is coupled to GND. The first clock output terminal 110 is coupled to the positive charge pump 92.

[0059] The multimode antenna tuner circuit 54A may include a first filter circuit 112, a second filter circuit 114, a third filter circuit 116, a fourth filter circuit 118, a fifth filter circuit 120, and a sixth filter circuit 122. In a non-limiting example, each of the first filter circuit 112, the second filter circuit 114, the third filter circuit 116, the fourth filter circuit 118, the fifth filter circuit 120, and the sixth filter circuit 122 is a resistor-capacitor (RC) filter. The first filter circuit 112 is coupled between the voltage input terminal 62 and the positive LDO regulator 66. The second filter circuit 114 is coupled between the voltage input terminal 62 and the negative LDO regulator 68. The third filter circuit 116 is coupled between the voltage input terminal 62 and the tuner driver circuit 96. The first filter circuit 112, the second filter circuit 114, and the third filter circuit 116 are configured to reduce the ripple in the power supply voltage V SUP . The fourth filter circuit 118 is coupled between the first voltage output terminal 80 and the positive charge pump 92. The fourth filter circuit 118 is configured to reduce the ripple in the power supply voltage V SUP or the positive power supply voltage V PSUP . The fifth filter circuit 120 is coupled between the second voltage output terminal 86 and the negative charge pump 94. The fifth filter circuit 120 is configured to reduce the ripple in the power supply voltage V SUP or the negative power supply voltage V NSUP . The sixth filter circuit 122 is coupled between the positive charge pump 92 and the tuner driver circuit 96. The sixth filter circuit 122 is configured to reduce the ripple in the positive reference voltage V PREF .

[0060] The multimode antenna tuner circuit 54A further includes a low-current voltage switch 124 coupled between the first voltage output terminal 80 and the tuner driver circuit 96. In a non-limiting example, the low-current voltage switch 124 may be a silicon-on-insulator (SOI) switch that draws as little as 10 μA of current.

[0061] In this document, the low current voltage switch 124 is referred to as the first set of circuits in the multi-mode antenna tuner circuit 54A. The positive LDO regulator 66, the negative LDO regulator 68, the bandgap reference circuit 70, the linearization circuit 88, the positive charge pump 92, and the clock multiplexer 104 are collectively referred to as the second set of circuits in the multi-mode antenna tuner circuit 54A. The first set of circuits can perform reduced functionality and consume a first amount of current when activated. The second set of circuits can perform full-fledged functions when activated, but consume a second amount of current that is higher than the first amount of current.

[0062] Thus, the first set of circuits can be pre-configured to be activated in the low current mode and deactivated in the high power mode. In contrast, the second set of circuits can be pre-configured to be deactivated in the low current mode and activated in the high power mode. In a non-limiting example, the first set of circuits can be pre-configured to be automatically activated when the register 60 is set to the binary value "0", and automatically deactivated when the register 60 is set to the binary value "1". Similarly, the second set of circuits can be pre-configured to be automatically deactivated when the register 60 is set to the binary value "0", and automatically activated when the register 60 is set to the binary value "1". It should be noted that the positive voltage multiplexer 72, the negative voltage multiplexer 74, the oscillator 102, and the negative charge pump 94 are necessary in both the low current mode and the high power mode, and may not be deactivated.

[0063] In the low current mode, the positive voltage multiplexer 72 receives the power supply voltage V via the first voltage input terminal 76 SUP and outputs the power supply voltage V via the first voltage output terminal 80 SUP . The negative voltage multiplexer 74 receives the power supply voltage V via the third voltage input terminal 82 SUP and outputs the power supply voltage V via the second voltage output terminal 86 SUP . As a result, both the positive LDO regulator 66 and the negative LDO regulator 68 are bypassed. When the bandgap reference circuit 70 is deactivated, the oscillator 102 is self-biased to generate a reduced reference frequency f that is slower than the reference frequency f REF REF1 . The low current voltage switch 124 is configured to supply the power supply voltage V to the tuner drive circuit 96 SUP PSUP , thereby bypassing the positive charge pump 92.

[0064] In the high power mode, the positive LDO regulator 66 is activated. Therefore, the positive voltage multiplexer 72 receives the positive power supply voltage V via the second voltage input terminal 78 PSUP and outputs the positive power supply voltage V via the first voltage output terminal 80 PSUP。The negative LDO regulator 68 is also activated. Thus, the negative voltage multiplexer 74 receives the negative power supply voltage V via the fourth voltage input terminal 84 NSUP , and outputs the negative power supply voltage V via the second voltage output terminal 86 NSUP . The bandgap reference circuit 70 provides the clock reference voltage V to the oscillator 102 CLK to generate the reference frequency f REF . The clock multiplexer 104 provides the reference frequency f to the positive charge pump 92 REF . Since the low-current voltage switch 124 is deactivated, the positive charge pump 92 generates the positive reference voltage V PREF and supplies it to the tuner drive circuit 96.

[0065] As described above, the power supply voltage V generated by the capacitor C V can vary between 1.65V and 1.95V. Therefore, the negative voltage multiplexer 74 is configured to perform level conversion on the power supply voltage V SUP in the low-current mode to maintain the stability of the power supply voltage V SUP . At this point, SUP FIG. Figure 3B is a schematic diagram showing an exemplary illustration of the negative voltage multiplexer 74 in the multi-mode antenna tuner circuit 54A that provides Figure 3A .

[0066] The negative voltage multiplexer 74 includes a first switch SW1 and a second switch SW2. By way of example, each of the first switch SW1 and the second switch SW2 can be an SOI switch. The first switch SW1 and the second switch SW2 are configured to close and open respectively in the low-current mode, so that the third voltage input terminal 82 can be coupled to the second voltage output terminal 86. In contrast, the first switch SW1 and the second switch SW2 are configured to open and close respectively in the high-power mode, so that the fourth voltage input terminal 84 can be coupled to the second voltage output terminal 86.

[0067] The negative voltage multiplexer 74 includes a voltage compensation circuit 126 coupled between the third voltage input terminal 82 and the second voltage output terminal 86. In a non-limiting example, the voltage compensation circuit 126 includes a shunt path 128 and a transistor M3. The shunt path 128 is coupled between the third voltage input terminal 82 and GND. As an example, the transistor M3, which can be a metal-oxide silicon (MOS) transistor, includes a gate G coupled to the shunt path 128, a source S coupled to the third voltage input terminal 82, and a drain D coupled to the first switch SW1.

[0068] When the power supply voltage V at the third voltage input terminal 82 SUP is low (e.g., 1.65V), the gate G will be mostly closed to make the power supply voltage VSUP is level-shifted to the second voltage output terminal 86. When the power supply voltage V at the third voltage input terminal 82 SUP is high (e.g., 1.95V), the shunt path 128 becomes conductive to pull down the power supply voltage V SUP , thereby compensating for the increase in the power supply voltage V SUP . As a result, the voltage compensation circuit 126 can reduce the variability of the power supply voltage V in the low current mode SUP .

[0069] Figure 4A is a schematic diagram of an exemplary multi-mode antenna tuner circuit 54B configured according to another embodiment of the present disclosure. The multi-mode antenna tuner circuit 54B can be disposed in any one of the antenna front-end circuits 24(1)-24(N) of the antenna front-end circuit to be used as any one of the multi-mode antenna tuner circuits 30(1)-30(M).

[0070] The multi-mode antenna tuner circuit 54B includes a low current charge pump 130 coupled between the first voltage output terminal 80 and the tuner drive circuit 96. The multi-mode antenna tuner circuit 54B further includes a second clock multiplexer 132 (denoted as "CLK"). The second clock multiplexer 132 includes a third clock input terminal 134, a fourth clock input terminal 136, and a second clock output terminal 138. The third clock input terminal 134 is coupled to the oscillator 102, the fourth clock input terminal 136 is coupled to GND, and the second clock output terminal 138 is coupled to the low current charge pump 130. Herein, the low current charge pump 130 and the second clock multiplexer 132 are collectively referred to as the first set of circuits in the multi-mode antenna tuner circuit 54B, and the first set of circuits is activated in the low current mode and deactivated in the high power mode. The positive LDO regulator 66, the negative LDO regulator 68, the bandgap reference circuit 70, the linearization circuit 88, the positive charge pump 92, and the clock multiplexer 104 are collectively referred to as the second set of circuits in the multi-mode antenna tuner circuit 54B, and the second set of circuits is deactivated in the low current mode and activated in the high power mode. The positive voltage multiplexer 72, the negative voltage multiplexer 74, the oscillator 102, and the negative charge pump 94 are required in both the low current mode and the high power mode and may not be deactivated.

[0071] In the low current mode, the positive voltage multiplexer 72 receives the power supply voltage V via the first voltage input terminal 76 SUP , and outputs the power supply voltage V via the first voltage output terminal 80 SUP . The negative voltage multiplexer 74 receives the power supply voltage V via the third voltage input terminal 82 SUP , and outputs the power supply voltage V via the second voltage output terminal 86 SUPAs a result, both the positive LDO regulator 66 and the negative LDO regulator 68 are bypassed. With the bandgap reference circuit 70 deactivated, the oscillator 102 is self-biased to generate a reduced reference frequency f REF1 The low-current charge pump 130 is configured to boost (e.g., 1.5 times) the supply voltage V SUP to generate a boosted supply voltage V BSUP , and supply the boosted supply voltage V BSUP to the tuner driver circuit 96.

[0072] In the high-power mode, the positive LDO regulator 66 is activated. Accordingly, the positive voltage multiplexer 72 receives the positive supply voltage V PSUP via the second voltage input terminal 78, and outputs the positive supply voltage V PSUP via the first voltage output terminal 80. The negative LDO regulator 68 is also activated. Accordingly, the negative voltage multiplexer 74 receives the negative supply voltage V NSUP via the fourth voltage input terminal 84, and outputs the negative supply voltage V NSUP via the second voltage output terminal 86. The bandgap reference circuit 70 supplies the clock reference voltage V CLK to the oscillator 102 to generate the reference frequency f REF . The clock multiplexer 104 supplies the reference frequency f REF to the positive charge pump 92. Since the low-current charge pump 130 is deactivated, the second clock multiplexer 132 is also deactivated. As a result, the positive charge pump 92 generates the positive reference voltage V PREF and supplies it to the tuner driver circuit 96.

[0073] Figure 4B is a schematic diagram of an exemplary multi-mode antenna tuner circuit 54C configured according to another embodiment of the present disclosure. The multi-mode antenna tuner circuit 54C can be disposed in any one of the antenna front-end circuits 24(1)-24(N) of the antenna front-end circuit, and used as any one of the multi-mode antenna tuner circuits 30(1)-30(M).

[0074] In the multi-mode antenna tuner circuit 54C, the negative LDO regulator 68 is directly coupled to the fifth filter circuit 120. The multi-mode antenna tuner circuit 54C includes a low-current reference circuit 140. The low-current reference circuit 140 is configured to supply a stable reference voltage V REFS to the negative LDO regulator 68. As a result, the negative LDO regulator 68 is decoupled from the bandgap reference circuit 70.

[0075] The multi-mode antenna tuner circuit 54C further includes a low-frequency oscillator 142 (denoted as "LF oscillator"). The low-frequency oscillator 142 is configured to generate a reduced reference frequency f in the low-current modeREF1 . As a result, the oscillator 102 can be deactivated in the low current mode. Assume that the multi-mode antenna tuner circuit 54C no longer includes the negative voltage multiplexer 74, as Figure 4A shown, the negative LDO regulator 68 will not be deactivated in the low current mode.

[0076] At this point, the low current charge pump 130, the second clock multiplexer 132, and the low frequency oscillator 142 are collectively referred to as the first group of circuits in the multi-mode antenna tuner circuit 54C. The first group of circuits is activated in the low current mode and deactivated in the high power mode. The positive LDO regulator 66, the bandgap reference circuit 70, the linearization circuit 88, the positive charge pump 92, the clock multiplexer 104, and the oscillator 102 are collectively referred to as the second group of circuits in the multi-mode antenna tuner circuit 54C. The second group of circuits is deactivated in the low current mode and activated in the high power mode. The positive voltage multiplexer 72, the negative LDO regulator 68, the low current reference circuit 140, and the negative charge pump 94 are required in both the low current mode and the high power mode and cannot be deactivated.

[0077] In the low current mode, the positive voltage multiplexer 72 receives the power supply voltage V via the first voltage input terminal 76 SUP , and outputs the power supply voltage V via the first voltage output terminal 80 SUP . As a result, the positive LDO regulator 66 is bypassed. The negative LDO regulator 68 generates the negative power supply voltage V based on the stable reference voltage V REFS and supplies the negative power supply voltage V NSUP to the negative charge pump 94. When the oscillator 102 is deactivated, the low frequency oscillator 142 generates a reduced reference frequency f NSUP and supplies it to the negative charge pump 94. The second clock multiplexer 132 supplies the reduced reference frequency f to the low current charge pump 130 REF1 . The low current charge pump 130 is configured to boost (e.g., 1.5 times) the power supply voltage V REF1 to generate a boosted power supply voltage V SUP and supply the boosted power supply voltage V BSUP to the tuner driver circuit 96. BSUP

[0078] In the high power mode, the positive LDO regulator 66 is activated. Therefore, the positive voltage multiplexer 72 receives the positive power supply voltage V via the second voltage input terminal 78 PSUP , and outputs the positive power supply voltage V via the first voltage output terminal 80 PSUP . The negative LDO regulator 68 generates the negative power supply voltage V based on the stable reference voltage V REFS and supplies the negative power supply voltage V NSUP to...NSUP is supplied to the negative charge pump 94. The bandgap reference circuit 70 supplies a clock reference voltage V to the oscillator 102 CLK to generate a reference frequency f REF . The clock multiplexer 104 supplies the reference frequency f to the positive charge pump 92 REF . Since the low current charge pump 130 is also deactivated, the low frequency oscillator 142 and the second clock multiplexer 132 are also deactivated. As a result, the positive charge pump 92 generates a positive reference voltage V PREF and supplies it to the tuner drive circuit 96.

[0079] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. A multi-mode antenna tuner circuit, the multi-mode antenna tuner circuit comprising: A voltage input terminal, the voltage input terminal being coupled to a voltage source to receive a power supply voltage; A tuner driver circuit, coupled to a signal output terminal, the signal output terminal being coupled to an antenna port to output a radio frequency (RF) signal; A first group of circuits, the first group of circuits including a low-current voltage switch, and when the first group of circuits is activated to supply the power supply voltage to the tuner driver circuit, the first group of circuits jointly consume a first current amount; A second group of circuits, the second group of circuits including a positive low-dropout LDO regulator, a negative LDO regulator, a bandgap reference circuit, a linearization circuit, and a positive charge pump, and when the second group of circuits is activated to supply the power supply voltage to the tuner driver circuit, the second group of circuits jointly consume a second current amount greater than the first current amount; And A control circuit, the control circuit including a register and being configured to: In response to receiving an instruction indicating a low-current mode, set the register to a first value so that the first group of circuits is activated and the second group of circuits is deactivated; And And In response to receiving an instruction indicating a high-power mode, set the register to a second value different from the first value so that the first group of circuits is deactivated and the second group of circuits is activated.

2. The multi-mode antenna tuner circuit according to claim 1, wherein the control circuit is further configured to set the register to the first value after a delay period from the receipt of the instruction indicating the low-current mode.

3. The multi-mode antenna tuner circuit according to claim 1, wherein: The positive LDO regulator, the negative LDO regulator, and the bandgap reference circuit are each coupled to the voltage input terminal; The linearization circuit and the positive charge pump are each coupled to a first voltage output terminal; The multi-mode antenna tuner circuit further includes: A positive voltage multiplexer, the positive voltage multiplexer having a first voltage input terminal coupled to the voltage input terminal, a second voltage input terminal coupled to the positive LDO regulator, and a first voltage output terminal; A bias voltage circuit, the bias voltage circuit being coupled to the first voltage output terminal; A negative charge pump, the negative charge pump being coupled to the negative LDO regulator; An oscillator, the oscillator being coupled to the bandgap reference circuit; A clock multiplexer, the clock multiplexer having a first clock input terminal coupled to the oscillator and the negative charge pump, a second clock input terminal coupled to ground, and a first clock output terminal coupled to the positive charge pump; A tuner circuit, the tuner circuit being coupled to the tuner driver circuit, the linearization circuit, the control circuit, and the signal output terminal; and A bus interface circuit, the bus interface circuit being coupled to the voltage input terminal and the control circuit; and The second group of circuits further includes the clock multiplexer.

4. The multi-mode antenna tuner circuit according to claim 3, the multi-mode antenna tuner circuit further comprising: A first filter circuit, the first filter circuit being coupled between the voltage input terminal and the positive LDO regulator; A second filter circuit, the second filter circuit being coupled between the voltage input terminal and the negative LDO regulator; A third filter circuit, the third filter circuit being coupled between the voltage input terminal and the tuner drive circuit; A fourth filter circuit, the fourth filter circuit being coupled between the first voltage output terminal and the positive charge pump; A fifth filter circuit, the fifth filter circuit being coupled between the negative LDO regulator and the negative charge pump; and A sixth filter circuit, the sixth filter circuit being coupled between the positive charge pump and the tuner drive circuit.

5. The multi-mode antenna tuner circuit according to claim 3, the multi-mode antenna tuner circuit further comprising a negative voltage multiplexer having a third voltage input terminal coupled to the voltage input terminal, a fourth voltage input terminal coupled to the negative LDO regulator, and a second voltage output terminal coupled to the negative charge pump.

6. The multi-mode antenna tuner circuit according to claim 5, wherein the negative voltage multiplexer includes a voltage compensation circuit coupled between the third voltage input terminal and the second voltage output terminal, the voltage compensation circuit being configured to reduce the variability of the power supply voltage.

7. The multi-mode antenna tuner circuit according to claim 5, wherein the low-current voltage switch is coupled between the first voltage output terminal and the tuner drive circuit.

8. The multi-mode antenna tuner circuit according to claim 7, wherein in the low-current mode: The positive voltage multiplexer is configured to receive the power supply voltage via the first voltage input terminal and output the power supply voltage via the first voltage output terminal; The negative voltage multiplexer is configured to receive the power supply voltage via the third voltage input terminal and output the power supply voltage via the second voltage output terminal; The oscillator is configured to self-bias to a reduced reference frequency; and The low-current voltage switch is configured to supply the power supply voltage to the tuner drive circuit.

9. The multi-mode antenna tuner circuit according to claim 5, wherein the first group of circuits further includes: A low-current charge pump, the low-current charge pump being coupled between the first voltage output terminal and the tuner drive circuit; and A second clock multiplexer having a third clock input terminal coupled to the oscillator, a fourth clock input terminal coupled to the ground, and a second clock output terminal coupled to the low-current charge pump.

10. The multi-mode antenna tuner circuit according to claim 9, wherein in the low-current mode: The positive voltage multiplexer is configured to receive the power supply voltage via the first voltage input terminal and output the power supply voltage via the first voltage output terminal; The negative voltage multiplexer is configured to receive the power supply voltage via the third voltage input terminal and output the power supply voltage via the second voltage output terminal; The oscillator is configured to be self - biased to generate a reduced reference frequency; The second clock multiplexer is configured to provide the reduced reference frequency to the low - current charge pump; And The low - current charge pump is configured to provide a boosted supply voltage to the tuner driver circuit.

11. The multi - mode antenna tuner circuit according to claim 3, the multi - mode antenna tuner circuit comprising: A low - current reference circuit, the low - current reference circuit being coupled to the negative LDO regulator; A low - current charge pump, the low - current charge pump being coupled between the first voltage output terminal and the tuner driver circuit; A second clock multiplexer, the second clock multiplexer having a third clock input terminal coupled to the oscillator, a fourth clock input terminal coupled to ground, and a second clock output terminal coupled to the low - current charge pump; And A low - frequency oscillator, the low - frequency oscillator being coupled to the third clock input terminal; Wherein: The first set of circuits includes the low - current charge pump, the second clock multiplexer, and the low - frequency oscillator.

12. The multi - mode antenna tuner circuit according to claim 11, wherein in the low - current mode: The positive voltage multiplexer is configured to receive the supply voltage via the first voltage input terminal and output the supply voltage via the first voltage output terminal; The low - frequency oscillator is configured to generate a reduced reference frequency; The second clock multiplexer is configured to provide the reduced reference frequency to the low - current charge pump; And The low - current charge pump is configured to provide a boosted supply voltage to the tuner driver circuit.

13. A wireless communication device, the wireless communication device comprising: One or more antenna front - end circuits, each of the antenna front - end circuits comprising: An antenna port, the antenna port being coupled to an antenna; and A plurality of multi - mode antenna tuner circuits, each of the multi - mode antenna tuner circuits being coupled to the antenna port and comprising: A voltage input terminal, the voltage input terminal being coupled to a voltage source to receive a supply voltage; A tuner driver circuit, coupled to a signal output terminal, the signal output terminal being coupled to the antenna port to output a radio - frequency (RF) signal; A first set of circuits, the first set of circuits including a low - current voltage switch, which together consume a first current amount when the first set of circuits is activated to provide a supply voltage to the tuner driver circuit; A second set of circuits, the second set of circuits including a positive low - dropout LDO regulator, a negative LDO regulator, a band - gap reference circuit, a linearization circuit, and a positive charge pump, which together consume a second current amount greater than the first current amount when the second set of circuits is activated to provide a supply voltage to the tuner driver circuit; and A main control circuit, the main control circuit being coupled to the one or more antenna front - end circuits and being configured to: Determine that at least one of the plurality of multi - mode antenna tuner circuits in at least one of the one or more antenna front - end circuits can operate in a low - current mode; Provide an instruction indicating a low current mode, such that the at least one multimode antenna tuner circuit activates the first set of circuits and deactivates the second set of circuits; Determine that at least another multimode antenna tuner circuit among the plurality of multimode antenna tuner circuits in the at least one antenna front-end circuit of the one or more antenna front-end circuits is capable of operating in a high power mode; and Provide an instruction indicating a high power mode, such that the at least another multimode antenna tuner circuit deactivates the first set of circuits and activates the second set of circuits.

14. The wireless communication device according to claim 13, wherein the main control circuit is further configured to determine the low current mode and the high power mode based on one or more factors selected from the group consisting of: environmental conditions, RF conditions, antenna impedance measurements, and battery conditions.

15. The wireless communication device according to claim 13, wherein each multimode antenna tuner circuit among the plurality of multimode antenna tuner circuits further comprises a control circuit, the control circuit comprising a register and being configured to: In response to receiving an instruction indicating the low current mode, set the register to a first value so that the first set of circuits is activated and the second set of circuits is deactivated; and In response to receiving an instruction indicating the high power mode, set the register to a second value different from the first value so that the first set of circuits is deactivated and the second set of circuits is activated.

16. The wireless communication device according to claim 15, the wireless communication device further comprising: A bus control circuit, the bus control circuit being coupled to the main control circuit; And One or more single-wire buses configured to couple the bus control circuit to the plurality of multimode antenna tuner circuits in each antenna front-end circuit of the one or more antenna front-end circuits, each multimode antenna tuner circuit in each antenna front-end circuit of the one or more antenna front-end circuits being identified by a unique slave identifier (USID); Wherein the bus control circuit is configured to receive instructions from the main control circuit and provide the instructions to the control circuit in at least another multimode antenna tuner circuit.

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