Memory page isolation method, memory monitoring system and computer readable storage medium

Abstract

This invention provides a memory page isolation method, comprising: obtaining memory error information, including correctable memory errors; determining, based on the memory error information, the probability of an uncorrectable error occurring in the memory page and / or its row where the correctable memory error occurred; determining, based on the memory error information, the probability of an error storm occurring in the row where the memory page is located; determining an isolation strategy based on the probability of an uncorrectable error and the probability of an error storm; and applying the isolation strategy to the memory page and / or its row. This invention also provides a memory monitoring system. By collecting memory error verification information and more accurate CE (Error Detection) counts, this invention analyzes and predicts the probability of future UE (User Error Detection) and a large number of CEs occurring in the pages and rows to which the CEs belong, as well as the correlation between CE row errors and error storms. Based on the total number of isolateable pages and the probability of risk, strategies are flexibly set, ultimately reducing overall system downtime and performance impact.

Description

Technical Field

[0001] This invention relates generally to the field of computers, and more particularly to memory page isolation methods, memory monitoring systems, and computer-readable storage media. Background Technology

[0002] Memory errors are the most common type of error in hardware systems, significantly impacting system reliability, availability, and performance. Memory errors typically include uncorrectable memory errors (UE) and correctable errors (CE). Uncorrectable memory errors (UE) usually lead to system crashes, while correctable error (CE) storms can affect performance and even cause system freezes. Typically, memory errors exhibit spatial and temporal locality, meaning a large number of errors occur in specific memory regions within a short period. Therefore, memory page isolation technology was developed. When the characteristics of a memory error reach a threshold, the operating system (OS) calls an interface to copy the contents of the page to a new physical page frame and updates the virtual page to physical page frame mapping table. The goal is to isolate the faulty page and prevent further memory errors. Traditional Linux and Windows page isolation strategies are based on a threshold for correctable errors (CE) over a certain period, but this strategy has two drawbacks. First, while it can avoid correctable errors, it is difficult to avoid the performance impact of uncorrectable errors (UE) and correctable error (CE) storms. Second, due to the error suppression mechanisms of the CPU and OS, the number of correctable errors collected by the OS is sometimes far less than the actual number of correctable errors, thus significantly reducing the effectiveness of page isolation.

[0003] Furthermore, existing operating system handling methods lack predictability for uncorrectable errors. For example, some studies have found that Linux's default page isolation policy can prevent less than 6% of UEs from making mistakes. At the same time, the number of suppressed CEs also lacks predictability for CE storms.

[0004] The content in the background section is merely technology known to the public and does not necessarily represent existing technology in this field. Summary of the Invention

[0005] In view of at least one deficiency of the prior art, the present invention provides a memory page isolation method, comprising:

[0006] Obtain information about memory errors, including correctable memory errors;

[0007] Based on the information about the memory error, determine the likelihood that an uncorrectable error has occurred in the memory page and / or row where the correctable memory error occurred;

[0008] Based on the information about the memory error, determine the likelihood of an error storm occurring in the row containing the memory page;

[0009] Based on the probability of uncorrectable errors occurring and the probability of error storms occurring, an isolation strategy is determined; and

[0010] Apply the isolation policy to the memory page and / or the row it belongs to.

[0011] According to one aspect of the present invention, the step of obtaining memory error information includes: obtaining a correctable memory error log through an EDAC driver; the memory error information includes one or more of the following: the physical location of the correctable memory error, error bit information of the correctable memory error, and the number of correctable memory errors.

[0012] According to one aspect of the invention, the step of determining the likelihood of an uncorrectable error occurring includes:

[0013] Based on whether the memory page has an uncorrectable error pattern, the probability of an uncorrectable error occurring in the memory page is determined; and

[0014] When the probability of an uncorrectable error occurring in the memory page exceeds a first threshold, the probability of an uncorrectable error occurring in the row is determined based on all error address information and error bit information of correctable errors in the row.

[0015] According to one aspect of the invention, the step of determining the likelihood of an error storm occurring includes:

[0016] Determine the number of addresses in the memory page that are faulty;

[0017] When the number exceeds the second threshold, the probability of an error storm occurring in the row containing the memory page is determined.

[0018] According to one aspect of the invention, the step of determining the likelihood of an error storm includes: determining the correlation between a correctable memory error in the row containing the memory page and the error storm.

[0019] According to one aspect of the invention, the isolation strategy includes:

[0020] The memory page is not isolated when the probability of an uncorrectable error occurring in the memory page is lower than a first threshold and the number of such errors does not exceed a second threshold.

[0021] When the probability of an uncorrectable error occurring in the memory page is higher than a first threshold or the number exceeds a second threshold, it is determined whether to isolate the memory page based on the probability of an uncorrectable error and error storm occurring in the row and the number of redundant memory pages that are not isolated in the row.

[0022] According to one aspect of the invention, the step of determining whether to isolate the memory page includes:

[0023] When the number of redundant memory pages exceeds a third threshold, it is determined that the memory pages should be isolated.

[0024] When the number of redundant memory pages is lower than the third threshold, it is determined that the memory pages will not be isolated.

[0025] According to one aspect of the present invention, the step of determining the isolation strategy further includes: determining whether to perform soft isolation or hard isolation on the memory page and / or the row in which it is located;

[0026] The memory page isolation method further includes dynamically adjusting the third threshold based on the number of redundant memory pages.

[0027] The present invention also provides a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement the memory page isolation method described above.

[0028] The present invention also provides a memory monitoring system, comprising:

[0029] A memory error monitoring unit is configured to acquire memory error information in real time, including correctable memory errors.

[0030] The memory page risk assessment unit communicates with the memory error monitoring unit to receive the information about the acquired memory errors, and is configured to determine the possibility of an uncorrectable error or error storm occurring in a memory page where a correctable memory error has occurred based on the memory error information.

[0031] A memory row risk prediction unit communicates with the memory error monitoring unit to receive information about acquired memory errors, and is configured to determine, based on the memory error information, the likelihood of an uncorrectable error or error storm occurring in the row containing the memory page; and

[0032] The resource management unit communicates with the memory page risk assessment unit and the memory row risk prediction unit, and determines whether to isolate the memory page based on the probability of an uncorrectable error or error storm occurring in the memory page, the probability of an uncorrectable error or error storm occurring in the row, and the number of unisolated redundant memory pages.

[0033] According to one aspect of the present invention, the memory error monitoring unit is configured to: obtain a correctable memory error log via an EDAC driver; the memory error information includes one or more of the following: the physical location of the correctable memory error, error bit information of the correctable memory error, and the number of correctable memory errors.

[0034] According to one aspect of the present invention, the memory page risk assessment unit is configured to: determine the probability of an uncorrectable error occurring in the memory page based on whether the memory page has an uncorrectable error mode; determine the number of erroneous addresses in the memory page; and determine the probability of an error storm occurring in the memory page.

[0035] The memory row risk prediction unit is configured to: determine the probability of an uncorrectable error occurring in the row based on all error address information and error bit information of correctable errors; determine the number of error addresses in the memory page; and when the number exceeds a second threshold, determine the probability of an error storm occurring in the row.

[0036] According to one aspect of the invention, the resource management unit is configured to:

[0037] The memory page is not isolated when the probability of an uncorrectable error occurring in the memory page is lower than a first threshold and the number of such errors does not exceed a second threshold.

[0038] When the probability of an uncorrectable error occurring in the memory page is higher than a first threshold or the number exceeds a second threshold, it is determined whether to isolate the memory page based on the probability of an uncorrectable error and error storm occurring in the row and whether the number of unisolated redundant memory pages in the row exceeds a third threshold.

[0039] According to one aspect of the invention, the isolation includes soft isolation and hard isolation; wherein the resource management unit is configured to dynamically adjust the third threshold based on the number of redundant memory pages.

[0040] This solution analyzes and predicts the probability of future User Error Detection (UE) and a large number of CEs by collecting memory error verification information and more accurate CE counts. It also examines the correlation between CE row errors and error storms, attempting to isolate as few pages as possible while reducing the risk of UE and CE storms. By flexibly setting strategies based on the total number of isolateable pages and the probability of risk occurrence, the solution ultimately reduces overall system downtime and performance impact.

[0041] This solution obtains more accurate ECC error information and corresponding ECC error information for cache block data by collecting EDAC retry read error logs. Combined with memory domain knowledge, it more accurately identifies and removes memory pages that are prone to causing UE and CE storms. It flexibly sets strategies based on the total number of isolateable pages and the probability of risk, so as to isolate as few memory pages as possible while reducing the risk of uncorrectable errors and error storms, and ultimately reducing the probability of node downtime and performance impact. Attached Figure Description

[0042] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:

[0043] Figure 1 A memory page isolation method according to an embodiment of the present invention is shown;

[0044] Figure 2 A memory page isolation method according to a preferred embodiment of the present invention is shown;

[0045] Figure 3 A memory monitoring system according to an embodiment of the present invention is shown; and

[0046] Figure 4 A computer program product arranged according to at least some embodiments of the present invention is shown. Detailed Implementation

[0047] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0048] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0049] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0050] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0051] The following disclosure provides many different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0052] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0053] To improve the effectiveness of existing memory page isolation schemes, this invention provides an improved solution. Embodiments of this invention collect memory error verification information, analyze and predict the probability of uncorrectable errors and correctable error storms occurring in the pages and rows to which correctable errors belong, as well as the correlation between correctable errors and error storms. This aims to isolate as few pages as possible while reducing the risk of uncorrectable errors and correctable error storms. By flexibly setting the total number of isolateable pages and the probability of risk occurrence, the overall system downtime and performance impact are ultimately reduced.

[0054] Figure 1 A memory page isolation method 100 according to an embodiment of the present invention is shown below, with reference to... Figure 1 Detailed description.

[0055] like Figure 1 As shown, in step S101, information about memory errors is obtained, including correctable memory errors. For example, a log of correctable memory errors can be collected using an EDAC (error detection and correction driver). The EDAC driver can not only parse the microscopic location information of correctable memory errors, but also read more accurate information about the number of correctable memory errors and which bits in the memory data corresponding to the cache block were detected as faulty by ECC.

[0056] The memory error information obtained in step S101 may include one or more of the following: the physical location of the correctable memory error, the error bit information of the correctable memory error, and the number of correctable memory errors.

[0057] Memory modules typically consist of two ranks, each containing multiple DRAM (Dynamic Random Access Memory) chips, and each DRAM chip containing multiple banks. Each bank is a 2D array of basic cells, indexed by row and column. Basic cells in the same row are connected by word lines, while basic cells in the same column share a set of bit lines. Memory pages are typically 4KB in size. The operating system (OS) manages a contiguous 4KB logical address space, while the corresponding physical page frames are distributed across contiguous areas in the same row on multiple different DRAM chips. Cache blocks are 64 bytes in size. The memory storage block corresponding to a cache block is the basic unit of memory access. A 4KB memory page consists of 64 cache blocks, and multiple cache blocks are located in contiguous areas in the same row on the same DRAM chip. Typically, a memory row can store portions of dozens of memory page frames. ECC information indicates which bits of a cache block's data are corrupted.

[0058] According to one embodiment of the present invention, the physical locations where memory errors can be corrected include: socket (processor), IMC (memory controller), channel, slot, block, library, group, row, column, etc.; the error bit information of the memory errors that can be corrected includes: which DRAM chip is faulty, which burst is faulty, which DQ (data queue) is faulty, and which bits are faulty; the number of memory errors that can be corrected is, for example, the number of errors counted in registers, which is usually greater than the number of error events sent by the CPU to the operating system.

[0059] In step S102, based on the information about the memory error, the likelihood of an uncorrectable error occurring in the memory page and / or row where the correctable memory error occurred is determined.

[0060] As described above, the memory error information obtained in step S101 may include the physical location of the memory error, based on which the memory page where the correctable memory error occurred and the memory row (also referred to as the "row" in this application) where the memory page is located can be determined.

[0061] According to one embodiment of the present invention, the probability of an uncorrectable error occurring in the memory page can be determined based on whether the memory page has an uncorrectable error pattern. Typically, error checking and correction (ECC) techniques can correct some error patterns, thereby preventing further uncorrectable errors. However, error patterns that ECC techniques cannot fully correct may lead to uncorrectable errors in the future. In this invention, the probability of an uncorrectable error occurring in the memory page can be determined based on the presence and number of uncorrectable error patterns. Furthermore, the probability of such an uncorrectable error occurring can be determined or predicted using a trained neural network.

[0062] Furthermore, when the probability of an uncorrectable error occurring in a memory page exceeds a first threshold, the probability of an uncorrectable error occurring in that row is determined based on all error address information and correctable error bit information within that row. If uncorrectable errors occur simultaneously in multiple memory pages within the same row, a specific combination of the faulty bits may lead to an uncorrectable error. For example, if bits 2 and 18 from DRAM chip 1 both err simultaneously, the ECC cannot correct the error, resulting in an uncorrectable error and system crash.

[0063] In step S103, based on the memory error information, the likelihood of an error storm occurring in the row containing the memory page is determined.

[0064] In this invention, an error storm refers to a situation where a large number of correctable errors are generated within a short period of time. For example, 5000 correctable errors may occur within one second. This invention is not limited to a specific number; the number can be 500, 1000, 2000, 3000, 4000, 5000, 8000, 10000, or even higher, and can be set according to specific circumstances and scenarios. When an error storm occurs, the CPU will retry memory accesses, and the operating system needs to handle a large number of exceptions, leading to excessive system load, severely impacting the performance of user processes, and even causing system crashes. Although both the CPU and the operating system will employ error suppression mechanisms, the impact is still significant, and the operating system can only record information about a small number of correctable errors.

[0065] According to a preferred embodiment of the present invention, the likelihood of an error storm occurring is determined by the following method:

[0066] Determine the number of addresses in the memory page that are faulty;

[0067] When the number exceeds a second threshold, the probability of an error storm occurring in the row containing the memory page is determined. The probability of such an error storm can be determined or predicted using a trained neural network.

[0068] In step S104, an isolation strategy is determined based on the probability of uncorrectable errors and the probability of error storms. By using error information from the logs of correctable memory errors, the probability of uncorrectable errors and error storms is predicted, and an isolation strategy is determined. This allows for more accurate identification and removal of memory pages that are prone to causing uncorrectable errors and error storms. The strategy is flexibly set based on the total number of isolateable pages and the probability of their occurrence, aiming to isolate as few memory pages as possible while reducing the risk of uncorrectable errors and error storms, ultimately reducing the probability of node downtime and performance impact.

[0069] In step S105, the isolation policy is applied to the memory page and / or the row it belongs to.

[0070] The above embodiments of the present invention can be implemented in an operating system and can reuse the operating system's real-time monitoring and memory page isolation interfaces.

[0071] Figure 2 A memory page isolation method 200 according to a preferred embodiment of the present invention is shown below, with reference to... Figure 2 Detailed description.

[0072] In step S201, information about a memory error is obtained. This is essentially the same as step S101 in method 100 described above.

[0073] In step S202, the probability of an uncorrectable error occurring in the memory page is determined based on whether the memory page has an uncorrectable error pattern. For example, the probability of an uncorrectable error occurring in the memory page can be determined based on whether the pattern of the error information in the log is an error pattern or type that ECC can correct. This probability can be a specific probability value between 0 and 100%, or it can be a binary value of 0 or 1. For example, the probability is 0 when there is no ECC-uncorrectable error, and 1 otherwise. These are all within the scope of the present invention. If an uncorrectable error is likely, proceed to step S203; otherwise, proceed to step S204.

[0074] In step S203, the probability of an uncorrectable error occurring in the memory row containing the page is determined. For example, when the probability of an uncorrectable error occurring in the memory page exceeds a first threshold, the probability of an uncorrectable error occurring in the row is determined based on all error address information and correctable error bit information in the row. For example, when bits 2 and 18 from DRAM chip 1 are simultaneously faulty, the ECC cannot correct the error, leading to an uncorrectable error. A list of combinations of error bits that the ECC cannot correct can be preset. In step S203, multiple faulty bits are compared with this preset list of combinations to confirm whether there are combinations that would lead to an uncorrectable error. Preferably, the specific probability can be determined based on the quantity. Alternatively, binary values ​​of 0 and 1 can be set. Then, proceed to step S206.

[0075] In step S204, the number of addresses with errors in the memory page is determined, and it is determined whether the number exceeds a second threshold. If the number exceeds the second threshold, proceed to step S205; otherwise, proceed to step S210.

[0076] In step S205, when the number exceeds a second threshold, the probability of an error storm occurring in the row containing the memory page is determined. Preferably, in step S205, the correlation between correctable memory errors in the row containing the memory page and the error storm can also be determined. Then, the process proceeds to step S206.

[0077] In step S206, based on the number of unisolated redundant memory pages in the row, it is determined whether to isolate the memory page. According to a preferred embodiment of the present invention, when the number of redundant memory pages exceeds a third threshold, it is determined that the memory page should be isolated, i.e., soft isolation, and the process proceeds to step S207; when the number of redundant memory pages is less than the third threshold, it is determined that the memory page should not be isolated, and the process proceeds to step S210.

[0078] In this invention, the third threshold can be dynamically adjusted, for example, based on the number of redundant memory pages. Generally, when there are many redundant pages, the third threshold can be appropriately lowered; when there are few redundant pages, the third threshold can be increased.

[0079] In step S207, the memory pages are isolated, i.e., softly isolated. Then proceed to step S208.

[0080] In step S208, it is determined whether hard isolation of the memory page is necessary. If so, proceed to step S209 to perform hard isolation of the memory page; otherwise, proceed to step S210, and the method ends. Soft isolation will be lost after a system restart, while hard page isolation requires permanent storage of the isolated page and isolates it only when the system restarts, permanently isolating the failed physical page.

[0081] In the above embodiments, not only are the error characteristics of pages, uncorrectable errors, and the correlation with error storms considered, but the probability of uncorrectable errors and error storms is also predicted for memory rows with multiple (e.g., 128) cache blocks corresponding to physical storage blocks. By combining page and row-level error information to set strategies, the risk of uncorrectable errors and error storms is reduced.

[0082] The present invention also provides a memory monitoring system 300, such as Figure 3 As shown below, please refer to... Figure 3 Detailed description.

[0083] like Figure 3 As shown, the memory monitoring system 300 includes a memory error monitoring unit 301, a memory page risk assessment unit 303, a memory row risk prediction unit 305, and a resource management unit 307. The memory error monitoring unit 301 is configured to acquire memory error information in real time, including correctable memory errors. The memory error monitoring unit 301 is a real-time monitoring module that collects correctable memory error information in real time and can simultaneously save this information to an offline database or storage device.

[0084] The memory page risk assessment unit 303 communicates with the memory error monitoring unit 301 to receive the information about the acquired memory error, and is configured to determine the possibility of an uncorrectable error or error storm occurring in the memory page where a correctable memory error has occurred based on the memory error information.

[0085] The memory row risk prediction unit 305 communicates with the memory error monitoring unit 301 to receive the information about the acquired memory error, and is configured to determine the possibility of an uncorrectable error or error storm occurring in the row where the memory page is located based on the memory error information.

[0086] The memory page risk assessment unit 303 and the memory row risk prediction unit 305 can each include a neural network, which predicts the probability of uncorrectable errors or error storms occurring on memory pages and in their respective rows, based on information about correctable memory errors. The neural networks of the memory page risk assessment unit 303 and the memory row risk prediction unit 305 can be trained in advance using actual memory errors and labeled data. The trained neural networks are then used for memory page risk assessment and memory row risk prediction.

[0087] Resource management unit 307 communicates with memory page risk assessment unit 303 and memory row risk prediction unit 305, and determines whether to isolate the memory page based on the probability of an uncorrectable error or error storm occurring in the memory page, the probability of an uncorrectable error or error storm occurring in the row it belongs to, and the number of unisolated redundant memory pages. The resource management module decides whether to isolate the page based on the remaining isolable redundant memory pages and the probability of risk occurrence. Generally, the standard can be appropriately relaxed when there are many redundant pages, and the conditions are relatively strict when there are few redundant pages.

[0088] According to one embodiment of the present invention, the memory error monitoring unit 301 is configured to obtain a correctable memory error log through an EDAC driver; the memory error information includes one or more of the following: the physical location of the correctable memory error, the error bit information of the correctable memory error, and the number of correctable memory errors.

[0089] According to one embodiment of the present invention, the memory page risk assessment unit 303 is configured to: determine the probability of an uncorrectable error occurring in the memory page based on whether the memory page has an uncorrectable error mode; determine the number of erroneous addresses in the memory page; and determine the probability of an error storm occurring in the memory page.

[0090] The memory row risk prediction unit 305 is configured to: determine the probability of an uncorrectable error occurring in the row based on all error address information and error bit information of correctable errors; determine the number of erroneous addresses in the memory page; and when the number exceeds a second threshold, determine the probability of an error storm occurring in the row.

[0091] According to a preferred embodiment of the present invention, the resource management unit 307 is configured to: not isolate the memory page when the probability of an uncorrectable error occurring in the memory page is lower than a first threshold and the number does not exceed a second threshold; and determine whether to isolate the memory page when the probability of an uncorrectable error occurring in the memory page is higher than the first threshold or the number exceeds the second threshold, based on the probability of an uncorrectable error and error storm occurring in the row and whether the number of unisolated redundant memory pages in the row exceeds a third threshold.

[0092] According to a preferred embodiment of the present invention, the isolation includes soft isolation and hard isolation; wherein the resource management unit is configured to dynamically adjust the third threshold based on the number of redundant memory pages.

[0093] Figure 4 This is a block diagram of a computer program product 400 arranged according to at least some embodiments of the present invention. The signal carrying medium 402 may be implemented as or include a computer-readable medium 406, a computer-recordable medium 408, a computer communication medium 410, or a combination thereof, storing configurable processing units to execute all or some of the programming instructions 404 of the previously described process. These instructions may include, for example, one or more executable instructions for causing one or more processors to perform the following processes: obtaining information about a memory error, including a correctable memory error; determining, based on the memory error information, the probability of an uncorrectable error occurring in the memory page and / or row containing the correctable memory error; determining, based on the memory error information, the probability of an error storm occurring in the row containing the memory page; determining an isolation strategy based on the probability of an uncorrectable error and the probability of an error storm; and applying the isolation strategy to the memory page and / or row.

[0094] The technical solutions according to various embodiments of the present invention have been described above. Among them, detailed information on memory errors is collected by the EDAC driver to analyze whether memory pages are likely to experience uncorrectable errors or error storms, and to predict the probability of uncorrectable errors and error storms occurring in the row to which the memory page belongs. Simultaneously, the embodiments of the present invention creatively combine page and row fault characteristics for page isolation, which can effectively isolate memory pages that may experience uncorrectable errors and isolate consecutive pages that may experience a large number of errors, thereby reducing the probability of system-wide error storms and ultimately achieving the goal of improving the overall memory reliability of the server.

[0095] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A memory page isolation method, comprising: Obtain information about memory errors, including correctable memory errors; Based on the information about the memory error, determine the likelihood that an uncorrectable error has occurred in the memory page and / or row where the correctable memory error occurred; Based on the information about the memory error, determine the likelihood of an error storm occurring in the row containing the memory page; Based on the probability of uncorrectable errors occurring and the probability of error storms occurring, an isolation strategy is determined; and Apply the isolation policy to the memory page and / or the row it belongs to; The isolation strategy mentioned above includes: The memory page is not isolated when the probability of an uncorrectable error occurring in the memory page is lower than a first threshold and the number of erroneous addresses in the memory page does not exceed a second threshold. When the probability of an uncorrectable error occurring in the memory page is higher than a first threshold or the number exceeds a second threshold, it is determined whether to isolate the memory page based on the probability of an uncorrectable error and error storm occurring in the row and the number of redundant memory pages that are not isolated in the row.

2. The memory page isolation method as described in claim 1, wherein the step of obtaining memory error information includes: Obtain a correctable memory error log through the EDAC driver; The memory error information includes one or more of the following: the physical location of the correctable memory error, the error bit information of the correctable memory error, and the number of correctable memory errors.

3. The memory page isolation method as described in claim 2, wherein the step of determining the probability of an uncorrectable error occurring includes: The likelihood of an uncorrectable error occurring in the memory page is determined based on whether the memory page has an uncorrectable error pattern. and When the probability of an uncorrectable error occurring in the memory page exceeds a first threshold, the probability of an uncorrectable error occurring in the row is determined based on all error address information and error bit information of correctable errors in the row.

4. The memory page isolation method as described in claim 3, wherein the step of determining the probability of an error storm occurring includes: Determine the number of addresses in the memory page that are faulty; When the number exceeds the second threshold, the probability of an error storm occurring in the row containing the memory page is determined.

5. The memory page isolation method as described in claim 4, wherein the step of determining the probability of an error storm occurring includes: Determine the correlation between correctable memory errors in the row containing the memory page and the error storm.

6. The memory page isolation method as described in claim 4 or 5, wherein the step of determining whether to isolate the memory page includes: When the number of redundant memory pages exceeds a third threshold, it is determined that the memory pages should be isolated. When the number of redundant memory pages is lower than the third threshold, it is determined that the memory pages will not be isolated.

7. The memory page isolation method as described in claim 6, wherein the step of determining the isolation strategy further includes: Determine whether to perform soft isolation or hard isolation on the memory page and / or the row it belongs to; The memory page isolation method further includes dynamically adjusting the third threshold based on the number of redundant memory pages.

8. A computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement the memory page isolation method as described in any one of claims 1-7.

9. A memory monitoring system, comprising: A memory error monitoring unit is configured to acquire memory error information in real time, including correctable memory errors. The memory page risk assessment unit communicates with the memory error monitoring unit to receive the information about the acquired memory errors, and is configured to determine the possibility of an uncorrectable error or error storm occurring in a memory page where a correctable memory error has occurred based on the memory error information. The memory row risk prediction unit communicates with the memory error monitoring unit to receive the information about the acquired memory errors, and is configured to determine the possibility of an uncorrectable error or error storm occurring in the row where the memory page is located based on the memory error information. and The resource management unit communicates with the memory page risk assessment unit and the memory row risk prediction unit, and determines whether to isolate the memory page based on the probability of an uncorrectable error or error storm occurring in the memory page, the probability of an uncorrectable error or error storm occurring in the row, and the number of redundant memory pages that have not been isolated. The resource management unit is configured to not isolate the memory page when the probability of an uncorrectable error occurring in the memory page is lower than a first threshold and the number of erroneous addresses in the memory page does not exceed a second threshold. When the probability of an uncorrectable error occurring in the memory page is higher than a first threshold or the number exceeds a second threshold, it is determined whether to isolate the memory page based on the probability of an uncorrectable error and error storm occurring in the row and whether the number of unisolated redundant memory pages in the row exceeds a third threshold.

10. The memory monitoring system of claim 9, wherein the memory error monitoring unit is configured to: obtain a correctable memory error log via an EDAC driver; the memory error information includes: One or more of the following: the physical location of the memory error that can be corrected, the error bit information of the memory error that can be corrected, and the number of memory errors that can be corrected.

11. The memory monitoring system of claim 9 or 10, wherein the memory page risk assessment unit is configured to: determine the probability of an uncorrectable error occurring in the memory page based on whether the memory page has an uncorrectable error mode; determine the number of erroneous addresses in the memory page; and determine the probability of an error storm occurring in the memory page. The memory row risk prediction unit is configured to: determine the probability of an uncorrectable error occurring in the row based on all error address information and error bit information of correctable errors; determine the number of error addresses in the memory page; and when the number exceeds a second threshold, determine the probability of an error storm occurring in the row.

12. The memory monitoring system of claim 9, wherein the isolation includes soft isolation and hard isolation; wherein the resource management unit is configured to dynamically adjust the third threshold according to the number of redundant memory pages.

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