Memory, method of programming memory, and memory system

Abstract

The embodiments of the present disclosure disclose a memory and system, a programming method, the method comprising: applying an Nth pulse to a selected memory cell with a target state of an i-th state; after applying the Nth pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, obtaining a first sub-result and an Nth second sub-result; the first sub-result indicating whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicating whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state; determining, according to the Nth second sub-result, a memory cell that needs to be applied with an N+1th pulse among the memory cells with the target state of the i-th state; the difference between the N+1th pulse and the Nth pulse being greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the N+1th pulse to the memory cell that needs to be applied with the N+1th pulse; after applying the N+1th pulse, when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, determining that the programming of the i-th state is passed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor, and in particular, to a memory, a programming method of the memory and a memory system. BACKGROUND

[0002] Flash memories are widely used as storage media for portable electronic devices such as mobile phones, digital cameras, etc. Flash memories generally use single-transistor memory cells that allow high memory density, high reliability, and low power consumption. By programming a charge storage structure (e.g., a floating gate or a charge trap) or other physical phenomena (e.g., phase change or ferroelectric), the change of threshold voltage of the memory cell determines the data state (e.g., data value) of each memory cell.

[0003] In the related art, after a programming pulse is applied to the memory for programming, a verification operation needs to be performed. The number of times of applying the programming pulse and the number of times of performing the verification operation are important factors to determine the programming time. Therefore, how to shorten the programming time while ensuring high programming quality has become a problem to be solved. SUMMARY

[0004] Embodiments of the present disclosure provide a memory, a programming method of the memory and a memory system.

[0005] According to a first aspect of embodiments of the present disclosure, a programming method of a memory is provided, the memory comprising a plurality of memory cells to be programmed; the programming method comprising:

[0006] applying an Nth programming pulse to a selected memory cell whose target state is an i-th state; wherein i is a natural number, and N is a positive integer;

[0007] after applying the Nth programming pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, to obtain a first sub-result and an Nth second sub-result; wherein the first sub-result indicates whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicates whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state, the target threshold voltage being greater than the preset voltage;

[0008] determining, according to the Nth second sub-result, a memory cell among the memory cells whose target state is the i-th state, which needs to be applied with an N+1th programming pulse; wherein the difference between the N+1th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage;

[0009] applying an (N+1)th programming pulse to the memory cell in need of the (N+1)th programming pulse; wherein after applying the (N+1)th programming pulse, and when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, it is determined that the programming to the i-state is passed.

[0010] According to a second aspect of the embodiments of the present disclosure, a memory is provided, comprising:

[0011] a memory cell array comprising a plurality of memory cell rows;

[0012] a plurality of word lines respectively coupled to the plurality of memory cell rows; and

[0013] a peripheral circuit coupled to the plurality of word lines and configured to perform a programming operation on a selected memory cell row in the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein to perform the programming operation, the peripheral circuit is configured to perform the programming method according to the first aspect of the embodiments of the present disclosure.

[0014] According to a third aspect of the embodiments of the present disclosure, a memory system is provided, comprising:

[0015] one or more memories according to the second aspect of the embodiments of the present disclosure;

[0016] a memory controller coupled to the memory and configured to control the memory.

[0017] In the related art, when programming a single level cell (SLC), one way is to complete the programming of the SLC with one large programming pulse. However, for a single level cell with a faster programming speed, this way can cause over-programming and reduce the reliability of the programming operation. Another way is to complete the programming of the SLC by applying two programming pulses. In this way, during the second verification, all the single level cells that have not reached the target threshold voltage after applying the first programming pulse need to be verified, resulting in a longer programming time. In addition, in the related art, when programming a multi-level cell, a triple-level cell or a quad-level cell, etc., after applying each programming pulse, at least the programming verification needs to be performed on all the memory cells to which the programming pulse is applied, resulting in a longer programming time.

[0018] In the embodiments of the present disclosure, after the Nth programming pulse is applied, the storage units with threshold voltages between the preset voltage and the target threshold voltage are determined according to the first sub result and the Nth second sub result by performing the first sub verification and the Nth second sub verification. Since the difference between the N+1th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage, the storage units with threshold voltages greater than or equal to the preset voltage and less than the target threshold voltage can reach the target threshold voltage after the N+1th programming pulse is applied without over programming. Therefore, after the N+1th programming pulse is applied, the verification operation is not needed for the storage units, and when the first sub result indicates that the number of failed bits of the first sub verification is less than the first preset value, it is considered that the programming of the i state is successful. Compared with the related art, the programming method provided by the embodiments of the present disclosure reduces the number of programming verifications to be performed on the basis of ensuring reliability, and is beneficial to shorten the programming time. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a flowchart of a programming method according to an exemplary embodiment;

[0020] Figure 2 is a graph of a word line voltage change over time according to an exemplary embodiment;

[0021] Figure 3 is a threshold voltage distribution graph according to an exemplary embodiment;

[0022] Figure 4 is a flowchart of another programming method according to an exemplary embodiment;

[0023] Figure 5 is a schematic diagram of a memory according to an exemplary embodiment;

[0024] Figure 6 is a partial cross-sectional view of a memory cell array including NAND memory strings according to an exemplary embodiment;

[0025] Figure 7 is a block diagram of a memory including a memory cell array and a peripheral circuit according to an exemplary embodiment;

[0026] Figure 8 is a schematic diagram of a memory system according to an exemplary embodiment;

[0027] Figure 9a is a schematic diagram of a memory card according to an exemplary embodiment;

[0028] Figure 9bis a schematic diagram of a solid state drive according to an example embodiment. DETAILED DESCRIPTION

[0029] For the purposes of the present disclosure, technical solutions and advantages, the technical solutions of the present disclosure will be further described in detail below with reference to the drawings and examples. Although the example implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail in the following paragraphs with reference to the drawings. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting in the description of the embodiments of the present disclosure.

[0031] It can be understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" with intervening features or layers therebetween.

[0032] In the embodiments of the present disclosure, the term "A is connected with B" includes the case where A and B are connected with each other in contact with A and B, or the case where A and B are connected with each other without contact with A and B with other components interposed therebetween.

[0033] In the embodiments of the present disclosure, the terms "first", "second", and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It can be understood that "first", "second", and the like can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0034] In embodiments of the disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent that is less than the underlying or overlying structure. Further, a layer can be a region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can include multiple sub-layers. For example, an interconnect layer can include one or more conductor and contact sub-layers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing embodiments of the disclosure only and is not intended to be limiting of the disclosure.

[0036] It should be noted that the technical solutions described in the embodiments of the disclosure can be combined arbitrarily without conflict.

[0037] NAND memory belongs to a non-volatile memory device, has the advantages of large capacity and fast rewriting speed, and is suitable for storing a large amount of data. NAND memory is widely used in embedded products, such as digital cameras, MP3 memory cards, and small U disks.

[0038] In the development of NAND memory, the storage unit of the early NAND memory grain is mainly a single-level cell (Single-Level Cell, SLC), that is, one storage unit stores 1 bit of data, at this time, there are two states for each storage unit, specifically 0 and 1.

[0039] With the development of NAND memory, the storage unit of the NAND memory grain gradually evolves from a single-level storage unit to a multi-level storage unit, for example, MLC (one storage unit stores 2 bits of data, Multi-Level Cell), TLC (one storage unit stores 3 bits of data, also known as a three-level storage unit, Triple-Level Cell, TLC), or QLC (one storage unit stores 4 bits of data, also known as a four-level storage unit, Quad-Level Cell, QLC), and so on. Correspondingly, the state of the storage unit of the NAND memory grain also changes from 2 to 4, 8, or 16, etc.

[0040] The operation of a NAND memory includes three parts: an erase operation, a program (write) operation, and a read operation. Generally, the erase operation can be performed in a block unit, and the program operation and the read operation can be performed in a page unit. For the program operation of a NAND memory, the process is divided into, for example, a stress program (i.e., applying a program pulse), a program verify (PV), and a scan verify operation.

[0041] For a NAND memory, the program duration (t PROG ) is an important indicator for measuring the performance of the NAND memory. Therefore, researchers have been committed to studying how to shorten the program duration while ensuring the program quality. Generally, the number of applied program pulses, the number of program verifications, the time for each program verification, and the time for scanning the verification result are important factors for determining the program duration. If the total number of applied program pulses and / or the total number of program verifications can be reduced, the program duration can be effectively shortened.

[0042] For a single-level cell, which has an erase state (E0) and one program state (L1 state), generally, a large program pulse can be applied to program the selected single-level cell, and the programming of the selected single-level cell can be completed by applying the program pulse. Although this way of programming has a shorter program duration, for a single-level cell with a faster program speed, this way can cause over-programming, thereby reducing the reliability.

[0043] In order to obtain better program performance while ensuring better reliability, the programming of a single-level cell can also be completed by applying two program pulses. Specifically, after applying a first program pulse, the single-level cell is subjected to a first program verification, then a second program pulse is applied, and then a second program verification is performed. In this way, the programming of the single-level cell is completed by performing two "program-verify" cycles. However, this way has a longer program duration. If at least part of the second program verification can be omitted after applying the second program pulse, the program duration can be shortened.

[0044] For a MLC, which has an erase state and three program states, the highest state of the MLC is the program state with the highest target threshold voltage.

[0045] For a memory cell capable of storing more than 2 bits per memory cell, taking a triple-level memory cell (TLC) as an example, the triple-level memory cell has an erased state and 7 program states, and the 7 program states are sequentially recorded as a first program state L1, a second program state L2, a third program state L3, a fourth program state L4, a fifth program state L5, a sixth program state L6 and a seventh program state L7 in order of gradually increasing target threshold voltage. It should be emphasized that the highest state of the triple-level memory cell is the seventh program state L7.

[0046] The present disclosure provides a programming method of a memory, which is applied to programming a memory comprising a plurality of memory cells to be programmed, Figure 1 is a schematic diagram of a memory programming method according to an exemplary embodiment. As shown in Figure 1 The programming method comprises the following steps:

[0047] S100: applying an Nth programming pulse to a selected memory cell with a target state of an i state; wherein i is a natural number, and N is a positive integer;

[0048] S110: after applying the Nth programming pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, and obtaining a first sub-result and an Nth second sub-result; wherein the first sub-result indicates whether the voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicates whether the voltage of the selected memory cell is less than a target threshold voltage of the i state, the target threshold voltage being greater than the preset voltage;

[0049] S120: determining, according to the Nth second sub-result, a memory cell of the memory cell with the target state of the i state that needs to be applied with an N+1th programming pulse; wherein the difference between the N+1th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage;

[0050] S130: applying the N+1th programming pulse to the memory cell that needs to be applied with the N+1th programming pulse; wherein after applying the N+1th programming pulse, and when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, it is determined that the programming of the i state is passed.

[0051] Exemplarily, the Nth programming pulse can include an Nth programming voltage pulse or an Nth programming current pulse. The N+1th programming pulse can include an N+1th programming voltage pulse or an N+1th programming current pulse. It can be understood that the N+1th programming pulse is the next programming pulse applied after the Nth programming pulse. The first sub-verification and the Nth second sub-verification are two programming verification steps performed during a programming verification operation of the selected memory cell after the Nth programming pulse is applied and before the N+1th programming pulse is applied.

[0052] In S110, the first sub-verification and the Nth second sub-verification can be understood as two programming verification steps performed during the same programming verification operation on the selected memory cell after the Nth programming pulse is applied and before the N+1th programming pulse is applied.

[0053] For example, a selected memory cell can be programmed and programmed verified by applying programming pulses and programming verification pulses to word lines coupled to the selected memory cell. It is understood that the programming pulses may include an Nth programming pulse and an (N+1)th programming pulse, and the programming verification may include a first sub-verification and an Nth second sub-verification.

[0054] Specifically, Figure 2 This diagram illustrates the relationship between the voltage applied to the word line coupled to the gate of a selected memory cell and time. (Example:) Figure 2 As shown, at time t1, the voltage applied to the word line reaches the pass voltage V. pass At time t2, the voltage applied to the word line is the Nth programming pulse V. pgm At time t3, the voltage applied to the word line reaches the first sub-verification voltage (V). vry1 This involves performing the first sub-verification on the memory cell coupled to the word line. At time t4, the voltage applied to the word line reaches the second sub-verification voltage (V). vry2 This means performing a second sub-verification on the memory cell coupled to the word line.

[0055] Since the first sub-verification indicates that the threshold voltage of the memory cell is less than the preset voltage, the next programming operation continues for that memory cell. Specifically, at time t5, the voltage applied to the word line reaches the pass voltage; at time t6, the voltage applied to the word line reaches the (N+1)th programming pulse, and the difference between the (N+1)th programming pulse and the Nth programming pulse is the step size V. step .

[0056] In some embodiments, the storage unit may include a single-level storage unit. When N is 1, the Nth programming pulse can be understood as the first programming pulse applied to the single-level storage unit after an erase operation is performed on it.

[0057] In some embodiments, the storage unit may include multi-level storage units, such as MLC, TLC, QLC, etc., and the programming method can be applied to program the highest state of the multi-level storage units. Specifically, when the programming method is applied to program the highest state of the multi-level storage units, the Nth programming pulse can be understood as: a programming pulse applied to the selected storage unit whose target state is the highest state. The (N+1)th programming pulse can be understood as: the next programming pulse applied after applying the Nth programming pulse to the multi-level storage unit whose target state is the highest state.

[0058] It should be emphasized that, when the highest state is programmed by using the technical solution provided by the embodiments of the present disclosure, the number of times of the second sub-verification is less, and the programming time is shortened more preferably. That is, the highest state of the storage unit is programmed by using the technical solution provided by the embodiments of the present disclosure, which is a preferred embodiment.

[0059] In some embodiments, the storage unit can include a three-level storage unit or a four-level storage unit, the target programming state of the storage unit includes a lowest state, an intermediate state and a highest state, the target threshold voltage of the intermediate state is greater than the target threshold voltage of the lowest state, and the target threshold voltage of the intermediate state is less than the target threshold voltage of the highest state, and the programming method can be applied to programming the intermediate state of the three-level storage unit or the four-level storage unit.

[0060] Specifically, when the programming method is applied to programming the intermediate state of the three-level storage unit or the four-level storage unit, the Nth programming pulse can be understood as a programming pulse applied to a selected storage unit whose target state is the intermediate state. The N+1th programming pulse can be understood as the next programming pulse applied after the Nth programming pulse is applied to the multi-level storage unit whose target state is the intermediate state.

[0061] It should be noted that the method provided by the embodiments of the present disclosure can also be used to program the intermediate state or the highest state of a higher level storage unit capable of storing more than 4 bits of data for each storage unit. It can be understood that the values of the preset voltage and the target threshold voltage are different for different target states.

[0062] It should be emphasized that, when the highest state of the multi-level storage unit, the three-level storage unit or the four-level storage unit is programmed by using the method provided by the embodiments of the present disclosure, or when the intermediate state of the three-level storage unit or the four-level storage unit is programmed by using the method provided by the embodiments of the present disclosure, and the value of N is 1, the 1st programming pulse can be the 1st programming pulse applied from the erased state, or the 1st programming pulse can also be a verification start pulse (verify start loop) for starting verification of the storage unit whose target state is the i state.

[0063] Taking a three-level storage unit as an example, the three-level storage unit has 1 erased state and 7 programming states, the erased state is denoted as L0, and the programming states from the 1st state to the 7th state are denoted as L1, L2, L3, L4, L5, L6 and L7, respectively, Figure 3 A threshold voltage distribution diagram of the three-level storage unit is shown. It can be understood that the threshold voltage gradually increases from the L0 state to the L7 state.

[0064] For the programming states of L1 to L7, starting from the erased state L0, each programming state is verified in turn until all programming states are verified or a maximum programming pulse count is reached, and the programming is ended.

[0065] Table 1 shows a specific programming scheme for programming a three-level memory cell, which can include multiple programming loops, each of which includes applying a programming pulse and performing a programming verify (V). It should be noted that "V" in Table 1 is used to represent performing a programming verify, a space in Table 1 is used to represent not performing a programming loop, and "\" in Table 1 is used to represent not performing a programming verify.

[0066] For example, the programming of the memory cell to be programmed with the target state of L1 is verified starting at the 1st programming loop, and the verification of the memory cell to be programmed with the target state of L1 is ended after the 4th programming loop, i.e., the verification starting pulse of L1 is the 1st programming pulse. It can be understood that after the 4th programming loop, i.e., after the 4th programming verify pulse is applied, the first sub-result of the selected memory cell with the target state of L1 indicates that the number of failed bits of the first sub-verification is less than the first preset value, and thus, after the 5th programming pulse is applied, the programming of L1 is passed and does not need to be verified.

[0067] It should be noted that in the related art, the programming verify of the selected memory cell with the target state of L1 also needs to be performed after the 5th programming pulse is applied. The scheme provided by the embodiments of the present disclosure reduces the programming verify process after the 5th programming pulse for the programming of L1, which is beneficial to shorten the programming time.

[0068] For example, the programming of the memory cell to be programmed with the target state of L2 is not verified at the 1st programming loop, and the verification of the memory cell to be programmed with the target state of L2 is started at the 3rd programming loop and ended after the 6th programming loop, i.e., the verification starting pulse of L2 is the 3rd programming pulse. It can be understood that after the 6th programming loop, i.e., after the 6th programming verify pulse is applied, the first sub-result of the selected memory cell with the target state of L2 indicates that the number of failed bits of the first sub-verification is less than the first preset value, and thus, after the 7th programming pulse is applied, the programming of L2 is passed and does not need to be verified. The programming of L3 to L7 is similar and will not be described again.

[0069] In some embodiments, for a multi-level memory cell, at least two target states can be programmed at the same time, and in the multiple target states that are programmed at the same time, if the number of failed bits of the first sub-verification of the lowest target state among the multiple target states is less than the first preset value, the lowest target state is programmed to pass after the next programming pulse is applied, and thus, the first second sub-verification of the next target state of the lowest target state can be started.

[0070] For example, in conjunction with Table 1, during the 5th programming cycle and the 6th programming cycle, since the L2 state is the lowest target state, the L3 state is not the lowest target state, the first sub-verification is performed on the selected memory cells with the target state of L3, and the second sub-verification is not performed. During the 6th programming cycle, the number of failed bits of the first sub-verification performed on the selected memory cells with the target state of L2 is less than the first preset value, thus, during the 7th programming cycle, the 7th programming pulse is applied to the selected memory cells with the target state of L2 and needs to be applied with the programming pulse, the 7th programming pulse is applied to the selected memory cells with the target state of L3 and L4, and the first second sub-verification is started to be performed on the L3 state after the 7th programming pulse is applied.

[0071] It should be noted that the verification start pulse for starting the verification for any target state can be fixed or varied, which is not limited in the present disclosure.

[0072] Table 1

[0073]

[0074] Exemplarily, in conjunction with Figure 3 It can be known that the target threshold voltage is the voltage range of the target state. When the threshold voltage of the selected memory cell increases to the voltage range of the target state, it can be considered that the selected memory cell is programmed to the target state, and the programming of the selected memory cell is completed.

[0075] It should be emphasized that by performing the first sub-verification and the Nth second sub-verification, it can be judged whether the threshold voltage of the selected memory cell reaches two different voltages. Specifically, the first sub-verification is used to verify whether the threshold voltage of the selected memory cell reaches a preset voltage, and the Nth second sub-verification is used to verify whether the threshold voltage of the selected memory cell reaches the target threshold voltage.

[0076] The first sub-result is the verification result obtained by performing the first sub-verification on the selected memory cell after the Nth programming pulse is applied. The Nth second sub-result is the verification result obtained by performing the Nth second sub-verification on the selected memory cell after the Nth programming pulse is applied.

[0077] During the programming verification operation, the generated verification result can be stored in a page buffer. Specifically, the verification result can be stored in a specific latch in the page buffer, which is only used to temporarily store the verification result of the programming verification operation. Alternatively, the verification result can also be stored in some other latches in the page buffer, which can also be used to store programming data, or programming inhibition information, etc.

[0078] Exemplarily, the first sub-result can be used to count the number of bits or the number of memory cells whose voltage is less than the preset voltage after the Nth programming pulse is applied to the selected memory cells. According to the first sub-result, the first indication information indicating the memory cells whose threshold voltage is less than the preset voltage after the Nth programming pulse is applied can be obtained.

[0079] The Nth second sub-result can be used to count the number of bits or the number of memory cells whose programming fails after the Nth programming pulse is applied to the selected memory cells. According to the Nth second sub-result, the second indication information indicating the memory cells whose threshold voltage is greater than or equal to the target threshold voltage after the Nth programming pulse is applied can be obtained.

[0080] According to the first sub-result and the Nth second sub-result, the third indication information indicating the memory cells whose threshold voltage is greater than or equal to the preset voltage and less than the target threshold voltage after the Nth programming pulse is applied can be obtained.

[0081] Exemplarily, the first indication information, the second indication information and the third indication information can include address information used to indicate the address of the corresponding memory cell. In some embodiments, S120 includes: when the threshold voltage of the selected memory cell is less than the target threshold voltage, determining that the selected memory cell belongs to the memory cells that need to be applied with the N+1th programming pulse.

[0082] In S120, according to the Nth second sub-result, the memory cells that reach the target threshold voltage after the Nth programming pulse is applied can be determined, and these memory cells are programmed successfully (i.e., the programming of these memory cells is passed). Thus, during the process of applying the N+1th programming pulse, the programming inhibition condition can be applied to the memory cells that are programmed successfully, so as to ensure that these memory cells will not be over-programmed, and the reliability is improved.

[0083] In S120, according to the Nth second sub-result, the memory cells that do not reach the target threshold voltage after the Nth programming pulse is applied can also be determined, and these memory cells are not programmed successfully. Therefore, the second programming pulse needs to be applied to these memory cells.

[0084] Exemplarily, since the error correction code (ECC) error correction mechanism is provided, when the number of bits that fail to be programmed is within the range allowed by the ECC error correction mechanism, the ECC error correction mechanism can be used to correct at least part of the bits that fail to be programmed, so as to ensure that the data written into the memory has high correctness.

[0085] Exemplarily, the value range of the first preset value can be within the range allowed by the ECC error correction mechanism, or the value range of the first preset value can be slightly greater than the range allowed by the ECC error correction mechanism.

[0086] When the value range of the first preset value is within the range allowed by the ECC correction mechanism, the number of failed bits indicated by the first sub-verification result is within the range allowed by the ECC correction mechanism, so that the ECC correction mechanism can be used to ensure high accuracy of the programming without the need for re-executing the programming verification, and the programming can be considered as passing, thereby shortening the programming time.

[0087] When the value range of the first preset value is slightly greater than the range allowed by the ECC correction mechanism, since the difference between the N+1 programming pulse and the N programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage, for the storage cells whose threshold voltages are less than the preset voltage after the N programming pulse is applied and before the N+1 programming pulse is applied, the threshold voltages of at least some of the storage cells will increase to be greater than or equal to the target threshold voltage after the N+1 programming pulse is applied, i.e., the number of failed bits after the N programming pulse is applied is less than the first preset value, so that the number of failed bits after the N+1 programming pulse is applied is within the range allowed by the ECC correction mechanism, and the probability of passing the programming after the N+1 programming pulse is applied is high, and the programming for the i state can be considered as passing, without the need for re-executing the programming verification process, thereby shortening the programming time.

[0088] In addition, under ideal conditions, since the difference between the N+1 programming pulse and the N programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage, for the storage cells whose threshold voltages are greater than or equal to the preset voltage and less than the target threshold voltage after the N programming pulse is applied, the threshold voltages of the storage cells will increase to be greater than or equal to the target threshold voltage after the N+1 programming pulse is applied.

[0089] In actual applications, due to the influence of programming noise and other interference, after the N+1 programming pulse is applied to the storage cells whose threshold voltages are greater than or equal to the preset voltage and less than the target threshold voltage after the N programming pulse is applied, there can still be a very small number of storage cells whose threshold voltages are less than the target threshold voltage.

[0090] In summary, for the storage cells whose threshold voltages are greater than or equal to the preset voltage and less than the target threshold voltage after the N programming pulse is applied, the probability of successfully programming after the N+1 programming pulse is applied is high, so that the result of the programming verification performed on the storage cells after the N+1 programming pulse is applied is highly likely to be successful programming, and thus the verification on the storage cells is not needed, the number of storage cells that need to be verified after the N+1 programming pulse is applied is reduced, the programming verification time is shortened, and the programming time is shortened.

[0091] In the embodiments of the present disclosure, by establishing the step between the (N+1)th programming pulse and the Nth programming pulse (i.e. the difference between the second programming pulse and the first programming pulse), and the above-mentioned relationship between the target threshold voltage and the preset voltage, at least most of the selected storage cells whose threshold voltages are originally between the preset voltage and the target threshold voltage can be programmed by applying the (N+1)th programming pulse to move their threshold voltages to the target threshold voltage, so as to complete the programming of these storage cells.

[0092] It should be noted that when the difference between the (N+1)th programming pulse and the Nth programming pulse is greater than the difference between the target threshold voltage and the preset voltage, the probability of over-programming the selected storage cells can be reduced by reasonably setting the value of the (N+1)th programming pulse.

[0093] In the embodiments of the present disclosure, after applying the Nth programming pulse, the two verification steps of the first sub-verification and the Nth second sub-verification are performed, and then the selected storage cells whose threshold voltages are between the preset voltage and the target threshold voltage can be determined according to the first sub-result and the Nth second sub-result. Since the difference between the (N+1)th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage, the probability that the selected storage cells whose threshold voltages are greater than or equal to the preset voltage and less than the target threshold voltage reach the target threshold voltage after applying the (N+1)th programming pulse is relatively high, and the probability of over-programming is relatively low. Therefore, after applying the (N+1)th programming pulse, the verification operation on these storage cells is not required, and when the first sub-result indicates that the number of failed bits of the first sub-verification is less than the first preset value, it can be determined that the programming of the i-state is successful. Compared with the related art, the programming method provided by the embodiments of the present disclosure reduces the number of programming verifications to be performed on the basis of ensuring reliability, which is conducive to shortening the programming time.

[0094] In some embodiments, S110 comprises:

[0095] After applying the Nth programming pulse, a first sub-verification voltage is applied to the word line coupled to the selected storage cells to perform a first sub-verification on the selected storage cells, and a first sub-result is obtained;

[0096] After applying the Nth programming pulse, a second sub-verification voltage is applied to the word line coupled to the selected storage cells to perform an Nth second sub-verification on the selected storage cells, and an Nth second sub-result is obtained; wherein the second sub-verification voltage is greater than the first sub-verification voltage.

[0097] Exemplarily, the first sub-verification can be performed on the selected memory cell first, and the Nth second sub-verification can be performed on the selected memory cell subsequently. Specifically, S110 can include: performing the first sub-verification on the selected memory cell to obtain a first sub-result; determining, according to the first sub-result, a memory cell that needs to perform the Nth second sub-verification; and performing the Nth second sub-verification on the memory cell that needs to perform the Nth second sub-verification to obtain an Nth second sub-result.

[0098] For example, for the memory cell that fails the first sub-verification (i.e., the memory cell with the threshold voltage less than the preset voltage), since the preset voltage is less than the target threshold voltage, the threshold voltage of the memory cell that fails the first sub-verification is less than the target threshold voltage, and thus the Nth second sub-verification is not needed for the memory cell.

[0099] For the memory cell that passes the first sub-verification (i.e., the memory cell with the threshold voltage greater than or equal to the preset voltage), since the preset voltage is less than the target threshold voltage, the size relationship between the threshold voltage of the memory cell that passes the first sub-verification and the target threshold voltage needs to be further verified, i.e., the Nth second sub-verification is needed for the memory cell.

[0100] Compared with performing the first sub-verification and the Nth second sub-verification on all the selected memory cells with the target state being the i state after the Nth programming pulse is applied, the technical solution provided by the embodiment of the present disclosure can reduce the number of selected memory cells that need to perform the Nth second sub-verification, and thus reduce the verification time, which is conducive to shortening the programming time.

[0101] In some embodiments, the Nth second sub-verification can also be performed on the selected memory cell first, and the memory cell that needs to perform the first sub-verification can be determined according to the result of the Nth second sub-verification. Specifically, S110 can include: performing the Nth second sub-verification on the selected memory cell to obtain an Nth second sub-result; determining, according to the Nth second sub-result, a memory cell that needs to perform the first sub-verification; and performing the first sub-verification on the memory cell that needs to perform the first sub-verification to obtain a first sub-result.

[0102] For example, for the memory cell that passes the Nth second sub-verification (i.e., the memory cell with the threshold voltage greater than or equal to the target threshold voltage), since the target threshold voltage is greater than the preset voltage, the threshold voltage of the memory cell that passes the Nth second sub-verification is greater than the preset voltage, and thus the first sub-verification is not needed for the memory cell.

[0103] For the memory cell that fails the Nth second sub-verification (i.e., the memory cell with the threshold voltage less than the target threshold voltage), since the target threshold voltage is greater than the preset voltage, the size relationship between the voltage of the memory cell that fails the Nth second sub-verification and the preset voltage needs to be further verified, i.e., the first sub-verification is needed for the memory cell.

[0104] Compared with performing the first sub-verification and the Nth second sub-verification on all selected memory cells in the i-th target state after applying the Nth programming pulse, the technical solution provided by the embodiment of the present disclosure can reduce the number of memory cells subjected to the first sub-verification, and further reduce the verification time, which is conducive to shortening the programming time.

[0105] Since the scheme of performing the N+1th programming verification on all memory cells subjected to the N+1th programming pulse in the related art needs to spend a long time and provide a large power to establish the programming verification condition after applying the programming pulse, although the scheme provided by the embodiment of the present disclosure needs an additional time for setting the word line, the scheme provided by the embodiment of the present disclosure can reduce the number of second verifications by flexibly setting the start time of the first second verification, and further reduce the time for setting the word line, so that the time required is shorter and the power required is lower.

[0106] Further, when the technical solution provided by the embodiment of the present disclosure is used for programming the single-level memory cell, only the voltage of the selected word line coupled to the selected memory cell needs to be changed in the process of the first programming verification (i.e., performing the first sub-verification and the first second verification), which can further shorten the time and reduce the power.

[0107] In some embodiments, S110 comprises:

[0108] After applying the Nth programming pulse, a first pre-charge voltage is applied to the bit line coupled to the selected memory cell, and the first sub-verification is performed on the selected memory cell based on a preset sensing time to obtain a first sub-result.

[0109] After applying the Nth programming pulse, a second pre-charge voltage is applied to the bit line coupled to the selected memory cell, and the Nth second sub-verification is performed on the selected memory cell based on a preset sensing time to obtain an Nth second sub-result; wherein the second pre-charge voltage is greater than the first pre-charge voltage.

[0110] It should be emphasized that when the first sub-verification and the Nth second sub-verification are performed on the selected memory cell by applying different pre-charge voltages to the bit line coupled to the selected memory cell, the sensing time is the same. In some embodiments, S110 comprises:

[0111] After applying the Nth programming pulse, the first sub-verification is performed on the selected memory cell based on a first sensing time to obtain a first sub-result.

[0112] After the Nth programming pulse is applied, the selected memory cell is subjected to the Nth second sub-verification based on a second sensing duration, and an Nth second sub-result is obtained; the second sensing duration is greater than the first sensing duration.

[0113] Exemplarily, when performing the programming verification, generally includes: pre-charging the bit line coupled to the selected memory cell, a sensing stage, and a readout stage. After the pre-charging voltage is applied to the bit line coupled to the selected memory cell to pre-charge the bit line, the bit line voltage or the current flowing through the bit line is sensed after the sensing duration, and then the programming verification of the memory cell can be performed according to the sensed bit line voltage or the bit line current.

[0114] In some embodiments, the bit line voltage or the bit line current can be sensed by a sensing circuit in the peripheral circuit. The sensing circuit can be arranged in a page buffer of the peripheral circuit.

[0115] It can be understood that the preset sensing duration, the first sensing duration, and the second sensing duration are all sensing durations. The duration of the sensing stage is the sensing duration. After pre-charging, the bit line is charged to a preset level. After stopping pre-charging, in the sensing stage, the level of the bit line changes depending on the threshold voltage of the memory cell coupled to the bit line. After the sensing duration, i.e., at the end of the sensing stage, the readout is performed based on the bit line potential level at the current time to determine the threshold voltage of the memory cell coupled to the bit line, and then the programming verification of the memory cell is performed according to the determined threshold voltage of the memory cell.

[0116] In the embodiments of the present disclosure, by performing the first sub-verification on the selected memory cell based on the shorter first sensing duration and performing the second sub-verification on the selected memory cell based on the longer second sensing duration, compared with the scheme of applying different word line voltages or different bit line pre-charging voltages, the different voltages do not need to be set for the word line and / or the bit line coupled to the selected memory cell, and the programming verification duration can be effectively shortened, which is more conducive to saving the programming duration.

[0117] However, in the scheme provided by the embodiments of the present disclosure, the difference between the bit line voltage sensed based on the first sensing duration and the bit line voltage sensed based on the second sensing duration can be small, and therefore, in order to increase the difference between the bit line voltage sensed based on the first sensing duration and the bit line voltage sensed based on the second sensing duration, a larger Nth programming pulse needs to be provided, and the step between the Nth+1 programming pulse and the Nth programming pulse is smaller.

[0118] In some embodiments, the programming method further includes:

[0119] determine, according to the first sub-result, the memory cells that need to be verified after the application of the N+1th programming pulse;

[0120] perform the N+1th second sub-verification on the memory cells that need to be verified after the application of the N+1th programming pulse, and obtain an N+1th second sub-result.

[0121] Exemplarily, the determining, according to the first sub-result, of the memory cells that need to be verified after the application of the N+1th programming pulse comprises:

[0122] when the threshold voltage of the selected memory cell is less than the preset voltage, determining that the selected memory cell belongs to the memory cells that need to be verified after the application of the N+1th programming pulse;

[0123] when the threshold voltage of the selected memory cell is greater than or equal to the preset voltage, determining that the selected memory cell does not belong to the memory cells that need to be verified after the application of the N+1th programming pulse.

[0124] According to the first sub-result, the memory cells that do not reach the preset voltage after the application of the Nth programming pulse can be determined. After the application of the N+1th programming pulse, at least some of the memory cells (for example, the memory cells whose voltage is slightly less than the preset voltage after the application of the Nth programming pulse) may have their threshold voltages reach the target threshold voltage, and at least some other memory cells may still have their threshold voltages less than the target threshold voltage. Therefore, after the application of the N+1th programming pulse and when the first sub-result indicates that the number of failed bits of the first sub-verification is greater than or equal to the first preset value, the programming verification needs to be performed on the memory cells that do not reach the preset voltage after the application of the Nth programming pulse, and it can be determined that these memory cells belong to the memory cells that need to be verified after the application of the N+1th programming pulse.

[0125] According to the first sub-result, the memory cells whose threshold voltages reach the preset voltage after the application of the Nth programming pulse can be determined. Since the difference between the N+1th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage, the threshold voltages of these memory cells will reach the target threshold voltage with a high probability after the application of the N+1th programming pulse. Thus, without performing programming verification on these memory cells again, it can be determined that these memory cells belong to the memory cells that do not need to be verified after the application of the N+1th programming pulse.

[0126] Compared with performing the program verify process on all the memory cells to which the N+1th program pulse is applied in the related art, the scheme provided in the embodiments of the present disclosure can predict, according to the first sub-result obtained after the Nth program pulse is applied, the program verify pass of the memory cells to which the Nth program pulse is applied and whose threshold voltage reaches the preset voltage after the N+1th program pulse is applied, so as to reduce the number of memory cells that need to be verified after the N+1th program pulse is applied on the basis of ensuring program reliability, and to further shorten the program time.

[0127] In some embodiments, the program method further includes;

[0128] According to the first sub-result, a first sub-verification failure bit count is counted to obtain a first count result.

[0129] S140 includes: after the N+1th program pulse is applied, and when the first count result is less than a first preset value, determining that the i-state program passes.

[0130] When the first count result is greater than or equal to the first preset value, after the N+1th program pulse is applied, the memory cells to which the N+1th program pulse is applied and which need to be verified are subjected to the N+1th second sub-verification to obtain an N+1th second sub-result.

[0131] The first count result includes: the number of bits whose threshold voltage is less than the preset voltage after the memory is programmed by the Nth program pulse.

[0132] Exemplarily, binary coding can be used to represent whether the threshold voltage of the memory cell is less than the preset voltage, for example, 0 can be used to represent that the threshold voltage of the memory cell is less than the preset voltage, and 1 can be used to represent that the threshold voltage of the memory cell is greater than or equal to the preset voltage; or 1 can be used to represent that the threshold voltage of the memory cell is less than the preset voltage, and 0 can be used to represent that the threshold voltage of the memory cell is greater than or equal to the preset voltage. In implementation, a person skilled in the art can select a suitable way to represent whether the memory cell is programmed to pass according to the actual situation, and the embodiments of the present disclosure are not limited thereto.

[0133] In some embodiments, during the application of the N+1th program pulse, the step of counting the first sub-verification failure bit count according to the first sub-result to obtain the first count result is performed.

[0134] After each programming verification operation, it is usually required to count the result of the current verification operation, i.e., to count the number of storage units that fail to pass the verification, i.e., to perform fail bit count (FBC). In the related art, in terms of timing, the operation of performing fail bit count is performed between the application of the current programming pulse and the application of the next programming pulse, which needs to occupy additional time, resulting in a long programming time.

[0135] Exemplarily, the process of applying the N+1th programming pulse can include an N+1th programming preparation operation phase and an N+1th programming stable execution phase. The N+1th programming preparation operation phase is a preparation operation of performing the N+1th programming operation related state and data, which corresponds to the phase of applying a pass voltage (Vpass) to the selected word line in the voltage timing. The N+1th programming stable execution phase is a phase of controlling the potential level of the bit line of the memory cell array in response to the programming data during the N+1th programming pulse application operation, which corresponds to the phase of applying the N+1th programming pulse to the selected word line in the voltage timing.

[0136] In some embodiments, after the N+1th programming preparation operation phase, i.e., after the pass voltage is applied to the selected word line, the first sub result can be read in the N+1th programming stable execution phase, and fail bit count can be performed on the first sub verification to obtain a first count result.

[0137] Compared with performing fail bit count on the first sub verification between the application of the Nth programming pulse and the application of the N+1th programming pulse, the programming method provided by the embodiments of the present disclosure can perform fail bit count on the first sub verification in the process of applying the N+1th programming pulse. Thus, the step of obtaining the first count result in the whole programming operation process does not occupy additional time, which can save the programming operation time and improve the programming efficiency. Moreover, the embodiments of the present disclosure can save logic overhead by hiding the process of performing fail bit count on the first sub verification after the application of the Nth programming pulse in the process of applying the N+1th programming pulse.

[0138] In some embodiments, the programming method further includes:

[0139] According to the N+1th second sub result, fail bit count is performed on the N+1th second sub verification to obtain a second count result;

[0140] When the second count result is less than a second preset value, it is determined that the i-state programming passes;

[0141] When the second count result is greater than or equal to the second preset value and the number of currently applied programming pulses is less than the maximum number of pulses, it is determined that the storage unit needs to be applied with the N+2th programming pulse according to the N+1th second sub result.

[0142] When the second counting result is greater than or equal to the second preset value, and the number of currently applied programming pulses is equal to the maximum number of pulses, it is determined that the programming of the i-th state fails.

[0143] The second counting result includes the number of failed bits after the memory is programmed by applying the programming pulse.

[0144] Exemplarily, whether the threshold voltage of the storage unit is less than the preset voltage can be represented by binary coding.

[0145] Exemplarily, the second preset value is in a range allowed by an error correction code (ECC) correction mechanism.

[0146] Due to the ECC correction mechanism, when the number of failed bits in programming the memory is within the range allowed by the ECC correction mechanism, at least part of the failed bits can be corrected by the ECC correction, so that correct data can be read from the memory.

[0147] In the embodiments of the present disclosure, since the second preset value is in a range allowed by the ECC mechanism, when the number of failed bits in programming the memory is less than the second preset value, the failed bits can be corrected by the ECC correction mechanism, so that the programming effect is good.

[0148] In some embodiments, the second preset value is less than or equal to the first preset value.

[0149] It can be understood that, since the N+1 programming pulse is applied to the storage unit with the threshold voltage less than the target threshold voltage after the first sub-verification, at least part of the threshold voltage of the storage unit originally less than the target threshold voltage will increase to reach the target threshold voltage after the N+1 programming pulse is applied, that is, the number of storage units that fail to program after the N+1 programming pulse is applied will be less than the first counting result, and therefore, the first preset value can be set to be slightly greater than the second preset value, and the programming of the i-th state can still be monitored well.

[0150] Figure 4 FIG. 3 is a flowchart of another memory programming method according to an exemplary embodiment, which is applied to a single-level cell programming mode (SLC mode), and the programming method includes the following steps:

[0151] S200: Start single-level cell programming.

[0152] S210: Apply a programming pulse.

[0153] S220: performing a first sub-verification to determine whether the threshold voltage of the single-level storage unit reaches a lower preset voltage, and performing a first second sub-verification to determine whether the voltage of the single-level storage unit reaches a target threshold voltage;

[0154] S230: applying a programming pulse and simultaneously performing a failure bit count on the first sub-verification to obtain a first count result;

[0155] S240: determining whether the first count result is less than a first preset value; when the first count result is less than the first preset value, jumping to perform S241; when the first count result is greater than or equal to the first preset value, jumping to perform S250;

[0156] S241: programming success, ending the programming;

[0157] S250: performing a second sub-verification to determine whether the voltage of the single-level storage unit reaches the target threshold voltage;

[0158] S260: performing a failure bit count on the second sub-verification performed in S250 to obtain a second count result;

[0159] S270: determining whether the second count result is less than a second preset value; when the second count result is less than the second preset value, jumping to perform S241; when the second count result is greater than or equal to the second preset value, jumping to perform S280;

[0160] S280: determining whether the number of applied pulses reaches a maximum number; when the number of applied pulses reaches the maximum number, jumping to perform S281; when the number of applied pulses does not reach the maximum number, jumping to perform S290;

[0161] S290: applying a programming pulse.

[0162] S210 is to apply a first programming pulse, and S230 is to apply a second programming pulse. It is emphasized that the difference between the programming pulse applied in S230 and the programming pulse applied in S210 is large enough to ensure that, after performing S230, the single-level storage unit whose threshold voltage is originally greater than or equal to the preset voltage and less than the target threshold voltage will increase to reach the target threshold voltage. Specifically, the difference between the programming pulse applied in S230 and the programming pulse applied in S210 is greater than or equal to the difference between the target threshold voltage and the preset voltage.

[0163] In S240, since the first counting result is the result of counting the single-level memory cells whose threshold voltage is less than the preset voltage after the first programming pulse is applied, and the difference between the programming pulse applied in S230 and the programming pulse applied in S210 is greater than or equal to the difference between the target threshold voltage and the preset voltage, after S230 is performed, when the first counting result is less than the first preset value, it can be considered that the programming of the first state is successful, and thus the step of second programming verification can be directly omitted, and the programming time is shortened.

[0164] In S280, the maximum number can be reasonably set according to requirements, for example, can be set to 2, 3 or 4, etc.

[0165] Figure 5 is a schematic diagram of a memory 300 according to an exemplary embodiment. Referring to Figure 5 As shown, the memory 300 includes:

[0166] a memory cell array 301 including a plurality of memory cell rows;

[0167] a plurality of word lines 318 respectively coupled to the plurality of memory cell rows; and

[0168] a peripheral circuit 302 coupled to the plurality of word lines 318 and configured to perform a programming operation on a selected memory cell row of the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein, to perform the programming operation, the peripheral circuit 302 is configured to perform the programming method as described in any of the embodiments of the present disclosure

[0169] The memory cell array device 301 can be a NAND flash memory cell array, in which the memory cells 306 are provided in an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge capture transistor.

[0170] Exemplarily, each memory cell 306 can include a single-level memory cell having two possible memory states and thus can store one bit of data. For example, a first memory state "0" can correspond to a first voltage range, and a second memory state "1" can correspond to a second voltage range.

[0171] In some embodiments, the memory cells 306 can also include multi-level memory cells, such as MLC, TLC, or QLC, etc. It is emphasized that when the memory cells 306 are multi-level memory cells, the peripheral circuitry is configured to perform the programming method provided by the embodiments of the present disclosure when programming the highest state of the multi-level memory cells.

[0172] When the memory cells 306 are three-level memory cells or four-level memory cells, etc., the peripheral circuitry is configured to perform the programming method provided by the embodiments of the present disclosure when programming the middle state of the three-level memory cells or four-level memory cells, etc.

[0173] As shown in FIG. 3A, each NAND memory string 308 can include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The source select gate 310 and the drain select gate 312 can be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. Figure 5

[0174] In some implementations, the sources of the NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some implementations, all of the NAND memory strings 308 in the same block 304 have an array common source (ACS).

[0175] According to some implementations, the drain select gates 312 of each NAND memory string 308 are coupled to a respective bit line 316 from which data can be read or written via an output bus (not shown).

[0176] In some implementations, each NAND memory string 308 is configured to be selected or deselected by having a select voltage (e.g., higher than the threshold voltage of the transistor with the drain select gate 312) or a deselect voltage (e.g., 0V) applied to the respective drain select gate 312 via one or more drain select gate lines 313.

[0177] In some implementations, each NAND memory string 308 is configured to be selected or deselected by having a select voltage (e.g., higher than the threshold voltage of the transistor with the source select gate 310) or a deselect voltage (e.g., 0V) applied to the respective source select gate 310 via one or more source select gate lines 315.

[0178] As shown in FIG. 3A, each NAND memory string 308 can include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The source select gate 310 and the drain select gate 312 can be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. Figure 5 ​As shown in the middle, the NAND memory strings 308 can be organized into a plurality of blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each block 304 is the basic unit of data for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. It will be appreciated that in some examples, erase operations can be performed at a half-block level, at a quarter-block level, or at any suitable fraction of a block or blocks having any suitable number of blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0179] In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic unit of data for program operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 in a block 304 that are coupled by a word line 318. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding page 320 as well as a gate line that couples the control gates. It will be appreciated that a row of memory cells represents a plurality of memory cells 306 that are located in the same page 320.

[0180] Figure 6 A partial cross-sectional view showing a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown in accordance with some aspects of the present disclosure. As Figure 6 shown, the NAND memory strings 308 can extend vertically through the memory stack 404 above a substrate 402. The substrate 402 can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0181] The memory stack 404 can include alternating gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 can determine the number of memory cells 306 in the memory cell array 301.

[0182] The gate conductive layers 406 can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, e.g., a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 can include a control gate surrounding a memory cell 306 and can laterally extend at a top of the memory stack 404 as a drain select gate line 313, at a bottom of the memory stack 404 as a source select gate line 315, or between the drain select gate line 313 and the source select gate line 315 as a word line 318.

[0183] It should be appreciated that although not shown in Figure 6 , additional components of the memory cell array 301 can be formed including, but not limited to, gate line slits / source contacts, local contacts, interconnect layers, etc.

[0184] Referring back to Figure 5 , the peripheral circuitry 302 can be coupled to the memory cell array 301 through the bit lines 316, the word lines 318, the source lines 314, the source select gate lines 315, and the drain select gate lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 through the bit lines 316, the word lines 318, the source lines 314, the source select gate lines 315, and the drain select gate lines 313.

[0185] The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 7 Some example peripheral circuitry is shown, the peripheral circuitry 302 including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be appreciated that additional peripheral circuitry not shown in Figure 7 may also be included in some examples.

[0186] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one page 320 of the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense low power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0187] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and select / deselect blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from the voltage generator 510. In some implementations, the row decoder / word line driver 508 can also select / deselect and drive the SSG lines 315 and the DSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform erase operations on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0188] The control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic unit 512 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each of the peripheral circuits. The interface 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer status information received from the control logic unit 512 and relay them to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay them to or from the memory cell array 301.

[0189] It is emphasized that the peripheral circuits 302 are configured to perform the programming method provided by embodiments of the present disclosure on a selected memory cell row among a plurality of memory cell rows.

[0190] Figure 8 A block diagram of an exemplary system 100 having a memory in accordance with some aspects of the present disclosure is shown. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein.

[0191] As Figure 8 The system 100 can include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106, as shown in FIG. 1. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 can be configured to send data to or receive data from the memory 104.

[0192] The memory 104 can be any memory device disclosed in the present disclosure, for example, the memory 104 can include the memory 300 provided by the present disclosure. As disclosed in detail below, the memory 104 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows further scaling of the drive transistor.

[0193] According to some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108, and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104, and communicate with the host 108. It can be appreciated that the memory controller 106 is configured to control the memory 104 to perform the programming method as provided by any embodiment of the present disclosure.

[0194] In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0195] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smartphones, tablet computers, laptops, etc. and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0196] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0197] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0198] In such Figure 9a In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 8 The memory card connector 204 is coupled to the host 108.

[0199] In such Figure 9b In another example shown, the memory controller 106 and multiple memories 104 may be integrated into a solid-state drive (SSD) 206. The solid-state drive 206 may also include a connection between the solid-state drive 206 and a host computer (e.g., Figure 8 The solid-state drive connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0200] The descriptions of the above-described memory device embodiments are similar to those of the above-described method embodiments, and have similar beneficial effects. For technical details not disclosed in the memory device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0201] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0202] It should be noted that, in the present document, the terms "comprising", "containing" or any other similar term are intended to encompass non-exclusive inclusions, such that a process, method, article, or apparatus that comprises a list of elements does not only include those elements, but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0203] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0204] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the present embodiment.

[0205] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0206] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of programming a memory, characterized by, The memory includes a plurality of memory cells to be programmed; the programming method includes: applying an Nth programming pulse to a selected memory cell whose target state is an i-th state; wherein i is a natural number, and N is a positive integer; after applying the Nth programming pulse, performing a first sub-verification and an Nth second sub-verification on the selected memory cell, to obtain a first sub-result and an Nth second sub-result; wherein the first sub-result indicates whether the threshold voltage of the selected memory cell is less than a preset voltage, and the Nth second sub-result indicates whether the threshold voltage of the selected memory cell is less than a target threshold voltage of the i-th state, the target threshold voltage being greater than the preset voltage; determining, according to the Nth second sub-result, a memory cell among the memory cells whose target state is the i-th state that needs to be applied with an (N+1)th programming pulse; wherein the difference between the (N+1)th programming pulse and the Nth programming pulse is greater than or equal to the difference between the target threshold voltage and the preset voltage; applying the (N+1)th programming pulse to the memory cell that needs to be applied with the (N+1)th programming pulse; wherein after applying the (N+1)th programming pulse, and when the first sub-result indicates that the number of failed bits of the first sub-verification is less than a first preset value, it is determined that the programming of the i-th state is successful.

2. The programming method of claim 1, wherein: the memory cells include single-level memory cells; and / or, the memory cells include multi-level memory cells, and the programming method is applied to program a highest state of the memory cells.

3. The programming method of claim 1, wherein, the memory cells include three-level memory cells or four-level memory cells, the target programming states of the memory cells include a lowest state, an intermediate state, and a highest state, and the programming method is applied to program the intermediate state.

4. The programming method of claim 1, wherein, after applying the Nth programming pulse, performing the first sub-verification and the Nth second sub-verification on the selected memory cell based on a first sensing duration, to obtain the first sub-result; after applying the Nth programming pulse, performing the first sub-verification on the selected memory cell based on a first sensing duration, to obtain the first sub-result; after applying the Nth programming pulse, performing the Nth second sub-verification on the selected memory cell based on a second sensing duration, to obtain the Nth second sub-result; wherein the second sensing duration is greater than the first sensing duration.

5. The programming method of claim 1, wherein, after applying the Nth programming pulse, applying a first sub-verification voltage to a word line coupled to the selected memory cell, to perform the first sub-verification on the selected memory cell, to obtain the first sub-result; wherein the first sub-verification voltage is equal to the preset voltage; after applying the Nth programming pulse, applying a second sub-verification voltage to a word line coupled to the selected memory cell, to perform the Nth second sub-verification on the selected memory cell, to obtain the Nth second sub-result; wherein the second sub-verification voltage is equal to the target threshold voltage. ​ 6. The programming method of claim 1, wherein, The first sub-verification and the Nth second sub-verification are performed on the selected memory cell after the Nth programming pulse is applied, and a first sub-result and an Nth second sub-result are obtained. After the Nth programming pulse is applied, a first pre-charge voltage is applied to a bit line coupled to the selected memory cell, and the first sub-verification is performed on the selected memory cell based on a preset sensing time length, and the first sub-result is obtained. After the Nth programming pulse is applied, a second pre-charge voltage is applied to a bit line coupled to the selected memory cell, and the Nth second sub-verification is performed on the selected memory cell based on the preset sensing time length, and the Nth second sub-result is obtained; wherein the second pre-charge voltage is greater than the first pre-charge voltage.

7. The programming method of claim 1, wherein, The Nth second sub-result is used to determine a memory cell that needs to be applied with an N+1th programming pulse in the memory cell whose target state is the ith state, including: When the Nth second sub-result indicates that the threshold voltage of the selected memory cell is less than the target threshold voltage, it is determined that the selected memory cell belongs to the memory cell that needs to be applied with the N+1th programming pulse.

8. The programming method of claim 1, wherein, The programming method further includes: After the N+1th programming pulse is applied, and when the first sub-result indicates that the number of failed bits of the first sub-verification is greater than or equal to the first preset value, the first sub-result is used to determine a memory cell that needs to be verified after the N+1th programming pulse is applied; The N+1th second sub-verification is performed on the memory cell that needs to be verified after the N+1th programming pulse is applied, and an N+1th second sub-result is obtained, which indicates whether the threshold voltage of the memory cell is less than the target threshold voltage.

9. The programming method according to claim 8, characterized in that, The first sub-result is used to determine the memory cell that needs to be verified after the N+1th programming pulse is applied, including: When the threshold voltage of the memory cell is less than the preset voltage, it is determined that the memory cell belongs to the memory cell that needs to be verified after the N+1th programming pulse is applied; When the threshold voltage of the selected memory cell is greater than or equal to the preset voltage, it is determined that the memory cell does not belong to the memory cell that needs to be verified after the N+1th programming pulse is applied.

10. The programming method of claim 8, wherein, The programming method further includes: The N+1th second sub-verification is counted based on the N+1th second sub-result, and a second counting result is obtained; When the second counting result is less than a second preset value, it is determined that the programming of the ith state is successful; When the second counting result is greater than or equal to the second preset value, and the number of currently applied programming pulses is less than a maximum number of pulses, the N+1th second sub-result is used to determine a memory cell that needs to be applied with an N+2th programming pulse; When the second counting result is greater than or equal to the second preset value, and the number of currently applied programming pulses is equal to the maximum number of pulses, it is determined that the programming of the ith state fails.

11. The programming method according to claim 10, characterized in that, The second preset value is less than or equal to the first preset value.

12. The programming method of claim 1, wherein, The performing, after the applying of the Nth programming pulse, the first sub-verification and the Nth second sub-verification on the selected memory cells, corresponding to obtaining a first sub-result and an Nth second sub-result, comprises: The performing the first sub-verification on the selected memory cells, corresponding to obtaining the first sub-result; The determining, according to the first sub-result, memory cells that need to perform the Nth second sub-verification; The performing the Nth second sub-verification on the memory cells that need to perform the Nth second sub-verification, corresponding to obtaining the Nth second sub-result.

13. The programming method of claim 1, wherein, The performing, after the applying of the Nth programming pulse, the first sub-verification and the Nth second sub-verification on the selected memory cells, corresponding to obtaining a first sub-result and an Nth second sub-result, comprises: The performing the Nth second sub-verification on the selected memory cells, corresponding to obtaining the Nth second sub-result; The determining, according to the Nth second sub-result, memory cells that need to perform the first sub-verification; The performing the first sub-verification on the memory cells that need to perform the first sub-verification, corresponding to obtaining the first sub-result.

14. The programming method of claim 1, wherein, The programming method further comprises: during the applying of the N+1th programming pulse, performing, according to the first sub-result, a failure bit number counting on the first sub-verification, to obtain a first counting result.

15. A memory, comprising: Comprising: a memory cell array comprising a plurality of memory cell rows; a plurality of word lines respectively coupled to the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and configured to perform a programming operation on a selected memory cell row in the plurality of memory cell rows, the selected memory cell row being coupled to a selected word line, wherein the peripheral circuit is configured to perform the programming method according to any one of claims 1 to 14. Comprising:

16. A memory system, comprising: one or more memories according to claim 15; a memory controller coupled to the memories and configured to control the memories. ​

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