Three-dimensional memory structure and manufacturing method thereof, three-dimensional memory and storage system

Abstract

This application relates to a three-dimensional memory structure and its fabrication method, a three-dimensional memory, and a memory system, comprising: forming a stacked structure, the stacked structure including a plurality of gate sacrificial layers and a plurality of interlayer insulating layers, the gate sacrificial layers and interlayer insulating layers being alternately stacked in a first direction, the plurality of gate sacrificial layers including a select gate sacrificial layer and a storage gate sacrificial layer; forming a channel structure penetrating the stacked structure in the first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer; removing the select gate sacrificial layer, and at least removing the charge blocking layer and the charge trapping layer corresponding to the location of the select gate sacrificial layer to form a select gate gap; forming a select gate layer in the select gate gap, thereby improving the performance of the select transistor in the three-dimensional memory to improve the overall performance of the three-dimensional memory.

Description

[Technical Field]

[0001] This application relates to the field of memory technology, specifically to a three-dimensional memory structure and its fabrication method, a three-dimensional memory and a memory system. [Background Technology]

[0002] With the development of technology, the semiconductor industry is constantly seeking new production methods to enable each memory die in memory devices to have a greater number of memory cells. Among them, 3D NAND (3D NAND flash memory) has become a cutting-edge and highly promising memory technology due to its advantages such as high storage density and low cost.

[0003] However, how to improve the performance of transistors in three-dimensional memory is a rather troubling problem in current memory technology, and new methods to solve this problem are urgently needed. [Summary of the Invention]

[0004] This application provides a three-dimensional storage structure and its fabrication method, a three-dimensional memory and a storage system, to improve the performance of selected transistors in the three-dimensional storage structure, thereby improving the overall performance of the three-dimensional storage structure.

[0005] To at least partially solve the above problems, embodiments of this application provide a method for fabricating a three-dimensional memory structure. The method includes: forming a stacked structure comprising a plurality of gate sacrificial layers and a plurality of interlayer insulating layers, wherein the gate sacrificial layers and the interlayer insulating layers are alternately stacked in a first direction, and the plurality of gate sacrificial layers include a select gate sacrificial layer and a storage gate sacrificial layer; forming a channel structure penetrating the stacked structure in the first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer; removing the select gate sacrificial layer, and at least removing the charge blocking layer and the charge trapping layer corresponding to the location of the select gate sacrificial layer to form a select gate gap; and forming a select gate layer in the select gate gap.

[0006] The step of forming the select gate gap specifically includes: removing the select gate sacrificial layer to form a first gap, thereby exposing a portion of the charge blocking layer in the first gap; removing the charge blocking layer exposed in the first gap to form a second gap including the first gap, thereby exposing a portion of the charge trapping layer in the second gap; and removing the charge trapping layer exposed in the second gap to form the select gate gap including the second gap.

[0007] The method further includes: removing the memory gate sacrificial layer to form a memory gate gap when forming the first gap; and forming a memory gate layer in the memory gate gap before forming the second gap.

[0008] The step of forming the memory gate layer specifically includes: depositing a gate material and filling the memory gate gap with the gate material, and filling the first gap with the gate material along the inner wall portion of the first gap; removing the gate material located outside the memory gate gap to expose the inner wall of the first gap, and obtaining the memory gate layer formed in the memory gate gap.

[0009] The channel structure further includes a channel layer surrounded by the charge trapping layer, and the method further includes: forming a gate insulating layer in the selected gate gap corresponding to the channel layer position after forming the selected gate gap and before forming the selected gate layer.

[0010] The channel structure further includes a charge tunneling layer, which surrounds the channel layer and is surrounded by the charge trapping layer. The step of exposing a portion of the charge tunneling layer in the selected gate gap and forming the gate insulating layer specifically includes: forming the gate insulating layer on the surface of the charge tunneling layer that is exposed in the selected gate gap and extends along the first direction.

[0011] The channel structure further includes a charge tunneling layer, which surrounds the channel layer and is surrounded by the charge trapping layer. The step of forming the select gate gap specifically includes: removing the select gate sacrificial layer and removing the charge blocking layer, the charge trapping layer, and the charge tunneling layer corresponding to the location of the select gate sacrificial layer to form the select gate gap, thereby exposing a portion of the channel layer in the select gate gap; and the step of forming the gate insulating layer specifically includes: forming the gate insulating layer on the surface of the channel layer exposed in the select gate gap that extends along the first direction.

[0012] The number of storage gate sacrificial layers is multiple, and the multiple storage gate sacrificial layers are stacked continuously with intervals. The number of selected gate sacrificial layers is at least one, and the selected gate sacrificial layer is located on a first side of the multiple storage gate sacrificial layers in the first direction, or the selected gate sacrificial layer is located on a second side of the multiple storage gate sacrificial layers in the first direction, with the first side and the second side opposite to each other; or the number of selected gate sacrificial layers is multiple, and the multiple selected gate sacrificial layers are respectively disposed on the first side and the second side of the multiple storage gate sacrificial layers in the first direction.

[0013] The thickness of the selected gate sacrificial layer is greater than the thickness of the storage gate sacrificial layer.

[0014] The ratio of the thickness of the selected gate sacrificial layer to the thickness of the storage gate sacrificial layer is between 2 and 6.

[0015] The three-dimensional memory structure includes a gate line slot that penetrates the stacked structure in the first direction, and the thickness of the selected gate sacrificial layer is less than the width of the gate line slot.

[0016] The ratio of the thickness of the selected gate sacrificial layer to the width of the gate line gap is between 0.2 and 0.7.

[0017] To at least partially solve the above problems, embodiments of this application also provide a three-dimensional memory structure, which includes: a stack, the stack including a plurality of gate layers and a plurality of interlayer insulating layers, the gate layers and the interlayer insulating layers being alternately stacked in a first direction, the plurality of gate layers including a select gate layer and a storage gate layer; and a channel structure penetrating the stack in the first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer, wherein the charge blocking layer is disconnected at a position corresponding to the select gate layer.

[0018] The channel structure further includes a channel layer surrounded by the charge trapping layer, and the three-dimensional storage structure further includes a gate insulating layer located between the selected gate layer and the channel layer in a second direction, the second direction being perpendicular to the first direction.

[0019] The channel structure further includes a charge tunneling layer, which surrounds the channel layer and is surrounded by the charge trapping layer, and the thickness of the gate insulating layer in the second direction is greater than or equal to the thickness of the charge tunneling layer in the second direction.

[0020] The thickness of the selected gate layer is greater than the thickness of the storage gate layer.

[0021] The ratio of the thickness of the selected gate layer to the thickness of the storage gate layer is between 2 and 6.

[0022] The three-dimensional storage structure further includes a gate line slot structure that extends through the stack in the first direction, wherein the thickness of the selected gate layer is less than the width of the gate line slot structure.

[0023] The ratio of the thickness of the selected gate layer to the width of the gate line slot structure is between 0.2 and 0.7.

[0024] The storage gate layers are multiple, and the multiple storage gate sacrificial layers are stacked continuously at intervals. The selection gate layer is at least one, and the selection gate layer is located on a first side of the multiple storage gate layers in the first direction, or the selection gate layer is located on a second side of the multiple storage gate layers in the first direction opposite to the first side; or, the selection gate sacrificial layers are multiple, and the multiple selection gate sacrificial layers are respectively disposed on the first side and the second side of the multiple storage gate sacrificial layers in the first direction.

[0025] To at least partially solve the above problems, embodiments of this application also provide a three-dimensional memory, which includes a three-dimensional storage structure as described above and a peripheral circuit structure, wherein the peripheral circuit structure is electrically connected to the three-dimensional storage structure.

[0026] To at least partially solve the above problems, embodiments of this application also provide a storage system, which includes a controller and a three-dimensional memory as described above, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

[0027] To at least partially solve the above problems, embodiments of this application also provide an electronic device that includes the storage system described above.

[0028] The beneficial effects of the embodiments of this application are as follows: The three-dimensional memory structure and its fabrication method, three-dimensional memory and memory system provided by the embodiments of this application form a stacked structure, the stacked structure including multiple gate sacrificial layers and multiple interlayer insulating layers, the gate sacrificial layers and interlayer insulating layers are alternately stacked in a first direction, the multiple gate sacrificial layers include a select gate sacrificial layer and a storage gate sacrificial layer, then a channel structure is formed through the stacked structure in the first direction, the channel structure includes a charge trapping layer and a charge blocking layer surrounding the charge trapping layer, then the select gate sacrificial layer is removed, and at least the charge blocking layer and charge trapping layer corresponding to the position of the select gate sacrificial layer are removed to form a select gate gap, and then a select gate layer is formed in the select gate gap, thereby enabling the select transistor of the memory cell string in the finally fabricated three-dimensional memory structure to be a MOS (Metal-Oxide-Semiconductor) structure transistor, avoiding the problem of poor performance of the select transistor of the memory cell string in the three-dimensional memory structure due to the use of the same structure as the memory cell, thus improving the performance of the select transistor in the three-dimensional memory (e.g., threshold voltage stability, Id-Vg curve, etc.), and improving the overall performance of the three-dimensional memory. [Attached Image Description]

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional storage structure according to an embodiment of this application;

[0031] Figure 2 This is a cross-sectional structural diagram after step S11 is completed, as provided in the embodiments of this application.

[0032] Figure 3 This is a cross-sectional structural diagram after step S121 is completed, as provided in the embodiments of this application.

[0033] Figure 4 This is a cross-sectional structural diagram showing the structure after step S122 is completed, as provided in the embodiments of this application.

[0034] Figure 5 This is a schematic cross-sectional view of the channel plug provided in an embodiment of this application;

[0035] Figure 6 This is a schematic cross-sectional view of the structure after the grid line gaps are formed, provided in an embodiment of this application.

[0036] Figure 7 This is a cross-sectional structural diagram after step S131 is completed, as provided in the embodiments of this application.

[0037] Figure 8 This is a schematic cross-sectional view of the structure after the deposition of the first gate material, provided in an embodiment of this application.

[0038] Figure 9 This is a schematic cross-sectional view of the structure after the formation of the memory gate layer provided in an embodiment of this application;

[0039] Figure 10 This is a cross-sectional structural diagram showing the result after step S132 is completed, as provided in the embodiments of this application.

[0040] Figure 11 This is a cross-sectional structural diagram showing the result after step S133 is completed, as provided in the embodiments of this application.

[0041] Figure 12 This is a schematic cross-sectional view of the structure after the deposition of the second gate material, provided in an embodiment of this application.

[0042] Figure 13This is a schematic cross-sectional view of the structure after forming the selected gate layer provided in an embodiment of this application;

[0043] Figure 14 This is another cross-sectional structural diagram provided in the embodiments of this application after forming the selected gate layer;

[0044] Figure 15 This is a schematic cross-sectional view of the structure after the grid line slot structure is formed, as provided in the embodiments of this application.

[0045] Figure 16 This is a schematic cross-sectional view of the structure after forming the selected gate layer, provided in another embodiment;

[0046] Figure 17 This is a schematic diagram of the structure of the three-dimensional memory provided in the embodiments of this application;

[0047] Figure 18 This is a schematic diagram of the structure of the storage system provided in the embodiments of this application;

[0048] Figure 19 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application.

Detailed Implementation Methods

[0049] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be particularly noted that the following embodiments are only used to illustrate the embodiments of this application and do not limit the scope of the embodiments of this application. Similarly, the following embodiments are only some embodiments of the embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the embodiments of this application.

[0050] Furthermore, the directional terms mentioned in the embodiments of this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding the embodiments of this application, and not for limiting the embodiments of this application. In the various drawings, structurally similar units are represented by the same reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some related parts may not be shown in the drawings.

[0051] Embodiments of this application may be presented in various forms, some of which will be described below.

[0052] Please see Figure 1 , Figure 1 This is a flowchart illustrating the method for fabricating a three-dimensional storage structure according to an embodiment of this application. The specific process of fabricating the three-dimensional storage structure can be as follows:

[0053] Step S11: Form a stacked structure, the stacked structure including multiple gate sacrificial layers and multiple interlayer insulating layers, the gate sacrificial layers and interlayer insulating layers are alternately stacked in a first direction, and the multiple gate sacrificial layers include a select gate sacrificial layer and a storage gate sacrificial layer.

[0054] The cross-sectional structural diagram after step S11 can be as follows: Figure 2 As shown.

[0055] Specifically, a stacked structure 12 can be formed on the substrate 11. The substrate 11 is used to support the device structure thereon and may include semiconductor materials such as silicon, germanium, or silicon-on-insulator (SOI). The stacked structure 12 may include a plurality of gate sacrificial layers 121 and a plurality of interlayer insulating layers 122 alternately stacked in a first direction Z perpendicular to the substrate 11.

[0056] In the aforementioned stacked structure 12, the gate sacrificial layer 121 can be formed between two adjacent interlayer insulating layers 122. The gate sacrificial layer 121 can be, but is not limited to, silicon nitride, and the interlayer insulating layer 122 can be, but is not limited to, silicon oxide, thereby forming a silicon nitride / silicon oxide stacked structure. Furthermore, in subsequent process steps, the gate sacrificial layer 121 is replaced by a substitution process, and a conductive material (e.g., tungsten) is filled at the same location to form the corresponding gate layer.

[0057] In this embodiment, as Figure 2 As shown, the multiple gate sacrificial layers 121 included in the aforementioned stacked structure 12 can be divided into two categories: select gate sacrificial layers 121A / 121C and storage gate sacrificial layers 121B. Furthermore, select gate sacrificial layers 121A / 121C can be replaced with corresponding select gate layers in subsequent process steps, and storage gate sacrificial layer 121B can be replaced with corresponding storage gate layers in subsequent process steps. The select gate layer is used to provide a gate to the select transistor in the storage cell string in the three-dimensional storage structure, and the storage gate layer is used to provide a gate to the storage cell in the storage cell string in the three-dimensional storage structure.

[0058] Specifically, the number of the aforementioned select gate sacrificial layers 121A / 121C can be at least one, and the number of the aforementioned storage gate sacrificial layers 121B can be multiple. These multiple storage gate sacrificial layers 121B can be stacked continuously at intervals, and the select gate sacrificial layers 121A / 121C can be located on a first side (i.e., the side facing away from the substrate 11) of the multiple storage gate sacrificial layers 121B in the first direction Z, or the select gate sacrificial layers 121A / 121C can be located on a second side (i.e., the side facing the substrate 11) of the multiple storage gate sacrificial layers 121B in the first direction Z. The first side and the second side are opposite to each other.

[0059] In other embodiments, the number of the selected gate sacrificial layers 121A / 121C may be multiple, and the multiple selected gate sacrificial layers 121A / 121C may be disposed on the first side and the second side of the multiple storage gate sacrificial layers 121B in the first direction Z.

[0060] Specifically, in embodiments where the number of selected gate sacrificial layers 121A / 121C is at least one, the at least one selected gate sacrificial layer 121A / 121C may include at least one first selected gate sacrificial layer 121A, or at least one second selected gate sacrificial layer 121C. In embodiments where the number of selected gate sacrificial layers 121A / 121C is multiple, the multiple selected gate sacrificial layers 121A / 121C may include both at least one first selected gate sacrificial layer 121A and at least one second selected gate sacrificial layer 121C.

[0061] The first gate sacrificial layer 121A and the second gate sacrificial layer 121C are respectively located on opposite sides (i.e., the first side and the second side) of the plurality of memory gate sacrificial layers 121B in the first direction Z. Specifically, the first gate sacrificial layer 121A may be located on the side of the plurality of memory gate sacrificial layers 121B away from the substrate 11 (i.e., the first side), and the second gate sacrificial layer 121C may be located on the side of the plurality of memory gate sacrificial layers 121B facing the substrate 11 (i.e., the second side).

[0062] Specifically, the first gate selection layer 121A can provide a gate to the drain selection transistor in the memory cell string in the three-dimensional memory structure, and the second gate selection layer 121C can provide a gate to the source selection transistor in the memory cell string in the three-dimensional memory structure.

[0063] Step S12: Form a channel structure that runs through the stacked structure in a first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer.

[0064] In one embodiment, step S12 may specifically include steps S121 and S122, wherein:

[0065] Step S121: Form a channel hole that penetrates the stacked structure in the first direction.

[0066] The cross-sectional structure diagram after step S121 can be as follows: Figure 3 As shown.

[0067] Specifically, an anisotropic etching process can be used, for example, a dry etching process (such as plasma etching, reactive ion etching, etc.), to etch the stacked structure 12 from top to bottom in a first direction Z perpendicular to the substrate 11, forming a channel hole 16 that passes through the stacked structure 12 and reaches the substrate 11. In a specific embodiment, such as Figure 3 As shown, the aforementioned channel hole 16 can also penetrate the stacked structure 12 in the first direction Z and extend into the interior of the substrate 11 to form a groove 11A on the substrate 11, thereby achieving sufficient etching to ensure that the substrate 11 can be exposed through the channel hole 16.

[0068] Furthermore, in specific implementation, such as Figure 3 As shown, the formation of the aforementioned channel hole 16 may specifically include: forming a first mask layer 13 on the stacked structure 12; etching the first mask layer 13 to form a first opening 131, thereby obtaining a first mask layer 13 with the first opening 131; and etching the stacked structure 12 through the first mask layer 13 with the first opening 131 to form the channel hole 16. The first mask layer 13 may specifically be a photoresist layer, or may include a hard mask layer located on the stacked structure 12 and a photoresist layer located on the hard mask layer.

[0069] Understandably, during the etching process of the stacked structure 12 to form the channel hole 16, the first mask layer 13 with the first opening 131 can act as a barrier to etching, protecting the stacked structure 12 located below and covered by it from damage by the etchant. Furthermore, after the etching process of the stacked structure 12 to form the channel hole 16 is completed, the remaining first mask layer 13 on the stacked structure 12 can be removed.

[0070] Step S122: Form a channel structure in the channel hole.

[0071] The cross-sectional structure diagram after step S122 can be as follows: Figure 4 As shown.

[0072] In this embodiment, the channel structure 17 may include a charge trapping layer 172 and a charge blocking layer 171 surrounding the charge trapping layer 172, and may also include a charge tunneling layer 173 surrounded by the charge trapping layer 172 and a channel layer 174 surrounded by the charge tunneling layer 173. In one specific embodiment, the charge blocking layer 171, the charge trapping layer 172, the charge tunneling layer 173, and the channel layer 174 may be made of silicon oxide, silicon nitride, silicon oxide, and polycrystalline silicon, respectively.

[0073] Specifically, the charge blocking layer 171, charge trapping layer 172, charge tunneling layer 173, and channel layer 174 can be sequentially formed on the inner wall of the aforementioned channel hole 16. Furthermore, after forming the aforementioned channel layer 174, a dielectric material (e.g., silicon oxide) can be filled into the channel hole 16 where the channel layer 174 is formed to form an insulating filling layer 175 to fill the remaining space in the channel hole 16, thereby obtaining a channel structure 17 composed of the aforementioned insulating filling layer 175, channel layer 174, charge tunneling layer 173, charge trapping layer 172, and charge blocking layer 171.

[0074] In some specific embodiments, such as Figure 5 As shown, after forming the channel structure 17, the method may further include forming a corresponding channel plug 14 at one end of the channel structure 17 facing away from the substrate 11. The channel plug 14 contacts the channel layer 174 to achieve an electrical connection between the channel plug 14 and the channel layer 174. Furthermore, the material of the channel plug 14 may include a semiconductor material; for example, the material of the channel plug 14 may be the same as that of the channel layer 174 in the channel structure 17 (e.g., polycrystalline silicon).

[0075] Specifically, the aforementioned channel plug 14 can serve as the drain of its corresponding channel structure 17. Furthermore, in a specific implementation, the end (or top portion) of the aforementioned insulating filling layer 175 facing away from the substrate 11 can be etched, and conductive material can be filled at the etched location to form the aforementioned channel plug 14.

[0076] In some embodiments, such as Figure 6 As shown, after forming the aforementioned channel structure 17, the method may further include forming a gate line slot 18 that penetrates the stacked structure 12 in the first direction Z. Specifically, the stacked structure 12 may be etched from top to bottom in the first direction Z to form a gate line slot 18 that penetrates the stacked structure 12 in the first direction Z and extends into the substrate 11.

[0077] Furthermore, in specific implementation, such as Figure 6As shown, the formation of the gate line gap 18 may specifically include: forming an insulating capping layer 10 covering the channel structure 17 and the channel plug 14 on the stacked structure 12; forming a second mask layer 15 on the insulating capping layer 10; etching the second mask layer 15 to form a second opening 151, thereby obtaining a second mask layer 15 with the second opening 151; and etching the stacked structure 12 and the insulating capping layer 10 through the second mask layer 15 with the second opening 151 to form the gate line gap 18. The second mask layer 15 may specifically be a photoresist layer, or may include a hard mask layer located on the insulating capping layer 10 and a photoresist layer located on the hard mask layer. The insulating capping layer 10 may be made of an insulating material such as silicon oxide. In one specific embodiment, the insulating cover layer 10 may be made of the same material as the interlayer insulating layer 122 in the stacked structure 12. When the outermost layer of the stacked structure 12 that is away from the substrate 11 is the interlayer insulating layer 122, the insulating cover layer 10 and the outermost layer of the stacked structure 12 that is away from the substrate 11 may be connected to form an integral structure.

[0078] Understandably, during the etching process of the stacked structure 12 to form the gate line gaps 18, the second mask layer 15 with the second opening 151 and the insulating cover layer 10 can act as a barrier to the etching process, protecting the stacked structure 12, the channel structure 17, and the channel plug 14 located below and covered by them from damage by the etchant. Furthermore, after the etching process of the stacked structure 12 and the insulating cover layer 10 to form the gate line gaps 18 is completed, the remaining second mask layer 15 on the stacked structure 12, the channel structure 17, and the channel plug 14 can be removed, while the remaining insulating cover layer 10 on the stacked structure 12, the channel structure 17, and the channel plug 14 is retained. This allows the remaining insulating cover layer 10 to protect the stacked structure 12, the channel structure 17, and the channel plug 14 in subsequent processes, ensuring the yield of the final three-dimensional memory structure.

[0079] Step S13: Remove the select gate sacrificial layer, and at least remove the charge blocking layer and charge trapping layer corresponding to the location of the select gate sacrificial layer to form a select gate gap.

[0080] In one embodiment, step S13 may specifically include steps S131, S132, and S133, wherein:

[0081] Step S131: Remove the selected gate sacrificial layer to form a first gap, thereby exposing a portion of the charge blocking layer in the first gap.

[0082] The cross-sectional structural diagram after step S131 can be as follows: Figure 7 As shown.

[0083] Specifically, such as Figure 6 and Figure 7 As shown, the selected gate sacrificial layer 121A / 121C in the stacked structure 12 can be removed via the gate line gap 18 formed in the preceding process steps to form the first gap 19A / 19C. For example, a selective etchant can be used to selectively etch and remove the selected gate sacrificial layer 121A / 121C in the stacked structure 12 through the gate line gap 18, relative to the interlayer insulating layer 122 and the charge blocking layer 171, to form the first gap 19A / 19C.

[0084] In one specific embodiment, such as Figure 7 As shown, the storage gate sacrificial layer 121B in the stacked structure 12 can be removed simultaneously during the process step of removing the select gate sacrificial layers 121A / 121C. That is, the method may further include: removing the select gate sacrificial layers 121A / 121C to form the first gap 19A / 19C, while simultaneously removing the storage gate sacrificial layer 121B in the stacked structure 12 to form the storage gate gap 19B.

[0085] Furthermore, after the formation of the first gaps 19A / 19C, the surface of the charge blocking layer 171 that was originally in contact with the gate selection sacrificial layer 121A / 121C will be exposed. After the formation of the storage gate gap 19B, the surface of the charge blocking layer 171 that was originally in contact with the storage gate sacrificial layer 121B will be exposed.

[0086] In some embodiments, such as Figure 7 , Figure 8 and Figure 9 As shown, after forming the first gaps 19A / 19C and the storage gate gap 19B, the method may further include forming a storage gate layer 21 in the storage gate gap 19B. Specifically, the storage gate gap 19B may be filled with a first gate material 20 (e.g., a conductive material such as tungsten) to form the storage gate layer 21.

[0087] In one specific embodiment, such as Figure 7 , Figure 8 and Figure 9As shown, the formation of the aforementioned memory gate layer 21 may specifically include: depositing a first gate material 20 (e.g., titanium nitride, tungsten, and / or a high dielectric constant dielectric material), filling the memory gate gap 19B with the first gate material 20, and filling the first gap 19A / 19C along the inner wall portion of the first gap 19A / 19C; and removing the first gate material 20 located outside the memory gate gap 19B to expose the inner wall of the first gap 19A / 19C, thereby obtaining the memory gate layer 21 formed in the memory gate gap 19B. That is, the memory gate layer 21 may specifically be the first gate material 20 that is filled in the memory gate gap 19B and has not been removed.

[0088] Specifically, when forming the stacked structure 12, the thickness of the selected gate sacrificial layer 121A / 121C in the stacked structure 12 can be greater than the thickness of the storage gate sacrificial layer 121B. This ensures that the width of the first gap 19A / 19C formed by removing the selected gate sacrificial layer 121A / 121C in the first direction Z is greater than the width of the storage gate gap 19B formed by removing the storage gate sacrificial layer 121B in the first direction Z. It is understood that the width of the first gap 19A / 19C in the first direction Z can be equal to the thickness of the corresponding selected gate sacrificial layer 121A / 121C in the stacked structure 12, and the width of the storage gate gap 19B in the first direction Z can be equal to the thickness of the corresponding storage gate sacrificial layer 121B in the stacked structure 12.

[0089] Furthermore, in specific implementation, the first gate material 20 can be deposited along the inner wall of the first gap 19A / 19C and the inner wall of the storage gate gap 19B. The deposition of the first gate material 20 is stopped after it has filled the storage gate gap 19B but before it has filled the first gap 19A / 19C. This ensures that when the first gate material 20 fills the storage gate gap 19B, the first gap 19A / 19C is not completely sealed by the first gate material 20, leaving some space unfilled. That is, the first gate material 20 completely fills the storage gate gap 19B and simultaneously forms on the inner wall of the first gap 19A / 19C, while also partially filling the first gap 19A / 19C.

[0090] It is understood that in the embodiment where the thickness of the gate sacrificial layer 121A / 121C is greater than the thickness of the storage gate sacrificial layer 121B in the above stacked structure 12, the inner wall material of the first gap 19A / 19C and the inner wall material of the storage gate gap 19B can be the same (for example, both can be silicon oxide), so that the deposition rate of the first gate material 20 on the inner wall of the first gap 19A / 19C can be the same as its deposition rate on the inner wall of the storage gate gap 19B, thereby ensuring that when the storage gate gap 19B is filled by the first gate material 20, the first gap 19A / 19C is only partially filled by the first gate material 20.

[0091] Furthermore, in the embodiment where the thickness of the selected gate sacrificial layer 121A / 121C is greater than the thickness of the storage gate sacrificial layer 121B in the stacked structure 12 described above, the method may further include: when forming the stacked structure 12, making the thickness of the interlayer insulating layer 122 in the stacked structure 12 that contacts the selected gate sacrificial layer 121A / 121C greater than the thickness of the interlayer insulating layer 122 that contacts the storage gate sacrificial layer 121B, thereby reducing the coupling effect and leakage current between adjacent selected gate layers and between adjacent selected gate layers and storage gate layer 21 in the final fabricated three-dimensional storage structure, so as to ensure the performance of the final fabricated three-dimensional storage structure.

[0092] In a specific example, in the stacked structure 12 described above, the thickness of the interlayer insulating layer 122 located between adjacent select gate sacrificial layers 121A / 121C and storage gate sacrificial layer 121B can be greater than or equal to the thickness of the interlayer insulating layer 122 located between adjacent select gate sacrificial layers 121A / 121C, and the thickness of the interlayer insulating layer 122 located between adjacent select gate sacrificial layers 121A / 121C can be greater than the thickness of the interlayer insulating layer 122 located between adjacent storage gate sacrificial layers 121B.

[0093] In some alternative stacked structures 12 where the thickness of the gate sacrificial layer 121A / 121C is greater than the thickness of the storage gate sacrificial layer 121B, the inner wall material of the first gap 19A / 19C may be different from the inner wall material of the storage gate gap 19B. This is to ensure that when the first gate material 20 is deposited along the inner walls of the first gap 19A / 19C and the storage gate gap 19B, the deposition rate of the first gate material 20 on the inner wall of the first gap 19A / 19C is lower than its deposition rate on the inner wall of the storage gate gap 19B. Thus, even if the thickness of the gate sacrificial layer 121A / 121C in the stacked structure 12 is not greater than the thickness of the storage gate sacrificial layer 121B, it can still be ensured that when the storage gate gap 19B is filled with the first gate material 20, the first gap 19A / 19C is not filled with the first gate material 20.

[0094] For a specific example, in the embodiment where the thickness of the gate sacrificial layer 121A / 121C is greater than the thickness of the storage gate sacrificial layer 121B in the above-mentioned stacked structure 12, the ratio of the thickness of the gate sacrificial layer 121A / 121C to the thickness of the storage gate sacrificial layer 121B in the above-mentioned stacked structure 12 can be between 2 and 6, for example, it can be 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, etc.

[0095] In some specific embodiments, such as Figure 8 As shown, the above method may further include: during the deposition of the first gate material 20, the first gate material 20 is also partially filled along the inner wall of the gate line gap 18. That is, the first gate material 20 not only completely fills the memory gate gap 19B, but is also formed on the inner wall of the first gaps 19A / 19C, and partially fills the first gaps 19A / 19C, and is also formed on the inner wall of the gate line gap 18, and partially fills the gate line gap 18. In addition, as Figure 8 As shown, the first gate material 20 can also be formed on the side of the insulating cover layer 10 away from the substrate 11.

[0096] Furthermore, just as the width of the first gap 19A / 19C in the first direction Z is greater than the width of the storage gate gap 19B in the first direction Z, the opening width of the gate line gap 18 can also be greater than the width of the storage gate gap 19B in the first direction Z (or the thickness of the storage gate sacrificial layer 121B). In one specific embodiment, the opening width of the gate line gap 18 can be greater than twice the width of the storage gate gap 19B in the first direction Z. That is, the opening width of the gate line gap 18 can be greater than twice the thickness of the storage gate sacrificial layer 121B. Specifically, the opening width of the gate line gap 18 can be the spacing distance between the opposite side walls of the gate line gap 18.

[0097] In the above embodiment, the step of removing the first gate material 20 located outside the storage gate gap 19B to expose the inner wall of the first gap 19A / 19C and obtain the storage gate layer 21 formed in the storage gate gap 19B may specifically include: using an isotropic etching process (e.g., wet etching process) to selectively etch the first gate material 20 relative to the interlayer insulating layer 122, the charge blocking layer 171 and the insulating capping layer 10 until the charge blocking layer 171 is exposed and then the etching is stopped, thereby ensuring that the charge blocking layer 171 covered by the first gate material 20 in the previous process steps can be exposed again in the first gap 19A / 19C after the etching is completed.

[0098] Specifically, the first gate material 20 located outside the aforementioned storage gate gap 19B may include a first gate material 20 formed on the side of the aforementioned insulating cover layer 10 away from the substrate 11, a first gate material 20 formed on the inner wall of the aforementioned first gaps 19A / 19C and partially filling the aforementioned first gaps 19A / 19C, and a first gate material 20 formed on the inner wall of the aforementioned gate line gap 18 and partially filling the aforementioned gate line gap 18.

[0099] Accordingly, after removing the first gate material 20 located outside the aforementioned storage gate gap 19B, the inner walls of the aforementioned first gaps 19A / 19C and the inner walls of the aforementioned gate line gaps 18, which were covered by the first gate material 20 in the preceding process steps, can be exposed again.

[0100] In some specific embodiments, such as Figure 7 , Figure 8 and Figure 9As shown, when the first gate material 20 located outside the aforementioned storage gate gap 19B is removed, the portion of the first gate material 20 in the aforementioned storage gate gap 19B that is in contact with the inner wall of the aforementioned gate line gap 18 can be removed simultaneously, thereby forming a first gap 22 between the storage gate layer 21 and the gate line gap 18. Furthermore, in subsequent processes, when the gate line gap 18 is filled with insulating material and / or metal material, the first gap 22 will also be filled by the insulating material and / or metal material.

[0101] Step S132: Remove the charge blocking layer exposed in the first gap to form a second gap including the first gap, thereby exposing the charge trapping layer in the second gap.

[0102] The cross-sectional structure diagram after step S132 can be as follows: Figure 10 As shown.

[0103] Specifically, a selective etchant can be used to selectively etch the charge blocking layer 171 exposed in the first gap 19A / 19C relative to the storage gate layer 21 and the charge trapping layer 172 through the gate line gap 18 and the first gap 19A / 19C until the charge trapping layer 172 is exposed and then the etching is stopped. In this way, after the etching is completed, it is ensured that the second gap 23 formed by removing the charge blocking layer 171 exposed in the first gap 19A / 19C by etching can expose part of the charge trapping layer 172.

[0104] It is understood that after the charge blocking layer 171 exposed in the first gap 19A / 19C is removed to form the second gap 23, the remaining charge blocking layer 171 in the channel structure 17 can be divided by the second gap 23 into at least two portions that are spaced apart in the first direction Z.

[0105] In some specific embodiments, such as Figure 10 As shown, during the etching process to remove the charge blocking layer 171 exposed in the first gap 19A / 19C to form the second gap 23, the portion of the interlayer insulating layer 122 exposed in the first gap 22 and the portion of the interlayer insulating layer 122 exposed in the gate line gap 18 can be removed simultaneously.

[0106] Step S133: Remove the charge trapping layer exposed to the second gap to form a select gate gap including the second gap.

[0107] The cross-sectional structural diagram after step S133 is completed can be shown as follows: Figure 11 As shown.

[0108] Specifically, a selective etchant can be used to selectively etch the charge trapping layer 172 exposed in the second gap 23 relative to the storage gate layer 21, charge tunneling layer 173 and interlayer insulating layer 122 via the gate line gap 18 and the second gap 23 until the charge tunneling layer 173 is exposed and then the etching is stopped. In this way, after the etching is completed, it is ensured that the selected gate gap 25 formed by removing the charge trapping layer 172 exposed in the second gap 23 by etching can expose part of the charge tunneling layer 173.

[0109] It is understood that after removing the charge trapping layer 172 exposed to the second gap 23 to form the select gate gap 25, the remaining charge trapping layer 172 in the channel structure 17 can be divided by the select gate gap 25 into at least two portions that are spaced apart in the first direction Z.

[0110] In some specific embodiments, the widths of the selected gate gap 25 in the direction parallel to the substrate 11 (e.g., direction X) may be equal in the first direction Z.

[0111] Step S14: Form a select gate layer in the select gate gap.

[0112] In one embodiment, such as Figure 11 , Figure 12 and Figure 13 As shown, step S14 may specifically include: depositing a second gate material 26 (e.g., polysilicon), filling the select gate gap 25 with the second gate material 26, and filling the gate gap 18 along the inner wall portion of the gate gap 18 with the second gate material 26; and removing the second gate material 26 located outside the select gate gap 25, leaving the unremoved second gate material 26 as the select gate layer 27.

[0113] Specifically, the thickness of the selected gate sacrificial layer 121A / 121C in the stacked structure 12 (or the width of the selected gate gap 25 in the first direction Z) can be smaller than the opening width of the gate line gap 18. In a specific example, the ratio of the thickness of the selected gate sacrificial layer 121A / 121C to the opening width of the gate line gap 18 can be between 0.2 and 0.7, for example, it can be 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, etc. The width of the selected gate gap 25 in the first direction Z can be equal to the thickness of the corresponding selected gate sacrificial layer 121A / 121C in the stacked structure 12.

[0114] Furthermore, in specific implementation, the second gate material 26 can be deposited along the inner wall of the selected gate gap 25 and the inner wall of the gate line slot 18. The deposition of the second gate material 26 is stopped after it fills the selected gate gap 25 and before it fills the gate line slot 18. This ensures that when the second gate material 26 fills the selected gate gap 25, the gate line slot 18 is not completely sealed by the second gate material 26, leaving some space unfilled. That is, the second gate material 26 completely fills the selected gate gap 25 and simultaneously forms on the inner wall of the gate line slot 18, partially filling the gate line slot 18.

[0115] In some specific embodiments, such as Figure 12 As shown, the above method may further include: during the deposition of the second gate material 26, the second gate material 26 is also formed on the side of the insulating cover layer 10 away from the substrate 11.

[0116] In the above embodiment, the step of removing the second gate material 26 located outside the selected gate gap 25 and leaving the unremoved second gate material 26 as the selected gate layer 27 may specifically include: using an isotropic etching process (e.g., wet etching process) to selectively etch the second gate material 26 relative to the interlayer insulating layer 122, the storage gate layer 21 and the insulating capping layer 10 until the inner wall of the gate line gap 18 covered by the second gate material 26 in the previous process step and the insulating capping layer 10 are exposed, and then the etching is stopped.

[0117] Specifically, the second gate material 26 located outside the selected gate gap 25 may include a second gate material 26 formed on the side of the insulating cover layer 10 away from the substrate 11, and a second gate material 26 formed on the inner wall of the gate line gap 18 and partially filling the gate line gap 18.

[0118] In some specific embodiments, such as Figure 13 As shown, when the second gate material 26 located outside the selected gate gap 25 is removed, the portion of the second gate material 26 in the selected gate gap 25 that is in contact with the inner wall of the gate line gap 18 can be removed simultaneously, thereby forming a second gap 28 between the selected gate layer 27 and the gate line gap 18. In subsequent processes, when the gate line gap 18 is filled with insulating material and / or metal material, the second gap 28 will also be filled with the insulating material and / or metal material.

[0119] In some alternative embodiments, the gate material (e.g., polysilicon) can be directly filled into the selected gate gap 25 to form a selected gate layer.

[0120] In this embodiment, as Figure 13 As shown, the selected gate layer 27 can be in contact with the charge tunneling layer 173 in the channel structure 17.

[0121] Accordingly, the selected gate layer 27 can provide a gate to the selected transistor (e.g., source selected transistor or drain selected transistor) in the memory cell string in the three-dimensional memory structure, and the charge tunneling layer 173 corresponding to the position of the selected gate layer 27 can provide a gate insulating layer to the selected transistor in the memory cell string in the three-dimensional memory structure, and the channel layer 174 corresponding to the position of the selected gate layer 27 can provide a channel region to the selected transistor in the memory cell string in the three-dimensional memory structure, thereby enabling the selected transistor in the memory cell string in the three-dimensional memory structure to be a MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as "MOS transistor").

[0122] Specifically, the memory cell string in the aforementioned three-dimensional memory structure may include a source-select transistor, a drain-select transistor, and multiple memory cells connected in series between the source-select transistor and the drain-select transistor. Furthermore, in one specific embodiment, only the source-select transistor of the memory cell string in the final three-dimensional memory structure may be a MOS transistor, or only the drain-select transistor of the memory cell string in the final three-dimensional memory structure may be a MOS transistor. In another specific embodiment, both the source-select transistor and the drain-select transistor of the memory cell string in the final three-dimensional memory structure may be MOS transistors.

[0123] It should be noted that, in Figure 16 In the embodiment shown, the storage gate layer 21' and the select gate layer 27' are formed by replacing the select gate sacrificial layer and the storage gate sacrificial layer in the stacked structure with the same replacement process and filling the gate material at the same position. The select transistors and storage cells contained in the storage cell string in the final three-dimensional storage structure have the same structure, that is, they are all storage structures. This will greatly affect the performance of the select transistor (e.g., threshold voltage stability, Id-Vg curve, etc.).

[0124] Furthermore, compared to Figure 16In the embodiment shown, after removing the select gate sacrificial layers 121A / 121C in the stacked structure 12 and before forming the select gate layer 27, the charge blocking layer 171 and the charge trapping layer 172 corresponding to the select gate sacrificial layer positions 121A / 121C are removed. This makes the select transistor of the memory cell string in the final fabricated three-dimensional memory structure a MOS transistor, thus avoiding the problem of poor performance of the select transistor of the memory cell string in the three-dimensional memory structure due to the use of the same structure as the memory cell.

[0125] Additionally, in some embodiments where the selected gate layer 27 is in contact with the charge tunneling layer 173 in the channel structure 17, after the selected gate gap 25 is formed and before the selected gate layer 27 is formed, such as... Figure 14 As shown, the above method may further include forming a gate insulating layer 29 in the selected gate gap 25 at a location corresponding to the channel layer 174. That is, the gate insulating layer 29 is formed on the remaining channel structure 17 (i.e., the channel structure 17 after the removal of at least the charge blocking layer 171 and the charge trapping layer 172 at the locations corresponding to the selected gate sacrificial layers 121A / 121C) exposed on the surface of the selected gate gap 25 extending along the first direction Z.

[0126] In a specific example, the aforementioned gate gap 25 can be formed by removing the gate sacrificial layers 121A / 121C and the charge blocking layer 171 and charge trapping layer 172 corresponding to the positions of the gate sacrificial layers 121A / 121C. In other words, step S13 can specifically include: removing the gate sacrificial layers 121A / 121C and removing the charge blocking layer 171 and charge trapping layer 172 corresponding to the positions of the gate sacrificial layers 121A / 121C to form the gate gap 25, thereby exposing the charge tunneling layer 173 corresponding to the positions of the gate sacrificial layers 121A / 121C in the gate gap 25.

[0127] Accordingly, step S15 may specifically include forming a gate insulating layer 29 on the surface of the charge tunneling layer 173 exposed in the select gate gap 25 extending along the first direction Z. For example, the gate insulating layer 29 may be formed by depositing a thin film deposition process (e.g., atomic layer deposition process) on the surface of the charge tunneling layer 173 exposed in the select gate gap 25 extending along the first direction Z.

[0128] Thus, the gate insulating layer 29 and the charge tunneling layer 173 corresponding to the selected gate layer 27 can jointly provide a gate insulating layer to the selected transistor in the memory cell string in the three-dimensional memory structure. That is, by forming this gate insulating layer 29, the thickness of the gate insulating layer of the selected transistor in the memory cell string in the final fabricated three-dimensional memory structure can be increased, thereby improving the high voltage withstand capability of the selected transistor in the three-dimensional memory structure and further improving the overall performance of the three-dimensional memory structure.

[0129] In another specific example, the aforementioned gate gap 25 can also be formed by removing the gate sacrificial layers 121A / 121C and the charge blocking layer 171, charge trapping layer 172, and charge tunneling layer 173 corresponding to the positions of the gate sacrificial layers 121A / 121C. In other words, step S13 can specifically include: removing the gate sacrificial layers 121A / 121C and removing the charge blocking layer 171, charge trapping layer 172, and charge tunneling layer 173 corresponding to the positions of the gate sacrificial layers 121A / 121C to form the gate gap 25, thereby exposing the channel layer 174 corresponding to the positions of the gate sacrificial layers 121A / 121C in the gate gap 25.

[0130] Accordingly, step S15 may specifically include forming a gate insulating layer 29 on the surface of the channel layer 174 exposed above the select gate gap 25, extending along the first direction Z. For example, the gate insulating layer 29 may be formed by depositing a thin film deposition process (e.g., atomic layer deposition process) on the surface of the channel layer 174 exposed above the select gate gap 25, extending along the first direction Z.

[0131] Thus, the gate insulating layer 29 can replace the charge tunneling layer 173 corresponding to the selected gate sacrificial layer 121A / 121C positions, and provide a gate insulating layer to the selected transistor in the memory cell string in the three-dimensional memory structure. This ensures a greater thickness and better quality of the gate insulating layer of the selected transistor in the memory cell string in the final three-dimensional memory structure, thereby improving the overall performance of the three-dimensional memory structure.

[0132] Specifically, the material of the aforementioned gate insulating layer 29 may be, but is not limited to, insulating materials such as silicon oxide.

[0133] In the above embodiments, such as Figure 15As shown, after forming the selected gate layer 27, the method may further include forming a gate line gap structure 30 in the gate line gap 18. Specifically, the gate line gap structure 30 can be formed by filling the gate line gap 18 with an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials with high dielectric constants). In some alternative embodiments, a gate line gap structure 30 with a common source electrode can also be obtained by filling the gate line gap 18 with an insulating material (e.g., silicon oxide) as a spacer layer and a conductive material (e.g., titanium or titanium nitride, polysilicon, and / or tungsten) as a common source electrode.

[0134] The method for fabricating a three-dimensional memory structure provided in this embodiment involves forming a stacked structure on a substrate. The stacked structure includes multiple gate sacrificial layers and multiple interlayer insulating layers, which are alternately stacked in a first direction. The multiple gate sacrificial layers include a select gate sacrificial layer and a storage gate sacrificial layer. Then, a channel structure is formed that penetrates the stacked structure in the first direction. The channel structure includes a charge trapping layer and a charge blocking layer surrounding the charge trapping layer. Next, the select gate sacrificial layer is removed, and at least the charge blocking layer and charge trapping layer corresponding to the position of the select gate sacrificial layer are removed to form a select gate gap. Then, a select gate layer is formed in the select gate gap, thereby enabling the select transistors in the memory cell string of the final fabricated three-dimensional memory to be MOS transistors. This improves the performance of the select transistors in the three-dimensional memory (e.g., threshold voltage stability, Id-Vg curve, etc.) and enhances the overall performance of the three-dimensional memory.

[0135] The three-dimensional storage structure fabricated according to the above-described method embodiments of this application is as follows: Figure 15 As shown, the three-dimensional memory structure includes: a stack, which includes a plurality of gate layers 21 / 27 and a plurality of interlayer insulating layers 122, wherein the gate layers 21 / 27 and the interlayer insulating layers 122 are alternately stacked in a first direction Z, and the plurality of gate layers 21 / 27 include a select gate layer 27 and a storage gate layer 21; and a channel structure 17 extending through the stack in the first direction Z, wherein the channel structure 17 includes a charge trapping layer 172 and a charge blocking layer 171 surrounding the charge trapping layer 172, and the charge trapping layer 172 is disconnected at a position corresponding to the select gate layer 27, and the charge blocking layer 171 is disconnected at a position corresponding to the select gate layer 27.

[0136] In this embodiment, the charge trapping layer 172 can be continuous at the location corresponding to the storage gate layer 21, without being disconnected. Similarly, the charge blocking layer 171 can be continuous at the location corresponding to the select gate layer 27, without being disconnected.

[0137] Specifically, the storage gate layer 21 can be in contact with the charge blocking layer 171, or it can be insulated from the charge blocking layer 171 by a gap. The channel structure 17 has a sidewall extending along the first direction Z, and since the charge trapping layer 172 and the charge blocking layer 171 in the channel structure 17 are disconnected at the position corresponding to the select gate layer 27, the corresponding sidewall is recessed in a direction away from the select gate layer 27 at the position corresponding to the select gate layer 27, thus forming a groove in the sidewall. Wherein, as Figures 9 to 11 As shown, the groove can correspond to the remaining portion of the gate gap 25 selected in the above method embodiment, excluding the first gap 19A / 19C.

[0138] Specifically, the aforementioned groove extends through the charge blocking layer 171 and the charge trapping layer 172 to separate a portion of the charge blocking layer 171 located on one side of the groove in the first direction Z from another portion of the charge blocking layer 171 located on the other side of the groove in the first direction Z, and to separate a portion of the charge trapping layer 172 located on one side of the groove in the first direction Z from another portion of the charge trapping layer 172 located on the other side of the groove in the first direction Z.

[0139] Specifically, the aforementioned channel structure 17 may further include a charge tunneling layer 173 surrounded by a charge trapping layer 172 and a channel layer 174 surrounded by the charge tunneling layer 173.

[0140] In one specific embodiment, such as Figure 15 As shown, the charge tunneling layer 173 in the channel structure 17 can be continuous at the position corresponding to the select gate layer 27, and is not broken. Specifically, the select gate layer 27 can be in contact with the charge tunneling layer 173 in the channel structure 17, or it can be provided with an insulating gap from the charge tunneling layer 173 in the channel structure 17.

[0141] Thus, the aforementioned gate selection layer 27 can provide a gate to the selection transistor (e.g., source selection transistor or drain selection transistor) in the memory cell string in the three-dimensional memory structure, and the charge tunneling layer 173 corresponding to the location of the aforementioned gate selection layer 27 can provide a gate insulating layer to the selection transistor in the memory cell string in the three-dimensional memory structure, and the portion of the aforementioned channel layer 174 corresponding to the location of the aforementioned gate selection layer 27 can provide a channel region to the selection transistor in the memory cell string in the three-dimensional memory structure, thereby enabling the selection transistor in the memory cell string of the aforementioned three-dimensional memory structure to be a MOS transistor.

[0142] In some specific embodiments, such as Figure 15As shown, the above-mentioned three-dimensional memory structure may further include a gate insulating layer 29, which is located between the selected gate layer 27 and the channel layer 174 in the second direction X, and the second direction X is perpendicular to the first direction Z.

[0143] Specifically, the thickness of the gate insulating layer 29 in the second direction X can be greater than or equal to the thickness of the charge tunneling layer 173 in the second direction X.

[0144] In a specific example, such as Figure 15 As shown, the charge tunneling layer 173 in the channel structure 17 can be continuous at the position corresponding to the select gate layer 27, without being interrupted. Furthermore, the gate insulating layer 29 can be located between the select gate layer 27 and the charge tunneling layer 173 in the second direction Z, and can be in contact with the charge tunneling layer 173. The thickness of the gate insulating layer 29 in the second direction X can be greater than, equal to, or less than the thickness of the charge tunneling layer 173 in the second direction X.

[0145] Thus, the gate insulating layer 29 and the charge tunneling layer 173 corresponding to the position of the selected gate layer 27 can jointly provide a gate insulating layer to the selected transistor in the memory cell string in the three-dimensional memory structure, thereby enabling the selected transistor in the memory cell string in the three-dimensional memory structure to be a MOS transistor.

[0146] It is understandable that by forming the gate insulating layer 29, the thickness of the gate insulating layer of the selection transistor in the memory cell string of the above-mentioned three-dimensional memory structure can be increased, thereby improving the high voltage resistance of the selection transistor in the three-dimensional memory structure, and further improving the overall performance of the three-dimensional memory structure.

[0147] In another specific example, the charge tunneling layer 173 in the channel structure 17 can also be disconnected at the position corresponding to the selected gate layer 27, and the charge tunneling layer 173 can also extend through the groove, thus separating the part of the charge tunneling layer 173 located on one side of the groove in the first direction Z from the other part of the charge tunneling layer 173 located on the other side of the groove in the first direction Z.

[0148] Specifically, the gate insulating layer 29 can be located between the selected gate layer 27 and the channel layer 174 in the second direction Z, and can be in contact with the channel layer 174. The thickness of the gate insulating layer 29 in the second direction X can be greater than or equal to the thickness of the charge tunneling layer 173 in the second direction X.

[0149] Thus, the gate insulating layer 29 can independently provide a gate insulating layer to the select transistor in the memory cell string in the three-dimensional memory structure, thereby enabling the select transistor in the memory cell string of the three-dimensional memory structure to be a MOS transistor, and ensuring a greater thickness and better quality of the gate insulating layer of the select transistor in the memory cell string of the final three-dimensional memory structure, so as to improve the overall performance of the three-dimensional memory structure.

[0150] In the above embodiments, the memory cell string in the three-dimensional memory structure may include a source-select transistor, a drain-select transistor, and a plurality of memory cells connected in series between the source-select transistor and the drain-select transistor. Furthermore, in one specific embodiment, only the source-select transistor of the memory cell string in the three-dimensional memory structure may be a MOS transistor, or only the drain-select transistor of the memory cell string in the three-dimensional memory structure may be a MOS transistor. In another specific embodiment, both the source-select transistor and the drain-select transistor of the memory cell string in the three-dimensional memory structure may be MOS transistors.

[0151] Accordingly, the number of selected gate layers 27 in the stack can be at least one, and the number of stored gate layers 21 in the stack can be multiple. The multiple stored gate layers 21 can be stacked continuously at intervals, and the selected gate layer 27 can be located on a first side of the multiple stored gate layers 21 in the first direction Z, or the selected gate layer 27 can be located on a second side of the multiple stored gate layers in the first direction Z opposite to the first side.

[0152] In other embodiments, the number of the selected gate layers 27 may be multiple, and the multiple selected gate layers 27 may be disposed on the first side and the second side of the multiple storage gate layers 21 in the first direction Z.

[0153] Specifically, in embodiments where the number of select gate layers 27 is at least one, the at least one select gate layer 27 may include at least one first select gate layer or at least one second select gate layer. In embodiments where the number of select gate layers 27 is multiple, the multiple select gate layers 27 may include both at least one first select gate layer and at least one second select gate layer.

[0154] The first and second selected gate layers can be located on opposite sides of the plurality of memory gate layers 21 in the first direction Z. Furthermore, the first selected gate layer can provide a gate to the drain selected transistor in the memory cell string in the three-dimensional memory structure, and the second selected gate layer can provide a gate to the source selected transistor in the memory cell string in the three-dimensional memory structure.

[0155] In the above embodiments, the thickness of the selected gate layer 27 in the stack can be greater than the thickness of the storage gate layer 21. Specifically, the ratio of the thickness of the selected gate layer 27 to the thickness of the storage gate layer 21 in the stack can be between 2 and 6, for example, it can be 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, etc.

[0156] In some specific embodiments, the above-described three-dimensional storage structure may further include a gate line slot structure 30 that extends through the stack in the first direction Z, and the thickness of the selected gate layer 27 in the stack may be less than the width of the gate line slot structure 30 in the second direction X.

[0157] Specifically, the ratio of the thickness of the selected gate layer 27 to the width of the storage gate layer 21 in the second direction X in the above stack can be between 0.2 and 0.7, for example, it can be 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, etc.

[0158] It should be noted that the various structures of the three-dimensional storage structure in this embodiment can refer to the specific implementation methods described in the above method embodiments, so they will not be repeated here.

[0159] The three-dimensional memory structure provided in this embodiment improves the performance of the selection transistors in the three-dimensional memory (e.g., threshold voltage stability, Id-Vg curve, etc.) and improves the overall performance of the three-dimensional memory by designing the selection transistors of the memory cell string in the three-dimensional memory structure as MOS transistors.

[0160] Accordingly, such as Figure 17 As shown, this application embodiment also provides a three-dimensional memory 100, which includes a three-dimensional storage structure 200 and a peripheral circuit structure 300. The peripheral circuit structure 300 is electrically connected to the three-dimensional storage structure 200, and the peripheral circuit structure 300 is capable of storing data in the three-dimensional storage structure 200 or reading data from the three-dimensional storage structure 200.

[0161] The three-dimensional storage structure 200 can be the same as the three-dimensional storage structure described in any of the embodiments above, so it will not be described again here.

[0162] The three-dimensional memory provided in this application embodiment has the same beneficial effects as the three-dimensional storage structure described above due to the three-dimensional storage structure provided in this application embodiment.

[0163] Accordingly, such as Figure 18 As shown, this application embodiment also provides a storage system 40, which includes a controller 41 and a three-dimensional memory 42. The controller 41 is coupled to the three-dimensional memory 42 and is used to control the three-dimensional memory 42 to store data.

[0164] The three-dimensional memory 42 may be the same as the three-dimensional memory described in any of the embodiments above, and therefore will not be repeated here. The controller 41 controls the three-dimensional memory 42 via channel CH, and the three-dimensional memory 42 can perform operations based on the control of the controller 41 in response to requests from the host 50. The three-dimensional memory 42 receives commands CMD and addresses ADDR from the controller 41 via channel CH and accesses the region selected from the memory cell array in response to that address. In other words, the three-dimensional memory 42 can perform internal operations corresponding to commands on the region selected by the address.

[0165] In some implementations, the storage system 40 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0166] Specifically, the aforementioned storage system 40 can be used in terminal products such as computers, televisions, set-top boxes, and in-vehicle systems.

[0167] The storage system provided in this embodiment improves the performance of the selection transistors in the three-dimensional memory (e.g., threshold voltage stability, Id-Vg curve, etc.) and the overall performance of the three-dimensional memory by designing the selection transistors of the storage cell string in the three-dimensional memory as MOS transistors.

[0168] Accordingly, such as Figure 19 As shown, this application embodiment also provides an electronic device 60, which includes the storage system 61 provided in the above-mentioned application embodiment. Specifically, the electronic device 60 can be any device that can store data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle equipment, wearable device, power bank, etc.

[0169] An electronic device provided in this application embodiment has the same beneficial effects as the storage system described above due to the inclusion of the storage system provided in this application embodiment.

[0170] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included within the protection scope of the present application.

Claims

1. A method for fabricating a three-dimensional storage structure, characterized in that, include: A stacked structure is formed, the stacked structure including a plurality of gate sacrificial layers and a plurality of interlayer insulating layers, the gate sacrificial layers and the interlayer insulating layers being alternately stacked in a first direction, the plurality of gate sacrificial layers including a select gate sacrificial layer and a storage gate sacrificial layer; A channel structure is formed that extends through the stacked structure in the first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer; Remove the selected gate sacrificial layer, and at least remove the charge blocking layer and the charge trapping layer corresponding to the location of the selected gate sacrificial layer to form a selected gate gap; A select gate layer is formed in the select gate gap; The step of forming the selected gate gap specifically includes: Remove the selected gate sacrificial layer to form a first gap, thereby exposing a portion of the charge blocking layer in the first gap; Remove the charge blocking layer exposed in the first gap to form a second gap including the first gap, thereby exposing a portion of the charge trapping layer in the second gap; Remove the charge trapping layer exposed in the second gap to form the select gate gap including the second gap; The thickness of the selected gate sacrificial layer is greater than the thickness of the storage gate sacrificial layer; the ratio of the thickness of the selected gate sacrificial layer to the thickness of the storage gate sacrificial layer is between 2 and 6. The three-dimensional memory structure includes a gate line slot that extends through the stacked structure in the first direction, and the thickness of the selected gate sacrificial layer is less than the width of the gate line slot.

2. The method for fabricating a three-dimensional storage structure according to claim 1, characterized in that, The method further includes: When forming the first gap, the memory gate sacrificial layer is removed to form the memory gate gap; Before forming the second gap, a storage gate layer is formed in the storage gate gap.

3. The method for fabricating a three-dimensional storage structure according to claim 2, characterized in that, The step of forming the memory gate layer specifically includes: Deposit gate material and fill the storage gate gap with the gate material, and fill the first gap along the inner wall portion of the first gap with the gate material; Remove the gate material located outside the storage gate gap to expose the inner wall of the first gap and obtain the storage gate layer formed in the storage gate gap.

4. The method for fabricating a three-dimensional storage structure according to claim 1, characterized in that, The channel structure further includes a channel layer surrounded by the charge trapping layer, and the method further includes: After the selected gate gap is formed, and before the selected gate layer is formed, a gate insulating layer is formed in the selected gate gap corresponding to the channel layer location.

5. The method for fabricating a three-dimensional storage structure according to claim 4, characterized in that, The channel structure further includes a charge tunneling layer surrounding the channel layer and being surrounded by the charge trapping layer. The step of exposing a portion of the charge tunneling layer in the selected gate gap and forming the gate insulating layer specifically includes: The gate insulating layer is formed on the surface of the charge tunneling layer that is exposed in the selected gate gap and extends along the first direction.

6. The method for fabricating a three-dimensional storage structure according to claim 4, characterized in that, The channel structure further includes a charge tunneling layer, which surrounds the channel layer and is surrounded by the charge trapping layer, and the step of forming the selected gate gap specifically includes: Remove the selected gate sacrificial layer, and remove the charge blocking layer, the charge trapping layer and the charge tunneling layer corresponding to the location of the selected gate sacrificial layer to form the selected gate gap, thereby exposing a portion of the channel layer in the selected gate gap; Furthermore, the step of forming the gate insulating layer specifically includes: The gate insulating layer is formed on the surface of the channel layer that is exposed on the selected gate gap and extends along the first direction.

7. The method for fabricating a three-dimensional storage structure according to claim 1, characterized in that, The number of the memory gate sacrificial layers is multiple, and the multiple memory gate sacrificial layers are stacked continuously with intervals, wherein, The number of selected gate sacrificial layers is at least one, and the selected gate sacrificial layer is located on a first side of the plurality of memory gate sacrificial layers in the first direction, or the selected gate sacrificial layer is located on a second side of the plurality of memory gate sacrificial layers in the first direction, with the first side and the second side opposite to each other; or, The number of selected gate sacrificial layers is multiple, and the multiple selected gate sacrificial layers are respectively disposed on the first side and the second side of the multiple storage gate sacrificial layers in the first direction.

8. The method for fabricating a three-dimensional storage structure according to claim 1, characterized in that, The ratio of the thickness of the selected gate sacrificial layer to the width of the gate line gap is between 0.2 and 0.

7.

9. A three-dimensional storage structure, characterized in that, include: A stack, the stack including a plurality of gate layers and a plurality of interlayer insulating layers, the gate layers and the interlayer insulating layers being alternately stacked in a first direction, the plurality of gate layers including a select gate layer and a storage gate layer; A channel structure extending through the stack in a first direction, the channel structure including a charge trapping layer and a charge blocking layer surrounding the charge trapping layer, wherein the charge blocking layer is disconnected at a location corresponding to the selected gate layer; The channel structure further includes a channel layer surrounded by the charge trapping layer, and the three-dimensional storage structure further includes: A gate insulating layer, wherein the gate insulating layer is located between the selected gate layer and the channel layer in a second direction, the second direction being perpendicular to the first direction; The thickness of the select gate layer is greater than the thickness of the storage gate layer; the ratio of the thickness of the select gate layer to the thickness of the storage gate layer is between 2 and 6. The three-dimensional storage structure also includes: A gate line slot structure extends through the stack in the first direction, and the thickness of the selected gate layer is less than the width of the gate line slot structure.

10. The three-dimensional storage structure according to claim 9, characterized in that, The channel structure further includes a charge tunneling layer surrounding the channel layer and being surrounded by the charge trapping layer, and the thickness of the gate insulating layer in the second direction is greater than or equal to the thickness of the charge tunneling layer in the second direction.

11. The three-dimensional storage structure according to claim 9, characterized in that, The ratio of the thickness of the selected gate layer to the width of the gate slot structure is between 0.2 and 0.

7.

12. The three-dimensional storage structure according to claim 9, characterized in that, The number of the memory gate layers is multiple, and the multiple memory gate layers are stacked continuously with intervals, wherein, The number of selected gate layers is at least one, and the selected gate layer is located on a first side of the plurality of memory gate layers in the first direction, or the selected gate layer is located on a second side of the plurality of memory gate layers in the first direction opposite to the first side; or, The number of selected gate layers is multiple, and the multiple selected gate layers are respectively disposed on the first side and the second side of the multiple storage gate layers in the first direction.

13. A three-dimensional memory, characterized in that, The three-dimensional memory includes a three-dimensional storage structure as described in any one of claims 9 to 12 and a peripheral circuit structure, wherein the peripheral circuit structure is electrically connected to the three-dimensional storage structure.

14. A storage system, characterized in that, The storage system includes a controller and the three-dimensional memory of claim 13, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

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