An enhanced transistor and method of manufacturing the same

Abstract

The application provides an enhanced transistor manufacturing method and an enhanced transistor, and relates to the field of semiconductor devices. The enhanced transistor manufacturing method comprises the following steps: providing an epitaxial wafer, wherein source and drain electrodes are formed on the epitaxial wafer, and the epitaxial wafer has a gate deposition area; depositing a copper oxide film on the gate deposition area; depositing a gate material on the surface of the copper oxide film to form a gate, so as to obtain an enhanced transistor. Compared with the prior art, the method for depositing the copper oxide film is easier to control, and the P-type metal layer and the epitaxial layer of the epitaxial wafer do not need to be etched, so that the manufacturing process can be simplified to a certain extent, and the problem that the performance of the device is affected due to the difficulty in accurately controlling the manufacturing process can be avoided. In the manufacturing process, the ratio of divalent copper ions to monovalent copper ions in the copper oxide film can be determined, so that enhanced transistors with different threshold voltages can be manufactured.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically to an enhancement transistor and a method for manufacturing an enhancement transistor. Background Technology

[0002] Enhancement-mode HEMTs (High Electron Mobility Transistors) have a P-type gallium nitride (GaN) layer at the gate to forward bias the device's threshold voltage, thus forming an enhancement-mode HEMT. Current manufacturing processes for enhancement-mode HEMTs typically employ etching. Specifically, a P-type GaN layer is first epitaxially deposited on the surface of an epitaxial wafer. Then, the gate is fabricated on the surface of the P-type GaN layer. Next, a portion of the P-type GaN layer and a portion of the epitaxial layer are selectively etched using dry etching. Finally, source and drain electrodes are formed at the etched areas. However, in current manufacturing processes, due to the difficulty in precisely controlling the etching rate and precision, under-etching or over-etching of the P-type GaN layer and a portion of the epitaxial layer is prone to occur, affecting the device performance of the enhancement-mode HEMT. Summary of the Invention

[0003] In view of this, this application aims to provide a method for manufacturing an enhancement transistor and an enhancement transistor, thereby reducing the adverse effects on the performance of the enhancement transistor caused by the difficulty in precisely controlling the manufacturing process.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing an enhancement-mode transistor, comprising: providing an epitaxial wafer, wherein an active drain electrode is formed on the epitaxial wafer, and the epitaxial wafer has a gate deposition region; depositing a copper oxide film in the gate deposition region; and depositing a gate material on the surface of the copper oxide film to form a gate, thereby obtaining an enhancement-mode transistor.

[0005] In this embodiment, a copper oxide film is used as the P-type metal layer at the gate. This allows for the deposition of the copper oxide film on the epitaxial wafer where the active and drain electrodes are formed, in a deposition process. Gate material is then deposited on the surface of the copper oxide film to form the gate, thereby obtaining an enhancement-mode transistor. Compared to existing technologies, the copper oxide film deposition method is easier to control and eliminates the need for etching the P-type metal layer and the epitaxial layer of the epitaxial wafer. This simplifies the manufacturing process and avoids performance degradation caused by inaccurate manufacturing process control. Furthermore, since the source and drain electrodes are formed on the surface of the epitaxial layer, post-etching electrode fabrication is reduced, further simplifying the manufacturing process.

[0006] In one embodiment, depositing a copper oxide film in the gate deposition area includes: determining a required film thickness; determining a target deposition time, target deposition power, target gas flow rate, and target substrate temperature corresponding to the required film thickness based on the relationship between the thickness of the copper oxide film and deposition time, deposition power, gas flow rate, and substrate temperature; and depositing a copper oxide film of a corresponding thickness in the gate deposition area based on the target deposition time, the target deposition power, the target gas flow rate, and the target substrate temperature.

[0007] In this embodiment, the thickness of the copper oxide film can be accurately controlled by controlling the process parameters during deposition. Based on the relationship between the thickness of the copper oxide film and deposition time, deposition power, gas flow rate, and substrate temperature, the process parameters corresponding to the required film thickness can be determined. By controlling the deposition power, gas flow rate, and substrate temperature, the thickness of the formed copper oxide film layer can be accurately controlled.

[0008] In one embodiment, the deposition of a copper oxide film in the gate deposition region further includes: during the deposition of the copper oxide film, introducing a dopant material to increase the hole concentration of the copper oxide film.

[0009] In this embodiment, by appropriately doping the copper oxide film, the hole concentration of the copper oxide film in the enhancement transistor can be effectively increased, thereby increasing the threshold voltage. Thus, a higher-performance enhancement transistor can be fabricated.

[0010] In one embodiment, depositing a copper oxide film in the gate deposition region includes: depositing the copper oxide film in the gate deposition region based on a copper target and a mixed gas containing oxygen.

[0011] In this embodiment, a copper oxide film is deposited and grown in the gate deposition area by using a copper target and an oxygen-containing mixed gas. The deposition method is easy to control, thereby enabling precise control over the copper oxide film and, further, the performance of the enhancement transistor.

[0012] In one embodiment, the oxygen-containing mixed gas is a mixture of argon and oxygen; the deposition of the copper oxide film in the gate deposition area based on the copper target and the oxygen-containing mixed gas includes: determining the ratio of divalent copper ions to monovalent copper ions in the desired copper oxide film; determining a target ratio of argon to oxygen in the mixed gas based on the proportional correspondence between the ratio of argon to oxygen in the mixed gas and the ratio of divalent copper ions to monovalent copper ions in the copper oxide film; and introducing the mixed gas with the target ratio to deposit the copper oxide film having the corresponding ratio of divalent copper ions to monovalent copper ions.

[0013] In this embodiment, the copper oxide film includes divalent copper ions and monovalent copper ions. Different ratios of divalent and monovalent copper ions will have different effects on the performance of the enhancement-mode transistor, primarily affecting the hole concentration of the copper oxide film. By controlling the oxygen ratio in the mixed gas input during deposition, the ratio of divalent to monovalent copper ions in the formed copper oxide film can be controlled. Therefore, users can control the proportion of components in the generated copper oxide film according to their needs by controlling the ratio of argon to oxygen in the mixed gas, so that the formed transistor meets their performance requirements, thereby achieving control over the performance of the desired device.

[0014] In one embodiment, depositing a copper oxide film in the gate deposition region includes: forming the copper oxide film by sputtering copper oxide in the gate deposition region.

[0015] In this embodiment, a copper oxide film is sputtered in the gate deposition area using a copper oxide target. The sputtering method is easy to control and easy to dopant, thereby enabling precise control of the copper oxide film and device performance.

[0016] In one embodiment, after depositing a gate material on the surface of the copper oxide film to form a gate to obtain an enhancement-mode transistor, the method further includes: determining a corresponding target post-annealing parameter based on the relationship between the thickness of the copper oxide film and the post-annealing parameter; and performing post-annealing on the gate based on the target post-annealing parameter.

[0017] In this embodiment, post-annealing of the gate facilitates interface reconstruction at the contact surface between the copper oxide film and the AlGaN (aluminum gallium nitride) barrier layer, thereby reducing interface states and increasing the work function of the copper oxide film. This further enhances the conduction band of the AlGaN / GaN heterojunction, thus increasing the threshold voltage of the enhancement-mode transistor. By analyzing the relationship between the post-annealing parameters and the copper oxide film thickness, the corresponding target post-annealing parameters can be determined, thereby achieving precise control over the gate post-annealing.

[0018] Secondly, embodiments of this application provide an enhancement transistor, comprising: an epitaxial wafer including an epitaxial layer, wherein an active drain electrode is formed on the surface of the epitaxial layer; a copper oxide film deposited on the epitaxial layer; and a gate electrode deposited on the copper oxide film; wherein the copper oxide film comprises divalent copper ions and monovalent copper ions.

[0019] In this embodiment, by depositing a copper oxide film between the epitaxial layer and the gate, the threshold voltage of the device can be forward biased, thereby making the transistor an enhancement-mode transistor. Since the copper oxide film layer includes divalent copper ions and monovalent copper ions, enhancement-mode transistors with different threshold voltages can be fabricated by determining different ratios of divalent and monovalent copper ions.

[0020] In one embodiment, the epitaxial layer includes a GaN cap layer and an AlGaN barrier layer. The surface of the epitaxial wafer is a GaN cap layer, which covers the AlGaN barrier layer. The GaN cap layer has a via, through which a portion of the AlGaN barrier layer is exposed. The copper oxide film is deposited on the exposed area of ​​the AlGaN barrier layer.

[0021] In this embodiment, by depositing a copper oxide film on the exposed surface of the AlGaN barrier layer, an enhancement-type transistor with a recessed gate can be obtained.

[0022] In one embodiment, the copper oxide film is in contact with the source and drain electrodes, respectively.

[0023] In this embodiment, by contacting the copper oxide film with the source and drain electrodes respectively, an enhancement transistor with a MIS (Metal-Insulator-Semiconductor) structure or a grooved gate enhancement transistor with a MIS structure can be obtained.

[0024] Other features and advantages of this disclosure will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an enhancement transistor provided in an embodiment of this application;

[0028] Figure 2This is a schematic diagram of the structure of a grooved gate enhancement transistor provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of a MIS structure transistor provided in an embodiment of this application;

[0030] Figure 4 This application provides a schematic diagram of a grooved gate enhancement transistor with a MIS structure.

[0031] Figure 5 This is a flowchart illustrating an enhancement transistor manufacturing method provided in an embodiment of this application.

[0032] Icons: Source 111; Drain 112; Substrate 113; Buffer layer 114; AlGaN barrier layer 115; GaN cap layer 116; AlN spacer layer 117; Copper oxide film 120; Gate 130; Passivation layer 140. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] Please see Figure 1 , Figure 1 This is a schematic diagram of an enhancement transistor provided in an embodiment of this application.

[0035] The enhancement transistor includes an epitaxial wafer, a copper oxide film 120, and a gate 130.

[0036] An epitaxial wafer includes an epitaxial layer and a source 111 and a drain 112 formed on the surface of the epitaxial layer.

[0037] In this embodiment, an epitaxial layer covers the surface of the substrate 113. The epitaxial layer may include a buffer layer 114 and an AlGaN (aluminum gallium nitride) barrier layer 115 that are covered layer by layer. The substrate 113 may be a silicon substrate, and the buffer layer is a GaN layer composed of GaN material.

[0038] In some embodiments, the epitaxial layer may further include a GaN cap layer 116 covering the surface of the AlGaN barrier layer 115, and an AlN spacer layer (aluminum nitride barrier layer) 117 disposed between the buffer layer 114 and the AlGaN barrier layer 115. The GaN cap layer 116 can effectively improve the electron mobility of the two-dimensional electron gas, thereby increasing the Schottky barrier of the heterojunction and reducing the gate leakage current.

[0039] It is understood that the epitaxial layer structure of the epitaxial wafer can also refer to the epitaxial layer structure of HEMT devices in the prior art, and this application is not limited thereto.

[0040] A copper oxide film 120 is deposited on the epitaxial layer, and a gate 130 is deposited on the copper oxide film layer.

[0041] In this embodiment, a gate region is provided on the surface of the epitaxial layer for disposing a gate. A copper oxide film is also provided between the surface of the epitaxial layer and the gate.

[0042] In this embodiment, the copper oxide film 120 is CuO. x The composition, wherein the value of X can range from 0.5 to 1, specifically, the copper oxide film 120 is composed of divalent copper ions and monovalent copper ions.

[0043] In this embodiment, the ratio of divalent to monovalent copper ions in the copper oxide film 120 affects the device performance of the enhancement-mode transistor. A higher ratio of divalent to monovalent copper ions results in a higher hole concentration in the copper oxide film 120 layer, leading to a greater forward bias of the device's threshold voltage (i.e., a higher threshold voltage in the normal state). This reduces leakage current in the off-state. Therefore, by determining different ratios of divalent to monovalent copper ions, enhancement-mode transistors with different threshold voltages can be fabricated. For example, the forward bias of the threshold voltage is 0–3V, but the specific value can be determined based on other factors such as the device substrate, process, and doping.

[0044] In this embodiment, the gate 130 can be a Schottky gate made of nickel / gold or an ohmic gate made of titanium / gold.

[0045] In one embodiment, the enhancement transistor further includes a passivation layer 140 covering the surface of the epitaxial layer.

[0046] In this embodiment, the passivation layer has through holes at the source / drain electrodes and the gate to expose the source / drain electrodes and the gate.

[0047] In this embodiment, by depositing a copper oxide film between the epitaxial layer and the gate, the device threshold voltage can be forward biased, thereby making the transistor an enhancement-mode transistor. Since the copper oxide film layer includes divalent copper ions and monovalent copper ions, enhancement-mode transistors with different threshold voltages can be manufactured by determining different ratios of divalent copper ions to monovalent copper ions.

[0048] In one embodiment, the AlGaN barrier layer 115 of the epitaxial wafer can also be an ultrathin barrier layer with a thickness of less than 5 nm, thereby the enhancement transistor is an enhancement transistor with an ultrathin barrier.

[0049] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a grooved gate enhancement transistor provided in an embodiment of this application. Figure 2 The transistor shown is Figure 1 The transistors shown are largely the same; for a description of their similarities, please refer to [link to relevant documentation]. Figure 1 The corresponding embodiment differs in that: the copper oxide film 120(a) and Figure 1 The transistors shown are deposited at different locations, as detailed below.

[0050] In one embodiment, the surface epitaxial layer of the epitaxial wafer is a GaN cap layer 116, which covers the AlGaN barrier layer 115. The GaN cap layer 116 has a via that exposes the AlGaN barrier layer 115, and a copper oxide film 120 is deposited on the exposed surface of the AlGaN barrier layer 115.

[0051] In this embodiment, the epitaxial wafer can also be an epitaxial wafer fabricated using a grooved gate process, having a groove in the gate region. This groove can be considered as a via, penetrating the GaN layer 116 and exposing a portion of the AlGaN barrier layer 115. Thus, a copper oxide film can be deposited on the exposed surface of the AlGaN barrier layer 115, and the gate is deposited on the surface of the copper oxide film. The enhancement-mode transistor with this structure is a grooved gate enhancement-mode transistor.

[0052] Figure 3 This is a schematic diagram of a MIS structure transistor provided in an embodiment of this application.

[0053] Figure 3 The transistor shown is Figure 1 The transistors shown are largely the same; for a description of their similarities, please refer to [link to relevant documentation]. Figure 1 The corresponding embodiment differs in that the copper oxide film 120(b) is connected to the source and drain electrodes.

[0054] In one embodiment, the copper oxide film 120(b) is in contact with the source and drain electrodes, respectively.

[0055] In this embodiment, the copper oxide film 120(b) is in contact with the source 111 and the drain 112, respectively. Thus, the enhancement transistor is an enhancement transistor with a MIS (Metal-Insulator-Semiconductor) structure.

[0056] Figure 4 This is a schematic diagram of a grooved gate enhancement transistor with a MIS structure provided in an embodiment of this application.

[0057] Figure 4 The transistor shown is Figure 2 , Figure 3The transistors shown are largely the same; for a description of their similarities, please refer to [link to relevant documentation]. Figure 2 , Figure 3 The corresponding embodiment differs in that the device has a grooved gate structure and the copper oxide film (c) is connected to the source and drain electrodes.

[0058] In this embodiment, the copper oxide film 120(c) of the enhancement transistor is deposited on the surface of the AlGaN barrier layer 115 and is in contact with the source and drain electrodes. Thus, the enhancement transistor is a grooved gate enhancement transistor with a MIS structure.

[0059] Based on the same inventive concept, this application provides a manufacturing method corresponding to the aforementioned enhancement-mode transistor. Please refer to [link / reference]. Figure 5 , Figure 5 This is a flowchart illustrating a method for manufacturing an enhancement transistor, as provided in an embodiment of this application. The method may include the following steps.

[0060] S110 provides an epitaxial wafer on which an active drain electrode is formed, and the epitaxial wafer has a gate deposition region.

[0061] In this embodiment, a pre-fabricated epitaxial wafer without source / drain electrodes for a high electron mobility transistor (HEMT) can be obtained first. Exemplarily, the epitaxial wafer without source / drain electrodes includes a substrate and an epitaxial layer covering the substrate. The epitaxial layer may include a GaN buffer layer, an AlN spacer layer, an AlGaN barrier layer, and a GaN cap layer sequentially stacked from the direction closest to the substrate to the direction furthest from the substrate. It is understood that the fabrication process of the epitaxial layer of the epitaxial wafer can refer to the epitaxial process of HEMT devices in the prior art, and will not be described in detail here.

[0062] In this embodiment, after obtaining the epitaxial wafer without source / drain electrodes, the epitaxial wafer can be cleaned to remove surface contaminants, oxides, organic matter, etc. Exemplarily, an acidic solution is used to remove oxides from the GaN surface, and an organic solvent is used to remove organic matter from the epitaxial wafer surface. The specific solutions used can be found in existing technologies.

[0063] In this embodiment, after cleaning, mesa isolation can be performed on the epitaxial layer of the epitaxial wafer. Mesa isolation refers to isolating a region on the surface of the epitaxial layer of the epitaxial wafer for forming transistor devices, thereby separating different transistor devices on the epitaxial wafer. It is understood that mesa isolation is used to remove the barrier layer connecting the independent devices, so that the devices do not interfere with each other. For example, mesa isolation can be performed using the ICP dry etching isolation method.

[0064] In this embodiment, after isolating the mesa, photolithography can be used to remove a portion of the photoresist from each isolated device to form the source / drain electrode region, and then the source / drain electrode is formed in the source / drain electrode region. For example, ohmic metal can be deposited in the source / drain electrode region to obtain an epitaxial wafer with the active / drain electrode formed.

[0065] In this embodiment, after metal stripping to form source and drain electrodes, the epitaxial wafer can be rapidly annealed to ensure good ohmic contact at the source and drain electrodes.

[0066] In this embodiment, for the enhancement-mode transistor with a recessed gate, the epitaxial layer of the epitaxial wafer can be etched to form the recess, or the epitaxial wafer with a pre-etched recess can be directly obtained. The recess can be a via penetrating the GaN cap layer and part of the AlGaN barrier layer of the epitaxial wafer to expose the AlGaN barrier layer. Thus, the AlGaN barrier layer and the GaN cap layer together form the recess.

[0067] In this embodiment, after the source and drain electrodes are formed, a preset gate region can be photolithographically etched to form the gate deposition region.

[0068] S120, deposits a copper oxide film in the area to be deposited on the gate.

[0069] In one embodiment, depositing a copper oxide film includes: determining the required film thickness; determining the target deposition time, target deposition power, target gas flow rate, and target substrate temperature corresponding to the required film thickness based on the relationship between the thickness of the copper oxide film and deposition time, deposition power, gas flow rate, and substrate temperature; and depositing a copper oxide film of the corresponding thickness in the gate deposition area based on the target deposition time, target deposition power, target gas flow rate, and target substrate temperature.

[0070] In this embodiment, the required film thickness can be determined based on the performance of the desired enhancement transistor device. For example, the thickness can be 10nm, 20nm, 50nm, 100nm, 150nm, or any value between the two.

[0071] In this embodiment, the deposition thickness of the copper oxide film is related to process parameters such as deposition power, gas flow rate, and substrate temperature. Specifically, when the substrate temperature and gas flow rate remain constant, a higher deposition power results in a faster deposition rate; when the deposition power and gas flow rate remain constant, a higher substrate temperature results in a slower deposition rate; and when the substrate temperature and deposition power remain constant, a lower gas flow rate results in a slower deposition rate. Therefore, the corresponding deposition time, deposition power, gas flow rate, and substrate temperature can be selected according to the desired copper oxide film thickness.

[0072] For example, when the substrate temperature is 27°C, the gas flow rate is 150 sccm, and the deposition power is 50 W, the deposition rate of the copper oxide film is 1 nm / min.

[0073] At a substrate temperature of 27°C, a gas flow rate of 150 sccm, and a deposition power of 100 W, the deposition rate of the copper oxide film is 3 nm / min.

[0074] At a substrate temperature of 27°C, a gas flow rate of 150 sccm, and a deposition power of 150 W, the deposition rate of the copper oxide film was 6 nm / min.

[0075] At a substrate temperature of 200℃, a gas flow rate of 150 sccm, and a deposition power of 100 W, the deposition rate of the copper oxide film is 1 nm / min.

[0076] At a substrate temperature of 27°C, a gas flow rate of 50 sccm, and a deposition power of 50 W, the deposition rate of the copper oxide film was 0.5 nm / min.

[0077] It is understood that the above are merely examples and should not be construed as limiting this application. Users can select different process parameters according to their needs to deposit copper oxide films of different thicknesses.

[0078] In one embodiment, the copper oxide film can be deposited by depositing a copper oxide film in the gate region based on a copper target and a mixture of oxygen-containing gas.

[0079] In this embodiment, the material used can be a copper target. To form a copper oxide film, a mixed gas containing oxygen can be introduced, thereby generating a copper oxide film on the surface of the area to be deposited on the gate.

[0080] In one embodiment, a copper oxide film is formed by sputtering copper oxide into the gate region to be deposited.

[0081] In this embodiment, copper oxide can be deposited on the gate deposition area by sputtering a copper oxide target to form a copper oxide film. It is understood that the thickness of the formed copper oxide film can be controlled by adjusting process parameters such as the substrate temperature, gas flow rate, sputtering deposition power, and sputtering deposition time.

[0082] In one embodiment, the oxygen-containing mixed gas is a mixture of argon and oxygen; based on the copper target and the oxygen-containing mixed gas, depositing the copper oxide film in the gate deposition area includes: determining the ratio of divalent copper ions to monovalent copper ions in the desired copper oxide film; determining a target ratio of argon to oxygen in the mixed gas based on the proportional correspondence between the ratio of argon to oxygen in the mixed gas and the ratio of divalent copper ions to monovalent copper ions in the copper oxide film; and introducing the mixed gas with the target ratio to deposit a copper oxide film having the corresponding ratio of divalent copper ions to monovalent copper ions.

[0083] In this embodiment, the copper oxide film is composed of Cu₂O (monovalent copper ions) and CuO (divalent copper ions). By controlling the ratio of divalent to monovalent copper ions in the copper oxide film, the hole concentration of the copper oxide film can be controlled. A higher ratio of divalent to monovalent copper ions results in a higher hole concentration in the copper oxide film, leading to a greater positive bias of the device's threshold voltage. In other words, a larger and more positive threshold voltage results in a smaller leakage current in the off state and a correspondingly smaller output saturation current.

[0084] In this embodiment, the ratio of divalent to monovalent copper ions in the copper oxide film can be controlled by controlling the proportion of oxygen in the input mixed gas. Therefore, the desired ratio of divalent to monovalent copper ions can be determined based on the performance requirements of the device to be formed. Then, the oxygen content in the input mixed gas, i.e., the target ratio of argon to oxygen in the mixed gas, can be determined based on this ratio. Finally, the mixed gas with the target ratio is introduced during the deposition of the copper oxide film. It is understood that when depositing a copper oxide film by sputtering, a mixed gas containing oxygen can also be introduced to ensure that the formed copper oxide film includes copper ions with different valence states than the copper oxide target. For example, when the target is Cu₂O, oxygen can be introduced to form divalent copper ions.

[0085] For example, for Cu2O target material, when argon:oxygen = 14:1, the ratio of divalent to monovalent copper ions in the formed copper oxide film is Cu 2+ Cu + = 1:1; When argon:oxygen = 13:2, the ratio of divalent to monovalent copper ions in the formed copper oxide film is Cu 2+ Cu + = 5:1; When argon:oxygen = 12:3, the ratio of divalent to monovalent copper ions in the formed copper oxide film is Cu 2+ Cu +=20:1. It should be noted that the above is only an example and should not be construed as a limitation of this application. In practice, the proportion of oxygen in the mixed gas can be reasonably selected according to the requirements of the valence state ratio of copper ions in the copper oxide film.

[0086] In this embodiment, the gate area to be deposited can be surface-treated before depositing the copper oxide film. For example, a chemical solution such as TMAH (tetramethylammonium hydroxide) solution, HCl (hydrochloric acid) solution, or H2SO4 (sulfuric acid) solution can be used for surface treatment to remove oxides from the surface of the gate area to be deposited.

[0087] In one embodiment, during the deposition of a copper oxide film, a material to be doped is introduced to increase the hole concentration of the copper oxide film.

[0088] In this embodiment, during the deposition of the copper oxide film, doping can be used to increase the hole carrier concentration of the formed copper oxide film. The material to be doped can be manganese, boron, sodium, or other materials that can increase the hole concentration. Doping can be performed during the deposition of the copper oxide film via co-sputtering, or by using a target of the material to be doped during the growth of the copper oxide film.

[0089] In this embodiment, by increasing the hole carrier concentration, the ability of the fabricated enhancement transistor to consume the two-dimensional electron gas in the AlGaN / GaN heterojunction can be effectively improved, thereby making the threshold voltage positively biased.

[0090] S130, a gate material is deposited on the surface of a copper oxide film to form a gate, thereby obtaining an enhancement transistor.

[0091] In one embodiment, the gate is formed by depositing gate material on the surface of a copper oxide film using a deposition method. Exemplarily, the gate material can be nickel / gold, forming a nickel / gold Schottky gate; alternatively, the gate material can be titanium / gold, forming a titanium / gold ohmic gate. It is understood that the material for the gate can be selected according to requirements to form the corresponding gate. Specific deposition methods and materials can be found in existing technologies and will not be elaborated upon here.

[0092] In one embodiment, after the gate is formed, it can be further subjected to post-annealing. Specifically, based on the relationship between the thickness of the copper oxide film and the post-annealing parameters, a corresponding target post-annealing parameter is determined; the gate is then post-annealed based on the target post-annealing parameter.

[0093] In this embodiment, the annealing parameters include annealing temperature and annealing time. The greater the thickness of the copper oxide film, the longer the annealing time is required. The annealing temperature can be selected within the range of 200 to 600 degrees Celsius. For example, for a 50 nm thick copper oxide film, the annealing temperature is 300 degrees Celsius and the annealing time is 1 minute; for a 100 nm thick copper oxide film, the annealing temperature is 300 degrees Celsius and the annealing time is 5 minutes.

[0094] In this embodiment, post-gate annealing of the gate facilitates interface reconstruction at the contact surface between the copper oxide film and the AlGaN barrier layer, thereby reducing interface states and increasing the work function of the copper oxide. This can further enhance the conduction band of the AlGaN / GaN heterojunction, thereby increasing the threshold voltage of the enhancement-mode transistor.

[0095] In one embodiment, after the gate is formed, passivation layers can be formed on the surface of the epitaxial layer and the electrode surface to prevent device performance from being affected by the environment. Exemplarily, the passivation layer can be formed using low-pressure chemical vapor deposition to deposit a silicon nitride passivation layer, using atomic layer deposition to deposit aluminum oxide and aluminum nitride passivation layers, or using plasma-enhanced chemical vapor deposition to deposit silicon nitride passivation layers, silicon dioxide passivation layers, etc. It is understood that the formation of the passivation layer can refer to existing technologies, and will not be elaborated upon here.

[0096] In this embodiment, after the passivation layer is formed, the passivation layer on the surface of the gate region and the source / drain electrode region can be etched to expose the electrodes, which facilitates subsequent connection of electrode pins and performance testing.

[0097] In this embodiment, a copper oxide film is used as the P-type metal oxide layer at the gate. This allows for the deposition of a copper oxide film on the epitaxial wafer forming the active drain electrode in the area to be deposited for the gate, using a deposition method. Then, gate material is deposited on the surface of the copper oxide film to form the gate, thereby obtaining an enhancement-mode transistor. Compared to existing technologies, the copper oxide film deposition method is easier to control and eliminates the need for etching the P-type metal layer and the epitaxial layer of the epitaxial wafer. This simplifies the manufacturing process and avoids performance degradation caused by the difficulty in precisely controlling the manufacturing process. Furthermore, by determining different ratios of divalent and monovalent copper ions, enhancement-mode transistors with different threshold voltages and device performance can be manufactured to meet various production requirements.

[0098] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0099] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. An enhanced transistor fabrication method characterized by, The method comprises: providing an epitaxial wafer, a source / drain electrode being formed on the epitaxial wafer, and the epitaxial wafer having a gate deposition area; depositing a copper oxide film on the gate deposition area; depositing a gate material on a surface of the copper oxide film to form a gate, so as to obtain an enhancement-mode transistor; the step of depositing the copper oxide film on the gate deposition area comprises: determining a required film thickness of the copper oxide; determining target deposition time, target deposition power, target gas flow and target substrate temperature corresponding to the required film thickness based on a relationship between the thickness of the copper oxide film and the deposition time, the deposition power, the gas flow and the substrate temperature; and depositing the copper oxide film with the corresponding thickness on the gate deposition area based on the target deposition time, the target deposition power, the target gas flow and the target substrate temperature. the step of depositing the copper oxide film on the gate deposition area comprises: depositing the copper oxide film on the gate deposition area based on a copper target and a mixed gas containing oxygen; the mixed gas containing oxygen is a mixed gas of argon and oxygen; and the step of depositing the copper oxide film on the gate deposition area based on the copper target and the mixed gas containing oxygen comprises: determining a ratio of divalent copper ions to monovalent copper ions in the copper oxide film to be formed; determining a target ratio of the argon and oxygen in the mixed gas based on a ratio correspondence relationship between the ratio of the argon and oxygen in the mixed gas and the ratio of the divalent copper ions to the monovalent copper ions in the copper oxide film; and introducing the mixed gas with the target ratio to deposit the copper oxide film with the corresponding ratio of the divalent copper ions to the monovalent copper ions. The ratio of the divalent copper ions to the monovalent copper ions in the copper oxide film is used to determine a threshold voltage of the enhancement-mode transistor.

2. The method of claim 1, wherein, The step of depositing the copper oxide film on the gate deposition area further comprises: introducing a to-be-doped material during the deposition of the copper oxide film, the to-be-doped material being used to increase a hole concentration of the copper oxide film.

3. The method of claim 1, wherein, The step of depositing the copper oxide film on the gate deposition area comprises: forming the copper oxide film by sputtering copper oxide on the gate deposition area.

4. The method of claim 1, wherein, After the step of depositing the gate material on the surface of the copper oxide film to form the gate to obtain the enhancement-mode transistor, the method further comprises: determining a corresponding target post-annealing parameter based on a relationship between the thickness of the copper oxide film and the post-annealing parameter; and performing post-annealing on the gate based on the target post-annealing parameter.

5. An enhanced transistor, characterized by The enhancement-mode transistor manufactured by the method of any one of claims 1-4 comprises: an epitaxial wafer comprising an epitaxial layer, a source / drain electrode being formed on a surface of the epitaxial layer; a copper oxide film deposited on the epitaxial layer; a gate deposited on the copper oxide film; wherein the copper oxide film comprises divalent copper ions and monovalent copper ions, and the ratio of the divalent copper ions to the monovalent copper ions in the copper oxide film is used to determine a threshold voltage of the enhancement-mode transistor.

6. The enhancement mode transistor of claim 5, wherein, The epitaxial layer includes a GaN cap layer and an AlGaN barrier layer, a surface of the epitaxial wafer is the GaN cap layer, the GaN cap layer is on the AlGaN barrier layer, the GaN cap layer has a through hole, and part of the AlGaN barrier layer is exposed from the through hole, and the copper oxide film is deposited on a surface of the exposed area of the AlGaN barrier layer.

7. The enhancement mode transistor of claim 5 or 6, wherein, The copper oxide film is in contact with the source and drain electrodes, respectively.

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