A channel construction method, etching device, storage medium, equipment and photolithography machine
By using the ALD method to construct the buffer structure layer on the surface of the nitride layer of the workpiece film stacking model and controlling its etch rate, the problem of channel oxide recessed disc defects in the shallow channel isolation STI process is solved, and a higher quality channel structure is achieved.
Patent Information
- Application Number
- CN202210568196.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-24
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2042-05-24
AI Technical Summary
In the prior art, channel oxides often cause depression disc-shaped defects after the chemical mechanical polishing CMP process in the shallow channel isolation STI process, especially in channels with larger widths, which are difficult to effectively solve.
The buffer structure layer is constructed by atomic layer deposition ALD method on the surface of the nitride layer of the workpiece film stacking model, and the grinding progress of the imbalance between the trench top and the trench shoulder during the CMP process is compensated.
The problem of disc-shaped Dishing depressions in the prior art is effectively overcome, and the flatness and quality of the channel structure are improved.
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Figure CN115020320B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to a channel construction method, an etching device, a storage medium, equipment and a photolithography machine. Background Art
[0002] The shallow trench isolation (STI) process is one of the key technologies of the 40 / 28nm process. Its channel oxide often produces concave disk-shaped defects after the chemical mechanical polishing (CMP) process; in order to overcome such defects in the channel construction process, especially for relatively large channels, relevant technical upgrades are urgently needed. Summary of the invention
[0003] The embodiments of the present invention disclose a channel construction method, an etching device, a storage medium, a device and a photolithography machine; based on the STI application scenario and the CMP flattening technical solution, a buffer structure layer is constructed on the surface of the nitride layer of the workpiece thin film stacking model by using the atomic layer deposition ALD (Atomic Layer Deposition) method, and the unbalanced grinding progress between the groove top and the groove shoulder during the CPM process is compensated by controlling the etching rate of the buffer structure layer, thereby overcoming the technical problem of generating disc-shaped Dishing depressions in the prior art; in addition, the present invention also discloses an etching device, a storage medium, a polishing device and a photolithography machine corresponding to the method through embodiments.
[0004] The channel construction method includes a channel construction step, a buffer layer construction step, and a surface treatment step; wherein:
[0005] In the channel construction step, a channel is constructed on the substrate surface; at least a first thin film layer is constructed on the channel surface, and a second thin film layer is constructed on the surface of the first thin film layer outside the channel.
[0006] The channel can be realized by using a photolithography process; wherein, in the buffer layer construction step, a second buffer layer is constructed on the surface of the second thin film layer.
[0007] Furthermore, the surface treatment step includes a trench filling step and a grinding and polishing step; the trench filling step fills the third dielectric layer to the trench and the second buffer layer surface; the grinding and polishing step removes the dielectric on the workpiece surface for a preset time until the second buffer layer is removed, and exposes the second film layer to the workpiece surface again.
[0008] Specifically, the second buffer layer is constructed by an atomic layer deposition (ALD) method; and the etching rate of the second buffer layer when wet etching is performed is not less than 165 Å / min.
[0009] The construction method of the first thin film layer and / or the second thin film layer may include at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, spin coating, evaporation, and sputtering.
[0010] Specifically, the thickness of the second buffer layer can be 50 Å; wherein the substrate is made of single crystal silicon Si material, and the second thin film layer is made of silicon nitride SiN material.
[0011] Furthermore, a third thin film layer is deposited or constructed on the surface of the second buffer layer; wherein the third thin film layer is constructed using an advanced patterning film (APF) method, and the thickness of the third thin film layer (103) is 2000 Å; a fourth thin film layer can also be constructed on the surface of the third thin film layer (103), and the fourth thin film layer is a nitrogen-free anti-reflective coating (NFDARC), and the thickness of the fourth thin film layer can be 250 Å.
[0012] Specifically, the working pressure value is adjusted so that the construction process of the second buffer layer is carried out at a pressure of 8 Torr, the temperature of the second buffer layer construction process is maintained at 400° C., and the etching rate of the second buffer layer when wet etching is controlled at 165 Å / min.
[0013] Furthermore, the grinding and polishing step obtains the thickness or current state of the second buffer layer, and the grinding and polishing step is terminated when the thickness of the second buffer layer is zero or the second buffer layer disappears.
[0014] Specifically, the channel construction step, the buffer layer construction step, and the surface treatment step may be constructed using at least one of 28 nm, 32 nm, and / or 40 nm processes.
[0015] Furthermore, the surface treatment step may adopt a chemical mechanical polishing (CMP) process; the second film layer is used to construct an AA structure of an active area ACTIVE AREA of a metal oxide MOS device; and the channel may be constructed by a shallow trench isolation (STI) process.
[0016] Furthermore, an embodiment of the present invention also discloses an etching device corresponding to the above method, including a channel construction unit, a grinding buffer unit, and a surface treatment unit.
[0017] The channel construction unit constructs a channel on the substrate surface; at least a first thin film layer is constructed on the channel surface, and a second thin film layer is constructed on the surface of the first thin film layer outside the channel.
[0018] Furthermore, the grinding buffer unit constructs a second buffer layer on the surface of the second film layer.
[0019] Furthermore, a subsequent polishing process will be completed by a surface treatment unit.
[0020] Specifically, the surface treatment unit also includes a channel filling unit and a grinding and polishing unit; the channel filling unit fills the third dielectric layer to the channel and the second buffer layer surface; the grinding and polishing unit removes the dielectric on the workpiece surface for a preset time until the second buffer layer is removed.
[0021] Furthermore, the second buffer layer can be constructed by an atomic layer deposition (ALD) method, so that the etching rate of the second buffer layer when wet etching is performed is not less than 165 Å / min.
[0022] Specifically, the construction method of the first thin film layer and / or the second thin film layer includes at least one of chemical vapor deposition CVD, physical vapor deposition PVD, electroplating, spin coating, evaporation, and sputtering methods; the thickness of the second buffer layer can be 50 Å; its substrate can be made of single crystal silicon Si material, and its second thin film layer can be made of silicon nitride SiN material.
[0023] Furthermore, a third thin film layer may be deposited or constructed on the surface of the second buffer layer; the third thin film layer may be constructed using an advanced patterned film method APF, and the thickness of the third thin film layer may be 2000 Å.
[0024] Furthermore, a fourth thin film layer may be constructed on the surface of the third thin film layer. The fourth thin film layer may be a nitrogen-free anti-reflective coating NFDARC. The thickness of the fourth thin film layer is 250 Å.
[0025] Furthermore, by adjusting the working pressure value, the construction process of the second buffer layer can be carried out under a pressure of 8 Torr, so that the temperature of the second buffer layer construction process is maintained at 400°C; if necessary, the pressure and temperature are adjusted so that the etching rate of the second buffer layer using wet etching is controlled at 165 Å / min.
[0026] Furthermore, the grinding and polishing unit obtains the thickness or current state of the second buffer layer, and when the thickness of the second buffer layer is zero or the second buffer layer disappears, the execution process of the grinding and polishing unit is terminated.
[0027] Specifically, the channel construction unit, the grinding buffer unit, and the surface treatment unit may be constructed using at least one of 28 nm, 32 nm, and / or 40 nm processes.
[0028] The surface treatment step may adopt a chemical mechanical polishing (CMP) process; the second film layer is used to construct an AA structure of an active area ACTIVE AREA of a metal oxide MOS device; and its channel adopts a shallow trench isolation (STI) process structure.
[0029] Furthermore, the embodiments of the present invention also disclose a computer storage medium, a polishing device and an inhibitor lithography machine. The above three types of products all adopt the same or corresponding inventive concept as the method of the present invention, and obtain compensation for the grinding progress by adopting a buffer structure constructed by the ALD method, thereby overcoming the Dishing problem in the prior art.
[0030] It should be noted that the terms "first", "second" and similar terms used in this article are only for describing the various components in the technical solution, and do not constitute a limitation of the technical solution, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; elements with "first", "second" and similar terms indicate that the corresponding technical solution contains at least one of the element. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solution of the present invention and facilitate further understanding of the technical effects, technical features and purposes of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings. The accompanying drawings constitute an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.
[0032] The same reference numerals in the drawings represent the same components or blocks, specifically:
[0033] Figure 1 It is a schematic diagram of a thin film stacking model in the prior art;
[0034] Figure 2 This is a schematic diagram of a thin film stacking model according to an embodiment of the present invention;
[0035] Figure 3 This is a comparison table of film process characteristics;
[0036] Figure 4 This is a schematic diagram of a workpiece state before flattening treatment according to an embodiment of the present invention;
[0037] Figure 5 A schematic diagram of the workpiece state during the flattening process of an embodiment of the present invention;
[0038] Figure 6 A schematic diagram of the workpiece state after the flattening process is completed according to an embodiment of the present invention;
[0039] Figure 7 This is a schematic diagram of the workpiece state before flattening treatment in the prior art;
[0040] Figure 8 A schematic diagram of a Dishing defect that occurs after a chemical mechanical polishing (CMP) process is used in the prior art;
[0041] Fig. 9 It is a schematic diagram of the process flow of the method of the present invention;
[0042] Fig.10 - Schematic diagram of the composition structure of the product embodiment of the present invention.
[0043] in:
[0044] 001- Prior art stacking model 1,
[0045] 002- Stacking model 2 of the embodiment of the present invention,
[0046] 003-Comparison of process characteristics,
[0047] 004-Pre-planarization state of the embodiment of the present invention,
[0048] 005-The intermediate state of the flattening of the embodiment of the present invention,
[0049] 006-The flattening end state of the embodiment of the present invention,
[0050] 007- State 1 before prior art flattening treatment,
[0051] 008- Prior art Dishing defect,
[0052] 009-Construction process of the structural embodiment of the present invention,
[0053] 010- Composition structure of the product embodiment of the present invention;
[0054] 011-Channel construction steps,
[0055] 022-buffer layer construction steps,
[0056] 033-Surface treatment steps,
[0057] 044-Trench filling step,
[0058] 055-grinding and polishing steps;
[0059] 100-substrate,
[0060] 101- first film layer,
[0061] 102- second film layer,
[0062] 103- third film layer,
[0063] 104- fourth film layer,
[0064] 105- fifth film layer;
[0065] 200- second buffer layer;
[0066] 300-third dielectric layer;
[0067] 401, 402, 403 - channel;
[0068] 500-process to be compared,
[0069] 501-High Aspect Ratio Process (HARP) after annealing
[0070] 502-Atomic Layer Deposition ALD (Atomic Layer Deposition) Oxide Method,
[0071] 503-control group ALD method;
[0072] 510-power characteristic parameters,
[0073] 520-pressure characteristic parameters,
[0074] 530-temperature characteristic parameters,
[0075] 540-wet etching rate parameters;
[0076] 801-channel construction unit,
[0077] 802-grinding buffer unit,
[0078] 803-Surface treatment unit,
[0079] 805-grinding control unit,
[0080] 811 - computer memory chip,
[0081] 822- Etching device,
[0082] 833-Polishing equipment,
[0083] 888-photolithography machine. DETAILED DESCRIPTION
[0084] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Of course, the specific embodiments described below are only for explaining the technical solutions of the present invention, rather than for limiting the present invention. In addition, the parts described in the embodiments or the accompanying drawings are only examples of the relevant parts of the present invention, rather than the whole of the present invention.
[0085] like Fig. 9 As shown, an embodiment of the present invention discloses a channel construction method, including a channel construction step 011 , a buffer layer construction step 022 , and a surface treatment step 033 .
[0086] In the channel construction step 011 , channels 401 , 402 , and 403 are constructed on the surface of the substrate 100 . The number of channels can be adjusted according to the process requirements; the number is not limited.
[0087] Furthermore, at least a first thin film layer 101 is constructed on the surface of the channel, and a second thin film layer 102 is constructed on the surface of the first thin film layer 101 outside the channels 401, 402, 403; wherein, the first thin film layer 101 can be constructed as follows: Figure 1 The model of or 2 is combined with an etching process to obtain channels 401, 402, 403.
[0088] Furthermore, in the buffer layer construction step 022, a second buffer layer 200 is constructed on the surface of the second film layer 102; the construction process of the buffer layer 200 can also be referred to Figure 2 The model shown; the corresponding channels 401, 402, 403 are also obtained in combination with the etching process.
[0089] Furthermore, if Fig. 9 The surface treatment step 033 also includes a channel filling step 044 and a grinding and polishing step 055; wherein, the channel filling step 044 fills the third dielectric layer 300 to the surface of the channels 401, 402, 403 and the second buffer layer 200; the grinding and polishing step 055 removes the dielectric on the surface of the workpiece for a preset time until the second buffer layer 200 is removed, thereby obtaining the channel structure and smoothness to be prepared.
[0090] Specifically, the second buffer layer 200 may be constructed by an atomic layer deposition (ALD) method; the etching rate of the second buffer layer 200 when wet etching is performed should be no less than 165 Å / min.
[0091] Furthermore, the construction method of the first thin film layer 101 and / or the second thin film layer 102 may include at least one of chemical vapor deposition CVD, physical vapor deposition PVD, electroplating, spin coating, evaporation, and sputtering.
[0092] The thickness of the second buffer layer 200 may be 50 Å; the substrate may be made of single crystal silicon Si material, and the second thin film layer may be made of silicon nitride SiN material.
[0093] Furthermore, a third thin film layer 103 may be deposited or constructed on the surface of the second buffer layer 200; the third thin film layer 103 may be constructed using an advanced pattern film method APF, and the thickness of the third thin film layer 103 may be 2000 Å.
[0094] Specifically, a fourth thin film layer 104 may be further constructed on the surface of the third thin film layer 103. The fourth thin film layer 104 may be a nitrogen-free anti-reflective coating NFDARC. The thickness of the fourth thin film layer 104 may be 250 Å.
[0095] Furthermore, by adjusting the working pressure value, the construction process of the second buffer layer 200 is carried out under a pressure of 8 Torr, the temperature of the second buffer layer 200 during the construction process is maintained at 400°C, and the etching rate of the second buffer layer 200 when wet etching is controlled at 165 Å / min.
[0096] The grinding and polishing step 055 obtains the thickness or current state of the second buffer layer 200 , and when the thickness of the second buffer layer 200 is zero or the second buffer layer 200 disappears under the grinding process, the grinding and polishing step 055 is terminated.
[0097] Furthermore, the channel construction step 011 , the buffer layer construction step 022 , and the surface treatment step 033 may be constructed using at least one of 28 nm, 32 nm, and / or 40 nm processes.
[0098] The surface treatment step 033 may be processed by a chemical mechanical polishing (CMP) process; the second film layer is used to construct the AA structure of the active area ACTIVE AREA of the metal oxide MOS device; and the trenches 401, 402, 403 may be constructed by a shallow trench isolation (STI) process.
[0099] like Fig.10 The embodiment of the present invention further discloses an etching device 800 , including a channel construction unit 801 , a grinding buffer unit 802 , and a surface treatment unit 803 .
[0100] The channel construction unit 801 constructs channels 401 , 402 , 403 on the surface of the substrate 100 ; at least a first thin film layer 101 is constructed on the channel surface, and a second thin film layer 102 is constructed on the surface of the first thin film layer 101 outside the channels 401 , 402 , 403 .
[0101] Furthermore, the grinding buffer unit 802 constructs a second buffer layer 200 on the surface of the second film layer 102 .
[0102] Furthermore, the surface treatment unit 803 also includes a trench filling unit 804 and a grinding and polishing unit 805; the trench filling unit 804 fills the third dielectric layer 300 to the surface of the trenches 401, 402, 403 and the second buffer layer 200; the grinding and polishing unit 805 removes the dielectric on the surface of the workpiece for a preset time until the second buffer layer 200 is removed.
[0103] Specifically, the second buffer layer 200 may be constructed by an atomic layer deposition (ALD) method; and the etching rate of the second buffer layer 200 when wet etching is used is not less than 165 Å / min.
[0104] Furthermore, the construction method of the first thin film layer 101 and / or the second thin film layer 102 includes at least one of chemical vapor deposition CVD, physical vapor deposition PVD, electroplating, spin coating, evaporation, and sputtering methods; the thickness of the second buffer layer 200 can be 50 Å; its substrate 100 can be made of single crystal silicon Si material, and its second thin film layer 102 can be made of silicon nitride SiN material.
[0105] Furthermore, a third thin film layer 103 may be deposited or constructed on the surface of the second buffer layer 200; the third thin film layer 103 is constructed using an advanced pattern film method APF, and the thickness of the third thin film layer 103 may be 2000 Å.
[0106] Furthermore, if Figure 2 A fourth thin film layer 104 may also be constructed on the surface of the third thin film layer 103. The fourth thin film layer 104 is a nitrogen-free anti-reflective coating NFDARC. The thickness of the fourth thin film layer (104) is 250 Å.
[0107] Furthermore, if Figure 3 By adjusting the working pressure value, the construction process of the second buffer layer 200 can be carried out under a pressure of 8 Torr, the temperature of the second buffer layer 200 during the construction process is maintained at 400°C, and the etching rate of the second buffer layer 200 when wet etching is controlled at 165 Å / min.
[0108] Furthermore, the thickness or current state of the second buffer layer 200 may be acquired through the grinding control unit 805, and the execution process of the grinding control unit 805 is terminated when the thickness of the second buffer layer 200 is zero or the second buffer layer 200 disappears.
[0109] Specifically, the channel construction unit 801 , the grinding buffer unit 802 , and the surface treatment unit 803 may be constructed using at least one of 28 nm, 32 nm, and / or 40 nm processes.
[0110] The surface treatment step 033 may adopt a chemical mechanical polishing (CMP) process; the second film layer is used to construct an AA structure of an active area ACTIVE AREA of a metal oxide MOS device; and the trenches 401, 402, and 403 may be constructed by a shallow trench isolation (STI) process.
[0111] like Fig.10 The embodiment of the present invention also discloses a computer storage medium, polishing equipment and lithography machine corresponding to the above method and device, and the implementation process is similar to the above embodiment and will not be repeated here.
[0112] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present invention. Those skilled in the art will understand that the implementation methods of the present invention are not limited to the above contents, and obvious changes, replacements or substitutions based on the above contents do not exceed the scope of the technical solutions of the present invention; other implementation methods will also fall within the scope of the present invention without departing from the concept of the present invention.
Claims
1. A channel construction method, characterized in that: include: A channel construction step (011), a buffer layer construction step (022), and a surface treatment step (033); wherein the channel construction step (011) constructs channels (401, 402, 403) on the surface of the substrate (100); the surface of the channel is at least constructed with a first thin film layer (101), and the surface of the first thin film layer (101) outside the channels (401, 402, 403) is constructed with a second thin film layer (102); the buffer layer construction step (022) is constructed on the surface of the second thin film layer (102) The surface is structured with a second buffer layer (200), and the second buffer layer (200) is constructed by an atomic layer deposition (ALD) method; the surface treatment step (033) includes a trench filling step (044) and a grinding and polishing step (055); the trench filling step (044) fills the third dielectric layer (300) to the trench (401, 402, 403) and the surface of the second buffer layer (200); the grinding and polishing step (055) removes the dielectric on the surface of the workpiece for a preset time until the second buffer layer (200) is removed.
2. The trench construction method according to claim 1, wherein: The etching rate of the second buffer layer (200) when wet etching is performed is not less than 165 Å / min.
3. The trench construction method according to claim 1 or 2, wherein: The construction method of the first thin film layer (101) and / or the second thin film layer (102) comprises at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, spin coating, evaporation, and sputtering.
4. The trench construction method according to claim 3, wherein: The thickness of the second buffer layer (200) is 50 Å; the substrate is made of single crystal silicon Si material, and the second thin film layer is made of silicon nitride SiN material.
5. The trench construction method according to claim 1, 2 or 4, wherein: A third thin film layer (103) is also deposited or constructed on the surface of the second buffer layer (200); the third thin film layer (103) is constructed using an advanced pattern film method APF, and the thickness of the third thin film layer (103) is 2000 Å; a fourth thin film layer (104) is also constructed on the surface of the third thin film layer (103), and the fourth thin film layer (104) is a nitrogen-free anti-reflective coating NFDARC, and the thickness of the fourth thin film layer (104) is 250 Å.
6. The trench construction method according to claim 5, wherein: The working pressure value is adjusted so that the construction process of the second buffer layer (200) is carried out at a pressure of 8 Torr, the temperature of the construction process of the second buffer layer (200) is maintained at 400°C, and the etching rate of the second buffer layer (200) when wet etching is controlled at 165 Å / min; the grinding and polishing step (055) obtains the thickness or current state of the second buffer layer (200), and the grinding and polishing step (055) is terminated when the thickness of the second buffer layer (200) is zero or the second buffer layer (200) disappears.
7. The trench construction method according to claim 1, 2, 4 or 6, wherein: The channel construction step (011), the buffer layer construction step (022), and the surface treatment step (033) are constructed using at least one of 28nm, 32nm and / or 40nm processes; the surface treatment step (033) uses a chemical mechanical polishing (CMP) process; the second thin film layer is used to construct an AA structure of an active area ACTIVE AREA of a metal oxide MOS device; and the channels (401, 402, 403) are constructed using a shallow trench isolation (STI) process.
8. An etching device comprising: A channel construction unit (801), a grinding buffer unit (802), and a surface treatment unit (803); the channel construction unit (801) constructs channels (401, 402, 403) on the surface of a substrate (100); at least a first thin film layer (101) is constructed on the surface of the channel, and a second thin film layer (102) is constructed on the surface of the first thin film layer (101) outside the channels (401, 402, 403); the grinding buffer unit (802) constructs a second thin film layer (102) on the surface of the second thin film layer (102); A second buffer layer (200), wherein the second buffer layer (200) is constructed by an atomic layer deposition (ALD) method; the surface treatment unit (803) comprises a channel filling unit (804) and a grinding and polishing unit (805); the channel filling unit (804) fills a third dielectric layer (300) to the surface of the channel (401, 402, 403) and the second buffer layer (200); and the grinding and polishing unit (805) removes the dielectric on the surface of the workpiece for a preset time until the second buffer layer (200) is removed.
9. The etching apparatus of claim 8, wherein: The etching rate of the second buffer layer (200) when wet etching is not less than 165 Å / min; the construction method of the first thin film layer (101) and / or the second thin film layer (102) comprises at least one of chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, spin coating, evaporation, and sputtering; the thickness of the second buffer layer (200) is 50 Å; the substrate is made of single crystal silicon Si material, and the second thin film layer is made of silicon nitride SiN material.
10. The etching apparatus of claim 9, wherein: A third thin film layer (103) is also deposited or constructed on the surface of the second buffer layer (200); the third thin film layer (103) is constructed using an advanced pattern film method APF, and the thickness of the third thin film layer (103) is 2000 Å; a fourth thin film layer (104) is also constructed on the surface of the third thin film layer (103), and the fourth thin film layer (104) is a nitrogen-free anti-reflective coating NFDARC, and the thickness of the fourth thin film layer (104) is 250 Å; The working pressure value is adjusted so that the construction process of the second buffer layer (200) is carried out at a pressure of 8 Torr, the temperature of the construction process of the second buffer layer (200) is maintained at 400°C, and the etching rate of the second buffer layer (200) when wet etching is controlled at 165 Å / min; the grinding and polishing unit (805) obtains the thickness or current state of the second buffer layer (200), and terminates the execution process of the grinding and polishing unit (805) when the thickness of the second buffer layer (200) is zero or the second buffer layer (200) disappears.
11. The etching device according to any one of claims 8 to 10, wherein: The channel construction unit (801), the grinding buffer unit (802), and the surface treatment unit (803) are constructed using at least one of 28nm, 32nm and / or 40nm processes; the surface treatment step (033) uses a chemical mechanical polishing (CMP) process; the second film layer is used to construct an AA structure of an active area ACTIVE AREA of a metal oxide MOS device; and the channels (401, 402, 403) are constructed using a shallow trench isolation (STI) process.
12. A computer storage medium comprising: A storage medium body for storing a computer program; when the computer program is executed by a microprocessor, the channel construction method according to any one of claims 1 to 7 is implemented.
13. A polishing device comprising: The etching apparatus of any one of claims 8 to 11 and / or the computer storage medium of claim 12.
14. A photolithography machine, comprising: The etching apparatus of any one of claims 8 to 11 and / or the computer storage medium of claim 12.
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