Display device

Abstract

A display device includes a display region including pixels arranged on a substrate, a pad portion on the substrate and arranged in a non-display region at a periphery of the display region, and a circuit portion overlapping the pad portion and electrically connected to the pad portion, the pad portion including a conductive line, a first dummy line arranged at a periphery of the conductive line, and a first anti-fuse and a second anti-fuse arranged adjacent to the conductive line and spaced apart from each other along a length direction of the conductive line, the first anti-fuse and the second anti-fuse each including a first electrode electrically connected to a portion of the conductive line and a second electrode electrically connected to a portion of the first dummy line with a first insulating layer interposed therebetween.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices, and more specifically, to display devices provided with pad portions capable of repairing damage. Background Technology

[0002] A display device is a device that visually displays data. Display devices are used as displays for small products such as mobile phones, as well as for large products such as televisions.

[0003] Such a display device may include wiring for providing signals or voltages to pixels disposed in the display area. The display device may include pads for connecting various wirings, driving units, and control units that transmit electrical signals or voltages to the pixels. Summary of the Invention

[0004] Embodiments of the present invention can provide a display device including a structure that can be repaired when damage occurs to the pad portion. However, this subject matter is illustrative and does not limit the scope of the invention.

[0005] An embodiment of the present invention discloses a display device, comprising: a display area including pixels disposed on a substrate; a pad portion located on the substrate and disposed in a non-display area surrounding the display area; and a circuit portion overlapping the pad portion and electrically connected to the pad portion, the pad portion including: a conductive line; a first dummy line disposed around the conductive line; and a first anti-fuse and a second anti-fuse, configured to be adjacent to the conductive line and spaced apart from each other along the length direction of the conductive line, the first anti-fuse and the second anti-fuse each including: a first electrode electrically connected to a portion of the conductive line; and a second electrode electrically connected to a portion of the first dummy line, and a first insulating layer sandwiched between the second electrode and the first electrode.

[0006] Alternatively, the first electrode of the first anti-fuse and the first electrode of the second anti-fuse may be integrated with a portion of the conductive wire.

[0007] The conductive wire may include: a main body portion that overlaps with the circuit portion; and a pair of connecting portions disposed on both sides of the main body portion, wherein the pair of connecting portions are connected to the main body portion by at least one insulating layer between the main body portion and the pair of connecting portions.

[0008] Alternatively, the first anti-fuse and the second anti-fuse may each further include a third electrode, spaced apart from the first electrode while sandwiched between the first insulating layer.

[0009] Alternatively, the pad portion may further include a second dummy line, which is electrically connected to the third electrode of the first anti-fuse and the third electrode of the second anti-fuse.

[0010] Alternatively, the second dummy line may be integrated with the third electrode of the first anti-fuse and the third electrode of the second anti-fuse.

[0011] The first insulating layer may include: a first portion located on the substrate; a second portion between the first electrode and the second electrode; and a third portion between the first electrode and the third electrode, wherein the thickness of the second portion and the third portion is less than the thickness of the first portion.

[0012] It is possible that at least one of the first anti-fuse and the second anti-fuse further includes a metal oxide layer on the upper part of the first electrode.

[0013] It is possible that at least one of the first anti-fuse and the second anti-fuse further includes: a semiconductor layer, located between the first electrode and the second electrode, and connected to the second electrode.

[0014] Alternatively, at least one of the first anti-fuse and the second anti-fuse may further include an upper electrode on the upper part of the semiconductor layer.

[0015] Alternatively, the width of the upper electrode may be greater than the width of the first electrode.

[0016] Alternatively, the pad portion may further include: a third dummy line electrically connected to the third electrode of the first anti-fuse; and a fourth dummy line spaced apart from the third dummy line and electrically connected to the third electrode of the second anti-fuse.

[0017] Alternatively, the third dummy line may be integrated with the third electrode of the first anti-fuse, and the fourth dummy line may be integrated with the third electrode of the second anti-fuse.

[0018] Another aspect of the present invention discloses a display device, comprising: a display area including pixels disposed on a substrate; a pad portion located on the substrate and disposed in a non-display area surrounding the display area; and a circuit portion overlapping the pad portion and electrically connected to the pad portion, the pad portion including: a conductive line; a first anti-fuse electrically connected to the conductive line; and a first dummy line, the first anti-fuse including: a first electrode; and a second electrode spaced apart from the first electrode by a first insulating layer sandwiched between them and electrically connected to the first dummy line, the circuit portion including a relative conductive line overlapping the conductive line and a first relative conductive line overlapping the first dummy line.

[0019] Alternatively, the display device may further include: an upper insulating layer covering the edge of the first dummy line and including an opening overlapping the first dummy line.

[0020] Alternatively, the first anti-fuse may further include a third electrode, spaced apart from the first electrode while sandwiched between the first insulating layer.

[0021] Alternatively, the pad portion may further include a second dummy line, which is electrically connected to the third electrode of the first anti-fuse.

[0022] Alternatively, the circuit section may further include a second relative conductive line that overlaps with the second dummy line.

[0023] The first insulating layer may include: a first portion located on the substrate; a second portion between the first electrode and the second electrode; and a third portion between the first electrode and the third electrode, wherein the thickness of the second portion and the third portion is less than the thickness of the first portion.

[0024] The conductive wire may include: a main body portion that overlaps with the circuit portion; and a pair of connecting portions disposed on both sides of the main body portion, wherein the pair of connecting portions are connected to the main body portion by at least one insulating layer between the main body portion and the pair of connecting portions.

[0025] (Invention Effects)

[0026] The display devices according to various embodiments of the present invention can realize display devices that can improve defective solder pad portions. Of course, the scope of the present invention is not limited to this effect. Attached Figure Description

[0027] Figure 1 This is a schematic plan view of a display device according to an embodiment of the present invention.

[0028] Figure 2This is an equivalent circuit diagram illustrating the light-emitting diodes (LEDs) included in the display panel of a display device according to an embodiment of the present invention, and the pixel circuits electrically connected to the LEDs.

[0029] Figure 3 It was intercepted along Ⅲ-Ⅲ′. Figure 1 A cross-sectional view of a portion of the display device.

[0030] Figure 4 It is a schematic representation of an enlarged image. Figure 1 A plan view of part of the shape of region A.

[0031] Figure 5 It was cut off along V-V′. Figure 4 A cross-sectional view of the pad portion.

[0032] Figure 6 It is shown that... Figure 4 A cross-sectional view of the circuit section where the pads are electrically connected.

[0033] Figure 7 This is a schematic plan view of the pad portion according to an embodiment of the present invention.

[0034] Figure 8 It was intercepted along Ⅷ-Ⅷ′. Figure 7 A cross-sectional view of a portion of the conductive wire.

[0035] Figure 9 It was cut off along IX-IX′. Figure 7 A cross-sectional view of a portion of the conductive line and the second dummy line.

[0036] Figures 10a to 11d They are shown along Figure 7 A cross-sectional view of the first anti-fuse cutoff section X-X′.

[0037] Figure 12a This is a plan view schematically illustrating a method for repairing a damaged pad using a first dummy line according to an embodiment of the present invention.

[0038] Figure 12b This is a cross-sectional view showing the electrical short-circuit state of the first and second anti-fuse circuit breakers during the repair process.

[0039] Figure 13 This is a plan view schematically illustrating a method for repairing damaged pads using a second dummy line in other embodiments of the invention.

[0040] Figure 14a This is a schematic plan view illustrating the pad portion involved in other embodiments of the invention.

[0041] Figure 14bIt is shown schematically in Figure 14a A plan view of a method for repairing damaged conductive lines included in the pad section.

[0042] Figure 15a and Figure 15b This is a schematic plan view illustrating the pad portion involved in other embodiments of the invention.

[0043] Figure 15c It is along Figure 15a The cross-sectional view taken from XV-XV′.

[0044] Figure 16a and Figure 16b This is a plan view schematically illustrating a method for repairing a pad using dummy lines in the event of pad damage according to other embodiments of the present invention.

[0045] Symbol explanation:

[0046] 1: Display device; 10: Display panel; 20: Relative conductive line; 100: Substrate; 210: First insulating layer; 211: First portion; 213: Second portion; 215: Third portion; 217: Metal oxide layer; 230: Second insulating layer; 231: Upper electrode; 250: Third insulating layer; 270: Fourth insulating layer; 400: Conductive line; 410: Connecting portion; 420: Main body portion; DA: Display area; PA: Peripheral area; PX: Pixel; Cst: Energy storage capacitor; M 1: First transistor; M2: Second transistor; M3: Third transistor; DL1: First dummy line; DL2: Second dummy line; DL3: Third dummy line; DL4: Fourth dummy line; DL5: Fifth dummy line; DL6: Sixth dummy line; AF1: First anti-fuse; AF2: Second anti-fuse; E1: First electrode; E2: Second electrode; E3: Third electrode; Aa: Semiconductor layer; OP1: First opening; OP2: Second opening; OP3: Third opening; OP4: Fourth opening. Detailed Implementation

[0047] This invention can have various modifications and embodiments. Specific embodiments are illustrated in the accompanying drawings and described in detail herein. References and Appendix Figure 1 The effects, features, and methods of achieving these effects and features of the present invention will become clear from the detailed embodiments described below. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0048] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions thereof will be omitted.

[0049] In the following embodiments, terms such as "first" and "second" are not limiting terms, but are used to distinguish one constituent element from other constituent elements.

[0050] In the following embodiments, singular expressions include multiple expressions unless the opposite meaning is explicitly stated in the text.

[0051] In the following embodiments, terms such as "including" or "having" should be understood as referring to the presence of features or constituent elements described in the specification, and not as excluding the possibility of additional features or constituent elements.

[0052] In the following embodiments, when a membrane, region, constituent element, or other part is located on or above other parts, this includes not only the case where it is directly located on other parts, but also the case where other membranes, regions, constituent elements, etc. exist between them.

[0053] In the accompanying drawings, the sizes of the constituent elements may be enlarged or reduced for ease of explanation. For example, the sizes and thicknesses of the constituent elements shown are arbitrarily illustrated for ease of explanation, and the present invention is not necessarily limited to the illustrated cases.

[0054] In cases where a particular embodiment can be implemented in different ways, the specific sequence of operations may also be performed differently than the sequence described. For example, two operations described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0055] In this specification, "A and / or B" means either A, or B, or both A and B. Furthermore, in this specification, "at least one of A and B" means either A, or B, or both A and B.

[0056] In the following embodiments, when it is described as a membrane, region, or constituent element being connected, it includes not only the case where the membrane, region, or constituent element is directly connected, and / or, it also includes the case where other membranes, regions, or constituent elements are sandwiched between them and thus indirectly connected. For example, in this specification, when it is described as a membrane, region, or constituent element being electrically connected, it indicates the case where the membrane, region, or constituent element is directly electrically connected and / or the case where other membranes, regions, or constituent elements are sandwiched between them and thus indirectly electrically connected.

[0057] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system; they can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other, or they can refer to different directions that are not orthogonal to each other.

[0058] Figure 1 This is a schematic plan view of a display device 1 according to an embodiment of the present invention.

[0059] Reference Figure 1 The display device 1 includes a display area DA and a peripheral area PA outside the display area DA in a plane defined by the x-axis and y-axis directions. The peripheral area PA may be a non-display area without any display elements. The peripheral area PA may completely surround the display area DA.

[0060] When the display area DA is viewed in a planar shape, the display area DA can be as follows: Figure 1 As shown, it is set to a rectangular shape. As another embodiment, the display area DA can be set to a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, elliptical shape, or irregular shape.

[0061] The display area DA of the display panel 10 may include multiple pixels PX. Pixels PX can be configured in various forms such as stripe arrangement or Pentile arrangement to realize an image. Multiple pixels PX can be divided into multiple groups according to the displayed color. Multiple pixels PX can each realize an image using light emitted from a display element such as a light-emitting diode. Various wirings that transmit electrical signals to be applied to the display area DA, and pads PAD on which printed circuit boards or driver IC chips are attached, may be located in the peripheral area PA of the display panel 10.

[0062] The pad portion PAD is electrically connected to the circuit portion DDC. One side of the circuit portion DDC can be electrically connected to the pad portion PAD, and the other side of the circuit portion DDC can be electrically connected to the printed circuit board PB on which the control portion SC is disposed. The circuit portion DDC may include a flexible circuit board DCB, which includes a counterpad CPD connected to the pad portion PAD of the display panel 10. A driver DIC, which provides electrical signals such as data signals to the pixel PX, can be configured on the flexible circuit board DCB in the form of an IC chip.

[0063] Figure 2 This is an equivalent circuit diagram showing the light-emitting diodes (LEDs) and pixel circuits electrically connected to the LEDs in the display panel 10 of a display device according to an embodiment of the present invention.

[0064] Reference Figure 2 The anode of the LED 500 can be connected to the pixel circuit PC, and the cathode can be electrically connected to the common voltage line VSL that provides the common power supply voltage ELVSS. The LED 500 can emit light with a brightness corresponding to the amount of current supplied from the pixel circuit PC.

[0065] The pixel circuit PC may include a first transistor M1, a second transistor M2, a third transistor M3, and an energy storage capacitor Cst.

[0066] The first transistor M1, the second transistor M2, and the third transistor M3 can each be an oxide semiconductor thin film transistor (TFT) including a semiconductor layer made of oxide semiconductor, or a silicon semiconductor thin film transistor (TFT) including a semiconductor layer made of polycrystalline silicon.

[0067] The first transistor M1 can be a driving transistor. In the first transistor M1, the source electrode can be connected to the driving voltage line VDL that supplies the driving power supply voltage ELVDD, and the drain electrode can be connected to the light-emitting diode 500. The gate electrode of the first transistor M1 can be connected to the first node N1.

[0068] The second transistor M2 can be a switching transistor. The source electrode of the second transistor M2 can be connected to the data line DL, and the drain electrode can be connected to the first node N1. The gate electrode of the second transistor M2 can be connected to the scan line SL. The second transistor M2 can be turned on when the scan signal is supplied to the scan line SL, thereby electrically connecting the data line DL and the first node N1.

[0069] The third transistor M3 can be an initialization transistor and / or a sensing transistor. The source electrode of the third transistor M3 can be connected to the second node N2, and the drain electrode can be connected to the initialization sensing line ISL. The gate electrode of the third transistor M3 can be connected to the control line CL. The third transistor M3 can turn on when a control signal is supplied to the control line CL, thereby electrically connecting the initialization sensing line ISL and the second node N2. As one embodiment, the third transistor M3 can turn on according to a signal received through the control line CL, thereby initializing the anode of the light-emitting diode 500. As another embodiment, the third transistor M3 can turn on when a control signal is supplied to the control line CL, thereby sensing characteristic information of the light-emitting diode 500. The third transistor M3 has the functions of both an initialization transistor and a sensing transistor, or can have either of these functions. When the third transistor M3 functions as an initialization transistor, the initialization sensing line ISL can be named an initialization voltage line; and when it functions as a sensing transistor, the initialization sensing line ISL can be named a sensing line. The initialization and sensing operations of the third transistor M3 can be performed separately or simultaneously.

[0070] The energy storage capacitor Cst can be connected between the first node N1 and the second node N2. For example, the first capacitor electrode CE1 of the energy storage capacitor Cst can be connected to the gate electrode of the first transistor M1, and the second capacitor electrode CE2 of the energy storage capacitor Cst can be connected to the anode of the light-emitting diode 500.

[0071] exist Figure 2The illustration shows the first transistor M1, the second transistor M2, and the third transistor M3 as NMOS, but the invention is not limited thereto. For example, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 can be configured as PMOS.

[0072] exist Figure 2 Three transistors are shown, but the invention is not limited thereto. The pixel circuit PC may include four or more transistors.

[0073] Figure 3 It was intercepted along Ⅲ-Ⅲ′. Figure 1 A cross-sectional view of a portion of the display device.

[0074] Reference Figure 3 An embodiment of the present invention relates to a display device 1, which may include a substrate 100 and a thin-film transistor TFT disposed on the upper part of the display area DA.

[0075] The substrate 100 may comprise glass, metal, or a polymer resin. Assuming the substrate 100 has flexible or bendable properties, it may comprise, for example, a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. This is merely illustrative and the invention is not limited thereto.

[0076] The substrate 100 may have a single-layer or multi-layer structure of the aforementioned material, and in the case of a multi-layer structure, it may further include an inorganic insulating layer. In some embodiments, the substrate 100 may have a structure of organic / inorganic / organic / inorganic insulating material, such as a polymer resin.

[0077] In the display area DA, in the z-axis direction perpendicular to the x-axis and y-axis directions, the thin-film transistor (TFT) may be located on the upper part of the substrate 100, and the light-emitting diode (LED) 500 electrically connected to the TFT may be located on the upper part of the TFT. Specifically, the TFT may be electrically connected to the anode 510 included in the LED 500.

[0078] The thin-film transistor (TFT) may include a semiconductor layer 307, a gate electrode 301 overlapping the channel region of the semiconductor layer 307, and a source electrode 303 and a drain electrode 305 respectively connected to the source region and drain region of the semiconductor layer 307. Furthermore, the energy storage capacitor Cst may include a first capacitor electrode 405, a second capacitor electrode 401, and a third capacitor electrode 403.

[0079] The semiconductor layer 307 of the thin-film transistor (TFT) may include an oxide semiconductor material. The oxide semiconductor may include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), etc. The semiconductor layer 307 may include an oxide selected from, for example, containing at least one of the following: indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). As an example, the semiconductor layer 307 may be a semiconductor layer composed of any one of indium tin zinc oxide (ITZO, InSnZnO), indium gallium zinc oxide (IGZO, InGaZnO), and indium tin gallium oxide (ITGO, InSnGaO). This is merely an example, and the invention is not limited thereto. In other embodiments, the semiconductor layer 307 may include polycrystalline silicon, or may include amorphous silicon, or may include organic semiconductors, etc.

[0080] The gate electrode 301 of the thin-film transistor (TFT) may overlap with the channel region of the semiconductor layer 307, with a gate insulating layer 309 sandwiched therebetween. The gate insulating layer 309 may be formed in the same masking process as the gate electrode 301. The gate electrode 301 may include a conductive material containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or a single layer comprising the aforementioned materials. In some embodiments, the gate electrode 301 may have a multilayer structure, comprising a metal layer containing the aforementioned metal elements and a transparent conductive oxide layer such as ITO on the aforementioned metal layer. Furthermore, the gate insulating layer 309 may include inorganic materials such as silicon oxide, silicon nitride, and / or silicon nitride.

[0081] The source electrode 303 of the thin-film transistor (TFT) can be electrically connected to the semiconductor layer 307 through the first contact hole CNT1. The drain electrode 305 can be electrically connected to the semiconductor layer 307 through the second contact hole CNT2.

[0082] The energy storage capacitor Cst may include at least two electrodes. As one embodiment, Figure 3The diagram illustrates a storage capacitor Cst comprising a first capacitor electrode 405, a second capacitor electrode 401, and a third capacitor electrode 403. The second capacitor electrode 401 and the first capacitor electrode 405 may be spaced apart by an insulating layer sandwiched between them. The third capacitor electrode 403 and the first capacitor electrode 405 may also be spaced apart by an insulating layer sandwiched between them. The second capacitor electrode 401 and the third capacitor electrode 403 may be electrically connected via a third contact hole CNT3. The second capacitor electrode 401 may comprise one or more of the following materials: aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), and copper (Cu). In some embodiments, the capacitor electrode serving as the lower electrode may have a multilayer structure, comprising a metal layer containing the aforementioned metallic elements and a transparent conductive oxide layer such as ITO on the aforementioned metal layer.

[0083] The first capacitor electrode 405 of the energy storage capacitor Cst can be formed in the same process as the gate electrode 301, and may include the same material as the gate electrode 301. An insulating layer 407 comprising the same material as the gate insulating layer 309 may be disposed below the first capacitor electrode 405. The insulating layer 407 below the first capacitor electrode 405 may be formed together with the first capacitor electrode 405 in the same masking process. Alternatively, the gate insulating layer 309 and the insulating layer 407 may be formed integrally, and in this case, the processes of forming the gate electrode 301 and the first capacitor electrode 405 and the processes of forming the gate insulating layer 309 and the insulating layer 407 may be performed separately.

[0084] A first insulating layer 210 may be sandwiched between the thin-film transistor TFT and the substrate 100. A second insulating layer 230 may be disposed on the upper part of the first insulating layer 210. A third insulating layer 250 may be disposed on the upper part of the second insulating layer 230. A fourth insulating layer 270 may be disposed on the upper part of the third insulating layer 250.

[0085] The first insulating layer 210 may serve as a buffer layer to reduce or block the penetration of foreign matter, moisture, or external air from the lower part of the substrate 100 and to provide a flat surface on the substrate 100. The first insulating layer 210 may include inorganic materials such as oxides or nitrides, or organic materials, or organic-inorganic composites, and may be composed of a single layer or multiple layers of inorganic and organic materials.

[0086] The second insulating layer 230 may cover the upper surfaces of the gate electrode 301 and the first capacitor electrode 405, and may be disposed below the source electrode 303, the drain electrode 305, and the third capacitor electrode 403. The second insulating layer 230 may be an inorganic insulating film made of inorganic materials. Polysiloxanes, silicon nitrides, silicon oxides, and silicon nitrides may be used as inorganic materials. Furthermore, the second insulating layer 230 may be a single film or a multilayer film of inorganic materials such as silicon nitrides and silicon oxides. The second insulating layer 230 may be introduced to cover and protect a portion of the wiring disposed on the first insulating layer 210.

[0087] The third insulating layer 250 may cover at least a portion of the upper surface of each of the source electrode 303, the drain electrode 305, and the third capacitor electrode 403. The third insulating layer 250 may include inorganic materials such as silicon oxide, silicon nitride, and silicon nitride. The third insulating layer may be a passivation layer protecting the source electrode 303, the drain electrode 305, etc.

[0088] A fourth insulating layer 270 may be disposed on the third insulating layer 250. The fourth insulating layer 270 may be a planarized insulating layer. The fourth insulating layer 270 may include an organic insulator. Organic insulators may include, for example, general-purpose polymers such as polymethyl methacrylate (PMMA) or polystyrene (PS), phenolic polymer derivatives, acrylic polymers, imide polymers, aromatic ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof. This is merely illustrative and the invention is not limited thereto.

[0089] The thin-film transistor (TFT) can be electrically connected to the anode 510 disposed on the upper part of the fourth insulating layer 270. As an embodiment, the anode 510 can be electrically connected to the source electrode 303 of the thin-film transistor TFT or to the drain electrode 305 through the fourth contact hole CNT4 formed in the fourth insulating layer 270.

[0090] The anode 510 may comprise a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). As in other embodiments, the anode 510 may comprise a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof.

[0091] A dam layer 290 may be disposed on the upper part of the fourth insulating layer 270. The dam layer 290 may have pixel openings corresponding to each pixel PX. The pixel openings of the dam layer 290 may be openings that expose the central portion of the anode 510, and the dam layer 290 may serve to define the pixel PX through the pixel openings. The dam layer 290 as described above may, for example, include organic materials such as polyimide or hexamethyldisiloxane.

[0092] The intermediate layer 520 includes a light-emitting layer 522 disposed within an opening defined by the dam layer 290 and overlapping with the anode 510. The intermediate layer 520 may include a first functional layer 521 disposed below the light-emitting layer 522 and / or a second functional layer 523 disposed above the light-emitting layer 522.

[0093] The first functional layer 521 may be a single layer or multiple layers. The first functional layer 521 may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0094] The light-emitting layer 522 may include a high- or low-molecular-weight organic material that emits light of a predetermined color. The second functional layer 523 may include an electron transport layer (ETL) and / or an electron injection layer (EIL). On the other hand, as... Figure 3 As shown, the light-emitting layer 522 can be patterned to correspond to each anode 510, but according to an embodiment, it can be an integral layer covering multiple anodes 510.

[0095] The cathode 530 can be a transparent electrode or a reflective electrode. In some embodiments, the cathode 530 can be a transparent or translucent electrode and can be formed of a conductive material with a low work function, including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Furthermore, a transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, can also be included on the metal thin film. The cathode 530 can be configured to span the display area DA and can be configured on top of the intermediate layer 520. In a plurality of light-emitting diodes 500, the cathode 530 can be formed as a single unit to correspond to a plurality of anodes 510.

[0096] A multilayer light-emitting diode 500, including the aforementioned anode 510, intermediate layer 520, and cathode 530, may be easily damaged by external moisture or oxygen. Therefore, it can be protected by covering it with an encapsulation layer 600. The encapsulation layer 600 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. As an embodiment, the encapsulation layer 600 may include a first inorganic encapsulation layer 610, an organic encapsulation layer 620, and a second inorganic encapsulation layer 630 stacked sequentially.

[0097] The first inorganic encapsulation layer 610 and the second inorganic encapsulation layer 630 may each include one or more inorganic insulators. The inorganic insulators may include aluminum oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon nitride. The organic encapsulation layer 620 may include a polymer-based material. Polymer-based materials may include acrylic resins, epoxy resins, polyimide, and polyethylene, etc. Acrylic resins may include, for example, polymethyl methacrylate, polyacrylic acid, etc. This is merely an example, and the invention is not limited thereto.

[0098] Figure 4 It is a schematic representation of an enlarged image. Figure 1 A plan view of part of the shape of region A.

[0099] Reference Figure 4 A pad portion PAD for electrical connection with the circuit section DDC can be disposed on one side of the substrate 100. The flexible circuit board DCB of the circuit section DDC may include a corresponding pad CPD that corresponds to the pad portion PAD on the substrate 100. The corresponding pad CPD may include a corresponding conductive line 20 that can overlap and be electrically connected to each conductive line 400 of the pad portion PAD. As previously referred to Figure 1 As explained, the data signal or voltage generated based on the control signal of the control unit SC can be transmitted to the display area DA via the relative conductive lines 20 and 400. Figure 1 Pixel circuit PC () Figure 3 ).

[0100] Figure 5 It is along Figure 4 A cross-sectional view taken from V-V′ of the pad portion of the PAD, and Figure 6 It is shown that... Figure 4 A cross-sectional view of the circuit section DDC where the pads (PAD) are electrically connected.

[0101] Reference Figure 5 The conductive lines 400 of the pad portion PAD can be disposed on the substrate 100. A first insulating layer 210 and a second insulating layer 230 can be disposed below the conductive lines 400. The conductive lines 400 may include a main body portion 420. Further details will be provided later. Figure 7 This will be discussed later.

[0102] The third insulating layer 250 may include a first opening OP1 that exposes a portion of the upper surface of the main body portion 420. In other words, the third insulating layer 250 may include a first opening OP1 that covers the edge of the main body portion 420 but exposes the central portion of the main body portion 420.

[0103] A fourth insulating layer 270 may be disposed on the third insulating layer 250 and may include a second opening OP2 that overlaps with the first opening OP1. The first opening OP1 may have a wider width than the second opening OP2, but in other embodiments, the second opening OP2 may have a wider width than the first opening OP1.

[0104] Main body 420 can be referenced previously. Figure 3 The source electrode 303, drain electrode 305, and third capacitor electrode 403 described herein are formed in the same process. The main body 420 may include the same material as the source electrode 303, drain electrode 305, and / or third capacitor electrode 403. The main body 420 may include a metal layer containing a metal such as copper and a transparent conductive oxide layer 421 such as ITO, IZO, ZnO, or In2O3 disposed on top of the aforementioned metal layer.

[0105] Reference Figure 6 An anisotropic conductive film ACF may be sandwiched between the flexible circuit board DCB and the conductive line 400. The anisotropic conductive film ACF may include an adhesive resin layer RES and conductive particles CB irregularly distributed within the adhesive resin layer RES. The adhesive resin layer RES can bond the flexible circuit board DCB and the conductive line 400. Specifically, after the anisotropic conductive film ACF is disposed between the flexible circuit board DCB and the conductive line 400, it can be pressed at a high temperature to electrically connect the flexible circuit board DCB and the conductive line 400. The conductive particles CB can electrically connect the main body 420 of the conductive line 400 and the opposite conductive line 20 of the flexible circuit board DCB.

[0106] Figure 7 This is a schematic plan view of a pad portion PAD according to an embodiment of the present invention. Figure 8 It is cut along Ⅷ-Ⅷ′ Figure 7 A cross-sectional view of a portion of the conductive wire 400, and Figure 9 It is cut along IX-IX′ Figure 7 A cross-sectional view of a portion of the conductive line 400 and the second dummy line DL2.

[0107] Reference Figure 7 The pad portion PAD may include a conductive line 400, a first anti-fuse AF1 and a second anti-fuse AF2 electrically connected to the conductive line 400, and a first dummy line DL1 and a second dummy line DL2 electrically connected to the first anti-fuse AF1 and the second anti-fuse AF2.

[0108] The pad portion (PAD) may include multiple conductive lines 400. Some of the multiple conductive lines 400 may be used to provide data signals, another may be used to provide drive power voltage, and yet another may be used to provide a common power voltage.

[0109] Each conductive wire 400 may include multiple portions of electrical connection. Regarding this, Figure 7 The diagram shows a conductive wire 400 comprising a pair of connecting portions 410 and a main body portion 420. The pair of connecting portions 410 may be spaced apart from each other and may be respectively disposed on both sides of the main body portion 420.

[0110] The main body 420 and the connecting part 410 can be configured on different layers. For example, as Figure 8 As shown, a first insulating layer 210 and a second insulating layer 230 may be sandwiched between the connecting portion 410 and the main body portion 420. The main body portion 420 can be electrically connected to the connecting portion 410 through contact holes CNTs penetrating the first insulating layer 210 and the second insulating layer 230.

[0111] As previously referred to Figure 5 and Figure 6 As explained, the main body 420 allows the central portion to be exposed so that it can be electrically connected to the opposing conductive wire 20. Regarding this, Figure 8 The illustration shows a case where the third insulating layer 250 on the main body 420 includes a first opening OP1 overlapping the central portion of the main body 420, and the fourth insulating layer 270 includes a second opening OP2 overlapping the central portion of the main body 420. As described above, the main body 420 may include a metal layer containing a metal such as copper, and a transparent conductive oxide layer 421 such as ITO, IZO, ZnO, or In2O3 disposed on top of the aforementioned metal layer.

[0112] The connecting portion 410 can directly contact the lower part of the main body 420 (e.g., the upper surface of the substrate 100). The connecting portion 410 can be in direct contact with the previously referenced... Figure 3 The second capacitor electrode 401 described is formed in the same process and may include the same material as the second capacitor electrode 401.

[0113] The first anti-fuse AF1 and the second anti-fuse AF2 can be configured to be spaced apart from each other along the length of the conductive line 400. The first anti-fuse AF1 and the second anti-fuse AF2 can each include a first electrode E1, a second electrode E2, and a third electrode E3. The first electrode E1 of the first anti-fuse AF1 and the second anti-fuse AF2 can be electrically connected to the connection portion 410 of the conductive line 400. The first electrode E1 can be formed integrally in the same process as the connection portion 410. However, the present invention is not limited thereto. As an example, the first electrode E1 can be formed separately or in the same process as the connection portion 410, and electrically connected through a contact hole or the like.

[0114] The second electrode E2 of the first anti-fuse AF1 and the second anti-fuse AF2 can be electrically connected to the first dummy line DL1, and the third electrode E3 of the first anti-fuse AF1 and the second anti-fuse AF2 can be electrically connected to the second dummy line DL2.

[0115] Either the first dummy line DL1 or the second dummy line DL2 can be equivalent to a bypass line or repair line used to replace the damaged conductive line with an electrical signal or voltage applied to it when the conductive line 400 is damaged, thus providing the signal or voltage to the pixel circuit PC. Unlike the main body 420 of the conductive line 400, the first dummy line DL1 and the second dummy line DL2 are not exposed to the outside. For example, as... Figure 9 As shown, the main body 420 of the conductive wire 400 overlaps with the first opening OP1 and the second opening OP2, while conversely, the second dummy wire DL2 can be entirely covered by the third insulating layer 250 and the fourth insulating layer 270.

[0116] Either the first dummy line DL1 or the second dummy line DL2 can be electrically connected to the damaged conductive line simultaneously if the electrical insulation between the first electrode E1 and the second electrode E2 or between the first electrode E1 and the third electrode E3 is broken. Hereinafter, with reference to... Figures 10a to 11d After explaining the structure of the first anti-fuse AF1 and the second anti-fuse AF2, the path that becomes a bypass when the conductor 400 is damaged is explained.

[0117] Figures 10a to 11d They are shown along Figure 7 A cross-sectional view of the first anti-fuse, taken from X-X′. Although Figures 10a to 11d The structure of the first anti-fuse AF1 will be described, but the second anti-fuse AF2 also has the same structure as the first anti-fuse AF1.

[0118] Reference Figure 10a An embodiment of the present invention relates to a first anti-fuse AF1, which may include an electrically insulated first electrode E1, a second electrode E2, and a third electrode E3.

[0119] The first electrode E1 may be disposed directly above the upper surface of the substrate 100. (Refer to previous text) Figure 7 As explained, the first electrode E1 can be connected to the conductive line 400 ( Figure 7 The connecting part 410 is formed as a whole.

[0120] The second electrode E2 and the third electrode E3 may be formed on a different layer than the first electrode E1. The second electrode E2 and the third electrode E3 may be disposed on the second insulating layer 230 and covered by the third insulating layer 250. Either the second electrode E2 or the third electrode E3 may be referenced previously. Figure 7 The first dummy line DL1 is formed as a single unit, and another dummy line DL2 can be formed as a single unit. For example, the second electrode E2 can be a part of the first dummy line DL1, and the third electrode E3 can be a part of the second dummy line DL2.

[0121] The first electrode E1 and the second electrode E2, as well as the first electrode E1 and the third electrode E3, can be electrically insulated by the first insulating layer 210. The first insulating layer 210 may include a first portion 211 directly contacting the substrate 100 and the second insulating layer 230 respectively, a second portion 213 between the first electrode E1 and the second electrode E2, and a third portion 215 between the first electrode E1 and the third electrode E3. The second portion 213 and the third portion 215 may be formed thinner than the first portion 211, thereby easily disrupting the insulation between the first electrode E1 and the second electrode E2 or between the first electrode E1 and the third electrode E3 during the repair or bypass process described later. As an embodiment, the thickness of the second portion 213 and the third portion 215 may be approximately [missing information - likely a thickness value].

[0122] As some embodiments, the first anti-fuse AF1 may include a semiconductor layer Aa on the first insulating layer 210. The semiconductor layer Aa may be electrically connected to the second electrode E2 and / or the third electrode E3 through contact holes penetrating the second insulating layer 230. However, the invention is not limited thereto. As an example, an embodiment of the invention relates to a first anti-fuse AF1 that may not include a semiconductor layer.

[0123] Reference Figure 10b In other embodiments of the present invention, the first anti-fuse AF1 may further include an upper electrode 231 and an insulating layer 233 between the upper electrode 231 and the semiconductor layer Aa on the semiconductor layer Aa. The upper electrode 231 may be in an electrically floating state.

[0124] Semiconductor layer Aa and upper electrode 231 can be respectively in relation to reference Figure 3The semiconductor layer 307 and gate electrode 301 of the described thin-film transistor (TFT) are formed in the same process and include the same material. The upper electrode 231 may be formed to have a wider width than the first electrode E1. In this case, the portion of the semiconductor layer Aa that overlaps with the upper electrode 231 has a weaker conductivity than the portion that does not overlap with the upper electrode 231, and this can easily damage the insulation between the first electrode E1 and the second electrode E2 or between the first electrode E1 and the third electrode E3 during the repair process described later.

[0125] Reference Figure 11a In other embodiments of the present invention, the first anti-fuse AF1 may further include a metal oxide layer 217. The metal oxide layer 217 may be formed on the first electrode E1. As an example, the first electrode E1 may be composed of multiple layers of molybdenum (Mo) and aluminum (Al), and the upper part of the first electrode E1 may be subjected to plasma treatment or heat treatment to form the metal oxide layer 217 comprising metal oxides. As an embodiment, the metal oxide layer 217 may have insulating properties, such as aluminum oxide. The metal oxide layer 217 may have approximately The thickness.

[0126] Reference Figure 11b It may also include an upper electrode 231 on the semiconductor layer Aa of the first anti-fuse AF1 and an insulating layer 233 between the upper electrode 231 and the semiconductor layer Aa, and the description of the upper electrode 231 and the insulating layer 233 is as follows: Figure 10b As explained in the text.

[0127] Figure 11a The illustration shows a case where the metal oxide layer 217 only covers the upper surface of the first electrode E1, but the invention is not limited thereto. As another embodiment, see [reference needed]. Figure 11c The metal oxide layer 217 can extend through the first electrode E1 and directly contact the upper surface of the substrate 100.

[0128] Reference Figure 11d The first anti-fuse AF1 may also include an upper electrode 231 and an insulating layer 233 between the upper electrode 231 and the semiconductor layer Aa on the semiconductor layer Aa.

[0129] Figure 12a This is a schematic plan view illustrating a method for repairing a damaged pad (PAD) using a first dummy line (DL1) according to an embodiment of the present invention. Figure 12b This is a cross-sectional view showing the electrical short-circuit state of the first anti-fuse AF1 and the second anti-fuse AF2 during the repair process.

[0130] Figure 12aThe illustration shows a damaged ER in any one of a plurality of conductive lines 400 (hereinafter referred to as the damaged conductive line) 400a. As an embodiment, the conductive line 400 may include, for example, a metal layer such as copper and an indium tin oxide (ITO) layer on the metal layer, and the indium tin oxide layer may be crystallized by a heat treatment process that may be included in the manufacturing process of the display device. The crystallized ITO may include a large number of pinholes. As previously described... Figure 5 As explained, the main body 420 of the conductive wire 400 can be exposed through the first opening OP1 and the second opening OP2. If the anode is etched in the exposed state of the main body 420, the etchant used in the etching process may damage the metal layer of the main body 420 through the pinhole.

[0131] As a method to resolve this situation, a first voltage V1, a second voltage V2, and a third voltage V3 can be applied to the damaged conductive wire 400a, the first dummy wire DL1, and the second dummy wire DL2, respectively. At this time, if the voltage difference between the first voltage V1 and the second voltage V2 is greater than the voltage difference between the first voltage V1 and the third voltage V3, then simultaneously, the insulation between the first electrode E1 and the second electrode E2 of each of the first anti-fuse AF1 and the second anti-fuse AF2 is broken, such as... Figure 12b As shown, the first electrode E1 and the second electrode E2 can be electrically connected.

[0132] Therefore, as Figure 12a As indicated by the arrow, the signal transmitted to the damaged conductive line 400a can be transmitted sequentially through the first electrode E1 of the second anti-fuse AF2, the second electrode E2 of the second anti-fuse AF2, the first dummy line DL1, the second electrode E2 of the first anti-fuse AF1, and the first electrode E1 of the first anti-fuse AF1 to the line of the pixel circuit PC (e.g., data line, etc.).

[0133] Figure 13 This is a plan view schematically illustrating a method for repairing a damaged pad (PAD) using a second dummy line (DL2) in other embodiments of the invention.

[0134] Reference Figure 13 A first voltage V1, a second voltage V2, and a third voltage V3 can be applied to the damaged conductive wire 400a, the first dummy wire DL1, and the second dummy wire DL2, respectively. If the voltage difference between the first voltage V1 and the third voltage V3 is greater than the voltage difference between the first voltage V1 and the second voltage V2, then the insulation between the first electrode E1 and the third electrode E3 of each of the first and second anti-fuse AF1 and anti-fuse AF2 is broken, and the first electrode E1 and the third electrode E3 can be electrically connected.

[0135] Therefore, as Figure 13As indicated by the arrow, the signal transmitted to the damaged conductive line 400a can be transmitted sequentially through the first electrode E1 of the second anti-fuse AF2, the third electrode E3 of the second anti-fuse AF2, the second dummy line DL2, the third electrode E3 of the first anti-fuse AF1, and the first electrode E1 of the first anti-fuse AF1 to the line of the pixel circuit PC (e.g., data line, etc.).

[0136] Figure 14a This is a schematic plan view of the pad portion PAD according to other embodiments of the invention.

[0137] Reference Figure 14a The pad portion PAD may include a conductive line 400, a first anti-fuse AF1 and a second anti-fuse AF2 electrically connected to the conductive line 400, and a first dummy line DL1, a third dummy line DL3, and a fourth dummy line DL4 electrically connected to the first anti-fuse AF1 and the second anti-fuse AF2. The conductive line 400, the first anti-fuse AF1 and the second anti-fuse AF2, and the first dummy line DL1, comprising the main body portion 420 and the connecting portion 410, are respectively referred to previously. Figures 7 to 11d As explained.

[0138] Figure 14a The pad shown is different from the pad area. Figure 7 The difference between the pad portion PAD and the previous one is that the second dummy line DL2 is not included, and the third dummy line DL3 and the fourth dummy line DL4 are electrically separated. The third dummy line DL3 can be electrically connected to the third electrode E3 of the first anti-fuse AF1. The fourth dummy line DL4 can be electrically connected to the third electrode E3 of the second anti-fuse AF2.

[0139] Figure 14b It is shown schematically. Figure 14a A plan view of a method for repairing a damaged conductive line 400 included in the pad portion PAD.

[0140] Reference Figure 14b First, a first voltage V1, a second voltage V2, and a third voltage V3 are applied to the damaged conductive wire 400a, the first dummy wire DL1, and the third dummy wire DL3, respectively. At this time, the voltage difference between the first voltage V1 and the second voltage V2 can be greater than the voltage difference between the first voltage V1 and the third voltage V3. Simultaneously, as the insulation between the first electrode E1 and the second electrode E2 of the first anti-fuse AF1 is broken, ... Figure 12b As shown, the first electrode E1 and the second electrode E2 can be electrically connected.

[0141] Subsequently, a first voltage V1, a second voltage V2, and a fourth voltage V4 can be applied to the damaged conductive wire 400a, the first dummy wire DL1, and the fourth dummy wire DL4, respectively. At this time, the voltage difference between the first voltage V1 and the second voltage V2 can be greater than the voltage difference between the first voltage V1 and the fourth voltage V4. Simultaneously, as the insulation between the first electrode E1 and the second electrode E2 of the second anti-fuse AF2 is broken, as... Figure 12b As shown, the first electrode E1 and the second electrode E2 can be electrically connected.

[0142] Therefore, as Figure 14b As indicated by the arrow, the signal transmitted to the damaged conductive line 400a can be transmitted sequentially through the first electrode E1 of the second anti-fuse AF2, the second electrode E2 of the second anti-fuse AF2, the first dummy line DL1, the second electrode E2 of the first anti-fuse AF1, and the first electrode E1 of the first anti-fuse AF1 to the line of the pixel circuit PC (e.g., data line, etc.).

[0143] Figure 15a and Figure 15b This is a schematic plan view of the pad portion PAD according to other embodiments of the invention. Figure 15c It is along Figure 15a A sectional view taken at XV-XV′. Figure 15a and Figure 15c In, with Figure 7 The same symbols indicate the same parts, so their repeated descriptions are omitted.

[0144] Reference Figure 15a The pad portion PAD may include a conductive line 400 having a main body portion 420 and a connecting portion 410, a first anti-fuse AF1 electrically connected to the conductive line 400, a dummy line (hereinafter referred to as the fifth dummy line) DL5 electrically connected to the second electrode E2 of the first anti-fuse AF1, and a dummy line (hereinafter referred to as the sixth dummy line) DL6 electrically connected to the third electrode E3 of the first anti-fuse AF1.

[0145] Reference Figure 15b ,and Figure 15a The flexible circuit board DCB connected to the pad portion PAD may also include a first relative conductive line 21a and a second relative conductive line 21b that overlap and are electrically connected to the sixth dummy line DL6 and the fifth dummy line DL5, respectively.

[0146] The sixth dummy line DL6 can have its central portion exposed for electrical connection with the first opposing conductive line 21a. Regarding this, Figure 15cThis illustrates a case where the third insulating layer 250 on the sixth dummy line DL6 includes a third opening OP3 overlapping the central portion of the sixth dummy line DL6, and the fourth insulating layer 270 includes a fourth opening OP4 overlapping the central portion of the sixth dummy line DL6. Although Figure 15c Only the sixth dummy line DL6 is shown, but the fifth dummy line DL5 may also have the same structure as the sixth dummy line DL6.

[0147] Figure 16a and Figure 16b This is a plan view schematically illustrating a method for repairing a pad PAD using dummy lines in the event of damage to the pad PAD according to other embodiments of the present invention. Figure 16a and Figure 16b In, with Figure 7 The same symbols indicate the same parts, so their repeated descriptions are omitted.

[0148] Reference Figure 16a A first voltage V1 can be applied to the damaged conductive wire 400a, and a fifth voltage V5 and a sixth voltage V6 can be applied to the fifth dummy wire DL5 and the sixth dummy wire DL6, respectively. At this time, the voltage difference between the first voltage V1 and the fifth voltage V5 can be greater than the voltage difference between the first voltage V1 and the sixth voltage V6. At this time, while the insulation between the first electrode E1 and the second electrode E2 of the first anti-fuse AF1 is broken, as... Figure 12b As shown, the first electrode E1 and the second electrode E2 can be electrically connected.

[0149] Therefore, through the second relative conductive line 21b ( Figure 15b The signal transmitted to the fifth dummy line DL5 can be transmitted to the line (e.g., data line, etc.) of the pixel circuit PC in sequence through the second electrode E2 and the first electrode E1 of the first anti-fuse AF1.

[0150] Reference Figure 16b The voltage difference between the first voltage V1 and the sixth voltage V6 can be greater than the voltage difference between the first voltage V1 and the fifth voltage V5. At this time, while the insulation between the first electrode E1 and the third electrode E3 of the first anti-fuse AF1 is broken, the first electrode E1 and the third electrode E3 can be electrically connected.

[0151] Therefore, through the first relative conductive line 21a ( Figure 15b The signal transmitted to the sixth dummy line DL6 can be transmitted to the line (e.g., data line, etc.) of the pixel circuit PC in sequence through the third electrode E3 and the first electrode E1 of the first anti-fuse AF1.

[0152] As described above, the present invention has been illustrated with reference to the various embodiments shown in the accompanying drawings. However, these are merely illustrative, and those skilled in the art should understand that various modifications and variations of the embodiments are possible therefrom. Therefore, the true scope of protection of the present invention should be defined by the technical concept of the claims.

Claims

1. A display device, comprising: The display area includes pixels disposed on the substrate; The pad portion is located on the substrate and is disposed in the non-display area surrounding the display area; as well as The circuit section overlaps with and is electrically connected to the pad section. The pad portion includes: Conductive wire; A first dummy line is disposed around the conductive line; and The first and second anti-fuse circuit breakers are configured to be adjacent to the conductive wire and spaced apart from each other along the length of the conductive wire. The first anti-fuse and the second anti-fuse each include: A first electrode is electrically connected to a portion of the conductive wire; and The second electrode is electrically connected to a portion of the first dummy line, and a first insulating layer is sandwiched between the second electrode and the first electrode.

2. The display device according to claim 1, wherein, The first electrode of the first anti-fuse and the first electrode of the second anti-fuse are integrated with a portion of the conductive wire.

3. The display device according to claim 1, wherein, The conductive wire includes: The main body overlaps with the circuit section; and A pair of connecting parts are respectively disposed on both sides of the main body. The pair of connecting portions are connected to the main body portion by at least one insulating layer between the main body portion and the pair of connecting portions.

4. The display device according to claim 1, wherein, The first anti-fuse and the second anti-fuse each further include a third electrode, which is spaced apart from the first electrode while being sandwiched between the first insulating layer.

5. The display device according to claim 4, wherein, The pad portion further includes a second dummy line, which is electrically connected to the third electrode of the first anti-fuse and the third electrode of the second anti-fuse.

6. The display device according to claim 5, wherein, The second dummy line is integrated with the third electrode of the first anti-fuse and the third electrode of the second anti-fuse.

7. The display device according to claim 6, wherein, The first insulating layer includes: The first portion located on the substrate; The second portion between the first electrode and the second electrode; and the third portion between the first electrode and the third electrode, The thickness of the second part and the third part is less than the thickness of the first part.

8. The display device according to claim 1, wherein, At least one of the first anti-fuse and the second anti-fuse further includes a metal oxide layer on the upper part of the first electrode.

9. The display device according to claim 1, wherein, At least one of the first anti-fuse and the second anti-fuse further includes: a semiconductor layer, located between the first electrode and the second electrode, and connected to the second electrode.

10. The display device according to claim 9, wherein, At least one of the first anti-fuse and the second anti-fuse further includes an upper electrode on the upper part of the semiconductor layer.

11. The display device according to claim 10, wherein, The width of the upper electrode is greater than the width of the first electrode.

12. The display device according to claim 4, wherein, The pad portion also includes: The third dummy line is electrically connected to the third electrode of the first anti-fuse; and The fourth dummy line is spaced apart from the third dummy line and is electrically connected to the third electrode of the second anti-fuse.

13. The display device according to claim 12, wherein, The third dummy line is integrated with the third electrode of the first anti-fuse. The fourth dummy line is integrated with the third electrode of the second anti-fuse.

14. A display device, comprising: The display area includes pixels disposed on the substrate; The pad portion is located on the substrate and is disposed in the non-display area surrounding the display area; as well as The circuit section overlaps with and is electrically connected to the pad section. The pad portion includes: a conductive line; a first anti-fuse electrically connected to the conductive line; and a first dummy line. The first anti-fuse includes: a first electrode; and a second electrode, spaced apart from the first electrode by a first insulating layer sandwiched between them, and electrically connected to the first dummy line. The circuit section includes a relative conductive line that overlaps with the conductive line and a first relative conductive line that overlaps with the first dummy line.

15. The display device according to claim 14, further comprising: The upper insulating layer covers the edge of the first dummy line and includes an opening that overlaps with the first dummy line.

16. The display device according to claim 14, wherein, The first anti-fuse further includes a third electrode, spaced apart from the first electrode while sandwiched between the first insulating layer.

17. The display device according to claim 16, wherein, The pad portion further includes a second dummy line, which is electrically connected to the third electrode of the first anti-fuse.

18. The display device according to claim 17, wherein, The circuit section further includes a second relative conductive line that overlaps with the second dummy line.

19. The display device according to claim 17, wherein, The first insulating layer includes: The first portion located on the substrate; The second portion between the first electrode and the second electrode; and The third portion between the first electrode and the third electrode, The thickness of the second part and the third part is less than the thickness of the first part.

20. The display device according to claim 14, wherein, The conductive wire includes: The main body overlaps with the circuit section; and A pair of connecting parts are respectively disposed on both sides of the main body. The pair of connecting portions are connected to the main body portion by at least one insulating layer between the main body portion and the pair of connecting portions.

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