An insulated gate bipolar transistor and a method of manufacturing the same

Abstract

The application provides an insulated gate bipolar transistor and a manufacturing method thereof. The insulated gate bipolar transistor comprises a body layer, the body layer comprising a cell region and a transition region surrounding the cell region, the transition region comprising a convergence region; a gate structure on or in part of the cell region; a gate convergence strip on the convergence region, the gate convergence strip having a first opening with part of the edge of the gate structure; a ballast structure in the convergence region and extending into part of the cell region at the bottom of the first opening; a well region in part of the cell region around the gate structure, the body layer at the bottom of the first opening having the well region, the well region having the same conductivity type as the ballast structure; a source doped region in the top region of the well region, the source doped region having the opposite conductivity type to the well region, and the source doped region being spaced from the ballast structure. The above insulated gate bipolar transistor can alleviate the current concentration of the cell region and reduce the risk of latch-up.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to an insulated gate bipolar transistor and a manufacturing method thereof. Background Art

[0002] Insulated gate bipolar transistors (IGBTs) are key components in high-voltage applications because they combine the advantages of both unipolar and bipolar devices, such as controllable gate voltage, low on-state voltage, and low device losses. They are widely used in inverters and converters for railways, electric vehicles, and power transmission systems.

[0003] like Figure 1 As shown, the insulated gate bipolar transistor substrate includes a body layer 100c, a buffer region 101c, and a collector region 11c stacked from top to bottom. On the back, the collector region 11c contacts the collector electrode. On the front, from left to right, are the cell region 1c and the terminal region 2c. The cell region 1c has a well region 6c and a source doped region 7c. The well region 6c surrounds the source doped region 7c. The source doped region 7c and the well region 6c are connected to the emitter electrode layer 9c. The collector region, body layer, and well region form a transistor. The gate electrode / oxide layer and the transistor together form a metal-oxide-semiconductor structure. The gate electrode controls the base current flowing into the transistor.

[0004] When the gate is on, the collector region located in the cell and terminal regions injects a high concentration of holes into the bulk layer. The high concentration of holes in the bulk layer of the cell region can achieve conductivity modulation and reduce the on-resistance, but the high concentration of holes in the bulk layer of the terminal region does not significantly reduce the on-resistance. However, when the gate is turned off, the holes need to be extracted, and the holes in the terminal region also need to be extracted. Because the terminal region is at a higher potential than the cell region during shutdown, the hole current in the terminal region ultimately flows to the low-potential cell region. The cell region adjacent to the terminal region receives the largest hole current. When the current reaches a certain level, the PN junction between the well region and the source doped region turns on, and the chip latches up. At high temperatures or in extremely harsh operating conditions such as high current shutdown, hole injection is enhanced, making these adverse effects more severe, degrading device performance and potentially causing thermal damage. The above situation applies to all voltage ranges, but ultra-high voltage (breakdown voltage > 3.3kV) insulated gate bipolar transistors (IGBTs) are particularly affected because their terminal regions are very large, often accounting for more than 50% of the total chip area, and the cells at the edge of the cell region are subject to greater current surges. Therefore, existing IGBTs have a greater risk of latch-up. Summary of the Invention

[0005] The technical problem to be solved by the present invention is that when the insulated gate bipolar transistor is turned off, the holes in the terminal region are concentrated at the edge of the cell region, causing current congestion at the edge of the cell region, thereby increasing the risk of latch-up of the insulated gate bipolar transistor.

[0006] To this end, the present invention provides an insulated gate bipolar transistor, comprising: a body layer, the body layer including a cell region and a transition region surrounding the cell region, the transition region including a bus region; a gate structure, located on or in part of the cell region; a gate bus bar located on the bus region, a first opening between the gate bus bar and a portion of the edge of the gate structure; a ballast structure, located in the bus region and in part of the cell region extending to the bottom of the first opening; a well region, located in part of the cell region surrounding the gate structure, a well region in the body layer at the bottom of the first opening, the conductivity type of the well region being the same as the conductivity type of the ballast structure; a source doping region located in the top area of ​​the well region, the conductivity type of the source doping region being opposite to the conductivity type of the well region, and the source doping region being spaced apart from the ballast structure.

[0007] Optionally, the insulated gate bipolar transistor further includes: a bus conductive layer located on the gate bus bar and connected to the gate bus bar.

[0008] Optionally, the insulated gate bipolar transistor also includes: an emitter electrode layer, located on the well region and extending into the first opening, the emitter electrode layer is connected to the source doping region and the well region, and the emitter electrode layer is also connected to the ballast structure at the bottom of the first opening; a ballast conductive layer, the ballast conductive layer is located on part of the ballast structure on the side of the gate bus bar, the ballast conductive layer is located on the side of the bus conductive layer away from the emitter electrode layer, and the ballast conductive layer and the emitter electrode layer have the same potential.

[0009] Optionally, the gate structure is located on a portion of the cell region, and the gate bus bar is connected to a portion of the edge of the gate structure.

[0010] Optionally, when the gate structure is located on a partial cell area, the source doping region also extends to the bottom of the partial gate structure; when the gate structure is located in the partial cell area, the source doping region is located on the side of the gate structure and adjacent to the gate structure.

[0011] Optionally, the transition region also includes a gate pad region, and the bus region is connected to the gate pad region; the insulated gate bipolar transistor also includes: a gate conduction layer located on the gate pad region, and the gate conduction layer is connected to the gate bus bar; a conduction conductive layer located on the gate conduction layer, and the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure.

[0012] Optionally, the gate pad area is located on one side of the corner of the cell area; or, the gate pad area has a relative first side and second side and a relative third side and fourth side, the direction from the first side to the second side is perpendicular to the direction from the third side to the fourth side, and the cell area only surrounds the first side, the second side and the third side of the gate pad area.

[0013] Optionally, the well region located at the bottom of the first opening is the first well region, and the first well region is connected to the ballast structure at the bottom of the first opening; the well region spaced apart from the first opening is the second well region; the projection area of ​​the first well region on the surface of the body layer is smaller than the projection area of ​​the second well region on the surface of the body layer.

[0014] Optionally, a projection area of ​​the first well region on the surface of the body layer is 20% to 50% of a projection area of ​​the second well region on the surface of the body layer.

[0015] The present invention also provides a method for manufacturing an insulated gate bipolar transistor, comprising: providing a body layer, the body layer including a cell region and a transition region surrounding the cell region, the transition region including a bus region; forming a ballast structure in the bus region and in part of the cell region; forming a gate structure on part of the cell region or in part of the cell region; forming a well region in part of the cell region around the gate structure and in the body layer at the bottom of a first opening, the conductivity type of the well region being the same as the conductivity type of the ballast structure; forming a source doping region in the top area of ​​the well region, the conductivity type of the source doping region being opposite to the conductivity type of the well region, and the source doping region being spaced from the ballast structure; forming a gate bus bar on the bus region, a first opening being formed between the gate bus bar and a portion of the edge of the gate structure, and the ballast structure extending to part of the cell region at the bottom of the first opening.

[0016] Optionally, the method for manufacturing the insulated gate bipolar transistor further includes: forming a bus conductive layer connected to the gate bus bar on the gate bus bar.

[0017] Optionally, the method for manufacturing the insulated gate bipolar transistor also includes: forming an emitter electrode layer on the well region, the emitter electrode layer also extending into the first opening, the emitter electrode layer being connected to the source doping region and the well region, and the emitter electrode layer being connected to the ballast structure at the bottom of the first opening; forming a ballast conductive layer on part of the ballast structure on the side of the gate bus bar, the ballast conductive layer being located on the side of the bus conductive layer away from the emitter electrode layer, the ballast conductive layer and the emitter electrode layer having the same potential.

[0018] Optionally, the transition region also includes a gate pad region, and the bus region is connected to the gate pad region; the method for manufacturing the insulated gate bipolar transistor also includes: forming a gate conduction layer on the gate pad region, and the gate conduction layer is connected to the gate bus bar; forming a conduction conductive layer on the gate conduction layer, and the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure.

[0019] The technical solution of the present invention has the following beneficial effects:

[0020] The insulated gate bipolar transistor provided by the technical solution of the present invention extends the ballast structure to a portion of the cell region at the bottom of the first opening. When the insulated gate bipolar transistor is turned off, the hole current will flow out through the ballast structure at the bottom of the first opening, thereby reducing the hole current density in the source doping region at the bottom of the first opening and reducing the risk of PN junction conduction between the source doping region and the well region at the bottom of the first opening. Secondly, because the source doping region is separated from the ballast structure, that is, the source doping region is not provided in the ballast structure, the ballast structure will not form a PN junction with the source doping region, and there will be no PN junction conduction. In summary, the risk of latch-up in the insulated gate bipolar transistor is reduced.

[0021] Furthermore, the present invention further includes a busbar conductive layer located on and connected to the gate busbar. A gate signal is applied to the gate busbar via the busbar conductive layer. When the gate busbar is connected to a portion of the edge of the gate structure, the gate signal on the gate busbar can be transmitted to the gate structure of the cell region.

[0022] Furthermore, the insulated gate bipolar transistor further includes: an emitter electrode layer, located on the well region and extending into the first opening, the emitter electrode layer being connected to the source doped region and the well region, and also connected to the ballast structure at the bottom of the first opening; and a ballast conductive layer, located on a portion of the ballast structure on the side of the gate bus bar, the ballast conductive layer being located on the side of the bus conductive layer facing away from the emitter electrode layer, the ballast conductive layer and the emitter electrode layer being at the same potential. By achieving the same potential for the ballast conductive layer and the emitter electrode layer, a current channel is added to the ballast structure in the transition region. When the insulated gate bipolar transistor is turned off, a portion of the holes are diverted to flow out of the ballast structure in the transition region and then out of the ballast conductive layer, thereby reducing the hole current passing through the cell region, further reducing the risk of latch-up, and improving the robustness of the insulated gate bipolar transistor.

[0023] Furthermore, the transition region also includes a gate pad region, the bus region is connected to the gate pad region; a gate conduction layer located on the gate pad region, the gate conduction layer is connected to the gate bus bar; a conduction conductive layer located on the gate conduction layer, the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure. The ballast conductive layer can apply voltage to the ballast structure, and the ballast structure is also connected to the emitter electrode layer in the first opening. In this way, the ballast conductive layer and the emitter electrode layer are electrically connected through the ballast structure, and the ballast conductive layer and the emitter electrode layer can be equal in potential, and the gate bus bar does not need to be interrupted. Since the gate bus bar does not need to be interrupted, the transmission speed of the gate voltage of the insulated gate bipolar transistor is improved, the switching speed is increased, and the switching loss is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 It is a cross-sectional schematic diagram of an insulated gate bipolar transistor in the prior art;

[0026] Figure 2 Schematic diagram of a cell region, a transition region, a terminal region, a gate pad region, and a bus region in an insulated gate bipolar transistor in one embodiment of the present application;

[0027] Figure 3 A schematic plan view of an insulated gate bipolar transistor according to an embodiment of the present application;

[0028] Figure 4 Insulated gate bipolar transistor according to an embodiment of the present application Figure 3 Schematic cross-section of the cutting line A-A';

[0029] Figure 5 A diagram showing a photolithography layout design for forming a ballast conductive layer in Example 2 of the present application;

[0030] Figure 6 A diagram showing a photolithography layout design for forming a ballast conductive layer in Example 3 of the present application;

[0031] Figure 7 This is a photolithography design diagram for forming a ballast conductive layer in Example 4 of the present application.

[0032] Reference numerals:

[0033] 3. Gate structure; 4. Gate bus bar; 5. Ballast structure; 6. Well region; 7. Source doping region; 8. Bus conductive layer; 9. Emitter electrode layer; 10. Ballast conductive layer; 11. Collector region; 61. First well region; 62. Second well region; 12. Conductive conductive layer; 1a. Cell region; 2a. Transition region; 2a-1 Bus region; 2a-2 Gate pad region; 21. Terminal region; 1c. Cell region; 2c. Terminal region; 6c. Well region; 7c. Source doping region; 9c. Emitter electrode layer; 100c. Body layer; 101c. Buffer zone; 11c. Collector region. DETAILED DESCRIPTION

[0034] In the application process of insulated gate bipolar transistors, in addition to paying attention to their conduction loss and switching loss, we must also pay attention to their reliability under some extreme application conditions. Among them, the latch-up problem is one of the important reasons that threaten the reliability of insulated gate bipolar transistors.

[0035] The technical solutions of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0036] Example 1

[0037] The embodiment of the present invention provides an insulated gate bipolar transistor, please refer to Figure 2 、 Figure 3 and Figure 4 , comprising: a body layer 100, the body layer 100 including a cell region 1a and a transition region 2a surrounding the cell region 1a, the transition region 2a including a bus region 2a-1; a gate structure 3, located on a portion of the cell region 1a; a gate bus bar 4 located on the bus region 2a-1, a first opening being provided between the gate bus bar 4 and a portion of the edge of the gate structure 3; a ballast structure 5, located in the bus region 2a-1 and in a portion of the cell region 1a extending to the bottom of the first opening; a well region 6, located in a portion of the cell region 1a surrounding the gate structure 3, the body layer 100 at the bottom of the first opening having a well region 6, the conductivity type of the well region 6 being the same as that of the ballast structure 5; a source doping region 7 located in the top region of the well region 6, the conductivity type of the source doping region 7 being opposite to that of the well region 6, and the source doping region 7 being spaced apart from the ballast structure 5.

[0038] In this embodiment, the ballast structure 5 extends into a portion of the cell region 1a at the bottom of the first opening. When the insulated gate bipolar transistor is turned off, the hole current flowing from the collector region 11 through the body layer 100 and the well region 6 will flow out through the ballast structure 5 at the bottom of the first opening, thereby reducing the hole current density in the source doped region 7 at the bottom of the first opening and reducing the risk of PN junction conduction between the source doped region 7 and the well region 6 at the bottom of the first opening. Secondly, because the source doped region 7 is separated from the ballast structure 5, that is, the source doped region 7 is not provided in the ballast structure 5, the ballast structure 5 does not form a PN junction with the source doped region 7, and there is no PN junction conduction. In summary, the risk of latch-up in the insulated gate bipolar transistor is reduced.

[0039] In this embodiment, reference Figure 2The cell region 1a acts as a current passage. The transition region 2a surrounds the cell region 1a. During the IGBT's turn-off process, the transition region 2a mitigates the electric field near the edge of the cell region 1a, preventing premature breakdown of the PN junction within the cell region. The terminal region 21 surrounds the transition region 2a to further mitigate the electric field at the cell region edge. The transition region 2a is located between the terminal region 21 and the cell region 1a.

[0040] Since the terminal region has a high potential and the active region has a low potential when the transistor is turned off, current will flow from the high-potential terminal region to the cell region. The distance from the source doped region 7 at the bottom of the first opening to the terminal region 21 is greater than the distance from the ballast structure 5 to the terminal region 21. Since current flows preferentially along the shortest path, when the insulated gate bipolar transistor is turned off, the hole current in the terminal region 21 will preferentially flow out through the ballast structure 5, reducing the current flowing through the source doped region 7.

[0041] It should be noted that, in this embodiment, the gate structure 3 is located on a portion of the cell region 1a as an example, and the gate bus bar 4 is connected to a portion of the edge of the gate structure 3. Figure 4 The cross-sectional view of the gate bus bar 4 and the gate structure 3 is shown in FIG. 1 , and the area where the gate bus bar 4 and the gate structure 3 are partially connected is not shown. Figure 4 Shown in.

[0042] The gate structure can be a planar gate. Although the planar gate will increase the on-resistance, the process of the planar gate is mature and can improve the reliability of the insulated gate bipolar transistor device.

[0043] In other embodiments, the gate structure may also be disposed in a portion of the cell region. When the gate structure is located in a portion of the cell region, the source doping region is located on the side of the gate structure and is adjacent to the gate structure. When the gate structure is located in a portion of the cell region, the gate structure is a trench-type. The trench-type gate structure corresponds to a vertical structure of an insulated gate bipolar transistor, which is more conducive to the design of compact cells than a planar gate structure. That is, more cells can be produced on the same chip area, thereby increasing the width of the conductive channel and reducing the channel resistance.

[0044] When the gate structure is located on a portion of the cell area, the source doping region also extends to the bottom of the portion of the gate structure; when the gate structure is located in the portion of the cell area, the source doping region is located on the side of the gate structure and adjacent to the gate structure.

[0045] The insulated gate bipolar transistor further includes a busbar conductive layer 8 located on and connected to the gate busbar 4. A gate signal is applied to the gate busbar 4 via the busbar conductive layer 8. In this embodiment, since portions of the edges of the gate busbar 4 and the gate structure 3 are connected, the gate signal on the gate busbar 4 can be transmitted to the gate structure 3 of the cell region 1.

[0046] In this embodiment, the insulated gate bipolar transistor further includes: an emitter electrode layer 9 located on the well region 6 and extending into the first opening. The emitter electrode layer 9 is connected to the source doped region 7 and the well region 6, and is also connected to the ballast structure 5 at the bottom of the first opening; and a ballast conductive layer 10 located on a portion of the ballast structure 5 on the side of the gate bus bar 4. The ballast conductive layer 10 is located on the side of the bus conductive layer 8 facing away from the emitter electrode layer 9, and is at the same potential as the emitter electrode layer 9. The ballast conductive layer 10 and the emitter electrode layer 9 are at the same potential, thereby increasing a current path at the ballast structure 5 in the transition region 2a. When the insulated gate bipolar transistor is turned off, a portion of holes are diverted from the ballast structure 5 in the transition region 2a and then directed out of the ballast conductive layer 10, reducing the hole current passing through the cell region 1a, further reducing the risk of latch-up, and improving the robustness of the insulated gate bipolar transistor.

[0047] In this embodiment, the transition region 2a further includes a gate pad region 2a-2, and the bus region 2a-1 is connected to the gate pad region 2a-2. The insulated gate bipolar transistor further includes: a gate conduction layer (not shown) located on the gate pad region 2a-2, the gate conduction layer being connected to the gate bus bar 4; a conduction conductive layer 12 located on the gate conduction layer, the conduction conductive layer 12 being connected to the bus bar conductive layer 8, and the conduction conductive layer 12 and the bus bar conductive layer 8 forming a closed ring structure. The ballast conductive layer 10 is connected to the ballast structure 5, and the ballast structure 5 is also connected to the emitter electrode layer 9 in the first opening. In this way, the ballast conductive layer 10 and the emitter electrode layer 9 are electrically connected through the ballast structure 5, achieving equal potential between the ballast conductive layer 10 and the emitter electrode layer 9, without interrupting the gate bus bar 4. Since the gate bus bar 4 does not need to be interrupted, it can quickly transmit the gate signal to the gate structure at various positions in the cell area, thereby improving the transmission speed of the gate voltage of the insulated gate bipolar transistor, increasing the switching speed, and reducing the switching loss.

[0048] In this embodiment, the ballast conductive layer 10 is connected to the ballast structure 5 and is also connected to the polysilicon field plate in the terminal region close to the transition region.

[0049] In this embodiment, the gate pad region 2a-2 is located at one side of a corner of the cell region 1a.

[0050] In other embodiments, the gate pad region has opposing first and second sides and opposing third and fourth sides, the direction from the first side to the second side being perpendicular to the direction from the third side to the fourth side, and the cell region only surrounds the first, second, and third sides of the gate pad region. The gate pad region is disposed at a corner of the cell region, or the cell region only surrounds the first, second, and third sides of the gate pad region, which is beneficial for shortening the connection distance between the gate structure and the gate bus bar and improving the gate voltage transmission speed.

[0051] In this embodiment, further advantages of setting the gate pad area 2a-2 on the corner side of the cell area 1a include: more flexible wiring during welding packaging, and the gate lead and the emitter lead are not easy to cross and short-circuit; the packaging can be welded or pressed, which increases the flexibility of the packaging.

[0052] The source doped region 7 , the well region 6 and the body layer 100 form a transistor, wherein the well region 6 between the source doped region 7 and the body layer 100 serves as the base of the transistor.

[0053] In this embodiment, the well region located at the bottom of the first opening is a first well region 61, which is connected to the ballast structure 5 at the bottom of the first opening. The well region spaced apart from the first opening is a second well region 62. The projected area of ​​the first well region 61 on the surface of the body layer 100 is smaller than the projected area of ​​the second well region 62 on the surface of the body layer 100. This advantageously results in a lower resistance of the first well region 61, acting as the base, between the source doped region 7 and the body layer 100. During the IGBT's shutdown process, hole current flowing from the collector region 11 through the body layer 100 and the well region 6 is less likely to open the PN junction between the source doped region 7 and the first well region 61, which serves as the base. This enhances latch-up resistance and increases the IGBT's reverse shutdown safe operating area. In a specific embodiment, the projected area of ​​the first well region 61 on the surface of the body layer 100 is 20% to 50%, for example, 30%, of the projected area of ​​the second well region 62 on the surface of the body layer 100. Because the projected area of ​​the first well region 61 on the surface of the body layer 100 is 20% to 50% of the projected area of ​​the second well region 62 on the surface of the body layer 100, the carrier concentration of the ballast structure 5 does not affect the carrier concentration distribution in the channel of the first well region 61, so that the threshold voltage corresponding to different gate structures remains unchanged, thereby improving the consistency of switches with different gate structures.

[0054] In this embodiment, the present invention further includes: a buffer layer located on the back side of the body layer; and a collector region located on the surface of the buffer layer facing away from the body layer.

[0055] In this embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. In this embodiment, the gate structure further includes: a first dielectric layer located between the gate conduction layer and the body layer; and a second dielectric layer located between the gate busbar and the body layer. The first and second dielectric layers may be made of silicon oxide.

[0056] In this embodiment, a polysilicon field plate and a field ring are provided in the terminal region.

[0057] The insulated gate bipolar transistor of this embodiment does not need to reduce the latch-up risk by maintaining the doping concentration of the collector region in the cell region unchanged while reducing the doping concentration of the collector region in the terminal region. Therefore, the number of photomasks that need to be injected in the collector region is reduced, reducing the wafer production cost. At the same time, it also avoids the collector contact changing from an ohmic contact to a Schottky contact due to the doping concentration of the collector region in the terminal region being too low, thereby avoiding an increase in leakage current.

[0058] The insulated gate bipolar transistor of this embodiment does not need to form a segmented P-type collector region and an N-type collector region between the P-type collector regions to reduce the risk of latch-up, thereby avoiding voltage foldback when the insulated gate bipolar transistor is forward-conducted, and avoiding the introduction of current oscillations and adverse harmonics during the process of switching between forward and reverse conduction.

[0059] The insulated gate bipolar transistor of this embodiment does not need to reduce the latch-up risk by setting a floating N+ island around the interface between the buffer region and the collector region, thereby reducing a separate photolithography process required for N+ island implantation and reducing process costs.

[0060] Example 2

[0061] This embodiment provides a method for manufacturing an insulated gate bipolar transistor, comprising the following steps:

[0062] S1: providing a body layer, wherein the body layer includes a cellular region and a transition region surrounding the cellular region, wherein the transition region includes a confluence region;

[0063] S2: forming a ballast structure in the confluence area and part of the cell area;

[0064] S3: forming a gate structure on or in a portion of the cell region;

[0065] S4: forming a well region in a portion of the cell region around the gate structure and in the body layer at the bottom of the first opening, wherein the conductivity type of the well region is the same as the conductivity type of the ballast structure;

[0066] S5: forming a source doping region in a top region of the well region, wherein the conductivity type of the source doping region is opposite to that of the well region, and the source doping region is spaced apart from the ballast structure;

[0067] S6: forming a gate bus bar on the bus region, forming a first opening between the gate bus bar and a portion of the edge of the gate structure, and extending the ballast structure into a portion of the cell region at the bottom of the first opening.

[0068] The gate electrode layer and the gate bus bar in the gate structure are formed in the same process.

[0069] This embodiment further includes forming a buffer layer on the back side of the bulk layer. The step of forming the buffer layer includes ion implantation on the back side of the bulk layer, followed by high-temperature push-up to form the buffer layer. In one embodiment, before forming the buffer layer on the back side of the bulk layer, the back side of the bulk layer is further cleaned, such as by chemical cleaning.

[0070] In this embodiment, the ballast structure is formed by an ion implantation process.

[0071] In one embodiment, after the ballast structure is formed, the gate structure is formed, after the gate structure is formed, the well region is formed, and after the well region is formed, the source doping region is formed.

[0072] The method for manufacturing the insulated gate bipolar transistor also includes: forming a bus conductive layer connected to the gate bus bar on the gate bus bar; forming an emitter electrode layer on the well region, the emitter electrode layer also extending into the first opening, the emitter electrode layer being connected to the source doping region and the well region, and the emitter electrode layer being also connected to the ballast structure at the bottom of the first opening; forming a ballast conductive layer on part of the ballast structure on the side of the gate bus bar, the ballast conductive layer being located on the side of the bus conductive layer away from the emitter electrode layer, the ballast conductive layer and the emitter electrode layer being at the same potential.

[0073] Specifically, when designing the photolithography pattern for forming the ballast conductive layer, it is necessary to connect the ballast conductive layer to both the ballast structure and the polysilicon field plate in the terminal region near the transition region; the ballast conductive layer is arranged in a discontinuous block shape in the photolithography pattern, and covers part of the ballast structure and the polysilicon field plate in the terminal region near the transition region, such as Figure 5 As shown, Figure 5 Only indicate Figure 3 The layout of the BB' segment is related to this embodiment.

[0074] In one embodiment, the transition region also includes a gate pad region, and the bus region is connected to the gate pad region; the method for manufacturing the insulated gate bipolar transistor also includes: forming a gate conduction layer on the gate pad region, and the gate conduction layer is connected to the gate bus bar; forming a conduction conductive layer on the gate conduction layer, and the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure.

[0075] The conducting conductive layer, the ballast conductive layer and the emission electrode layer are formed by the same process.

[0076] Example 3

[0077] The difference between this embodiment and embodiment 2 is that when designing the photolithography pattern for forming the ballast conductive layer, it is necessary to make the ballast conductive layer connected to both the ballast structure and the polysilicon field plate in the terminal region near the transition region; the ballast conductive layer is arranged in a continuous strip shape in the photolithography pattern, and covers part of the ballast structure and the polysilicon field plate in the terminal region near the transition region, such as Figure 6 The figure only shows Figure 3 The layout of the BB' segment is related to this embodiment.

[0078] The parts of this embodiment that are the same as those in embodiment 2 will not be described in detail.

[0079] Example 4

[0080] The difference between this embodiment and embodiment 2 is that when designing the photolithography pattern for forming the ballast conductive layer, it is necessary to ensure that the ballast conductive layer is connected to both the ballast structure and the polysilicon field plate in the terminal region near the transition region; the ballast conductive layer is arranged in two continuous strips in the photolithography pattern, one of which covers part of the ballast structure and the other covers the polysilicon field plate in the terminal region near the transition region. Figure 7 The figure only shows Figure 3 The layout of the BB' segment is related to this embodiment.

[0081] The parts of this embodiment that are the same as those in embodiment 2 will not be described in detail.

[0082] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. An insulated gate bipolar transistor, characterized in that include: a body layer, the body layer including a cellular region and a transition region surrounding the cellular region, the transition region including a confluence region; A gate structure is located on or in a portion of the cell region; a gate bus bar located on the bus region, wherein a first opening is formed between the gate bus bar and a portion of an edge of the gate structure; a ballast structure located in the confluence area and extending to a portion of the cell area at the bottom of the first opening; A well region is located in a portion of the cell region around the gate structure, wherein the body layer at the bottom of the first opening has a well region, and the conductivity type of the well region is the same as the conductivity type of the ballast structure; a source doping region located in a top region of the well region, the conductivity type of the source doping region being opposite to the conductivity type of the well region, the source doping region being spaced apart from the ballast structure; Among them, the well area located at the bottom of the first opening is the first well area, and the first well area is connected to the ballast structure at the bottom of the first opening; the well area spaced apart from the first opening is the second well area; the projection area of ​​the first well area on the surface of the body layer is smaller than the projection area of ​​the second well area on the surface of the body layer; the projection area of ​​the first well area on the surface of the body layer is 20% to 50% of the projection area of ​​the second well area on the surface of the body layer.

2. The insulated gate bipolar transistor according to claim 1, wherein: Also includes: A bus conductive layer is located on the gate bus bar and connected to the gate bus bar.

3. The insulated gate bipolar transistor according to claim 2, wherein: Also includes: an emitting electrode layer, located on the well region and extending into the first opening, the emitting electrode layer being connected to the source doping region and the well region, and the emitting electrode layer being further connected to the ballast structure at the bottom of the first opening; The ballast conductive layer is located on a portion of the ballast structure on the side of the gate bus bar, and is located on the side of the bus conductive layer away from the emitter electrode layer. The ballast conductive layer and the emitter electrode layer have the same potential.

4. The insulated gate bipolar transistor according to claim 1, wherein: The gate structure is located on a portion of the cell area, and the gate bus bar is connected to a portion of the edge of the gate structure.

5. The insulated gate bipolar transistor according to claim 1, wherein: When the gate structure is located on a portion of the cell area, the source doping region also extends to the bottom of the portion of the gate structure; when the gate structure is located in the portion of the cell area, the source doping region is located on the side of the gate structure and adjacent to the gate structure.

6. The insulated gate bipolar transistor according to claim 2 or 3, characterized in that: The transition region also includes a gate pad region, and the bus region is connected to the gate pad region; the insulated gate bipolar transistor also includes: a gate conduction layer located on the gate pad region, and the gate conduction layer is connected to the gate bus bar; a conduction conductive layer located on the gate conduction layer, and the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure.

7. The insulated gate bipolar transistor according to claim 6, wherein: The gate pad area is located on one side of the corner of the cell area; or, the gate pad area has a relative first side and second side and a relative third side and fourth side, the direction from the first side to the second side is perpendicular to the direction from the third side to the fourth side, and the cell area only surrounds the first side, the second side and the third side of the gate pad area.

8. A method for manufacturing an insulated gate bipolar transistor, characterized in that: include: providing a body layer, the body layer comprising a cellular region and a transition region surrounding the cellular region, the transition region comprising a confluence region; A ballast structure is formed in the confluence area and part of the cellular area; forming a gate structure on or in a portion of the cell region; A well region is formed in a portion of the cell region surrounding the gate structure and in the body layer at the bottom of the first opening, wherein the conductivity type of the well region is the same as the conductivity type of the ballast structure; wherein the well region located at the bottom of the first opening is a first well region, and the first well region is connected to the ballast structure at the bottom of the first opening; and the well region spaced apart from the first opening is a second well region; the projected area of ​​the first well region on the surface of the body layer is smaller than the projected area of ​​the second well region on the surface of the body layer; and the projected area of ​​the first well region on the surface of the body layer is 20% to 50% of the projected area of ​​the second well region on the surface of the body layer; forming a source doping region in a top region of the well region, wherein the conductivity type of the source doping region is opposite to the conductivity type of the well region, and the source doping region is spaced apart from the ballast structure; A gate bus bar is formed on the bus region, a first opening is formed between the gate bus bar and a portion of the edge of the gate structure, and the ballast structure extends into a portion of the cell region at the bottom of the first opening.

9. The method for manufacturing an insulated gate bipolar transistor according to claim 8, wherein: Also includes: A bus conductive layer connected to the gate bus bar is formed on the gate bus bar.

10. The method for manufacturing an insulated gate bipolar transistor according to claim 9, wherein: Also includes: An emitter electrode layer is formed on the well region, the emitter electrode layer also extends into the first opening, the emitter electrode layer is connected to the source doping region and the well region, and the emitter electrode layer is also connected to the ballast structure at the bottom of the first opening; a ballast conductive layer is formed on part of the ballast structure on the side of the gate bus bar, the ballast conductive layer is located on the side of the bus conductive layer away from the emitter electrode layer, and the ballast conductive layer and the emitter electrode layer have the same potential.

11. The method for manufacturing an insulated gate bipolar transistor according to claim 9, wherein: The transition region also includes a gate pad region, and the bus region is connected to the gate pad region; the method for manufacturing the insulated gate bipolar transistor also includes: forming a gate conduction layer on the gate pad region, and the gate conduction layer is connected to the gate bus bar; forming a conduction conductive layer on the gate conduction layer, and the conduction conductive layer is connected to the bus conductive layer, and the conduction conductive layer and the bus conductive layer form a closed ring structure.

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