A capacitance-inductance-pairing layering stacked resonator

Abstract

The application discloses a kind of capacitance inductance parity layer layered stack resonator, resonator includes the capacitance, inductance, first port, second port processed on substrate, the multilayer capacitance and multilayer inductance of resonator are layered stack and parallel and between first port and second port, inductance is inside capacitance, defect structure is arranged on each layer of capacitance between the uppermost layer of capacitance and the lowermost layer of capacitance, the via of inductance is vertically connected with the inductance of adjacent layer through defect structure.The application is only occupied with the plane area of one element in capacitance and inductance, with the characteristics of high integration, small size, high temperature resistance and integrated processing, can be applied to the design of passive devices such as filter, coupler with capacitance, inductance series-parallel structure.

Description

Technical Field

[0001] This invention belongs to the field of electronic device technology, specifically a capacitor and inductor odd-even layer stacked resonator. Background Technology

[0002] Resonators primarily function as frequency controllers and are widely used in electronic products involving frequency transmission and reception. With the development of next-generation wireless communication technologies, the demand for high integration and miniaturization in radio frequency devices is increasingly strong. Resonant circuits typically include capacitors and inductors; connecting these capacitors and inductors and operating them at a specific frequency generates resonance.

[0003] Currently, the main way to enhance the capacitance and inductance capabilities in this field is to increase their size, arranging components more horizontally, resulting in a large overall size of the resonator. Therefore, how to utilize a three-dimensional structure to improve the vertical utilization of the resonator and enhance its performance has become a technical problem that needs to be solved in this field.

[0004] Chinese invention patent application CN 113556094 A discloses a miniaturized resonator with a nested capacitor-inductor structure, comprising a substrate, an inductor, a capacitor, a first port, and a second port. The inductor and capacitor are connected in parallel, with the capacitor embedded inside the inductor and the inductor and capacitor connected together. The inductor and capacitor are positioned between the first port and the second port. The substrate is made of LTCC material. This design fully utilizes the characteristics of the LTCC multilayer structure and maximizes the use of three-dimensional space, reducing the horizontal dimension of the circuit and achieving miniaturization and high integration of the resonator. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a smaller-sized capacitor-inductor parity layer stacked resonator.

[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0007] This invention relates to a capacitor-inductor odd-even layer stacked resonator. The resonator includes a capacitor, an inductor, a first port, and a second port fabricated on a substrate. The multilayer capacitors and multilayer inductors of the resonator are stacked in parallel and located between the first port and the second port. The inductors are located inside the capacitors. An inductor is disposed between the interdigitation fingers of every two adjacent capacitor layers. A defect structure is disposed on each capacitor layer located between the top and bottom capacitor layers. The vias of the inductors pass perpendicularly through the defect structures and connect to the inductors of adjacent layers.

[0008] A further improvement of the present invention is that the resonator has six layers of square vertical interdigital capacitors and five layers of three-dimensional spiral inductors, with the microstrip lines or striplines constituting the capacitors located in odd-numbered layers and the striplines constituting the inductors located in even-numbered layers.

[0009] A further improvement of the present invention is that each layer of the vertical interdigitated capacitor has a square interdigitated finger, and the interdigitated fingers of the first, third and fifth vertical interdigitated capacitors from top to bottom are located on the left side, while the interdigitated fingers of the second, fourth and sixth vertical interdigitated capacitors are located on the right side.

[0010] A further improvement of the present invention is that: the first port is connected to the first layer of vertical interdigital capacitors, the third layer of vertical interdigital capacitors, the fifth layer of vertical interdigital capacitors and the first layer of three-dimensional spiral inductor through a vertical via; and the second port is connected to the second layer of vertical interdigital capacitors, the fourth layer of vertical interdigital capacitors, the sixth layer of vertical interdigital capacitors and the fifth layer of three-dimensional spiral inductor through a vertical via.

[0011] A further improvement of the present invention is that the three-dimensional spiral inductor is constructed from a high-impedance line with a width of 0.1 mm.

[0012] A further improvement of the present invention is that: the substrate is a low-temperature co-fired ceramic substrate, and the electromagnetically optimized parameters are: W C0 =r via =r C =0.2mm, W C1 =W C2 =3mm, W L0 =r L =0.1mm, W L1 =W L2 =2.4mm.

[0013] The beneficial effects of this invention are:

[0014] 1. Based on the traditional planar inductor, this invention extends the planar inductor to three dimensions by using a layered winding method. By adding defect structures to the vertical interdigital capacitor, the inductor vias can pass vertically through and connect to the adjacent layer inductors, reducing the need for unnecessary microstrip lines and striplines. Ultimately, the capacitor and inductor components occupy only one component size, making maximum use of three-dimensional space and achieving miniaturization and high integration of the resonator.

[0015] 2. The capacitor and inductor odd-even layer stacked resonator of the present invention is realized through an 11-layer low-temperature co-fired ceramic (LTCC) substrate. Compared with traditional resonators, it has the advantages of low cost, high yield, high temperature resistance and integrated processing. It can be applied to the design of passive devices such as filters and couplers with capacitor and inductor series and parallel structures. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the electromagnetic model structure of the present invention;

[0017] Figure 2 This is a schematic diagram of the topology of the present invention;

[0018] Figure 3 This is a schematic diagram of the vertical interdigitated capacitor structure with defects in this invention;

[0019] Figure 4 For the present invention Figure 3 Top view;

[0020] Figure 5 This is a schematic diagram of the three-dimensional spiral inductor structure in this invention;

[0021] Figure 6 For the present invention Figure 5 Top view;

[0022] Figure 7 The simulated S-parameter diagram of the resonator of this invention is shown.

[0023] Wherein: 1-capacitor, 2-inductor, 3-first port, 4-second port, 5-defect structure, 6-via, 7-vertical via. Detailed Implementation

[0024] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0025] like Figure 1 and Figure 2 As shown, this invention is a layered resonator with odd and even layers of capacitors and inductors, constructed using a topology of capacitor 1 and inductor 2 connected in parallel. The capacitor 1 of the resonator is designed as a 6-layer vertical interdigitated capacitor with a square structure, while the inductor 2 is a 5-layer square three-dimensional spiral structure. The inductor 2 and capacitor 1 are stacked alternately, one layer of capacitor and one layer of inductor. The microstrip lines or striplines constituting capacitor 1 are located on odd-numbered layers, and the striplines constituting inductor 2 are located on even-numbered layers, with inductor 2 located inside capacitor 1. The resonator has a first port 3 and a second port 4 on opposite sides. The left end of the first layer capacitor is connected to the first port via a microstrip line structure, and the right end of the sixth layer capacitor is connected to the second port 4 via a microstrip line structure. The left end of the first layer three-dimensional spiral inductor is connected to the first port 3 via a microstrip line structure, and the right end of the fifth layer three-dimensional spiral inductor is connected to the second port 4 via a microstrip line structure.

[0026] like Figure 3 , Figure 4As shown, the vertical interdigitated capacitor of the present invention has six square interdigitated fingers. The six interdigitated fingers are located to the left of the first, third, and fifth layer capacitors and to the right of the second, fourth, and sixth layer capacitors, respectively. The first port is located on the left side of the resonator and is connected to the first, third, and fifth layer capacitors of the vertical interdigitated capacitor through a vertical via 7. The second port is located on the right side of the resonator and is connected to the second, fourth, and sixth layer capacitors of the vertical interdigitated capacitor through a vertical via 7. The ports of the vertical interdigitated capacitor are connected by non-adjacent open terminals. Each of the second, third, fourth, and fifth layer capacitors has a defect structure 5, so that the via 6 of the inductor passes vertically through the defect structure 5 and connects to the adjacent layer inductor.

[0027] like Figure 5 , Figure 6 As shown, the three-dimensional spiral inductor consists of five layers, constructed from five 0.1mm wide high-impedance lines, with LTCC material filling the spaces between adjacent high-impedance lines. A via 6 on one side of the first port perpendicularly passes through the defect structure 5 on the fifth-layer capacitor, connecting the fourth and fifth-layer three-dimensional spiral inductors. A via 6 on the other side of the first port perpendicularly passes through the defect structure 5 on the fourth-layer capacitor, connecting the fourth and third-layer three-dimensional spiral inductors. Two vias 6 on either side of the second port sequentially connect the first, second, and third-layer three-dimensional spiral inductors. This structure allows the capacitor and inductor to occupy the size of only one component, maximizing the utilization of three-dimensional space and facilitating the miniaturization and high integration of the resonator.

[0028] The resonator of this invention is fabricated using low-temperature co-fired ceramic (LTCC) technology, enabling three-dimensional multilayer fabrication that is impossible with traditional printed circuit board (PCB) technology. This improves vertical utilization. After electromagnetic optimization, the parameters of the vertical interdigital capacitance and the three-dimensional spiral inductance in the resonator's topology are W. C0 =r via =r C =0.2mm, W C1 =W C2 =3mm, W L0 =r L =0.1mm, W L1 =W L2 =2.4mm.

[0029] Figure 7 The electromagnetic simulation S-parameter diagram of the resonator is shown in the figure. This invention is applicable to resonators with an extremely low center frequency of 100MHz, where the S-parameters at 100MHz are... 11 The value is -0.0002217 dB, S 21The value of -41.92dB indicates that the resonator has the characteristics of high integration, small size and low insertion loss.

[0030] The above are merely preferred embodiments of the present invention, but do not limit the patent scope of the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing specific embodiments, or make equivalent substitutions for some of the technical features. Any equivalent structures made using the content of the present invention specification and drawings, directly or indirectly applied to other related technical fields, are similarly within the patent protection scope of the present invention.

Claims

1. A resonator with alternating layers of capacitors and inductors stacked in parallel, the resonator comprising a first port, a second port, and capacitors and inductors fabricated on a substrate, wherein the multilayer interdigitated capacitors and multilayer inductors of the resonator are stacked in parallel and located between the first port and the second port, and the inductors are located inside the capacitors, characterized in that: An inductor is provided between each pair of adjacent capacitor interdigits. A defect structure is provided on each capacitor interdigit between the top and bottom capacitor interdigits. The via of the inductor passes vertically through the defect structure and connects to the inductor of the adjacent layer.

2. The capacitor-inductor parity-even layer stacked resonator according to claim 1, characterized in that: The resonator has six layers of square vertical interdigitated capacitors and five layers of three-dimensional spiral inductors. The microstrip lines or striplines that make up the capacitors are located in the odd-numbered layers, and the striplines that make up the inductors are located in the even-numbered layers.

3. The capacitor-inductor parity-even layer stacked resonator according to claim 2, characterized in that: Each layer of the vertical interdigitated capacitor has a square interdigitated finger. From top to bottom, the interdigitated fingers of the first, third, and fifth vertical interdigitated capacitors are located on the left side, while the interdigitated fingers of the second, fourth, and sixth vertical interdigitated capacitors are located on the right side.

4. The capacitor-inductor parity-even layer stacked resonator according to claim 3, characterized in that: The first port is connected to the first layer of vertical interdigital capacitors, the third layer of vertical interdigital capacitors, the fifth layer of vertical interdigital capacitors and the first layer of three-dimensional spiral inductor through a vertical via. The second port is connected to the second layer of vertical interdigital capacitors, the fourth layer of vertical interdigital capacitors, the sixth layer of vertical interdigital capacitors and the fifth layer of three-dimensional spiral inductor through a vertical via.

5. The capacitor-inductor parity-even layer stacked resonator according to claim 2, characterized in that: The three-dimensional spiral inductor is constructed from a high-impedance line with a width of 0.1 mm.

6. The capacitor-inductor parity-even layer stacked resonator according to claim 1, characterized in that: The substrate is a low-temperature co-fired ceramic substrate, and the electromagnetically optimized parameters are: W C0 =r via =r C =0.2mm, W C1 =W C2 =3mm, W L0 =r L =0.1mm, W L1 =W L2 =2.4mm.

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