An equalizer and electronic device

Abstract

The present application provides an equalizer and electronic equipment, the equalizer includes: continuous time linear equalizer, single-ended to differential circuit, adjustable gain amplifier and deserializer module, in the scheme, at least part of passive devices in the continuous time linear equalizer or single-ended to differential circuit is constituted by inverter, so that by using active devices instead of part of passive devices, the chip area and power consumption can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic equipment, in particular to a continuous-time linear equalizer based on pseudo-differential to differential inverter and electronic equipment applying the equalizer. BACKGROUND

[0002] With the further development of electronic communication systems and the large amount of data, people's requirements for data transmission rate are also increasing. Since parallel transmission cannot meet the increasing requirements of data transmission rate, SerDes technology has gradually become the first choice of people. However, there are non-ideal factors such as medium loss and skin effect in wired transmission channel, which will cause signal distortion and seriously reduce the signal quality of the receiving end. In order to restore the signal quality of the receiving end, equalization technology has become an essential part of high-speed SerDes system. How to provide an equalizer with low power consumption and small area has become one of the technical problems to be solved by the technical personnel in the field. SUMMARY

[0003] Therefore, the embodiments of the present application provide an equalizer and electronic equipment to provide an equalizer with low power consumption and small area.

[0004] To achieve the above object, the embodiments of the present application provide the following technical solutions:

[0005] An equalizer comprises:

[0006] A continuous-time linear equalizer, a single-ended to differential circuit, an adjustable gain amplifier and a deserializer module;

[0007] The continuous-time linear equalizer is used to obtain a single-ended signal transmitted by a transmitter and perform gain on the obtained single-ended signal;

[0008] The single-ended to differential circuit is used to obtain the single-ended signal after the gain of the continuous-time linear equalizer, and generate a complementary differential signal based on the obtained single-ended signal;

[0009] The adjustable gain amplifier is used to perform gain processing on the complementary differential signal and send the gain result to the deserializer module;

[0010] The deserializer module is used to convert the signal into a plurality of parallel signals and output;

[0011] At least part of the passive devices in the continuous-time linear equalizer or the single-ended to differential circuit is composed of inverters.

[0012] An electronic equipment applying the equalizer of any one of the above embodiments.

[0013] Based on the technical scheme, the application provides the above scheme, which can reduce power consumption and chip area of the inverter by replacing at least part of passive devices in the continuous-time linear equalizer or the single-ended to differential circuit with the inverter. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the provided drawings.

[0015] Figure 1 FIG. 1 is a structural schematic diagram of an equalizer disclosed in the embodiments of the present application;

[0016] Figure 2a , Figure 2b , Figure 2c FIGS. 1, 2 and 3 are respectively a circuit diagram, a small-signal circuit diagram and an equivalent circuit diagram when an inverter is used as a transconductor;

[0017] Figure 3a , Figure 3b , Figure 3c FIGS. 4, 5 and 6 are respectively a circuit diagram, a small-signal circuit diagram and an equivalent circuit diagram when an inverter is used as a load impedance;

[0018] Figure 4a , Figure 4b , Figure 4c FIGS. 7, 8 and 9 are respectively a circuit diagram, a small-signal circuit diagram and an equivalent circuit diagram when an inverter is used as an active inductor;

[0019] Figure 5 FIG. 10 is a structural schematic diagram of a continuous-time linear equalizer disclosed in the embodiments of the present application;

[0020] Figure 6 FIG. 11 is a structural schematic diagram of a high-frequency filtering capacitor disclosed in the embodiments of the present application;

[0021] Figure 7 FIG. 12 is a structural schematic diagram of a low-frequency filtering capacitor disclosed in the embodiments of the present application;

[0022] Figure 8 FIG. 13 is a large-signal analysis schematic diagram of a unit gain stage based on an inverter;

[0023] Figure 9a and Figure 9b FIGS. 14 and 15 are schematic diagrams of two single-ended to differential circuit structures provided in the present application;

[0024] Figure 10The schematic diagram of two single-ended to differential circuit structures provided for an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the protection scope of the present application.

[0026] The applicant finds, through research, that, on the basis of the difference between the carrier mobility of PMOS and NMOS being smaller due to advanced processes, different configurations are made to inverters, which are used as different analog devices in a circuit, active devices are used to replace part of passive devices, and the core area can be reduced. Based on this principle, the present application discloses an equalizer with low power consumption and small area.

[0027] Referring to Figure 1 The equalizer disclosed in the embodiments of the present application can include a continuous time linear equalizer (CTLE), a single-ended to differential circuit (S2D), an adjustable gain amplifier (PGA), and a deserializer module A.

[0028] The continuous time linear equalizer (CTLE) is used to acquire a single-ended signal transmitted by a transmitter and perform gain on the acquired single-ended signal. The CTLE is an essential component unit in a transceiver system, which reduces the loss of the system at high frequencies due to the influence of channel non-ideal effects and restores signal distortion. In the present solution, part of the devices in the CTLE can be composed of inverters, for example, the transconductors in the CTLE can be composed of inverters. By composing and replacing part of the devices in the CTLE with inverters, the power consumption and area of the CTLE can be effectively reduced, thereby the power consumption and area of the overall system can be effectively reduced.

[0029] The single-ended to differential circuit S2D is used to acquire a single-ended signal after gain by the continuous time linear equalizer, generate a complementary differential signal based on the acquired single-ended signal, and part of the elements in the single-ended to differential circuit S2D can also be composed of inverters, thereby the power consumption and area of the overall system can be further reduced.

[0030] The adjustable gain amplifier PGA is used to perform gain processing on the complementary differential signal and send the gain result to the deserializer module.

[0031] The deserializer module A is used to convert the signal into a plurality of parallel signals and output.

[0032] In the technical scheme disclosed in the embodiments of the present application, the inverter can be used to simulate and replace part of elements in the continuous-time linear equalizer and the single-ended to differential circuit S2D, so that the power consumption and area of the overall system (equalizer) can be reduced.

[0033] For example, the inverter described in the present application can be used as a transconductor, can be used as a load impedance, and can also be used as an active inductor.

[0034] Specifically, the inverter is normally connected as a transconductor, and a suitable bias voltage is selected, so that the transconductance values of PMOS and NMOS are equal to g m in the advanced process, and therefore the transconductance value of the inverter as an equivalent transconductor is 2g m . When the inverter is used as a transconductor, the circuit diagram of the inverter can be as shown in 2a, the small-signal circuit diagram is 2b, and the equivalent circuit diagram is 2c; see Figure 2a Figure 2a When the inverter is used as a load impedance, the circuit diagram of the inverter can be as shown in 3a, the small-signal circuit diagram is 3b, and the equivalent circuit diagram is 3c; see

[0035] When the inverter is used as a load impedance, the input end and the output end of the inverter are interconnected, the common node after interconnection serves as a first end of the impedance load, and the ground end of the inverter serves as a second end of the impedance load. Figure 3a Figure 3a When the inverter is used as an active inductor, the circuit diagram of the inverter can be as shown in 4a, the small-signal circuit diagram is 4b, and the equivalent circuit diagram is 4c; see

[0036] When the inverter is used as an active inductor, the circuit diagram of the inverter can be as shown in 4a, the small-signal circuit diagram is 4b, and the equivalent circuit diagram is 4c; see Figure 4a Figure 4a An active inductor is realized by adding a resistor between the output end of the inverter and the gate of each device (referring to the two mos tubes adjacent to the output end), and the resistors are equivalent due to the symmetry of the inverter in the advanced process, that is, the carrier mobility of PMOS and NMOS is not much different. This technology uses the gate capacitance of the inverter for high-frequency voltage boosting, thereby expanding the bandwidth and eliminating the need for a bulky inductor.

[0037] In the technical scheme disclosed in the embodiments of the present application, the transconductor, the load impedance, and the active inductor in each module of the equalizer can all be simulated by using the inverter.

[0038] For example, for the continuous-time linear equalizer, the continuous-time linear equalizer can include: ​​​

[0039] High-frequency path, all-through path, low-frequency path, and active inductor;

[0040] The high-frequency path, the all-pass path, and the low-frequency path are connected in parallel between the first node and the second node, with the first node serving as the input of the continuous-time linear equalizer.

[0041] The input terminal of the active inductor is connected to the second node, and the output terminal of the active inductor serves as the output terminal of the continuous-time linear equalizer.

[0042] The high-frequency path, all-pass path, transconductor in the low-frequency path, filter capacitor, and active inductor in the aforementioned continuous-time linear equalizer can all be implemented using inverters. Therefore, see [link to relevant documentation]. Figure 5 In the technical solution disclosed in this embodiment, the high-frequency path KEYI of the continuous-time linear equalizer includes: a first transconductor g mp2 Second transconductor g mp3 and the third transconductor g mHF and high-frequency filter capacitor C HF Among them, the first transconductor g mp2 Second transconductor g mp3 and the third transconductor g mHF All of them can be constructed from inverters.

[0043] The first transconductor g mp2 Second transconductor g mp3 and the third transconductor g mHF The first transconductor g is connected in series. mp2 The input terminal of the third transconductor g is connected to the first node. mHF The output terminal of the second transconductor is connected to the second node, and the second transconductor g mp3 The input and output terminals of the second transconductor g are shorted together. mp3 It can be a shorted inverter (in this case, the above can be ignored). Figure 5 The second transconductor g mp3 (a shorting wire between the input and output terminals), the third transconductor is an adjustable transconductor;

[0044] A high-frequency filter capacitor, wherein the first end of the high-frequency filter capacitor is connected to the common terminal of the second transconductor and the third transconductor, and the second end of the high-frequency filter capacitor is grounded.

[0045] See Figure 5 The low-frequency path includes:

[0046] Fourth transconductor g mp1 Fifth transconductor g mp0 The sixth transconductor g mLFand the low-frequency filter capacitor CLF, the fourth transconductor g mp1 Fifth transconductor g mp0 The sixth transconductor g mLF Both can be constructed from inverters;

[0047] The fourth transconductor g mp1 Fifth transconductor g mp0 The sixth transconductor g mLF The fourth transconductor g is connected in series. mp1 The input terminal of the sixth transconductor g is connected to the first node. mLF The output terminal of the fifth transconductor g is connected to the second node. mp0 The input and output terminals are shorted together, and the sixth transconductor g mLF It is an adjustable transconductor;

[0048] The low-frequency filter capacitor C LF The first end is connected to the common end of the fifth transconductor and the sixth transconductor, and the second end of the low-frequency filter capacitor is grounded.

[0049] See Figure 5 The omnichannel includes:

[0050] Seventh transconductor g mAP The seventh transconductor g mAP It is an adjustable transconductor, and the transconductance coefficient X of the seventh transconductor is: X = 1 + α + β, where α is the transconductance coefficient of the third transconductor and β is the transconductance coefficient of the sixth transconductor.

[0051] See Figure 5 As shown, the active inductor is an active inductor constructed based on an inverter. Specifically, the active inductor includes:

[0052] First resistor R1, second resistor R2, first MOSFET M1 and second MOSFET M2;

[0053] The first terminals of the first resistor and the second resistor are connected to the second node, the output terminal of the first MOSFET, and the input terminal of the second MOSFET.

[0054] The second end of the first resistor is connected to the control terminal of the first MOSFET;

[0055] The second terminal of the second resistor is connected to the control terminal of the second MOSFET;

[0056] The input terminal of the first MOSFET is connected to the input power supply, and the output terminal of the second MOSFET is grounded.

[0057] The first resistor and the first end of the second resistor serve as the output terminal of the active inductor.

[0058] Figure 5 The circuit shown can be called a subtraction CTLE because the path reduces the gain at low frequencies, while at high frequencies, the high-frequency poles introduced in the circuit impede the subtraction, resulting in a peak value that achieves high-frequency gain.

[0059] The entire circuit is divided into three branches (high-frequency path, all-pass path, and low-frequency path). At the nodes, the currents of the three branches are added together, and the transfer function is:

[0060]

[0061] In the formula, g corresponds to the circuit diagram above. mp1 g mLF g mAP g mp2 g mHF These are the transconductance coefficients for each transconductor, and g is... mp The g represents the transconductance coefficients of the second and fifth transconductors. mL C represents the transconductance of the first and second MOSFETs. HF and C LF These are the capacitance values ​​of the corresponding filter capacitors; s is the signal frequency; and R is the resistance value of the first resistor and the second resistor.

[0062] This application Figure 5 The CTLE shown has the following characteristics:

[0063] Fewer poles, yet achieving a larger gain-bandwidth product. The output impedance of the CTLE remains relatively constant throughout the frequency range and is set by the active load (gml). The first and second resistors added to the gate of the load inverter can provide inductance peaks to increase bandwidth. The low-frequency and high-frequency poles in the feedback loop are determined by gmp and their respective programmable MOS capacitor arrays. The circuit's equalization strength can be adjusted by changing the value of the current-summing transconductance.

[0064] exist Figure 5 In the CTLE shown, the zero point of the CTLE is determined by the capacitor C. HF and C LF It is determined that the capacitor C HF and C LF They can all be made of high-density MOS capacitors, and the capacitance value can be adjusted by a control switch.

[0065] like Figure 6 As shown, the high-frequency filter capacitor C HF It can consist of a series of programmable MOS capacitors, see [link to documentation].Figure 6 , the high-frequency filter capacitor C HF is composed of at least one set of serially connected editable MOS capacitors, and by controlling the on-off of the switch in the MOS capacitor series circuit, the capacitance value of the high-frequency capacitor C HF can be adjusted.

[0066] The C LF is composed of at least two high-frequency filter capacitors in parallel, as shown in Figure 7 , the C LF is composed of five high-frequency filter capacitors in parallel.

[0067] Regarding the bias voltage of the inverter, the application can ensure the reliability of the device by reasonably setting the bias voltage of each inverter, and specifically, since when the switch tube in the inverter is in saturation, the DIBL (Drain Induced Barrier Low) effect under advanced process, i.e. short channel effect, causes the nonlinearity of the output conductance to be negligible. Therefore, it is necessary to ensure that the device is in saturation state under the condition of large signal swing (while leaving some margin) to maximize the front-end signal-to-noise ratio.

[0068] With the inverter shown in Figure 8 , the signal gain analysis is carried out, assuming that the bias voltage of the inverter is 1 / 2 of the power supply voltage, and the gain is the unit gain, the Vgs and Vds of the switch tube constituting the inverter are opposite, that is, when the input signal changes, the change trend of Vgs and Vds is opposite, that is, Vdsat = 2 / Vd + vi-Vt, and Vds = Vdd-Vi, it can be known that under the premise of saturation of the switch tube, the maximum signal amplitude needs to ensure that Vi < Vt / 2. Finally, it can be concluded that the threshold voltage of the switch tube plays an important role in determining the voltage linear range.

[0069] Under the 28nm CMOS process, the standard threshold voltage device Vt = 0.4V, which means that the peak-to-peak maximum swing of the pseudo-differential circuit composed of switch tubes is 0.8V. However, considering that the transition of the device from the saturation region to the triode region is gradual, some margin needs to be left for voltage limitation in the design, so in actual design, the output swing of the pseudo-differential circuit is ±300mv.

[0070] After the threshold voltage of the device is determined, the operating voltage of the inverter is also determined, for example, assuming that the threshold voltage is 0.4V, the required overdrive voltage Vgs-Vth = 0.1V, then the power supply voltage of the inverter is 1V. If the system is not very strict in terms of linearity and swing, the super-low threshold voltage device with Vt = 0.15V can also be used in the system, so the power supply voltage of the inverter only needs 0.7V.

[0071] The output of the analog front end must be converted from single-ended to differential because the differential signal is required to drive the subsequent sampling module and DE-MUX circuit. It is appropriate to place the single-ended to differential circuit directly after the CTLE circuit because this minimizes the impact of non-linearity.

[0072] Applicant has proposed a very unconventional method to generate the differential reference signal, which is a single-ended to differential circuit structure based on inverters. In principle, an inverter can generate a differential complementary signal as shown below Figure 9a However, simulation shows that Figure 9a The frequency response of the structure shows that the pole frequency is very low, only a few GHz, and there is a very large group delay, which means that the use of Figure 9a The structure will introduce a relatively large phase offset between the real signal and the differential signal, which is not suitable for our application. Therefore, the Figure 9b structure is introduced, as shown in Figure 9b The single-ended to differential circuit can be composed of two inverters in series, one of which is a shorted inverter. In this structure, the pole is pushed to a very high frequency, close to the unit gain frequency f T of the device, and its frequency response is relatively flat, and the group delay is relatively small. Simulation shows that the delay difference between the real signal and the differential complementary signal is less than 1 ps, as shown in Figure 10 Figure 9b The input terminals of the two inverters in series serve as the input terminal and the first output terminal Vp of the single-ended to differential circuit, and the output terminals of the two inverters in series serve as the second output terminal Vn of the single-ended to differential circuit. In order to solve the problem of limited output resistance of the transistor, the size of the shorted inverter is slightly smaller than the other inverter in series (which can be called the driving inverter). The voltage gain of this stage will be close to unity gain, and the output Vp and Vn have almost equal amplitudes, and the delay between them is very small. It should be noted that the amplitude mismatch and / or phase mismatch of the first output terminal Vp and the second output terminal Vn do not cause signal distortion, but the phase mismatch causes the signal eye diagram to close in the horizontal direction, so the subsequent stage needs to correct these mismatches. How to correct is not within the scope of this application.

[0073] Corresponding to the above equalizer, the electronic device using the equalizer is also within the protection scope of the present application, which can be a mobile phone, a computer or any terminal that applies an equalizer.

[0074] ​The various embodiments described in this specification are described in progressive order, with each embodiment building on the previous one. However, the same or equivalent elements can be used in other embodiments and the description makes no assumption as to priority of such embodiments. Each embodiment is aimed at highlighting different aspects and advantages of the present disclosure. The above described system and system embodiments are merely illustrative, where the units described as separate units can or can not be physically separate, and where the units shown as separate units can or can not be physical units, i.e. can be located at one place or distributed over multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment. Those skilled in the art can understand and implement without creative labor.

[0075] The skilled person will further appreciate that the elements and algorithm steps of the examples described in relation to the embodiments disclosed herein can be implemented in electronic hardware, computer software, or combinations of both. The disclosure has been made in the context of a general description of the elements and steps of the examples to clearly illustrate the interchangeability of hardware and software. The decision to implement the functions in either hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0076] It should also be noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0077] The above description of disclosed embodiments enables a person skilled in the art to implement or use the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An equalizer characterized by, The application relates to a continuous-time linear equalizer, a single-end-to-differential circuit, an adjustable gain amplifier and a deserializer module. The continuous-time linear equalizer is used for acquiring a single-end signal transmitted by a transmitter and performing gain on the acquired single-end signal. The single-end-to-differential circuit is used for acquiring the single-end signal after the gain of the continuous-time linear equalizer and generating a complementary differential signal based on the acquired single-end signal. The adjustable gain amplifier is used for gain processing of the complementary differential signal and sending the gain result to the deserializer module. The deserializer module is used for converting the signal into a plurality of parallel signals and outputting the parallel signals. At least part of passive devices in the continuous-time linear equalizer or the single-end-to-differential circuit is composed of inverters. The continuous-time linear equalizer comprises a high-frequency channel, a full-path channel, a low-frequency channel and an active inductor.

2. The equalizer of claim 1, wherein, The high-frequency channel, the full-path channel and the low-frequency channel are connected in parallel between a first node and a second node, and the first node is used as an input end of the continuous-time linear equalizer. An input end of the active inductor is connected with the second node, and an output end of the active inductor is used as an output end of the continuous-time linear equalizer. The active inductor is an active inductor based on an inverter. The active inductor comprises a first resistor, a second resistor, a first MOS tube and a second MOS tube.

3. The equalizer of claim 2, wherein, First ends of the first resistor and the second resistor are connected with the second node, an output end of the first MOS tube and an input end of the second MOS tube.

4. The equalizer of claim 3, wherein, A second end of the first resistor is connected with a control end of the first MOS tube. A second end of the second resistor is connected with a control end of the second MOS tube. An input end of the first MOS tube is connected with an input power supply, and an output end of the second MOS tube is grounded. The first ends of the first resistor and the second resistor are used as an output end of the active inductor. The high-frequency channel comprises a first transconductor, a second transconductor and a third transconductor connected in series, an input end of the first transconductor is connected with the first node, an output end of the third transconductor is connected with the second node, an input end and an output end of the second transconductor are short-circuited, and the third transconductor is an adjustable transconductor. A high-frequency filter capacitor, a first end of the high-frequency filter capacitor is connected with common ends of the second transconductor and the third transconductor, and a second end of the high-frequency filter capacitor is grounded. The low-frequency channel comprises a fourth transconductor, a fifth transconductor and a sixth transconductor connected in series, an input end of the fourth transconductor is connected with the first node, an output end of the sixth transconductor is connected with the second node, an input end and an output end of the fifth transconductor are short-circuited, and the sixth transconductor is an adjustable transconductor.

5. The equalizer of claim 2, wherein, A low-frequency filter capacitor, a first end of the low-frequency filter capacitor is connected with common ends of the fifth transconductor and the sixth transconductor, and a second end of the low-frequency filter capacitor is grounded. The full-path channel comprises ​ 6. The equalizer of claim 5, wherein, ​ ​ ​ 7. The equalizer of claim 6, wherein, ​ A seventh transconductor, the seventh transconductor being a tunable transconductor, and a transconductance of the seventh transconductor X being: X = 1 + a + b, where a is a transconductance of the third transconductor, and b is a transconductance of the sixth transconductor.

8. The equalizer of claim 5, wherein, The high-frequency filtering capacitor is composed of at least one set of series-editable MOS capacitors.

9. The equalizer of claim 6, wherein, The low-frequency filtering capacitor is composed of at least two high-frequency filtering capacitors in parallel.

10. An electronic device, comprising: An equalizer comprising any one of claims 1-9.

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