Timing Conversion Device, Method, Write Equalization System, and Computer Readable Medium
By designing a timing conversion device including a time digital conversion unit, a fine code adjustment unit, a multiplication unit and a digital time conversion unit, the problem of increasing circuit scale and increasing power consumption caused by signal timing delay in the prior art is solved, and high-precision and low-power signal timing delay is achieved.
Patent Information
- Application Number
- CN202210699757.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-20
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2042-06-20
AI Technical Summary
When the prior art realizes signal timing delay, it leads to an increase in circuit scale, an increase in memory cost and an increase in power consumption, and requires control with a memory controller, which increases its processing burden.
A time series conversion device is designed, including a time digital conversion unit, a fine code adjustment unit, a multiplication unit and a digital time conversion unit. Through the coordinated work of these units, high-precision timing delay of the signal is realized. The specific steps include time digital conversion, fine code adjustment, multiplication operation and digital time conversion.
High precision and low power consumption of signal timing delay are realized, the circuit structure is simplified, the processing burden of the memory controller is reduced, and the cost and power consumption of the memory is reduced.
Smart Images
Figure CN115021725B_ABST
Abstract
Claims
1. A timing conversion device, characterized in that, Comprising: A time digital conversion unit, which obtains a first signal with a first period from the outside and generates a coarse code based on the first period; A fine code adjustment unit, which obtains the coarse code from the time digital conversion unit and outputs a fine code to the time digital conversion unit for generating the coarse code. When the coarse code is not an integer multiple of Y, the fine code is adjusted until the coarse code becomes an integer multiple of Y, where Y is a positive integer; A multiplication unit, which obtains the coarse code from the time digital conversion unit and calculates X / Y times of the coarse code, where X is a positive integer; and A digital time conversion unit, which obtains the fine code from the fine code adjustment unit, obtains X / Y times of the coarse code from the multiplication unit, and obtains a second signal from the outside. Based on X / Y times of the coarse code and the fine code, the second signal is delayed by X / Y times of the first period and output to the outside.
2. The timing conversion device according to claim 1, wherein: The time digital conversion unit includes a plurality of first delay parts with a first delay time. By dividing the first period by the first delay time and taking the integer, the number of used first delay parts is calculated, and the coarse code corresponds to the number of used first delay parts. The fine code adjustment unit synchronously adjusts the length of the first delay time of each first delay part by adjusting the fine code until the coarse code becomes an integer multiple of Y.
3. The timing conversion device according to claim 2, wherein: The digital time conversion unit includes a plurality of second delay parts with the first delay time. Based on X / Y times of the coarse code, the number of used second delay parts is calculated, and based on the fine code, the length of the first delay time of each second delay part is synchronously adjusted, and the second signal passes through the used second delay parts to delay the second signal.
4. The timing conversion device according to claim 3, wherein: The time digital conversion unit further includes an encoding part, which encodes the number of used first delay parts to generate the coarse code. The digital time conversion unit further includes a decoding part, which decodes X / Y times of the coarse code to generate the number of used second delay parts.
5. The timing conversion device according to claim 2 or 3, wherein: The fine code adjustment unit makes the first delay time longer by adjusting the fine code.
6. The timing conversion device according to claim 2 or 3, wherein: The fine code adjustment unit makes the first delay time shorter by adjusting the fine code.
7. The timing conversion device according to any one of claims 1 to 4, wherein: The first period is the period of a clock signal, and X / Y = 1 / 4.
8. A write equalization system for writing data to a memory, characterized in that, Comprising: A write delay module, which receives a write command and a clock signal and delays the clock signal according to the write command; The timing conversion device according to any one of claims 1 to 7, which delays the data strobe signal by X / Y times the period of the clock signal; and a signal alignment module, which samples the clock signal delayed by the write delay module by using the rising edge of the data strobe signal delayed by the timing conversion device. When the clock signal jumping from low level to high level is not sampled, a control instruction is sent to the timing conversion device to adjust X / Y. When the clock signal jumping from low level to high level is sampled, the delayed data strobe signal is output for data writing of the memory.
9. The write equalization system according to claim 8, wherein it further includes a write delay internal loop alignment module, which further performs phase shift on the clock signal delayed by the write delay module. The timing conversion device delays the data strobe signal in steps of 1 / 4 times the period of the clock signal. The signal alignment module samples the clock signal phase-shifted by the write delay internal loop alignment module by using the rising edge of the data strobe signal delayed by the timing conversion device. Based on whether the clock signal jumping from low level to high level is sampled, the phase shift amount of the write delay internal loop alignment module is determined and the delay amount of the timing conversion device is adjusted, and the phase shift amount and the delayed data strobe signal are output for data writing of the memory.
10. The write equalization system according to claim 8 or 9, wherein the timing conversion device is arranged on one side of the memory, receives the data strobe signal from the storage controller interface and delays it.
11. The write equalization system according to claim 8 or 9, wherein the timing conversion device is arranged on one side of the storage controller interface, delays the data strobe signal and sends it to the memory.
12. A timing conversion method, characterized in that, comprising: a time-to-digital conversion step, in which a first signal with a first period is obtained and the first period is converted into a coarse code; a fine code adjustment step, in which the coarse code is obtained and a fine code is generated for generating the coarse code in the time-to-digital conversion step. When the coarse code is not an integer multiple of Y, the fine code is adjusted until the coarse code becomes an integer multiple of Y, where Y is a positive integer; a multiplication step, in which the coarse code is obtained and X / Y times of the coarse code is calculated, where X is a positive integer; and a digital time conversion step, in which the fine code, X / Y times of the coarse code and a second signal are obtained, and based on X / Y times of the coarse code and the fine code, the second signal is delayed by X / Y times the first period and output.
13. The timing conversion method according to claim 12, wherein In the time-to-digital conversion step, the number of uses of the first delay unit having the first delay time is calculated by dividing the first period by the first delay time and taking the integer, and the coarse code corresponds to the number of uses of the first delay unit. In the fine code adjustment step, the length of the first delay time of each of the first delay units is synchronously adjusted by adjusting the fine code until the coarse code becomes an integer multiple of Y.
14. The timing conversion method according to claim 13, wherein In the digital-to-time conversion step, the number of uses of the second delay unit having the first delay time is calculated based on X / Y times of the coarse code, and the length of the first delay time of each of the second delay units is synchronously adjusted based on the fine code, so that the second signal passes through the used second delay unit to delay the second signal.
15. The timing conversion method according to claim 14, wherein The time-to-digital conversion step further includes an encoding step, in which the number of uses of the first delay unit is encoded to generate the coarse code. The digital-to-time conversion step further includes a decoding step, in which X / Y times of the coarse code is decoded to generate the number of uses of the second delay unit.
16. The timing conversion method according to claim 13 or 14, wherein In the fine code adjustment step, the first delay time is made longer by adjusting the fine code.
17. The timing conversion method according to claim 13 or 14, wherein In the fine code adjustment step, the first delay time is made shorter by adjusting the fine code.
18. The timing conversion method according to any one of claims 12 to 15, wherein The first period is the clock signal period. And X / Y = 1 / 4.
19. A computer-readable medium storing a program for performing the timing conversion method according to any one of claims 12 to 18.
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