Memory device, control method of memory device, and manufacturing method of memory device

Abstract

A memory device includes a first nonvolatile memory die, a second nonvolatile memory die stacked above the first nonvolatile memory die, a controller, and first and second temperature sensors respectively built-in the first and the second nonvolatile memory dies. The controller reads out temperatures measured by the first and second temperature sensors from the first and second nonvolatile memory dies. In a case where at least one of the temperatures read out from the first and second nonvolatile memory dies is equal to or higher than a threshold temperature, the controller reduces an instruction issuance frequency to the first and second nonvolatile memory dies, or an access speed to the first and second nonvolatile memory dies.

Description

Technical Field

[0001] The embodiments of the present invention relate to a memory device including a non-volatile memory and a controller, a control method for the memory device, and a method for manufacturing the memory device. Background Technology

[0002] In recent years, memory devices that include a controller and multiple non-volatile memory dies have been developed.

[0003] In this memory device, a structure is sought to prevent the temperature of the non-volatile memory die from exceeding its operating temperature limit without causing an unnecessary reduction in the access performance of the memory device.

[0004] [Background Technical Documents]

[0005] [Patent Literature]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2016-167167 Summary of the Invention

[0007] [The problem the invention aims to solve]

[0008] The problem to be solved by the present invention is to provide a memory device, a method for controlling the memory device, and a method for manufacturing the memory device that can prevent the temperature of the non-volatile memory die from exceeding the upper limit of its operating guarantee temperature without causing an unnecessary reduction in access performance.

[0009] [Technical means to solve the problem]

[0010] According to one embodiment, the memory device includes: a first non-volatile memory die; a second non-volatile memory die stacked on top of the first non-volatile memory die; a controller for controlling the first and second non-volatile memory dies; and first and second temperature sensors, respectively embedded in the first and second non-volatile memory dies. The controller reads temperatures measured by the first and second temperature sensors from the first and second non-volatile memory dies. If at least one temperature read from the first and second non-volatile memory dies is above a threshold temperature, the controller reduces the instruction issuance frequency or the access speed to the first and second non-volatile memory dies. Attached Figure Description

[0011] Figure 1 This is a diagram illustrating an example of the configuration of a memory device according to an implementation method.

[0012] Figure 2This is a block diagram illustrating an example of the configuration of a controller included in a memory device according to an implementation method.

[0013] Figure 3 It means by Figure 2 The flowchart shows the sequence of thermal control actions performed by the controller.

[0014] Figure 4 This is a graph illustrating an example of the relationship between Tj_N_max during memory access and the transfer speed.

[0015] Figure 5 This is a diagram illustrating an example of the hierarchical structure of the cell array contained in each NAND flash memory die.

[0016] Figure 6 This diagram illustrates an example of the connection between a controller and multiple NAND flash memory dies in a memory device according to an embodiment.

[0017] Figure 7 This diagram illustrates an example of accessing multiple NAND flash memory dies in an interleaved and parallel manner.

[0018] Figure 8 This is a diagram used to illustrate a comparative example of thermal control performed using the temperature sensor of the controller.

[0019] Figure 9 This diagram illustrates a thermal control implementation using multiple temperature sensors contained in each of multiple NAND flash memory dies.

[0020] Figure 10 This is a diagram illustrating the temperature trends of the various NAND flash memory dies within the memory device when the memory device of the embodiment is mounted on the printed circuit substrate of a host machine.

[0021] Figure 11 This is a diagram illustrating the temperature trends of multiple NAND flash memory dies within a memory device when the memory device of the embodiment is mounted on a printed circuit substrate of a host machine and a heat conduction component is disposed on the upper surface of the memory device.

[0022] Figure 12 This is a flowchart illustrating the sequence of learning processes that pre-determine the temperature tendencies of multiple NAND flash dies during memory access.

[0023] Figure 13 It means based on Figure 12 The flowchart shows the sequence of thermal control performed by selecting one or more specific NAND flash memory dies from multiple NAND flash memory dies and using only the temperature sensors contained in each of the selected one or more specific NAND flash memory dies.

[0024] Figure 14 This is a diagram illustrating a comparative example of calibration procedures for calibrating temperature sensors contained in individual NAND flash memory dies within a wafer at room temperature using a tester.

[0025] Figure 15 This is a diagram illustrating a calibration operation example of an implementation method for calibrating temperature sensors contained in each NAND flash memory die within a wafer using a tester at a temperature close to the start of thermal control.

[0026] Figure 16 This is another example of a calibration operation used to illustrate an implementation method for calibrating the temperature sensors contained in each NAND flash memory die within a wafer by using a tester to ensure the upper limit of the operating temperature of the NAND flash memory die.

[0027] Figure 17 This is a block diagram illustrating an example of the configuration of a temperature sensor contained in each NAND flash memory die.

[0028] Figure 18 This is a flowchart illustrating an example of the sequence of calibration processes for a temperature sensor performed using a tester.

[0029] Figure 19 This is a diagram used to illustrate an example of adjusting the slope of the temperature characteristics of a temperature sensor using a tester.

[0030] Figure 20 This is a diagram used to illustrate an example of adjusting the intercept of the temperature characteristics of a temperature sensor using a tester.

[0031] Figure 21 This diagram illustrates a packaging example when the memory device of the embodiment is implemented as a removable memory device.

[0032] Figure 22 This diagram illustrates a packaging example when the memory device of the embodiment is implemented as a surface-mount memory device. Detailed Implementation

[0033] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0034] Figure 1 This is a diagram illustrating an example configuration of the memory device 10 according to an embodiment. The memory device 10 is a device that integrates a controller and multiple stacked NAND flash memory dies within a single package.

[0035] The memory device 10 can be connected to various information processing devices such as personal computers and mobile devices that function as host machines. The memory device 10 can also be implemented as a removable memory device with a connector (also called a socket) not shown that can be mounted on a printed circuit board (PCB) 201 inside the host machine. Alternatively, the memory device 10 can also be implemented as a surface-mount memory device mounted on the printed circuit board 201 inside the host machine.

[0036] The package (body) 11 of the memory device 10 has a thickness along the Z-axis direction, including the lower surface of the package 11, namely the first surface 21, and the upper surface of the package 11, namely the second surface 22. The second surface 22 is the surface opposite to the first surface 21.

[0037] The memory device 10 includes a package substrate 12, a NAND flash memory 13, a controller 14, and multiple terminals P. The NAND flash memory 13 and the controller 14 are covered and sealed, for example, by molding resin 40.

[0038] On the surface of the packaging substrate 12, a NAND flash memory 13 and a controller 14 are mounted. Figure 1 As shown, the back side of the packaging substrate 12 can also be exposed to the outside as a first surface 21. A plurality of terminals P are disposed on the first surface 21 and exposed on the first surface 21. When the back side of the packaging substrate 12 is exposed to the outside as the first surface 21, a plurality of terminals P are disposed on the back side of the packaging substrate 12.

[0039] Multiple terminals P may include, for example, multiple power terminals, multiple ground terminals, and multiple signal terminals.

[0040] The second surface 22 is used as a printing surface, etc., and no terminal P is configured on the second surface 22.

[0041] The NAND flash memory 13 comprises a plurality of NAND flash memory dies (also referred to as NAND flash memory chips) stacked in a direction from the first surface 21 toward the second surface 22. The plurality of NAND flash memory dies are stacked on the surface of the package substrate 12 along the Z-axis direction.

[0042] The number of stacked NAND flash memory dies is not limited. Figure 1 The example shown illustrates a configuration with eight NAND flash memory dies 131 to 138 stacked together. The bottom NAND flash memory die 131 is disposed on the surface of the package substrate 12. NAND flash memory die 132 is stacked on top of NAND flash memory die 131. The top NAND flash memory die 138 is stacked on top of NAND flash memory die 137. NAND flash memory dies 131 to 138 are examples of non-volatile memory dies.

[0043] NAND flash memory dies 131 to 138 each have built-in temperature sensors TH_N0 to TH_N7. Temperature sensors TH_N0 to TH_N7 measure the temperatures (also known as junction temperatures) Tj_N0 to Tj_N7 of NAND flash memory dies 131 to 138, respectively.

[0044] Each temperature sensor TH_N0 to TH_N7 includes, for example, a temperature detection circuit and an analog-to-digital converter.

[0045] The controller 14 is also mounted on the surface of the package substrate 12. The controller 14 is an LSI (Large Scale Integrated Circuit) configured to control NAND flash memory dies 131 to 138. The controller 14 also has a built-in temperature sensor TH_C.

[0046] Temperature sensor TH_C measures the temperature (also called the interface temperature) Tj_C of controller 14. Temperature sensor TH_C, like the other temperature sensors TH_N0 to TH_N7, includes, for example, a temperature detection circuit and an analog-to-digital converter.

[0047] During the period when the controller 14 accesses the NAND flash memory 13 (that is, the NAND flash memory dies 131 to 138), each of the NAND flash memory dies 131 to 138 generates heat corresponding to its power consumption.

[0048] The heat from each of the NAND flash memory dies 131 to 138 is mainly dissipated from the first surface 21 to the printed circuit substrate 201 of the host machine through thermal conduction. A portion of the heat from each of the NAND flash memory dies 131 to 138 is also dissipated to the air from the second surface 22 through thermal transfer, but the amount of heat dissipated to the air through thermal transfer is less than the amount of heat dissipated to the printed circuit substrate 201 through thermal conduction.

[0049] The temperatures of each NAND flash memory die (131-138) must not exceed the upper limit of the guaranteed operating temperature for the NAND flash memory die. The guaranteed operating temperature is the temperature range that ensures the safe operation of each NAND flash memory die.

[0050] Therefore, in order to suppress the heat generation of each of the NAND flash memory dies 131 to 138, the controller 14 is equipped with a function to reduce the frequency of instruction issuance to the NAND flash memory dies 131 to 138 or the access speed to the NAND flash memory dies 131 to 138. This function is called thermal control (or thermal regulation).

[0051] The action of reducing the instruction issuance frequency is as follows: that is, by reducing the number of instructions issued from controller 14 to each NAND flash memory die in each period, the frequency of instructions issued to each NAND flash memory die in each period is reduced.

[0052] The action to reduce access speed is as follows: that is, by extending the period of the control signals (e.g., read start signal, write start signal, etc.) sent from the controller 14 to each NAND flash memory die, the time required for read / write access is extended.

[0053] The controller 14 performs thermal control in a manner that prevents the temperature of any of the NAND flash memory dies 131 to 138 from exceeding the upper limit of the guaranteed operating temperature.

[0054] Here, we will first explain the thermal control operation of the comparative example.

[0055] In the comparative example, the thermal control action is derived from the temperature Tj_C measured by the temperature sensor TH_C built into the controller 14, which is the highest temperature among Tj_N0 to Tj_N7.

[0056] Generally, in most cases, Tj_C > Tj_N_max holds true. However, it is difficult to express the correlation between Tj_C and Tj_N_max in a numerical form.

[0057] Therefore, in instances where Tj_N_max is inferred from Tj_C, a significant margin needs to be allowed when obtaining the inferred value of Tj_N_max. As a result, in most cases, the inferred value of Tj_N_max is higher than the actual value of Tj_N_max.

[0058] This results in thermal control being activated prematurely before the actual Tj_N_max rises to the temperature at which thermal control should be initiated, causing an unnecessary reduction in the access performance of the NAND flash memory 13.

[0059] Next, the thermal control operation of this embodiment will be explained.

[0060] In this embodiment, the controller 14 does not deduce Tj_N_max from Tj_C, but uses the temperatures Tj_N0 to Tj_N7 measured by temperature sensors TH_N0 to TH_N7, which are respectively built into the NAND flash memory dies 131 to 138 of the stack, to deduce Tj_N_max.

[0061] In this case, the controller 14 reads the temperatures Tj_N0 to Tj_N7 measured by temperature sensors TH_N0 to TH_N7 from the NAND flash memory dies 131 to 138. Furthermore, the controller 14 uses the highest temperature among the read temperatures Tj_N0 to Tj_N7 as Tj_N_max.

[0062] When the highest temperature Tj_N_max in the range of temperatures Tj_N0 to Tj_N7 is above the threshold temperature, the controller 14 performs thermal control.

[0063] Therefore, compared to the thermal control operation of the comparative example which infers Tj_N_max from TH_C, the accuracy of Tj_N_max can be improved. Thus, compared to the thermal control operation of the comparative example, the timing of initiating thermal control can be delayed, thereby extending the time during which the NAND flash memory dies 131-138 can operate with maximum access performance. In other words, access performance can be improved to near the limits of the thermal design of the memory device 10.

[0064] Furthermore, in this embodiment, a configuration is also adopted to reduce the measurement temperature error of each of the temperature sensors TH_N0 to TH_N7 built into the NAND flash memory dies 131 to 138.

[0065] Next, an example of the configuration of the controller 14 included in the memory device 10 will be described. Figure 2 This is a block diagram illustrating an example of the configuration of controller 14.

[0066] The controller 14 includes a host interface control circuit 141, a control unit 142, a NAND interface control circuit 143, a buffer memory 144, and an ECC (Error Correcting Code) encoding / decoding unit 145.

[0067] The host interface control circuit 141, control unit 142, NAND interface control circuit 143, buffer memory 144, and ECC encoding / decoding unit 145 are connected to bus 140.

[0068] The host interface control circuit 141 is configured to communicate with the host machine. The host interface control circuit 141 receives various requests from the host machine. These requests include write requests, read requests, etc.

[0069] The control unit 142 is configured as a host interface control circuit 141, a NAND interface control circuit 143, a buffer memory 144, and an ECC encoding / decoding unit 145. The control unit 142 is implemented by a processor such as a CPU (Central Processing Unit).

[0070] The control unit 142 performs various processes, including write control processing and read control processing, by executing a control program (firmware). The write control processing is the process of writing data to the NAND flash memory die to be written via the NAND interface control circuit 143. The read control processing is the process of reading data from the NAND flash memory die to be read via the NAND interface control circuit 143.

[0071] Furthermore, the control unit 142 includes a thermal regulation control unit 142a. The thermal regulation control unit 142a reads the temperature from each of the plurality of NAND flash memory dies 131 to 138 included in the NAND flash memory 13. The temperatures read from the NAND flash memory dies 131 to 138 are the temperatures measured by temperature sensors TH_N0 to TN_N7 built into the NAND flash memory dies 131 to 138.

[0072] The thermal regulation control unit 142a can read the temperature measured by the temperature sensor inside the NAND flash memory die by sending a read command to a specific address for obtaining a specified temperature to each NAND flash memory die. Hereinafter, the temperature measured by the temperature sensor will also be referred to as "sensor output" or "temperature output".

[0073] The thermal regulation control unit 142a uses the highest temperature among the multiple temperature outputs read from multiple NAND flash memory dies 131 to 138 as Tj_N_max.

[0074] The thermal control unit 142a compares Tj_N_max with a threshold temperature. If Tj_N_max is above the threshold temperature, it performs thermal control by reducing the instruction issuance frequency of the NAND flash memory dies 131-138 included in the NAND flash memory 13, or by reducing the access speed of the NAND flash memory dies 131-138. Here, the case where there is only one threshold temperature for thermal control has been described, but multiple different threshold temperatures can also be used for thermal control.

[0075] The NAND interface control circuit 143 is a memory control circuit configured to control multiple NAND flash memory dies under the control of the control unit 142. The NAND interface control circuit 143 is connected to multiple NAND flash memory dies via multiple channels Ch (Ch#0 to Ch#n).

[0076] The buffer memory 144 functions as a write buffer to temporarily store write data received from the host machine and a read buffer to temporarily store data read from the NAND flash memory die.

[0077] The ECC encoding / decoding unit 145 encodes the user data to be written to the NAND flash memory die (ECC encoding) and appends an error correction code (ECC) as a redundancy code to the user data. When reading user data from the NAND flash memory die, the ECC encoding / decoding unit 145 uses the ECC appended to the read data to perform error correction on the user data (ECC decoding).

[0078] Next, an example of the sequence of thermal control operations in this embodiment will be explained. Figure 3 This is a flowchart showing the sequence of thermal control actions performed by controller 14.

[0079] For example, such as Figure 1 As explained, when there are 8 NAND flash memory dies stacked together (131 to 138), the maximum value among Tj_N0 to Tj_N7 is used as Tj_N_max.

[0080] Here, it is assumed that the transfer speed of each NAND flash memory die is defined by the following four states (internal states) L1 to L4, which are different from each other. The transfer speed, for example, represents the throughput of read access or write access.

[0081] L1: Sets the transfer speed of each NAND flash memory die to the maximum transfer speed (MAX).

[0082] L2: Sets the transfer speed of each NAND flash memory die to transfer speed A. Transfer speed A is slower than the maximum transfer speed MAX but faster than transfer speed B, which will be described later.

[0083] L3: Set the transfer speed of each NAND flash memory die to transfer speed B. Transfer speed B is slower than transfer speed A but faster than transfer speed C (described later).

[0084] L4: Sets the transfer speed of each NAND flash memory die to transfer speed C. Transfer speed C is slower than transfer speed B.

[0085] The controller 14 uses Tj_N_max and three threshold temperatures (TMT1, TMT2, TMT3) to control the transfer speed of each NAND flash memory die. Here, TMT1, TMT2, and TMT3 have the relationship TMT1 < TMT2 < TMT3.

[0086] First, the controller 14 compares Tj_N_max with the threshold temperature TMT1 to determine whether Tj_N_max has not reached the threshold temperature TMT1 (step S11). During the period when Tj_N_max has not reached the threshold temperature TMT1 (YES in step S11), the controller 14 controls the access to each NAND flash memory die in a manner where the internal state of each NAND flash memory die is state L1 (step S14). In this case, the transfer speed of each NAND flash memory die is set to the maximum transfer speed MAX.

[0087] If Tj_N_max is above the threshold temperature TMT1 (NO in step S11), the controller 14 determines whether Tj_N_max is above the threshold temperature TMT1 but below the threshold temperature TMT2 (step S12).

[0088] During the temperature period when Tj_N_max is above the threshold temperature TMT1 but below the threshold temperature TMT2 (as in step S12), the controller 14 controls access to the NAND flash memory die in a manner where the internal state of each NAND flash memory die is state L2 (step S15). In this case, the transfer speed of each NAND flash memory die is set to a transfer speed A that is slower than the maximum transfer speed MAX.

[0089] If Tj_N_max is above the threshold temperature TMT2 (No in step S12), the controller 14 determines whether Tj_N_max is above the threshold temperature TMT2 but below the threshold temperature TMT3 (step S13).

[0090] During the temperature period when Tj_N_max is above the threshold temperature TMT2 but below the threshold temperature TMT3 (as in step S13), the controller 14 controls access to each NAND flash memory die in a manner where the internal state of each NAND flash memory die is state L3 (step S16). In this case, the transfer speed of each NAND flash memory die is set to a transfer speed B that is slower than transfer speed A.

[0091] When Tj_N_max is above the threshold temperature TMT3 (No in step S13), the controller 14 controls access to each NAND flash memory die by setting the internal state of each NAND flash memory die to state L4 (step S17). In this case, the transfer speed of each NAND flash memory die is set to a transfer speed C that is slower than the transfer speed B.

[0092] This section describes the case of using 3 threshold temperatures, but the number of threshold temperatures used can be less than 2 or more than 4.

[0093] Figure 4 This is a diagram illustrating an example of the relationship between Tj_N_max and transfer speed in memory access.

[0094] exist Figure 4 For example, this example illustrates a case where transmission speed A is 1 / 2 of the maximum transmission speed MAX, transmission speed B is 1 / 4 of the maximum transmission speed MAX, and transmission speed C is 1 / 8 of the maximum transmission speed MAX. The ratios of transmission speeds A, B, and C relative to the maximum transmission speed MAX are not limited to the example described; any other ratio satisfying the relationship MAX > A > B > C can be used. For example, transmission speed A could be 3 / 5 of the maximum transmission speed MAX, transmission speed B 2 / 5 of the maximum transmission speed MAX, and transmission speed C 1 / 5 of the maximum transmission speed MAX.

[0095] During the period when Tj_N_max is below TMT1, the transmission speed is set to the maximum transmission speed MAX. When Tj_N_max becomes above TMT1 (at time t1), the transmission speed is reduced from the maximum transmission speed MAX to the transmission speed A.

[0096] By reducing the transmission speed to transmission speed A, when Tj_N_max decreases to below TMT1 (time point t2), the transmission speed increases from transmission speed A to the maximum transmission speed MAX. If, in the stated state, Tj_N_max again becomes above TMT1 (time point t3), then the transmission speed decreases again from the maximum transmission speed MAX to transmission speed A.

[0097] When Tj_N_max continues to rise and becomes above TMT2 (time point t4), the transmission speed decreases again from transmission speed A to transmission speed B. Therefore, when Tj_N_max decreases to below TMT2 (time point t5), the transmission speed increases from transmission speed B back to transmission speed A. If, in this state, Tj_N_max again becomes above TMT2 (time point t6), then the transmission speed decreases again from transmission speed A to transmission speed B.

[0098] If Tj_N_max continues to rise and becomes above TMT3 (time point t7), the transmission speed decreases from transmission speed B to transmission speed C. Therefore, when Tj_N_max decreases to below TMT3 (time point t8), the transmission speed increases from transmission speed C back to transmission speed B. If, in this state, Tj_N_max again becomes above TMT3 (time point t9), the transmission speed decreases from transmission speed B back to transmission speed C. Therefore, when Tj_N_max decreases to below TMT3 (time point t10), the transmission speed increases from transmission speed C back to transmission speed B.

[0099] Next, examples of the configuration of each NAND flash memory die will be explained. Figure 5 This is a diagram illustrating an example of the hierarchical structure of the cell array contained in each NAND flash memory die.

[0100] exist Figure 5 The diagram illustrates the hierarchical structure of the cell array contained in NAND flash memory die 131 (also referred to as NAND flash memory die #0).

[0101] NAND die #0 has a chip start terminal CE for receiving the chip start signal. When the chip start signal is determined, access can be made to NAND die #0.

[0102] Typically, the cell array of NAND die #0 contains multiple planes. Figure 5 The example illustrates a NAND die #0 whose cell array comprises two planes (plane #0 and plane #1). Each plane contains multiple blocks. Each block is the unit for erasing data. Each block contains multiple pages. Each page is the unit for data write and data read operations. A page contains multiple memory cells connected to the same word line.

[0103] Figure 6 This diagram illustrates an example of the connection between the controller 14 and the NAND flash memory dies 131 to 138.

[0104] exist Figure 6 The example shown illustrates a controller 14 connected to NAND flash memory dies 131-138 via four channels Ch#0 to Ch#3, with two NAND flash memory dies connected to each channel.

[0105] Channels Ch#0 to Ch#3 each contain, for example, an 8-bit wide I / O bus and multiple control signal lines (instruction latch start signal line, address latch start signal line, read start signal line, write start signal line, etc.).

[0106] NAND flash memory dies 131 and 132 are connected to channel Ch#0. Similarly, NAND flash memory dies 133 and 134 are connected to channel Ch#1, NAND flash memory dies 135 and 136 are connected to channel Ch#2, and NAND flash memory dies 137 and 138 are connected to channel Ch#3.

[0107] In addition, chip start signals CE0 to CE7 from controller 14 are individually supplied to the chip start terminals of each NAND flash memory die 131 to 138.

[0108] Figure 7 This is an example of accessing NAND flash memory dies 131-138 through interleaved parallel processing. Figure 7The example illustrates the operation of writing and accessing NAND flash memory dies 131 to 138 in an interleaved parallel manner.

[0109] exist Figure 7 In this context, DIN represents the data input cycle used to transfer one page of write data (e.g., 16KB of data) to a NAND flash memory die. In an example where each NAND flash memory die has a multi-plane configuration consisting of two planes, #0 and #1, two pages of write data (e.g., 32KB of data) are transferred through two consecutive data transfer cycles, DIN(0) and DIN(1).

[0110] In data transfer cycle DIN(0), a page of write data to be written to the write target block belonging to plane #0 is transferred to the NAND flash memory die. Similarly, in data transfer cycle DIN(1), a page of write data to be written to the write target block belonging to plane #1 of the NAND flash memory die is transferred to the NAND flash memory die.

[0111] tPROG represents the programming time for page programming operations in each NAND flash memory die. Within tPROG, page programming operations corresponding to plane #0 and page programming operations corresponding to plane #1 are executed in parallel.

[0112] In each channel Ch#0 to Ch#3, during the programming operation of a certain NAND flash memory die, write data is transferred to another NAND flash memory die (interleaving).

[0113] Thus, by interleaving and parallel access to NAND flash memory dies 131 to 138, all NAND flash memory dies 131 to 138 can operate in parallel.

[0114] Next, the details of the thermal control in this embodiment will be explained. Before explaining the details of the thermal control in this embodiment, the thermal control of the comparative example will be explained first. Figure 8 This is a diagram used to illustrate a comparative example of thermal control performed using the temperature sensor TH_C of controller 14.

[0115] In the comparative example, thermal control is performed by inferring Tj_N_max from the temperature of controller 14 measured by temperature sensor TH_C of controller 14.

[0116] However, since the controller 14 is located separately from the NAND flash memory dies 131-138, it is difficult to accurately deduce Tj_N_max from the temperature of the controller 14. In addition, there is also an error inherent in the temperature measurement of the temperature sensor TH_C (measurement temperature error).

[0117] Therefore, in instances where Tj_N_max is deduced from the temperature of controller 14, the following is essential: firstly, a large margin is allowed, the temperature of controller 14 is deduced from the temperature output of temperature sensor TH_C, and then Tj_N_max is deduced from the deduced temperature of controller 14. In the comparative example of thermal control, for example, a margin of 4°C is needed to deduce the temperature of controller 14 from the measured value of temperature sensor TH_C.

[0118] Figure 9 This diagram illustrates the thermal control implementation using temperature sensors TH_N0 to TH_N7, each included in NAND flash memory dies 131 to 138.

[0119] In the thermal control implementation, the controller 14 reads the temperature outputs of temperature sensors TH_N0 to TH_N7 from NAND flash memory dies 131 to 138, and infers Tj_N_max from the read temperature outputs of temperature sensors TH_N0 to TH_N7, thereby performing thermal control.

[0120] The temperatures of the stacked NAND flash memory dies 131 to 138 are not the same. Furthermore, the temperature of any one of the stacked NAND flash memory dies 131 to 138 must not exceed the upper limit of the guaranteed operating temperature of the NAND flash memory die.

[0121] Therefore, the controller 14 performs thermal control by reading the temperature outputs of all temperature sensors TH_N0 to TH_N7 from the NAND flash memory dies 131 to 138, and using the highest temperature among the read temperature outputs of temperature sensors TH_N0 to TH_N7 as Tj_N_max.

[0122] This indicates that the temperature output data of each of the temperature sensors TH_N0 to TH_N7 can be read from each NAND flash memory die by sending a read command to a specific address.

[0123] The process of reading the temperature outputs of temperature sensors TH_N0 to TH_N7 from each NAND flash memory die is performed using a method that does not affect the access performance of memory device 10.

[0124] For example, the controller 14 may not always monitor the measured values ​​of all temperature sensors TH_N0 to TH_N7, but may read the temperature outputs of all temperature sensors TH_N0 to TH_N7 from the NAND flash memory dies 131 to 138 at specific intervals (e.g., 1 second).

[0125] In this embodiment, since Tj_N_max is estimated from the temperature measured by temperature sensors TH_N0 to TH_N7 built into NAND flash memory dies 131 to 138, when estimating Tj_N_max, it is sufficient to only reserve the measurement temperature error of each temperature sensor TH_N0 to TH_N7 as a margin.

[0126] Therefore, the 4°C margin required in the thermal control of the comparative example can be eliminated.

[0127] In addition, in this embodiment, the method of using the heat dissipation tendency of the NAND flash memory dies 131 to 138 in the package 11 to quickly search for the highest Tj_N is also adopted.

[0128] Furthermore, this embodiment also employs a method to reduce the measurement temperature error of the temperature sensor by changing the calibration temperature of the temperature sensor.

[0129] Next, the heat dissipation tendency of the NAND flash memory dies 131 to 138 within package 11 will be explained. Figure 10 This is a diagram illustrating the temperature trends of the NAND flash memory dies 131 to 138 stacked within the memory device 10 when the memory device 10 is mounted on the printed circuit substrate 201 of the host machine.

[0130] The heat from the memory device 10 is primarily dissipated to the printed circuit substrate 201 of the host machine via thermal conduction through the first surface 21. Therefore, the heat dissipation efficiency is higher near the first surface 21. On the other hand, the heat from the memory device 10 is also dissipated to the air via thermal transfer through the second surface 22, but less heat is dissipated to the air via thermal transfer.

[0131] Therefore, in the memory device 10 containing the stacked NAND flash memory dies 131 to 138, there is a tendency for one or more NAND flash memory dies close to the printed circuit substrate 201 to have a relatively low temperature, and for one or more NAND flash memory dies located far from the printed circuit substrate 201 to have a relatively high temperature.

[0132] Therefore, when the total number of stacked NAND flash memory dies is N (N is an integer greater than or equal to 2), the controller 14 does not need to read the temperature of all N NAND flash memory dies. In other words, by taking into account the heat dissipation tendency of the NAND flash memory dies 131 to 138 within the package 11, the highest temperature Tj_N can be searched at high speed.

[0133] In this case, the controller 14 reads the temperatures measured by the temperature sensors embedded in the N-1 or fewer NAND flash memory dies selected from NAND flash memory dies 131 to 138, which are the targets of temperature monitoring. Furthermore, if the highest temperature among the read temperatures is above a threshold temperature, the controller 14 performs thermal control.

[0134] The bottommost NAND flash memory die 131 among the stacked NAND flash memory dies 131-138 is positioned closer to the first surface 21 than the second surface 22, and is more likely to have the lowest temperature among the NAND flash memory dies 131-138. Therefore, NAND flash memory die 131 can be excluded from temperature monitoring. Not only NAND flash memory die 131, but also two or more NAND flash memory dies close to the first surface 21 can be excluded from temperature monitoring.

[0135] Therefore, the N-1 or fewer NAND flash memory dies of the temperature monitoring object include at least one other non-volatile memory die excluding NAND flash memory 131 from NAND flash memory 131 to 138.

[0136] Figure 11 This diagram illustrates the temperature tendencies of the NAND flash memory 131 to 138 stacked within the memory device 11 when the memory device 11 is mounted on a printed circuit substrate 201 of a host machine and a heat-conducting component such as a TIM (thermal interface material) 202 is disposed on the upper surface (second side 22) of the memory device.

[0137] like Figure 11 When TIM202 is attached to the second surface 22, the heat of the memory device 10 is dissipated to TIM202 via thermal conduction through the second surface 22, thus improving the heat dissipation efficiency of one or more NAND flash memory dies located away from the printed circuit substrate 201.

[0138] therefore, Figure 11 In the structure, among the stacked NAND flash memory dies 131 to 138, the temperature tends to be highest in one or more NAND flash memory dies near the central part.

[0139] In this case, at least the NAND flash memory die 131 located at the bottom layer and the NAND flash memory die 138 located at the top layer can be excluded from the temperature monitoring targets.

[0140] It can accurately determine the N-1 or fewer NAND flash memory dies to be monitored by learning in advance the individual temperatures of the NAND flash memory dies 131 to 138 during the access stacking period.

[0141] In other words, by processing in advance which NAND flash memory dies 131-138 have a higher / lower temperature, the controller 14 can perform thermal control by reading only the temperature output of the temperature sensor in one or more specific NAND flash memory dies with a higher temperature, without reading the temperature of all NAND flash memory dies 131-138.

[0142] Figure 12 This is a flowchart illustrating a sequential example of the learning process that pre-confirms the temperature tendencies of each of the NAND flash memory dies 131 to 138 in memory access.

[0143] During the learning process, the controller 14 performs sequential access to the NAND flash memory dies 131 to 138 (step S21). During the sequential access, the controller reads the temperatures measured by the temperature sensors TH_N0 to TH_N7 from the NAND flash memory dies 131 to 138 (each of the measured values ​​of the temperature sensors TH_N0 to TH_N7) (step S22).

[0144] The controller 14 saves the measured values ​​of the temperature sensors TH_N0 to TH_N7 as learning results (step S23). The learning results can also be saved in the firmware table of the controller 14, for example.

[0145] By performing this learning process, NAND flash memory dies with a higher temperature tendency can be specifically selected as NAND flash memory dies for temperature monitoring. Therefore, from the N NAND flash memory dies stacked within package 11, only the temperature outputs of the N-1 or fewer temperature sensors within the N-1 or fewer NAND flash memory dies selected as temperature monitoring targets through the learning process are read, thereby enabling thermal control. Information indicating the N-1 or fewer NAND flash memory dies selected as temperature monitoring targets is also stored in the firmware table of controller 14 as information for specifying the NAND flash memory dies for temperature monitoring.

[0146] The following are examples of points in time when learning and processing are performed in advance.

[0147] (1) The developer of memory device 11 performs learning processing during the development of firmware for controller 14.

[0148] (2) Learning processing is performed during the final test before the memory device 11 is shipped.

[0149] (3) The equipment manufacturer that manufactures the main machine conducts learning processes during the development of the main machine.

[0150] Figure 13 This indicates that only the method used is employed. Figure 12 The flowchart describes the learning process for the temperature sensors contained in N-1 or fewer NAND flash dies specifically for temperature monitoring, and the sequence of thermal control actions performed.

[0151] After the memory device 11 is shipped, the controller 14 reads the temperature outputs of the temperature sensors contained in each of the specific N-1 or fewer NAND flash memory dies at regular intervals (e.g., 1 second) (step S31). Then, the controller 14 uses the highest temperature among the read temperature outputs of the N-1 or fewer temperature sensors as Tj_N_max to perform... Figure 3 Thermal control (step S32).

[0152] Alternatively, a method can be explored to infer Tj_N_max by simulating, rather than learning, the composite thermal resistance corresponding to the NAND flash memory dies 131-138 in the stacked layers of package 11. When inferring Tj_N_max, the thermal resistance model is calculated using the temperature outputs of temperature sensors TH_N0-TH_N7 and the composite thermal resistance corresponding to the NAND flash memory dies 131-138 in the stacked layers.

[0153] Next, a method for reducing the error in the temperature value measured by the temperature sensor by changing the temperature at which the temperature sensor is calibrated will be described. Hereinafter, specific numerical values ​​will be used for ease of understanding; however, these values ​​are presented as examples and this embodiment is not limited to these values.

[0154] The temperature sensor TH_N embedded in each NAND flash memory die is calibrated using a tester before each NAND flash memory die is cut from the wafer. Here, TH_N represents any temperature sensor included in the wafer for calibration.

[0155] The tester is a device that uses a detector to inspect multiple LSI chips (dies) formed on a wafer. A wafer containing multiple NAND flash memory dies is mounted on the detector, and then the temperature sensors TH_N of each NAND flash memory die built into the wafer are calibrated.

[0156] Figure 14 This is a diagram illustrating the calibration process of a comparative example, where a temperature sensor TH_N is calibrated at room temperature using a tester on each NAND flash memory die within a wafer.

[0157] There are two types of errors between the actual temperature Tj_N of the NAND flash memory die and the temperature measured by the temperature sensor TH_N.

[0158] Tester error: In the comparative example, the temperature sensor TH_N was calibrated using a tester at room temperature (around 30°C). The accuracy of the ambient temperature set using the tester was, for example, 30°C ± 1.5°C. Therefore, an error of ± 1.5°C was generated as the tester error.

[0159] Temperature measurement error: The temperature measurement error is the error caused by the linearity of the temperature sensor TH_N. Even when the temperature sensor TH_N is calibrated at 30°C, the temperature measurement error of the temperature sensor TH_N increases as the temperature difference between the measured object and 30°C increases. For example, at 90°C, the temperature output of the temperature sensor TH_N contains a temperature measurement error of ±1.5°C.

[0160] Therefore, at 90℃, the total error is ±3.0℃, consisting of the tester error ±1.5℃ and the measurement temperature error ±1.5℃.

[0161] In current NAND flash memory dies, thermal control is performed within a temperature range above room temperature (e.g., 30°C) (a temperature range above 70°C). This temperature range is, for example, from the first half of 70°C to 85°C.

[0162] Therefore, in this embodiment, to reduce the measurement temperature error of the temperature sensor TH_N, the temperature sensor TH_N is calibrated at a temperature higher than room temperature. This reduces the temperature difference between the temperature at which the temperature sensor TH_N is calibrated and the temperature at which thermal control is performed, thus reducing the measurement temperature error of the temperature sensor TH_N within the temperature range requiring thermal control.

[0163] Figure 15 This is a diagram illustrating a calibration operation example of an implementation method for calibrating the temperature sensor TH_N contained in each NAND flash memory die within a wafer using a tester at a temperature close to the starting temperature of thermal control.

[0164] Figure 15 The example shown illustrates the calibration of the temperature sensor TH_N at 70°C using a tester.

[0165] The ambient temperature around the wafer is set to approximately 70°C using a tester. Next, the temperature sensor TH_N is calibrated using the tester with the temperature measured by the temperature sensor TH_N (hereinafter also used as the temperature output reference for the temperature sensor TH_N) set to 70°C. Calibration of the temperature sensor TH_N can be performed, for example, by adjusting the slope (gain) and intercept (offset) of the straight line representing the temperature characteristics of the temperature sensor TH_N. The correction values ​​used to adjust the slope and intercept are then non-volatilely written to the NAND flash memory die using the tester.

[0166] The temperature characteristics of the temperature sensor TH_N can be approximated by the following linear function.

[0167] y = ax + b

[0168] x represents the ambient temperature of the temperature sensor TH_N (temperature input), y represents the temperature measured by the temperature sensor TH_N (temperature output), a represents the slope of the straight line (approximate straight line) representing the temperature characteristics of the temperature sensor TH_N, and b represents the intercept of the approximate straight line (y-intercept).

[0169] and Figure 14 Similarly, this results in a tester error of ±1.5℃. However, since the temperature sensor TH_N is calibrated at 70℃, the temperature difference between the calibration temperature and the thermal control temperature can be reduced. For example, at 90℃, the error in the measured value of the temperature sensor TH_N can be reduced to ±0.5℃.

[0170] Therefore, at 90°C, the combined error of the tester (±1.5°C) and the measurement temperature (±0.5°C) is reduced to ±2.0°C. As a result, due to the ability to perform thermal control with greater accuracy, unnecessary degradation of the access performance of the memory device 11 can be suppressed.

[0171] Figure 16 This is another example of a calibration operation used to illustrate an implementation method for calibrating the temperature sensor TH_N contained in each NAND flash memory die within a wafer by using a tester to ensure an upper limit (e.g., 85°C) of the operating temperature of the NAND flash memory die.

[0172] The ambient temperature around the wafer was set to approximately 85°C using a tester. Furthermore, the temperature sensor TH_N was calibrated using the tester with the temperature measured by the temperature sensor TH_N (the temperature output of the temperature sensor TH_N) set to 85°C.

[0173] and Figure 14Similarly, this results in a tester error of ±1.5°C. However, since the temperature sensor TH_N is calibrated at 85°C, the temperature difference between the calibration temperature and the thermal control temperature can be reduced. For example, at 90°C, the error in the measured value of the temperature sensor TH_N can be reduced to ±0.375°C.

[0174] Therefore, at 90°C, the combined error of the tester (±1.5°C) and the measurement temperature (±0.375°C) is reduced to ±1.875°C. As a result, because Tj_N_max can be measured with greater accuracy, thermal control can be prevented from starting at an earlier point in time before Tj_N_max rises to the threshold temperature at which thermal control should begin.

[0175] In this embodiment, each NAND flash memory die 131-138 within the memory device 11 stores a correction value used to calibrate the temperature characteristics of the temperature sensor TH_N in a non-volatile manner, such that the temperature output of the temperature sensor TH_N is set to the first temperature (70°C or 85°C) at a first temperature higher than room temperature (30°C). Furthermore, the temperature sensor TH_N embedded in each NAND flash memory die 131-138 is configured to operate using the correction value non-volatilely stored in the corresponding NAND flash memory die. Therefore, the measurement temperature error of each temperature sensor TH_N within the temperature range where thermal control is performed can be reduced.

[0176] The correction value can be obtained by calibrating the temperature sensor TH_N of each non-volatile memory die embedded in the wafer at a first temperature using a tester that inspects each NAND flash memory die within the wafer. The correction value includes the slope of the temperature characteristic of the temperature sensor TH_N and correction values ​​for each intercept.

[0177] Next, an example of a method for calibrating the temperature sensor TH_N will be described. Figure 17 This is a block diagram illustrating an example of the configuration of a temperature sensor TH_N contained in a NAND flash memory die.

[0178] The temperature sensor TH_N includes a temperature detection circuit 301 and an analog-to-digital converter (AD converter) 302. The AD converter 302 is a circuit that converts the analog output value (output voltage) of the temperature detection circuit 301 into a digital value (e.g., 10-bit) representing the temperature. The AD converter 302 includes, for example, a successive approximation digital-to-analog converter (DAC) 311, a comparator (CMP) 312, and successive approximation logic 313.

[0179] The successive comparison logic 313 instructs DAC311 to gradually increase its output voltage. CMP312 compares the output voltage of DAC311 with the output voltage of temperature detection circuit 301, and outputs a comparison result indicating the magnitude relationship between the output voltage of DAC311 and the output voltage of temperature detection circuit 301.

[0180] While the output voltage of DAC311 is below the output voltage of temperature detection circuit 301, successive comparison logic 313 instructs DAC311 to gradually increase its output voltage. The output voltage of DAC311 gradually increases. When the output voltage of DAC311 becomes above the output voltage of temperature detection circuit 301, the comparison result output of comparator 312 is inverted. Successive comparison logic 313 outputs a digital value (e.g., 10 bits) representing the temperature of the output voltage of temperature detection circuit 301 at the time the assigned comparison result output was inverted.

[0181] The temperature sensor TH_N is calibrated by setting correction values ​​(slope and intercept) for the successive approximation logic 313. The correction values ​​(slope and intercept) set in the successive approximation logic 313 are used by the AD converter 302 to convert the output voltage of the temperature detection circuit 301 into temperature.

[0182] In addition, the temperature sensor TH_C built into the controller 14 can also be implemented with the same configuration as the temperature sensor TH_N contained in the NAND flash memory die.

[0183] Figure 18 This is a flowchart illustrating a sequence example of the calibration process for the temperature sensor TH_N, performed by a tester used to inspect the wafer.

[0184] Here, we illustrate the calibration process of a temperature sensor at room temperature (e.g., 30°C) to explain the sequence of calibration procedures.

[0185] The tester sets the ambient temperature around the wafer to be inspected, which has multiple NAND flash memory dies, to 30°C (e.g., 30°C ± 1.25°C) (step S101).

[0186] The tester sends a read command specifying a particular address to the NAND flash memory die being inspected, and reads the temperature (temperature output) measured by the temperature sensor TH_N contained in the NAND flash memory die being inspected (step S102).

[0187] According to the test procedure, the tester first obtains the correction value (slope correction value) to be set on the temperature sensor TH_N from the pre-evaluation result corresponding to the ambient temperature of 30°C and the temperature output read. Then, the slope correction value is written into the calibration buffer of the temperature sensor TH_N, thereby adjusting the slope of the temperature characteristic of the temperature sensor TH_N (step S103).

[0188] In the slope adjustment of steps S102 and S103, such as Figure 19 As shown, the slope of the temperature characteristic of the temperature sensor TH_N is adjusted to make it the slope shown by the correction value. Figure 19 In the diagram, the solid line represents the temperature characteristics of the temperature sensor TH_N before the slope was adjusted, and the dashed line represents the temperature characteristics of the temperature sensor TH_N after the slope was adjusted.

[0189] The tester again sends a read instruction to the NAND flash memory die of the object under inspection to read the temperature (temperature output) measured by the temperature sensor TH_N contained in the NAND flash memory die of the object under inspection (step S104).

[0190] The tester obtains the correction value (intercept correction value) to be set on the temperature sensor TH_N from the pre-evaluation result corresponding to the ambient temperature of 30°C and the temperature output read. Then, the correction value of the intercept is written into the calibration buffer of the temperature sensor TH_N, thereby adjusting the intercept (offset) of the temperature characteristic of the temperature sensor TH_N (step S105).

[0191] In the intercept adjustment of steps S104 and S105, such as Figure 20 As shown, the intercept of the temperature characteristic of the temperature sensor TH_N is adjusted to make it the intercept shown by the correction value. Figure 20 In the diagram, the solid line represents the temperature characteristics of the temperature sensor TH_N before the intercept is adjusted, and the dashed line represents the temperature characteristics of the temperature sensor TH_N after the intercept is adjusted. Thus, the intercept is adjusted so that the temperature sensor TH_N correctly outputs a temperature of 30°C at an ambient temperature of 30°C.

[0192] Next, the tester sends a read command specifying a particular address to the NAND flash memory die being inspected, and reads the temperature (temperature output) measured by the temperature sensor TH_N contained in the NAND flash memory die being inspected (step S106).

[0193] To determine whether the temperature sensor TH_N has been successfully calibrated, the tester confirms that the read temperature output has an accuracy of 30℃ ± 0.25℃ (step S107). If the read temperature output has an accuracy of 30℃ ± 0.25℃, the temperature sensor TH_N is considered to have been successfully calibrated.

[0194] The sum of the error of 1.25°C in step S101 and the error of 0.25°C in step S107 is equivalent to the tester error of 1.5°C.

[0195] Next, the tester writes the correction values ​​(slope, intercept) into the non-volatile storage area within the NAND flash memory die under inspection (step S108). Within the NAND flash memory die, the correction values ​​(slope, intercept) are written into a rewritable ROM (Read-Only Memory) area used to store control information different from user data. After the NAND flash memory die is packaged as a memory device 10, the temperature sensor TH_N within the NAND flash memory die operates using the correction values ​​(slope, intercept) stored in the ROM area.

[0196] In addition, if the temperature sensor TH_C of the controller 14 has been calibrated, the correction value (slope, intercept) is written into the electronic fuse (eFuse) that can be used as a non-volatile storage area within the controller 14.

[0197] The tester sets the ambient temperature around the wafer under inspection to 90°C (e.g., 90°C ± 1.25°C) (step S109).

[0198] The tester again sends a read instruction to a specific address to the NAND flash memory die being inspected, and reads the temperature (temperature output) measured by the temperature sensor TH_N contained in the NAND flash memory die being inspected (step S110).

[0199] The tester confirms that the read temperature output has an accuracy of, for example, 90℃ ± 1.75℃ (step S111). If the read temperature output deviates from 90℃ ± 1.75℃, the NAND flash memory die under inspection is marked as a defective chip. 1.75℃ is equivalent to the sum of the error of 0.25℃ in step S107 and the measurement temperature error of 1.5℃ at 90℃.

[0200] In this embodiment, the slope adjustment in steps S102 and S103 and the intercept adjustment in steps S104 and S105 are performed with the ambient temperature set at 70°C (e.g., 70°C ± 1.25°C) or 85°C (e.g., 85°C ± 1.25°C).

[0201] Furthermore, in this embodiment, in step S107, it is confirmed that the read temperature output has an accuracy of 70℃ ± 0.25℃, or that the read temperature output has an accuracy of 85℃ ± 0.25℃. And, in step S108, the correction values ​​(slope, intercept) are written to the non-volatile storage area within the NAND flash memory die being inspected. Within the NAND flash memory die, the correction values ​​(slope, intercept) are written to the electrically rewritable ROM area. After the NAND flash memory die is packaged as a memory device 10, the temperature sensor TH_N within the NAND flash memory die can operate using the correction values ​​(slope, intercept) stored in the ROM area. This reduces the temperature measurement error of each temperature sensor TH_N within the temperature range for which thermal control is performed.

[0202] In addition, in this embodiment, when calibrated at 70°C, in step S111, the accuracy of the read temperature output is confirmed to be, for example, 90°C ± 0.75°C; when calibrated at 85°C, in step S111, the accuracy of the read temperature output is confirmed to be, for example, 90°C ± 0.625°C.

[0203] Thus, in this embodiment, the calibration method calibrates the temperature sensors built into each of the NAND flash memory dies 131-138, which are integrated with the controller 14 in the stack of the package 11 of the memory device 10, before the NAND flash memory dies 131-138 are packaged.

[0204] In this case, the calibration method of this embodiment (1) uses a tester to inspect each NAND flash memory die in the wafer to calibrate the temperature characteristics of the temperature sensor built into each NAND flash memory die in the wafer at a first temperature higher than room temperature (e.g., 70°C or 85°C), and (2) uses the tester to write the correction value of the temperature characteristics of the temperature sensor obtained by calibration into each NAND flash memory die in the wafer.

[0205] By packaging the NAND flash memory dies calibrated with temperature sensors at 70°C or 85°C as memory device 10, the controller 14 in memory device 11 can read the measured temperature with less error from the temperature sensors of each of the stacked NAND flash memory dies 131 to 138 within the temperature range for thermal control.

[0206] Next, the structure of the package applied to the memory device 10 will be described. Figure 21 This is a diagram showing a packaging example of memory device 10 implemented as a removable memory device.

[0207] The package (body) 11 of the memory device 10 is formed, for example, as a generally rectangular plate extending in the Y-axis direction. The Y-axis direction is the direction of the long side of the memory device 10 and the package 11. The outer edge of the package (body) 11 has a first edge 31, a second edge 32, a third edge 33, a fourth edge 34, a first corner 35, a second corner 36, a third corner 37, and a fourth corner 38.

[0208] Edge 1 31 extends along the X-axis towards the positive Y-axis. Edge 2 32 extends along the Y-axis towards the negative X-axis. Edge 33 is located on the opposite side of Edge 2 32 and extends along the Y-axis towards the positive X-axis. Edge 4 34 is located on the opposite side of Edge 1 31 and extends along the X-axis towards the negative Y-axis.

[0209] The lengths of the second edge 32 and the third edge 33 are each longer than the lengths of the first edge 31 and the fourth edge 34. The first edge 31 and the fourth edge 34 form the short side of the generally rectangular memory device 10, and the second edge 32 and the third edge 33 form the long side (side) of the generally rectangular memory device 10.

[0210] The first corner 35 is the corner between the first edge 31 and the second edge 32, and connects the negative X-axis end of the first edge 31 to the positive Y-axis end of the second edge 32.

[0211] The first corner portion 35 extends linearly between the negative X-axis end of the first edge 31 and the positive Y-axis end of the second edge 32. The first corner portion 35 is provided by setting the angle between the first edge 31 and the second edge 32 as a chamfered angle of C1.1 (also called a C-chamfer). Alternatively, the first corner portion 35 may be a chamfered angle C formed between the first edge 31 and the second edge 32.

[0212] The second corner portion 36 is the corner portion between the first edge 31 and the third edge 33, connecting the positive X-axis end of the first edge 31 to the positive Y-axis end of the third edge 33. The second corner portion 36 extends in an arc shape between the positive X-axis end of the first edge 31 and the positive Y-axis end of the third edge 33. The second corner portion 36 is provided by setting the angle between the first edge 31 and the third edge 33 to a so-called R0.2 rounded arc angle (also known as R chamfer).

[0213] The third corner portion 37 connects the negative Y-axis end of the second edge 32 to the negative X-axis end of the fourth edge 34. The fourth corner portion 38 connects the negative Y-axis end of the third edge 33 to the positive X-axis end of the fourth edge 34. Both the third corner portion 37 and the fourth corner portion 38 extend in the same arc shape as the second corner portion 36.

[0214] For example, the length of package 11 in the Y-axis direction can be set to about 18 ± 0.10 mm, the length in the X-axis direction can be set to about 14 ± 0.10 mm, and the thickness in the Z-axis direction can be set to about 1.4 mm ± 0.10 mm.

[0215] Alternatively, on the first side 21 of the memory device 10, multiple terminals P can be configured into three columns: column 1 R1, column 2 R2, and column 3 R3. In column 1 R1, for example, signal terminals for two channels of a high-speed serial interface such as PCIe (registered trademark) can be configured.

[0216] Figure 21 The example shown is of a memory device 10 having 32 terminals P, but the number of terminals P is only one example and is not limited to this example. That is, the number of terminals P may be less than 32 or more than 32.

[0217] Multiple terminals P are arranged in three columns, forming column 1 R1, column 2 R2, and column 3 R3. The terminal group P belonging to column 1 R1 is used, for example, as a signal terminal for transmitting differential signal pairs between two channels according to the PCIe specification. The terminal group P belonging to column 2 R2 can also be used as a signal terminal for any selectable signal, depending on the specific product. In the terminal group belonging to column 3 R3, common control signal and power terminals are configured for each product. These terminals are primarily used as signal terminals for differential clock signals, signal terminals for common PCIe sideband signals, power terminals, and other signal terminals.

[0218] The first column R1 contains 13 terminals P101 to P113 arranged at intervals along the X-axis in a position closer to the first edge 31 than the fourth edge 34. Terminals P101 to P113 are arranged along the X-axis near the first edge 31.

[0219] The second column R2 includes three terminals P114 to P116 arranged at intervals along the X-axis, located closer to the fourth edge 34 than the first edge 31. Furthermore, the second column R2 includes three terminals P117 to P119 arranged at intervals along the X-axis, also closer to the fourth edge 34 than the first edge 31.

[0220] Terminals P114 to P116 are arranged in the X-axis direction between the center line (represented by a dashed line) of the memory device 10 and the second edge 32, and terminals P117 to P119 are arranged in the X-axis direction between the center line of the memory device 10 and the third edge 33.

[0221] The spacing between terminals P116 and P117 is wider than the spacing in the X direction between other terminals belonging to column R2 (specifically, the spacing between terminals P114 and P115, the spacing between terminals P115 and P116, the spacing between terminals P117 and P118, and the spacing between terminals P118 and P119).

[0222] The third column R3 contains 13 terminals P120 to P132 arranged at intervals along the X-axis, closer to the fourth edge 34 than the first edge 31. The terminals P120 to P132 belonging to the third column R3 are arranged closer to the fourth edge 34 than the terminals P114 to P119 belonging to the second row R2.

[0223] The distance D1 between the first column R1 and the third column R3 in the Y-axis direction is longer than the distance D2 between the first column R1 and the first edge 31 in the Y-axis direction, and the distance D3 between the third column R3 and the fourth edge 34 in the Y-axis direction.

[0224] The Y-axis length of terminals P in columns R1, R2, and R3 is set to be the same. That is, terminals P in columns R1, R2, and R3 are arranged such that the ends of terminals P in both the negative and positive Y-axis directions are the same.

[0225] The area A1 within the first surface 21, indicated by the dashed line, functions as a contact area for contacting the TIM (Tilt-In-Metr) attached to the printed circuit substrate 201 of the host machine. In other words, when the memory device 10 is mounted on the connector on the printed circuit substrate 201, not only do the terminals P within the first surface 21 contact the connector's lead frame, but area A1 within the first surface 21 also contacts the TIM attached to the printed circuit substrate 201. This significantly improves the heat dissipation efficiency from the first surface 21 to the printed circuit substrate 201 of the host machine via thermal conduction.

[0226] Figure 22 This is a diagram showing a packaging example of memory device 10 implemented as a surface-mount memory device.

[0227] Here, a BGA (Ball Grid Array) package is exemplified as a surface-mount memory device package. The BGA package is an example of a surface-mount package that is directly mounted on the printed circuit board substrate 201 of the host machine. In the BGA package of the memory device 10, a controller 14 and stacked NAND flash memory dies 131-138 are integrated. Furthermore, as... Figure 22 As shown, multiple solder balls are arranged as terminals P on the first surface 21.

[0228] As explained above, according to this embodiment, the controller 14 performs thermal control by reading the temperatures measured by temperature sensors TH_N0 to TH_N7 from NAND flash memory dies 131 to 138, and using the highest temperature among the read temperatures from temperature sensors TH_N0 to TH_N7 as Tj_N_max. Here, for example, it is assumed that the NAND flash memory 13 within the memory device 10 includes a first NAND flash memory die and a second NAND flash memory die stacked on top of the first NAND flash memory die. In this case, the controller 14 reads the temperatures measured by a first temperature sensor built into the first NAND flash memory die and the temperatures measured by a second temperature sensor built into the second NAND flash memory die from both the first and second NAND flash memory dies. Next, if at least one temperature read from the first and second NAND flash memory dies is above a threshold temperature, the controller 14 reduces the instruction issuance frequency or access speed to the first and second NAND flash memory dies.

[0229] In most cases, the temperature inside the controller 14 is higher than the temperature of each NAND flash memory die. Therefore, if the temperature measured by the temperature sensor TH_C inside the controller 14 is used to estimate Tj_N_max, there is a tendency to start thermal control prematurely before the actual Tj_N_max rises to the temperature at which thermal control should be initiated, causing an unnecessary reduction in the access performance of the NAND flash memory 13.

[0230] In this embodiment, by using the highest temperature among the temperatures measured by temperature sensors TH_N0 to TH_N7 as Tj_N_max, compared to using the temperature measured by temperature sensor TH_C within the controller 14 to infer Tj_N_max, the timing of initiating thermal control can be delayed. Therefore, the time for the NAND flash memory dies 131 to 138 to operate at maximum access performance can be extended. Consequently, unnecessary degradation of the access performance of the memory device 10 can be avoided, and the temperatures of the NAND flash memory dies 131 to 138 can be prevented from exceeding the upper limit of the guaranteed operating temperature for the NAND flash memory die.

[0231] Furthermore, the controller 14 can read only the temperature measured by the temperature sensors in N-1 or fewer N-type NAND flash memory dies selected as temperature monitoring objects from the N N-type NAND flash memory dies stacked in the package 11, thereby performing thermal control.

[0232] Therefore, the highest temperature among the N NAND flash memory dies stacked within package 11 can be searched at high speed. Furthermore, this reduces the number of read / write operations required to read the temperature, thus improving the read / write performance of user data. For example, consider the following scenario: In addition to the first and second NAND flash memory dies, the NAND flash memory 13 within memory device 10 includes a third NAND flash memory die, with the first NAND flash memory die stacked on top of the third NAND flash memory die, and the third NAND flash memory die being closer to the first surface 21 than the first and second NAND flash memory dies. In this case, the controller 14 reads the temperature measured by a first temperature sensor built into the first NAND flash memory die and the temperature measured by a second temperature sensor built into the second NAND flash memory die from the first and second NAND flash memory dies. Furthermore, if at least one temperature read from the first and second NAND flash memory dies is above a threshold temperature, the controller 14 reduces the instruction issuance frequency and access speed to the first and second NAND flash memory dies. In other words, the controller 14 does not read the temperature measured by the third temperature sensor built into the third NAND flash memory die, or does not compare the temperature measured by the third temperature sensor with the threshold.

[0233] The N-1 or fewer non-volatile memory dies targeted for temperature monitoring can be determined by learning in advance the temperatures of each of the NAND flash memory dies 131 to 138 during the access stack. This allows for the accurate determination of the N-1 or fewer non-volatile memory dies targeted for temperature monitoring. For example, if the NAND flash memory 13 within the memory device 10 is configured to include the first, second, and third NAND flash memory dies, the controller 14 stores information for identifying the first and second NAND flash memory dies.

[0234] Furthermore, in this embodiment, each of the stacked NAND flash memory dies 131 to 138 non-volatilely stores a correction value obtained below, that is, at a first temperature (70°C or 85°C) higher than room temperature (30°C), the temperature output of the temperature sensor TH_N falls within a preset allowable temperature range for the first temperature (70°C or 85°C). Moreover, each temperature sensor TH_N is configured to operate using the correction value non-volatilely stored in the corresponding NAND flash memory die. Therefore, the temperature measurement error of each temperature sensor TH_N within the temperature range for thermal control can be reduced. For example, in a method for manufacturing a memory device 10 including a controller 14 and the first and second NAND flash memory dies, firstly, a wafer including the first and second NAND flash memory dies is prepared. Next, the ambient temperature around the wafer is set to a first set value. The first set value is as follows: Figure 18 The description includes, for example, a temperature range of 70℃ ± 1.25℃, which is above 68.75℃ and below 71.25℃, or 85℃ ± 1.25℃, which is above 83.75℃ and below 86.25℃. After setting the ambient temperature to a first setpoint, a first temperature is measured using a first temperature sensor. Using the measured value from the first temperature sensor, a first correction value for temperature measurement using the first temperature sensor is obtained. The obtained first correction value is written to a first non-volatile memory die. Similarly, after setting the ambient temperature to a first setpoint, a second temperature is measured using a second temperature sensor. Using the measured value from the second temperature sensor, a second correction value for temperature measurement using the second temperature sensor is obtained. The obtained second correction value is written to a second non-volatile memory die. Furthermore, the ambient temperature is set to a second setpoint higher than the first setpoint (e.g., 90℃ ± 1.25℃). After setting the ambient temperature to the second setpoint, a third temperature is measured using the first temperature sensor. After setting the ambient temperature to a second set value, a fourth temperature is measured using a second temperature sensor. It is then determined whether the third and fourth temperatures are within threshold ranges. Next, first and second non-volatile memory dies are diced from the wafer. If the third and fourth temperatures are within the threshold ranges, the diced first and second non-volatile memory dies are packaged as memory device 10. Thus, a memory device 10 is manufactured that integrates the controller 14 and the first and second non-volatile memory dies into a single package 11.

[0235] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0236] [Symbol Explanation]

[0237] 10. Memory devices

[0238] 14 Controller

[0239] 21 Page 1

[0240] 22 Page 2

[0241] P terminal

[0242] 131-138 NAND flash memory die

[0243] 142a Thermal Control Unit

[0244] Temperature sensor inside the TH_C controller

[0245] Temperature sensors inside NAND flash memory dies (TH_N0~TH_N7)

[0246] 301 Temperature Detection Circuit

[0247] 302 AD converter.

Claims

1. A memory device comprising: First non-volatile memory die; The second non-volatile memory die is stacked on top of the first non-volatile memory die; The third non-volatile memory die; The controller controls the first, second, and third non-volatile memory dies; The first, second, and third temperature sensors are respectively embedded in the first, second, and third non-volatile memory dies; Page 1; The second surface is located on the opposite side of the first surface; and Multiple terminals are exposed on the first surface; and The first non-volatile memory die stack is on top of the third non-volatile memory die. The third non-volatile memory die is closer to the first surface than the first and second non-volatile memory dies. The controller By learning in advance the temperature tendencies of the first, second, and third non-volatile memory dies during access to the stacked layers, it is determined not to read the temperature measured by the third temperature sensor or not to compare it with a threshold temperature. The temperatures measured by the first and second temperature sensors are read from the first and second non-volatile memory dies. If at least one temperature read from the first and second non-volatile memory dies is above the threshold temperature, reduce the instruction issuance frequency or access speed of the first, second and third non-volatile memory dies.

2. The memory device of claim 1, wherein the controller stores information for specifying the first and second non-volatile memory dies to be read at a specific temperature.

3. The memory device of claim 1, wherein the threshold temperature is set to a temperature higher than 30°C. The first, second, and third non-volatile memory dies respectively non-volatilely store the first, second, and third correction values, which are obtained as follows: at a first temperature above 30°C, the temperature outputs of the first, second, and third temperature sensors fall within a preset allowable temperature range for the first temperature. The first, second, and third correction values ​​are obtained before the first, second, and third non-volatile memory dies are packaged. The first, second, and third temperature sensors are configured to use the first, second, and third correction values, respectively.

4. The memory device of claim 3, wherein the first temperature is set as the upper limit of the operational guarantee temperature of each of the first, second and third non-volatile memory dies.

5. The memory device of claim 3, wherein the first correction value comprises a first slope and a first intercept of an approximately straight line obtainable from the temperature characteristics of the first non-volatile memory die. The second correction value includes the second slope and second intercept of an approximately straight line obtainable from the temperature characteristics of the second non-volatile memory die. The third correction value includes the third slope and the third intercept of an approximate straight line obtainable from the temperature characteristics of the third non-volatile memory die.

6. The memory device of claim 1, wherein the first, second and third non-volatile memory dies are each NAND flash memory dies.

7. The memory device of claim 1, wherein the memory device is a removable memory device that can be mounted on a connector disposed on a printed circuit substrate of a host machine.

8. The memory device of claim 1, wherein the memory device is a surface-mount memory device mounted on a printed circuit substrate of a host machine.

9. The memory device of claim 1, further comprising a package, and The first, second, and third non-volatile memory dies and the controller are integrated into the package.

10. A control method for controlling a memory device, the memory device comprising: a first non-volatile memory die; a second non-volatile memory die stacked on top of the first non-volatile memory die; a third non-volatile memory die; first, second, and third temperature sensors respectively embedded in the first, second, and third non-volatile memory dies; a first surface; a second surface located on the opposite side of the first surface; and a plurality of terminals exposed on the first surface; and The first non-volatile memory die stack is on top of the third non-volatile memory die. The third non-volatile memory die is closer to the first surface than the first and second non-volatile memory dies. By learning in advance the temperature tendencies of the first, second, and third non-volatile memory dies during access to the stacked layers, it is determined not to read the temperature measured by the third temperature sensor, or not to compare it with a threshold temperature. Using the first, second, and third temperature sensors, the first, second, and third temperatures are measured. The measured values ​​of the first temperature and the second temperature are read from the first and second non-volatile memory dies. If at least one of the measured values ​​of the first temperature and the second temperature is above the threshold temperature, the instruction issuance frequency to the first, second, and third non-volatile memory dies, or the access speed to the first, second, and third non-volatile memory dies, shall be reduced.

11. The control method according to claim 10, wherein the threshold temperature is set to a temperature higher than 30°C. The first, second, and third non-volatile memory dies respectively non-volatilely store the first, second, and third correction values, which are obtained as follows: at a fourth temperature above 30°C, the temperature outputs of each of the first, second, and third temperature sensors fall within a preset allowable temperature range for the fourth temperature. The first, second, and third correction values ​​are obtained before the first, second, and third non-volatile memory dies are packaged. The first, second, and third temperatures are measured using the first, second, and third correction values, respectively.

12. A method for manufacturing a memory device, comprising preparing a wafer, the wafer including a first non-volatile memory die having a first temperature sensor, a second non-volatile memory die having a second temperature sensor, and a third non-volatile memory die having a third temperature sensor. The ambient temperature around the wafer is set to a first preset value of 30 degrees Celsius or higher. After setting the ambient temperature to the first preset value, the first temperature is measured using the first temperature sensor. Using the measured value from the first temperature sensor, a first correction value for the first temperature sensor used in temperature measurement is obtained. Write the first correction value into the first non-volatile memory die. After setting the ambient temperature to the first preset value, the second temperature is measured using the second temperature sensor. Using the measured value from the second temperature sensor, a second correction value for temperature measurement using the second temperature sensor is obtained. The second correction value is written into the second non-volatile memory die. After setting the ambient temperature to the first preset value, the third temperature is measured using the third temperature sensor. Using the measured value from the third temperature sensor, a third correction value for temperature measurement using the third temperature sensor is obtained. The third correction value is written into the third non-volatile memory die. The ambient temperature is set to a second setting value that is higher than the first setting value. After setting the ambient temperature to the second preset value, the fourth temperature is measured using the first temperature sensor. After setting the ambient temperature to the second set value, the fifth temperature is measured using the second temperature sensor. After setting the ambient temperature to the second preset value, the sixth temperature is measured using the third temperature sensor. Determine whether the fourth, fifth, and sixth temperatures are within the threshold range. The first, second, and third non-volatile memory dies are cut from the wafer. When the fourth, fifth, and sixth temperatures are within the threshold range, the cut-out first, second, and third non-volatile memory dies are packaged as a memory device in a stacked manner. A first surface, a second surface located opposite the first surface, and a plurality of terminals exposed on the first surface are included in the memory device. The stacked first non-volatile memory die is above the third non-volatile memory die, the stacked second non-volatile memory die is above the first non-volatile memory die, and the third non-volatile memory die is closer to the first surface than the first and second non-volatile memory dies. After packaging the first, second, and third non-volatile memory dies, by learning the temperature tendencies of the first, second, and third non-volatile memory dies, it is decided not to read the temperature measured by the third temperature sensor, or not to compare it with a threshold temperature. In the memory device, if the temperature measured by the first and second temperature sensors is read from the first and second non-volatile memory dies, and at least one temperature read from the first and second non-volatile memory dies is above the threshold temperature, the frequency of issuing instructions to the first, second, and third non-volatile memory dies, or the access speed to the first, second, and third non-volatile memory dies, is reduced.

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