Auxiliary power supply power failure protection for wireless power transmission system

Abstract

The present disclosure features a circuit and method for protecting transistors of a wireless power receiver that can be controlled by a gate driver powered by an auxiliary power source. The circuit can include: a comparator configured to generate a signal indicating a comparison of the value of the auxiliary power source with a predetermined threshold; and a fault latch coupled to the comparator. The fault latch can be configured to trigger based on the generated signal and transmit a signal to a corresponding input of the gate driver to place the corresponding gate of the transistor in a latched state. Switches respectively coupled to the gate drivers can be configured to disconnect the corresponding output of the gate driver from the corresponding transistor gate. Gate hold circuits respectively coupled to the corresponding transistor gates can be configured to maintain the latched state of the corresponding transistor gate for a period of time.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 62 / 967,328, filed on January 29, 2020, entitled “SYSTEMS AND METHODS FOR AUXILIARYPOWER DROPOUT PROTECTION,” and U.S. Provisional Application No. 63 / 036,975, filed on June 9, 2020, entitled “GATE DRIVER IMPLEMENTATIONS FOR SAFE WIRELESS POWER SYSTEM OPERATION,” each of which is incorporated herein by reference in its entirety. Technical Field

[0003] The following disclosure relates to methods and systems for protecting one or more components of a wireless power system, and more particularly to methods and systems for operating one or more gate drivers of a wireless power receiver under various fault modes. Background Art

[0004] A wireless power receiver or its components may be susceptible to various failure modes. For example, an auxiliary power supply may be used to provide a separate voltage or current source from a primary power source to components of an electronic system. In another example, an auxiliary power supply may be used to provide voltage to active components (e.g., transistors) used in complex electronic systems. In some instances, the auxiliary power supply may fail, causing the wireless power system to experience failure modes. Summary of the Invention

[0005] In one aspect, the present disclosure features a method for protecting one or more components of a wireless power receiver, the wireless power receiver including one or more transistors configured to be controlled by one or more corresponding gate drivers. The gate drivers may be configured to be powered by an auxiliary power supply. The method may include: generating, by a comparator, a signal indicating a comparison of a value of the auxiliary power supply with a predetermined threshold; triggering a fault latch based on the generated signal, the triggering comprising: transmitting a signal to a corresponding input of the gate driver to cause a latched state of a corresponding gate of the one or more transistors; disconnecting a corresponding output of the gate driver from a corresponding transistor gate by one or more switches respectively coupled to the one or more gate drivers; and maintaining the latched state of the corresponding transistor gate for a period of time by one or more gate holding circuits respectively coupled to the transistor gate.

[0006] Various embodiments of the example method may include one or more of the following features. The time period may at least partially overlap with a duration associated with a voltage induced on a resonator of the wireless power receiver. The auxiliary power source may be a voltage source. The time period may at least partially overlap with a duration during which the value of the auxiliary power source is zero volts. One or more gate drivers may be configured to drive corresponding transistor gates of a tunable matching network of the wireless power receiver. One or more gate drivers may be configured to drive corresponding transistor gates of a protection circuit coupled to a rectifier input or a rectifier output of the wireless power receiver. The value of the auxiliary power source may be a voltage value. The signal may indicate whether the value of the auxiliary power source is above or below a predetermined threshold.

[0007] The one or more gate hold circuits may each include at least one pull-up resistor. The one or more gate hold circuits may each include at least one capacitor having a capacitance value based on a time period. The time period may be 2 seconds or less.

[0008] In another aspect, the present disclosure features a protection circuit for one or more components of a wireless power receiver. The one or more components may include one or more transistors configured to be controlled by corresponding gate drivers. The gate drivers may be configured to be powered by an auxiliary power supply. The circuit may include a comparator configured to generate a signal indicating a comparison of a value of the auxiliary power supply with a predetermined threshold and a fault latch coupled to the comparator. The fault latch may be configured to trigger based on the generated signal and transmit a signal to a corresponding input of the gate driver to cause the corresponding gate of the one or more transistors to be in a locked state. The circuit may include one or more switches, each coupled to the one or more gate drivers and configured to disconnect the corresponding output of the gate driver from the corresponding transistor gate; and one or more gate holding circuits, each coupled to the transistor gate and configured to maintain the locked state of the corresponding transistor gate for a period of time.

[0009] Various embodiments of the example protection circuit may include one or more of the following features. The time period may at least partially overlap with a duration associated with a voltage induced on a resonator of the wireless power receiver. The auxiliary power supply may be a voltage source. The time period may at least partially overlap with a duration during which the value of the auxiliary power supply is zero volts. One or more gate drivers may be configured to drive one or more corresponding transistor gates of a tunable matching network of the wireless power receiver. One or more gate drivers may be configured to drive one or more corresponding transistor gates of a protection circuit coupled to a rectifier input or a rectifier output of the wireless power receiver. The value of the auxiliary power supply may be a voltage. The signal may indicate whether the value of the auxiliary power supply is above or below a predetermined threshold. The one or more gate hold circuits may each include at least one pull-up resistor. The one or more gate hold circuits may each include at least one capacitor having a capacitance value based on a time period. The time period may be 2 seconds or longer.

[0010] In another aspect, the present disclosure features a system for protecting one or more components of a wireless power receiver, wherein the receiver includes at least one transistor gate. The system may include a gate driver configured to provide at least one control signal to control switching of the transistor gate so that power is transferred to a load coupled to the receiver; and a first controller coupled to the gate driver and configured to generate a protection signal. The protection signal may include (i) a fault signal indicating a fault in one or more components of the receiver; (ii) a signal indicating that the transistor gate should be latched; and / or (iii) at least one undervoltage signal indicating that an undervoltage condition exists in a power supply of the gate driver. Based on the generated protection signal, the gate driver may be configured to adjust the provided control signal to latch the transistor gate so that power is not transferred to the load.

[0011] Various embodiments of the example system may include one or more of the following features. The transistor gate may form part of an active rectifier. Adjusting the control signal to latch the transistor gate may cause a short circuit at the input of the active rectifier. The transistor gate may comprise a low-side transistor of the active rectifier. The fault signal may include an undervoltage signal indicating that the output voltage of a power supply of the gate driver is below a predetermined voltage level. The adjusted control signal may be configured to turn on the transistor gate for a period of time. The power supply may include at least one of a DC-DC converter or an energy storage device. The control signal may be a pulse-width modulated (PWM) signal. The system may include a second controller coupled to the gate driver and configured to generate the PWM signal. The first controller and the second controller may be separate controllers. The load may be a battery. The system may also include a voltage regulator configured to provide a signal indicating a voltage level of the battery to the second controller. The first controller may be configured to monitor one or more signals associated with at least one of the wireless power receiver, the gate driver, or the power supply to generate a protection signal.

[0012] In another aspect, the present disclosure features a method for protecting one or more components of a wireless power receiver, wherein the receiver includes at least one transistor gate configured to be controlled by at least one gate driver. The method may include: providing, by the gate driver, at least one control signal to control switching of the transistor gate so that power is transferred to a load coupled to the receiver; and generating, by a first controller coupled to the gate driver, a protection signal. The protection signal may include at least one of: (i) a fault signal indicating a fault in one or more components of the receiver; (ii) a signal indicating that the transistor gate should be latched; and / or (iii) at least one undervoltage signal indicating the presence of an undervoltage condition in a power supply of the gate driver. The method may include: adjusting, by the gate driver, the control signal provided based on the received protection signal to latch the transistor gate so that power is not transferred to the load.

[0013] Various embodiments of the example method may include one or more of the following features. The transistor gate may form part of an active rectifier. Adjusting the control signal to latch the transistor gate causes a short circuit at the input of the active rectifier. The transistor gate may be a low-side transistor of the active rectifier. The fault signal may include an undervoltage signal indicating that the output voltage of a power supply of the gate driver is below a predetermined voltage level. The adjusted control signal may be configured to turn on the transistor gate for a period of time. The control signal may be a pulse width modulated (PWM) signal. The power supply may include at least one of the following: a DC-DC converter or an energy storage device.

[0014] The control signal may include a pulse width modulation (PWM) signal.The method may include generating the PWM signal by a second controller coupled to the gate driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of an exemplary wireless power system.

[0016] Figures 2A to 2D is a schematic diagram of an exemplary wireless power receiver coupled to an auxiliary power source.

[0017] Figure 2E It's a picture Figures 2A to 2D A graph of an exemplary voltage signal in a wireless power receiver.

[0018] Figures 3A to 3D is a schematic diagram of an exemplary wireless power receiver coupled to an auxiliary power source including an exemplary protection mechanism.

[0019] Figure 3E is coupled to Figure 3C An enlarged view of an exemplary gate holding circuit for one or more transistors.

[0020] Figure 3F is coupled to Figure 3D A magnified view of an exemplary gate-holding circuit for a transistor.

[0021] Figure 4A It is a diagram showing Figures 3A to 3F FIG. 5 is a graph of an exemplary voltage signal in a wireless power receiver illustrating an exemplary protection mechanism.

[0022] Figure 4B It's a picture Figure 4A A graph of an exemplary voltage signal over a longer period of time.

[0023] Figure 5 is a flow chart of an exemplary method for protecting one or more components of a wireless power receiver.

[0024] Figure 6 is a schematic diagram of an exemplary wireless power system utilizing active rectification.

[0025] Figure 7A Yes means it is configured to Figures 7B to 7C A block diagram of one or more components of a gate driver system providing signals.

[0026] Figures 7B to 7C It is used to protect Figure 7D Block diagram of an exemplary gate driver system for protecting a wireless power receiver from failure modes.

[0027] Figure 7D Yes Figures 7B to 7C Schematic diagram of the connection between an exemplary gate driver system and an exemplary active rectifier of a wireless power receiver.

[0028] Figure 8 is with 7A to 7D Logic table of various signals related to the circuit.

[0029] Figures 9A to 9B An exemplary rectifier for a wireless power receiver is shown. 7A to 7D Example signals related to the gate driver system of the MOSFET.

[0030] Figure 10 is a flow chart of an example method for driving a transistor gate during a protection mode of a wireless power receiver.

[0031] Figure 11 is a block diagram of an example computer system that can be used to implement the systems and methods described herein. DETAILED DESCRIPTION

[0032] Disclosed herein are exemplary embodiments of systems and methods for protecting one or more components of a wireless power system. Specifically, the exemplary systems and methods can protect one or more components of a wireless power receiver from an overvoltage condition caused by a reduction in auxiliary power used to supply circuitry controlling the one or more components.

[0033] Wireless power systems

[0034] Figure 1FIG1 is a block diagram of an exemplary wireless power system 100, which includes an exemplary system for auxiliary power brownout protection. System 100 includes a wireless power transmitter 102 and a wireless power receiver 104. In transmitter 104, a power source 105 (e.g., AC mains, battery, etc.) provides power to an inverter 108. Additional components may include a power factor correction (PFC) circuit 106 preceding inverter stage 108. Inverter 108 drives a transmitter resonator coil and a capacitive component 112 ("resonator") via an impedance matching network 110 (including fixed network components and / or tunable network components). Resonator 112 generates an oscillating magnetic field, which induces a current and / or voltage in a receiver resonator 114. The received energy is provided to a rectifier 118 via an impedance matching network 116 (including fixed network components and / or tunable network components). Ultimately, the rectified power is provided to a load 120 (e.g., one or more batteries of an electric or hybrid vehicle). In some embodiments, the battery voltage level may affect various parameters (e.g., impedance) of the wireless power system 100. Therefore, the battery voltage level may be received, determined, or measured to be provided as input to other portions of the wireless power system 100. For example, typical battery voltages for electric vehicles range from 280V to 420V.

[0035] In some embodiments, one or more components of transmitter 102 may be coupled to a controller 122, which may include a communication module (e.g., Wi-Fi, radio, Bluetooth, in-band signaling mechanism, etc.). In some embodiments, one or more components of transmitter 102 may be coupled to one or more sensors 124 (e.g., one or more current sensors, one or more voltage sensors, one or more power sensors, one or more temperature sensors, one or more fault sensors, etc.). Based on feedback signals from one or more sensors 124 and one or more sensors 128, controller 122 and one or more sensors 124 may be operably coupled to a control portion of transmitter 102.

[0036] In some embodiments, one or more components of the receiver 104 may be coupled to a controller 126, which may include a communication module (e.g., Wi-Fi, radio, Bluetooth, in-band signaling mechanism, etc.). In some embodiments, one or more components of the transmitter 102 may be coupled to one or more sensors 128 (e.g., one or more current sensors, one or more voltage sensors, one or more power sensors, one or more temperature sensors, one or more fault sensors, etc.). Based on feedback signals from the one or more sensors 124 and the one or more sensors 128, the controller 126 and the one or more sensors 128 may be operably coupled to a control portion of the transmitter 102.

[0037] Examples of wireless power systems can be found in U.S. Patent Application Publication No. 2010 / 0141042, published on June 10, 2010, entitled “Wireless energy transfer systems,” and U.S. Patent Application Publication No. 2012 / 0112535, published on May 10, 2012, entitled “Wireless energy transfer for vehicles,” both of which are incorporated herein by reference in their entirety.

[0038] In some embodiments, the exemplary impedance matching networks 110, 116 may include one or more variable impedance components. The one or more variable impedance components may be collectively referred to herein as a "tunable matching network" (TMN). The TMN may be used to adjust the impedance (e.g., including reactance) of the wireless power transmitter 102 and / or the receiver 104. In some embodiments, the tunable matching network may be referred to as a "tunable reactance circuit." In some applications, such as wireless power transmission, the impedance seen by the wireless power transmitter 102 and the receiver 104 may vary dynamically. In such applications, impedance matching may be required between the receiver resonator coil (114) and the load 120, and between the transmitter resonator coil (112) and the inverter 108 to prevent unnecessary energy loss and overheating.

[0039] The impedance seen by the resonator coil may be dynamic, in which case a dynamic impedance matching network may be provided to match the changing impedance to improve the performance (e.g., efficiency, power delivery, etc.) of the system 100. In the case of the power source 105 in the wireless power system 100, the impedance of the loading inverter 108 may be highly variable due to changes in the load 120 receiving power (e.g., a battery or battery charging circuitry) and changes in the coupling between the transmitter 102 and the receiver 104 (e.g., caused by changes in the relative positions of the transmitter and receiver resonator coils). Similarly, the impedance of the loading receiver resonator 114 may also change dynamically due to changes in the load 120 receiving power. In addition, the desired impedance match of the receiver resonator 114 may also be different for different coupling conditions and / or power supply conditions.

[0040] Thus, for example, a power transfer system that transmits and / or receives power via highly resonant wireless power transfer may need to configure or modify the impedance matching networks 110, 116 to maintain efficient power transfer. One or more components of the TMN can be configured to present an impedance between a minimum impedance and a maximum impedance achievable for the particular component. In various embodiments, the achievable impedance can depend on the operating frequency of the wireless power system 100 (e.g., 80 kHz to 90 kHz). This configuration can be performed continuously, intermittently, or at certain points in the power transfer (e.g., at the beginning of the power transfer). Examples of tunable matching networks can be found in U.S. Patent Application Publication No. 2017 / 0217325, entitled “Controlling Wireless Power Transfer Systems,” published on August 3, 2017, and U.S. Patent Application Publication No. 2017 / 0229917, entitled “PWM Capacitor Control,” published on August 10, 2017, both of which are incorporated herein by reference in their entireties.

[0041] High-power wireless power transmitters can be configured to transmit wireless power in applications such as powering and / or charging batteries for vehicles, industrial machines, robots, or electronic devices that rely on high power. For illustrative purposes, the following disclosure focuses on wireless power transmission for vehicles. However, it should be understood that any one or more of the embodiments described herein can be applied to other applications that can utilize wireless power.

[0042] Auxiliary power failure

[0043] In some embodiments, the wireless power receiver 104 may be coupled to an auxiliary power source 202 . Figures 2A to 2D Schematic diagrams of portions 200a, 200b, 200c, and 200d, respectively, of an exemplary wireless power receiver (collectively, receiver 200) coupled to an auxiliary power source 202. For example, auxiliary power source 202 can provide power to one or more components of receiver 104. These components can include one or more gate drivers 204a for one or more transistors 204b (e.g., one or more field-effect transistors (FETs)) of a tunable matching network (TMN) 206, a gate driver 208a for a transistor 208b (e.g., an insulated-gate bipolar transistor (IGBT)) of a protection circuit 210 at the output of a rectifier 212, and the like. Note that the exemplary systems and methods herein can be configured to operate with various types of transistors, including, but not limited to, FETs (e.g., junction FETs, metal-oxide-semiconductor FETs (MOSFETs)), IGBTs, bipolar junction transistors (BJTs), and the like.

[0044] In some cases, the auxiliary power supply 202 can be beneficial in providing isolated power to the gates of the transistors 204b, 208b, which can increase noise immunity of the low-voltage control circuitry. As discussed further below, when the power supplied by the auxiliary power supply 202 is low or the auxiliary power supply 202 is powered down (e.g., via the 12V power rail), the gates of the transistors 204b and / or 208b can be turned on and maintained to prevent overvoltage conditions when the wireless power transmitter 102 induces a voltage on the receiver resonator 214. For example, the voltage level of a battery configured to supply auxiliary power may decrease, e.g., when there is no alternator to charge the battery.

[0045] For comparison purposes, Figures 2A to 2D In the example provided in , the wireless power receiver 200 does not include an auxiliary power loss protection circuit for protecting the receiver 200 from damage during auxiliary power loss. Figure 2E 2 is a graph illustrating exemplary voltage signals in wireless power receiver 200. Specifically, when the auxiliary power supply's 12V rail (voltage signal 216) decreases, the voltage determined at the transistor gate also decreases (e.g., the gate driver power supply output decreases or browns out). For example, voltage signal 218, representing gate switching associated with transistor 204b, decreases over time. Voltage signal 220, representing gate switching associated with transistor 208b, remains at zero (as represented by voltage signal 216) due to the absence of auxiliary power supply brownout protection circuitry. In this example, signals 216, 218, and 220 approach zero or zero volts within 1 millisecond. If wireless power transmitter 102 continues to generate a magnetic field for several seconds, thereby inducing a voltage on the receiver resonator (e.g., resonator 214), transistor 204b and diode of rectifier 212 become susceptible to failure risk and / or damage due to an overvoltage condition caused by the transistor and diode being turned off.

[0046] Protection system and method

[0047] Figures 3A to 3D Schematic diagrams of portions 300a, 300b, 300c, and 300d, respectively, of an exemplary wireless power receiver (collectively, receiver 300) coupled to auxiliary power source 202 and including an exemplary protection mechanism. As described above, the protection mechanism can include a fault latch 302 and one or more gate hold circuits 304a, 304b, and 306 for protecting transistor 204b and rectifier diode 212 from potential overvoltage conditions. The exemplary gate hold circuits 304a and 304b are coupled between one or more transistors 204b and one or more gate drivers 204a. The exemplary gate hold circuit 306 is coupled between transistor 208b and gate driver 208a. Figure 3EFIG2 is an enlarged view of an exemplary gate-holding circuit 304 a coupled to one or more transistors 204 b. In the example provided, gate-holding circuit 304 b is identical or nearly identical to gate-holding circuit 304 a. Therefore, discussions related to circuit 304 a may apply to circuit 304 b. Figure 3F is an enlarged view of an exemplary gate hold circuit 306 coupled to transistor 208b.

[0048] Figure 4A It is a diagram showing Figures 3A to 3F FIG. 1 is a graph of an exemplary voltage signal in the wireless power receiver 300 according to an exemplary protection mechanism. Figure 4B It's a picture Figure 4A A graph of an exemplary voltage signal over a longer period of time. Figure 5 is a flow chart of an exemplary method 500 for protecting one or more components of the wireless power receiver 300. Note that for simplicity, various components are referred to below in groups (e.g., transistors 204b, 208b). However, the exemplary methods and systems discussed herein may be used and / or applied to a single component or a subset of components of the wireless power receiver 104 (e.g., one or more transistors 204b, transistor 208b, transistor Q of one or more transistors 204b, etc.). tmna1 wait).

[0049] In some embodiments, auxiliary power loss protection can be activated when auxiliary power supply 202 stops providing power to various components, as described above under the heading "Auxiliary Power Loss." Consequently, the 12V power rail (signal 216) is reduced to zero volts. If transmitter 102 is inducing a voltage on receiver 104 during this time, there is a risk of damage to one or more components that rely on the auxiliary power supply.

[0050] Reference together Figures 3A to 5In step 502, the comparator of the fault latch 302 may generate a signal indicating a comparison of the value of the auxiliary power supply 202 with a predetermined threshold or range. For example, the value may be the auxiliary power supply rail voltage. The voltage value may be compared to a predetermined threshold voltage or a predetermined voltage range. In some embodiments, the signal may indicate whether the value is above, equal to, or below the predetermined threshold. In some embodiments, the predetermined threshold is between 3% and 10% below the expected output of the auxiliary power supply 202. For example, for an auxiliary power supply configured to provide approximately 12V, the predetermined threshold 400 may be 11V (8.3% less than 12V) or less. In this example, when the auxiliary power supply 202 provides a voltage less than 11V, the fault latch may be triggered according to step 504. In some embodiments, the signal may indicate whether the value is within or outside a predetermined range. In some embodiments, the predetermined range is between ±3% and ±10% outside the expected output range of the auxiliary power supply 202. For example, for an auxiliary power supply configured to provide a voltage of approximately 12V, the predetermined range may be 11V to 13V (±8.3% relative to 12V). In this example, when the auxiliary power supply 202 provides a voltage lower than 11V or higher than 13V, the fault latch may be triggered according to step 504. Figures 4A to 4B As shown, signal 216 representing the 12V rail of the exemplary auxiliary power supply 202 decreases from approximately 12V at time t1.

[0051] In step 504, the fault latch of mechanism 302 may be triggered based on the generated signal (see signal 402 rising at t2). This may result in the transistor gate (e.g., transistor 204b or 208b) being turned on or latched. In some embodiments, when the fault latch is triggered, one or more signals may be transmitted to the input of gate driver 204a, 208a to cause the transistor gate to latch high (latched state). Figures 4A to 4B In FIG, signal 402 representing the fault latch output changes from 0V to approximately 3.3V at time t2, indicating that the fault latch has been triggered. At approximately time t2, one or more gates of one or more TMN transistors 204b latch high. After some propagation delay, at approximately time t3, the gate of protection circuit transistor 208b latches high.

[0052] In step 506, the outputs of the gate drivers 204a, 208a may be disconnected from the respective gates of the transistors 204b, 208b at t4, t5, respectively, via one or more respective switches (also referred to as switching circuits) 308, 310. In some embodiments, the disconnection of the gate driver outputs may occur within 50 microseconds, within 70 microseconds, within 100 microseconds, etc., after the fault latch is triggered. An exemplary switching circuit 308 may include:

[0053] A comparator U1 having inputs coupled to nodes N1 and N2 configured to be connected to gate drivers B1 and B2 when the power supply voltage is +15V. b Drop to the holding voltage +15V hub When the following is true, transistor Q1 is turned on;

[0054] A resistor divider configured to turn on transistors NMOS1 and NMOS2 when transistor Q1 is off, comprising:

[0055] o Resistor R1 coupled between node N1 and node N4;

[0056] Resistor R2 coupled between node N3 and node N4;

[0057] an NPN bipolar junction transistor (BJT) Q1 having an emitter coupled to node N3, a collector coupled to node N4, and a base coupled to the output of comparator U1, configured to turn off transistors NMOS1 and NMOS2 when turned on by comparator U1;

[0058] N-channel MOS transistor NMOS1 , with its gate coupled to node N4 , its drain coupled to node N5 , and its source coupled to node N3 , configured to turn off transistor PMOS1 when turned off by Q1 ;

[0059] an N-channel MOS transistor NMOS2 having a gate coupled to the node N4, a drain coupled to the node N6, and a source coupled to the node N3, configured to turn off the transistor PMOS2 when the transistor Q1 is turned off;

[0060] Capacitor C1 and resistor R3 , coupled in parallel between node N5 and node N7 , are configured to keep transistor PMOS1 turned on when transistor NMOS1 is turned on, and to discharge transistor PMOS1 and keep transistor PMOS1 turned on when transistor NMOS1 is turned off.

[0061] A P-channel MOS transistor PMOS1, with its gate coupled to node N5, its drain coupled to the output of gate driver B1, and its source coupled to node N7, configured to disconnect gate driver B1 from transistor Q1 when transistor NMOS1 is turned off. tmnb2 Disconnect;

[0062] Capacitor C2 and resistor R4, coupled in parallel between node N6 and node N8, configured to keep transistor PMOS2 turned on when transistor NMOS2 is turned on, and to keep transistor PMOS2 turned off when transistor NMOS2 is turned off; and

[0063] A P-channel MOS transistor PMOS2, with its gate coupled to node N6, its drain coupled to the output of gate driver B2, and its source coupled to node N8, configured to connect gate driver B2 to transistor Q when transistor NMOS2 is off. tmnb1 Disconnect.

[0064] In this exemplary embodiment, one objective is to align the outputs of gate drivers B1 and B2 with transistor Q tmnb2 and Q tmnb1 Disconnect. Thus, P-channel MOSFETs (e.g., PMOS1 and PMOS2) are selected to be connected in series with the high-side path because they are turned on by pulling their gate voltage below their source voltage. By connecting the P-channel MOSFET gate to -5Vb using N-channel MOSFETs (e.g., NMOS1 and NMOS2, respectively), the P-channel MOSFET can be turned on if the P-channel MOSFET source is +15V when the outputs of drivers B1 and B2 are high. Because the source to gate voltage is maintained by capacitors C1 and C2, respectively, the P-channel MOSFET can remain on for a short period of time after the driver output drops to -5Vb. By turning off the N-channel MOSFET, the P-channel MOSFET gate is disconnected from -5Vb, and the corresponding voltages across the source to gate capacitors C1 and C2 decay to zero (0)V by discharging through resistors R3 and R4, respectively. When comparator U1 detects that the gate supply voltage +15Vb has dropped to +15V hub Below, the N-channel MOSFET can be turned off.

[0065] An exemplary switching circuit 310 may include:

[0066] Resistor R5, coupled at node N 10 With node N 11 between them and is configured to allow current to flow through diode D Z1 , thereby blocking its specified voltage;

[0067] Zener diode D Z1 , when combined with resistor R5, coupled at node N 11 With node N 12 and is configured so that when +15Vg is greater than the diode D Z1 When the Zener voltage of the transistor NMOS3 is added to the gate voltage threshold of the transistor NMOS3, the transistor NMOS3 is kept turned on;

[0068] N-channel MOS transistor NMOS3, whose gate is coupled to node N 11 , the drain is coupled to node N 13 , and the source is coupled to node N 10, and is configured so that when +15Vg drops below the diode D Z1 When the Zener voltage of the transistor is added to the gate voltage threshold of the transistor NMOS3, the transistor PMOS3 is turned off;

[0069] A P-channel MOS transistor PMOS3, whose gate is coupled to node N 13 , the drain is coupled to the output of gate driver B3, and the source is coupled to node N 14 , and is configured to connect the gate driver B3 to the transistor Q when the transistor NMOS3 is turned off. prot Disconnect; and

[0070] Capacitor C3 and resistor R6 are coupled in parallel at node N 13 With node N 14 and is configured to keep the transistor PMOS3 turned on when the transistor NMOS3 is turned on; and to keep the transistor PMOS3 turned off when the transistor NMOS2 is turned off.

[0071] In this exemplary embodiment, one objective is to make the output of B3 and Q prot Disconnect. Thus, a P-channel MOSFET (e.g., PMOS3) is selected to be connected in series with the high-side path because it turns on by pulling the gate voltage below its source voltage. By connecting the P-channel MOSFET gate to 0Vg using an N-channel MOSFET (e.g., NMOS3), the P-channel MOSFET can be turned on if the P-channel MOSFET source is +15V when the output of driver B3 is high. Because the source to gate voltage is maintained by capacitor C3, the P-channel MOSFET can remain on for a short period of time after the driver output goes low to 0Vg. By turning off the N-channel MOSFET, the P-channel MOSFET gate is disconnected from 0Vg, and the voltage across the source to gate capacitor C3 decays to zero (0)V through the discharge of resistor R6. When +15Vg drops to diode D Z1 When the voltage is below the sum of the Zener voltage and the gate threshold voltage of NMOS3, the N-channel MOSFET can be turned off.

[0072] refer to Figures 4A to 4BAt time t4, signal 404a (the output of comparator U1 and the gate-source voltages of NMOS1 and NMOS2) drops to zero (0) V at time t3, thereby initiating disconnection of one or more outputs of gate driver 204a from the gates of one or more TMN transistors 204b. At time t5, signal 404b (the gate voltage of NMOS3) drops below the gate threshold voltage of NMOS3 and initiates disconnection of one or more outputs of gate driver 208a from the gates of one or more protection circuit transistors 208b. Note that the voltage at the switch begins to drop at or near time t1.

[0073] In step 508, the latched state of the respective gates of transistors 204b, 208b may be held or maintained via respective gate hold circuits 312, 314 coupled to the gates of transistors 204b, 208b. An exemplary gate hold circuit 312 may include:

[0074] Resistor R hu1 , coupled between node N7 and node N2, and configured so that when transistor PMOS1 switches transistor Q tmnb2 When disconnected from gate driver B1, transistor Q tmnb2 The gate is pulled to +15Vhub;

[0075] Resistor R hu2 , coupled between the node N2 and the node N8, and configured so that when the transistor PMOS2 switches the transistor Q tmnb1 When disconnected from gate driver B2, transistor Q tmnb1 The gate is pulled to +15Vhub;

[0076] Capacitor C hu1 , coupled between node N9 and node N2, and configured to store sufficient charge and maintain the AND transistor Q on node N2 after +15Vb has been powered down. tmnb2 and Q tmnb1 The high voltage +15Vhub on the gate of

[0077] Diode D hu1 , and the resistor R hu3 is coupled in series between the node N2 and the node N1 and is configured to be a capacitor C while +15Vb still has a voltage. hu1 charging and, after +15Vg has been powered down, preventing capacitor C hu1 discharge.

[0078] In this exemplary embodiment, one objective is to create a voltage source to continue to keep transistor Q on after +15Vb has powered down. tmnb2 and Qtmnb1 When +15Vb still has voltage, the large-capacity capacitor C hu1 can be connected with resistor R hu3 The diode D in series hu1 Charging; then at +15Vb, it has passed through R hu1 and R hu2 After power failure, the transistor Q tmnb2 and Q tmnb1 The gate supply voltage.

[0079] An exemplary gate hold circuit 314 may include:

[0080] Resistor R hu4 , coupled at node N 14 and node N 15 When transistor PMOS3 switches transistor Q prot When the gate driver B3 is disconnected, the transistor Q prot The gate is pulled to +15Vhug;

[0081] Capacitor C hu2 , coupled at node N 15 With node N 16 and is configured to store sufficient charge and maintain node N15 and transistor Q after +15Vg has been powered down. prot The high voltage +15Vhug on the gate of

[0082] Diode D hu2 , and the resistor R hu5 Series coupling at node N 15 With node N 12 and is configured to provide a voltage between the capacitor C and the +15Vg while still providing a voltage between the capacitor C and the +15Vg. hu2 charging and, after +15Vg has been powered down, preventing capacitor C hu2 discharge.

[0083] In this exemplary embodiment, one objective is to create a voltage source to continue to hold transistor Q after +15Vb has dropped. prot When +15Vb still has voltage, the large-capacity capacitor C hu2 can be connected with resistor R hu5 The diode D in series hu2 Charge, then +15Vg has passed through R hu4 After power failure, the transistor Q prot The gate supply voltage.

[0084] refer to Figures 4A to 4B, at and after time t4, signal 406a (the gate voltage of TMN transistor 204b) indicates that the latched state of the gate of TMN transistor 204b is maintained. At and after time t5, signal 406b (the gate voltage of protection circuit transistor 208b) indicates that the latched state of the gate of protection circuit transistor 208b is maintained.

[0085] In some embodiments, one or more of the hold circuits 312, 314 are configured to continue to hold the respective gates of transistors 204b, 208b for a period of time after the auxiliary power supply has dropped to or near 0 V. In some embodiments, one or more gates may be held for 1 second or less, 2 seconds or less, 3 seconds or less, or longer after the auxiliary power supply has dropped to or near 0 V. For example, in Figure 4B In the MOSFET, the gate is held as long as the auxiliary supply is at or near 0V.

[0086] In some embodiments, one or more holding circuits 312, 314 include one or more pull-up resistors for maintaining the latched state of the transistor gate. For example, the holding circuit 312 includes one or more pull-up resistors R hu1 and R hu2 (eg, one or more 10 kΩ resistors), and the holding circuit 314 includes one or more pull-up resistors R hu5 (eg, one or more 100 kΩ resistors), the one or more pull-up resistors R hu5 In some embodiments, capacitor C hu1 and C hu2 The corresponding capacitance value of the capacitor C can be selected so that the one or more holding circuits 312, 314 can maintain the locked state of the transistor gate for the expected time that the transmitter 102 is inducing a voltage on the resonator of the receiver 104. In general, the larger the capacitance value, the longer the locked state of the gate can be maintained. hu1 and C hu2 An example holding capacitance value for each capacitor in is 1 mF. In some embodiments, capacitor C hu1 and C hu2 The corresponding low discharge current is beneficial for maintaining the locked state. The discharge current comes from the gate leakage current IGSS of transistors 204b and 208b and the drain leakage current IDSS of the MOSFETs in the switching circuits 308 and 310.

[0087] An example calculation for the discharge rate of holding capacitor Chu2 is as follows:

[0088]

[0089] It is beneficial to keep the capacitor voltage above the gate threshold voltage of transistors 204b and 208b as long as the transmitter 102 is inducing a voltage on the resonator of the receiver 104. The example target hold duration is 2 seconds, and the example gate threshold voltage Q of transistor 208b is prot is 7.5V, and the capacitor C hu2 The example discharge current on the MOSFET is 2.4uA.

[0090] An example calculation of the minimum hold-up capacitor that meets these requirements is as follows:

[0091]

[0092] In some embodiments, if the value of the auxiliary power supply returns to an expected value (or within a range of values), the gate is released (eg, no longer held by the holding circuits 312, 314).

[0093] Gate Driver Operation

[0094] In an exemplary wireless power receiver, active rectification can be used to generate the desired DC signal for powering a load or charging the battery 120. Active rectification employs coupled, actively controlled switches to form a rectifier (e.g., in a half-bridge or full-bridge configuration). The switches can include transistors (e.g., FETs, MOSFETs, BJTs, IGBTs, etc.). In an exemplary wireless power system, an active rectifier can be used to convert an oscillating current (AC) received at the wireless power receiver into a direct current (DC), which can be used to ultimately transfer energy to a load, as further described below.

[0095] Figure 6 is a schematic diagram of an exemplary wireless power system 600 utilizing active rectification. Exemplary system 600 includes a wireless power transmitter 602 and a receiver 604. Exemplary transmitter 602 includes an inverter 606 (e.g., a half-bridge inverter, a full-bridge inverter, etc.) coupled to a filter circuit 608 (which may include, for example, one or more inductive components L3tA, L3tB, one or more capacitive components, etc.). Inverter 606 may include two or more switches (e.g., transistors Q1, Q2, Q3, and Q4). Switches Q1, Q2, Q3, and Q4 may be controlled via respective control signals PWM1, PWM2, PWM3, and PWM4. As described above, filter 608 may also be coupled to a transmission resonator and / or matching circuit 610 (including capacitors C2t, C1tA, C1tB, and resonator coil L1t).

[0096] In this exemplary system 600, resonator coil L1t of circuit 208 can be inductively coupled to resonator coil L1r of a receiving resonator and / or matching circuit 612 (including capacitors C1rA, C1rB, C2r, and inductor L1r) to wirelessly transmit power from transmitter 602 to receiver 604. Note that transmitter coil L1t generates an oscillating magnetic field that can induce an oscillating current in receiver coil L1r. This current can have a frequency of, for example, 85 kHz. In many examples, current I3r can include harmonics due to inverter 606. In some embodiments, the characteristics of current I3r (e.g., phase, amplitude, shape, harmonic content, etc.) can be further influenced (e.g., shaped, distorted, etc.) by one or more components of receiver 604. For example, circuits 612 and 614 can include inductive and / or capacitive components that can alter the phase or shape of current I3r. In some cases, distortion of current I3r can create challenges when operating rectifier switches, as described further below.

[0097] The exemplary receiver 604 may include a filter circuit 614 (including, for example, one or more inductive components L3rA, L3rB, one or more capacitive components, etc.) coupled to the receive resonator and / or matching circuit 612. The filter circuit 614 may change the characteristics of the current I3r (e.g., reduce distortion).

[0098] The filter circuit 614 can be coupled to a rectifier 616 (e.g., a half-bridge rectifier, a full-bridge rectifier, etc.), which can include two or more switches (e.g., transistors Q5, Q6, Q7, and Q8). The exemplary rectifier 616 can be directly or indirectly coupled to a load 618 (e.g., a battery). In some embodiments, a current sensor 620 can determine (e.g., measure, sense, etc.) characteristics of the current I3r. The current sensor 620 can be coupled to the output of the filter 614 and / or the input of the rectifier 616. For example, the current sensor 620 can determine the phase of the current I3r at the input of the rectifier 616. The sensor signal can be provided to a processor and / or controller (e.g., controller 126) for processing. In some embodiments, the processor and / or controller can generate a control signal (e.g., a PWM signal) for controlling one or more switches of the rectifier 616 based on one or more signals from the current sensor 620. Each switch (e.g., a transistor) of the rectifier 616 can be controlled by a corresponding gate driver. The processor and / or controller can provide control signals (e.g., PWM5, PWM6, PWM7, PWM8) to the gate drivers of one or more switches (e.g., transistors Q5, Q6, Q7, Q8, respectively) of the rectifier 616. In some embodiments, the current sensor 620 can include a zero-crossing detector configured to detect zero crossings of the current I3r. The detector signal can be provided to a controller (e.g., controller 126) to determine control signals for the switches.

[0099] In some embodiments, the control signal can cause the rectifier switch to operate in various modes. These modes can include hard switching and soft switching (e.g., zero voltage switching). In some embodiments, the rectifier switch can operate in one mode during a first time period and in another mode during a second time period. In some cases, the switch can alternate between the two modes within a given time period.

[0100] In some embodiments, one or more transistors of active rectifier 616 can operate as a safety mechanism to protect one or more components of wireless power system 600. For example, one or more of the following failure modes may be dangerous and / or have harmful effects: overcharging battery 618; vehicle disengagement during power transfer; an overvoltage condition in one or more components of receiver 604; a short circuit in one or more components of receiver 604; and / or circulating energy in receiver 604.

[0101] In some cases, to prevent one or more of the above-described failure scenarios, it may be beneficial for the transistors of receiver 604 to be turned on by gate drivers. These transistors may include (i) the transistors of the rectifier (e.g., turning on transistors Q7 and Q8 while turning off transistors Q5 and Q6); (ii) the gate driver 204a of transistor 204b of TMN 206; and / or (iii) the gate driver 208a of transistor 208b of protection circuit 210 at the output of rectifier 212. Failure of the gate driver may result in one or more of the above-described failure scenarios. The gate driver may fail and / or fail to turn on the transistors in any one or more of the following scenarios (also referred to as "failure modes"):

[0102] An undervoltage condition on the battery coupled to the gate driver. For example, an undervoltage condition could be when the voltage of a 12V battery falls below 6V.

[0103] An overvoltage condition on the battery coupled to the gate driver. For example, an overvoltage condition could be a 12V battery with a voltage greater than 18V.

[0104] A power failure event, undervoltage event, overvoltage event, or short circuit event occurs on the gate driver power supply.

[0105] • Improper PWM generation (eg, PWM signal is low (eg, zero or ground)).

[0106] A controller coupled to one or more gate drivers fails.

[0107] One or more gate drivers for one or more transistors of the active rectifier 616 can be configured to prevent one or more of the above-described failure modes. In various embodiments, one or more gate drivers can be configured to latch or turn on the gates of the rectifier transistors (e.g., turning on transistors Q7 and Q8 while turning off transistors Q5 and Q6) to effectively short-circuit the rectifier. By short-circuiting the rectifier, the wireless power receiver and / or coupled vehicle can be protected from various fault conditions as described.

[0108] Figure 7A A block diagram is shown showing one or more components 700a configured to provide Figures 7B to 7C The gate driver systems 700b and 700c provide signals. Figures 7B to 7C A block diagram illustrating exemplary gate driver systems 700b, 700c for protecting a wireless power receiver 700d from failure modes is shown. The exemplary gate driver systems 700b, 700c may include a pre-driver stage 702, a power supply 704, an energy storage 706, and a post-driver stage 710. Figure 7DIllustrated are connections between example gate driver systems 700b, 700c and an example active rectifier 726 for a wireless power receiver 700d (eg, having low-side transistors Q1, Q2).

[0109] refer to Figure 7A , the gate driver systems 700b, 700c may receive one or more signals from the safety controller 714 to enable the protection mode. The controller 714 may be configured to:

[0110] Monitoring one or more output voltage levels (eg, primary output voltage level VPRI and / or secondary output voltage level VSEC) of a power supply 704 (eg, an isolated DC-DC converter);

[0111] Monitor the voltage level of a 12V battery coupled to the power supply; and / or

[0112] • Generate a signal (eg, “HW ENABLE”) based on a fault condition of the gate driver system 700b, 700c.

[0113] HW ENABLE is a hardware control signal that enables normal operation of the hardware of the gate driver systems 700b, 700c during power transfer mode. The controller 714 can generate the hardware signal HW ENABLE based at least in part on the monitored voltage levels VPRI, VSEC from the power supply 704 for provision to the pre-driver stage 702. In some cases, the signal HW ENABLE can have a binary output. When there is no fault condition, the signal HW ENABLE can be "high" (also known as "asserted"). When there is no fault condition, the PWM signal enables switching in power transfer mode. When a fault condition occurs, HW ENABLE is "low" (also known as "disabled"). The hardware signal HW ENABLE can be de-asserted in response to a power stage overcurrent or overvoltage event detected by the safety controller 714. If the voltage of the 12V battery is too low, the HW ENABLE signal can be set to a too low level (when compared to a lower threshold (e.g., 6V, 8V, 10V, etc.)) or too high level (when compared to a higher threshold (e.g., 14V, 16, 18V, etc.)).

[0114] The safety controller 714 can be configured to de-assert the enable signal (SW ENABLE) to implement the protection mode of the gate driver systems 700b and 700c. The signal SW ENABLE is a software control signal that enables the software or firmware of the gate driver systems 700b and 700c to operate normally during the power transmission mode. The signal SW ENABLE is based at least in part on the monitored voltage levels VPRI and VSEC. When the system is in the power transmission mode, the signal SW ENABLE is high (valid), and when in the protection mode, it is low (invalid). The enable signal SW ENABLE can be generated (high or asserted) when the safety controller has cleared all fault latches in the system (e.g., the gate driver systems 700b and 700c, the wireless power receiver, the wireless power system, etc.), when one or more diagnostic self-test routines have been executed, and / or when the correct sequence of system initialization state transitions occurs.

[0115] In some embodiments, controller 714 may include one or more integrated circuits (ICs) tasked with monitoring one or more components of the wireless power system for safety. In some embodiments, controller 714 may be separate from other controllers or computing systems associated with the wireless power receiver. Controller 714 may be an application-specific integrated circuit (ASIC) configured to operate in accordance with one or more regulatory standards (e.g., those related to the automotive industry) and, in some instances, monitor one or more signals associated with the wireless power receiver.

[0116] In some embodiments, the gate driver systems 700b, 700c may receive one or more signals from a power controller (e.g., a microcontroller (MCU)) 720. The power controller 720 may be tasked with regulating the power of the vehicle battery (e.g., based on signals received from the voltage regulator 7160). The controller 720 may be configured to generate signals for controlling one or more transistor gates (e.g., Figure 7D A pulse width modulation (PWM) signal (e.g., PWMA, PWMB) is provided to the gates G1, G2 of the transistors Q1, Q2.

[0117] In some embodiments, the primary side voltage level VPRI of the power supply 704 can be generated by a voltage regulator 716 (e.g., including a DC-DC converter). The voltage regulator can monitor the battery voltage (e.g., the voltage of the battery of an electric vehicle that the wireless power receiver is configured to charge). The voltage VPRI can be used to power the controllers 714 and 720. In some embodiments, there may be one or more primary voltage levels depending on the requirements of the components of the system for different voltage levels (e.g., VPRI_1, VPRI_2, VPRI_3, etc.). These different primary voltage levels can be provided by one or more converters or regulators.

[0118] refer to Figure 7B , the exemplary power supply 704 is configured to generate a low voltage signal VPRI (e.g., 3.3V) on its primary side, which is provided to the controller 714, the controller 720 and / or the pre-driver circuit 702. When the primary voltage VPRI is lower than a predetermined threshold (e.g., 3V, 2.5V, 2V, 1V or lower), the pre-driver circuit 702 is configured to generate an undervoltage signal PRI UVLO. The exemplary power supply 704 can be configured to generate a high voltage signal VSEC (e.g., 15V) on its secondary side, which is provided to the energy storage 706C. E-BANK (e.g., one or more batteries, one or more capacitors, etc.) and / or one or more capacitors C VSEC In some embodiments, systems 700b, 700c rely on energy storage 706 to prevent VSEC from decreasing or losing power. The secondary voltage VSEC can be provided to a monitor in controller 714 and / or pre-driver circuit 702, for example, to detect an undervoltage condition. For example, the monitor can compare the voltage level VSEC with a lower threshold (e.g., 15V, 14V, 12V, 10V, or lower). In some embodiments, the monitor in controller 714 can compare the voltage level VSEC with an upper threshold (e.g., 16V, 18V, 20V, or higher).

[0119] The exemplary pre-driver circuit 702 can be coupled to (a) a first NOR logic gate 722a configured to receive the control signal PWMA and the fault signal HWENABLE and (b) a second NOR logic gate 722b configured to receive the control signal PWMB and the fault signal HW ENABLE. The pre-driver circuit 702 is configured to receive the outputs of the NOR gates 722a and 722b. The pre-driver circuit 702 and the NOR gates 722a and 722b are configured to generate an inverted control signal The pre-driver circuit 702 can be coupled to an AND logic gate 724, which is configured to receive a fault signal HW ENABLE and an enable signal SW ENABLE. The pre-driver circuit 702 can be configured to receive the output of the AND gate 724 on the primary low-voltage side and output a latching signal LATCH FETS on the secondary high-voltage side. The latching signal LATCH FETS is provided as an input to the post-driver circuit 710.

[0120] The exemplary inverting post-driver circuit 710 may receive, process and / or invert the control signal Therefore, in the power transmission mode, the post-driver circuit 710 outputs the control signals POST-PWMA, POST-PWMB (graphs 906a, 906b), which are configured to control the circuit 700d (see Figure 9A ) of the gates G1 and G2. In the protection mode, the post-driver circuit 710 outputs the control signals POST-PWMA and POST-PWMB (graphs 908a and 908b), so that the gates G1 and G2 are latched (see Figure 9B ). Signal LATCH FETS can be configured to enable the control signal when LATCHFETS is high The gates G1 and G2 are then latched to a high level by the signals POST-PWMA and POST-PWMB when the signal LATCH FETS is low.

[0121] Figure 8 FIG8 is a logic table 800 of various signals associated with one or more circuits 700a, gate driver systems 700b and 700c, and / or receiver 700d. Logic table 800 can be used to understand safe operation of gate driver systems 700b and 700c. Note that the left side of table 800 includes logic inputs 802, while the right side includes logic outputs 804.

[0122] In the example scenario of row #14 of table 800, logic input 802 indicates the fault signal HW ENABLE but does not indicate the enable signal SW ENABLE. In this example, gates G1 and G2 are latched high and no PWM signals (PWMA, PWMB) are generated.

[0123] In the example scenario of row #19, the logic input 802 indicates that there is no undervoltage condition (according to the inverted signal ) and enable signals HW ENABLE and SW ENABLE from controller 720. Thus, for example, the logic output 804 of row #19 includes the generation of control signals PWMA and PWMB, thereby enabling transistors Q1 and Q2 to operate in power transfer mode. As can be seen from table 800, the logic combinations in rows #16 to #19 are a set of signal combinations that enable the generation of PWM signals for power transfer mode (compare to rows #1 to #15).

[0124] Figures 9A to 9B Example signals related to gate driver systems 700b, 700c in an example rectifier 900 of a wireless power receiver are illustrated. Figure 9A The signals during the power transfer mode are depicted, where an AC current 902a and an AC voltage 902b are input to the rectifier 900, thereby generating an output current 904 to the battery VDC. Note that during the power transfer mode, the rear drive signals PWMA, PWMB cause the gates G1, G2 to switch states (as shown in graphs 906a, 906b). Therefore, the gates are not in protection mode. In contrast, in protection mode Figure 9B In the embodiment of FIG1 , the gate driver's back-drive signals PWMA and PWMB are in the on state (as shown in graphs 908a and 908b). When the transistor gates remain on, the input current is shorted through the low-side transistors Q1 and Q2, thereby enabling the safety or protection mode. This causes the rectifier output current 904 to drop to zero.

[0125] Note that one or more gate driver implementations and operations described herein may be applied to gate driver 204 a of transistor 204 b of TMN 206 and / or gate driver 208 a of transistor 208 b of protection circuit 210 at the output of rectifier 212 .

[0126] Figure 10 1 is a flow chart of an example method 1000 for protecting components of a wireless power receiver as described above. In step 1002, a gate driver (e.g., gate driver systems 700b, 700c) may provide one or more control signals (e.g., PWM signals POST-PWMA, POST-PWMB) to control switching of transistor gates (e.g., gates G1, G2 of a rectifier (e.g., rectifier 900)) in a power transfer mode, such that power is transferred to a load (e.g., a battery).

[0127] In step 1004, a controller coupled to the gate driver (e.g., safety controller 714) may generate protection signals. The protection signals may include (i) a fault signal indicating a fault in one or more components of the receiver; (ii) an enable signal indicating that a transistor gate (e.g., gate G1 or G2) should be latched; and / or (ii) at least one undervoltage signal indicating that an undervoltage condition exists in a power supply of the gate driver (e.g., power supply 704 and / or energy reservoir 706).

[0128] In step 1006, the gate driver may adjust the control signal based on the received protection signal to latch the transistor gate so that power is not transmitted to the load. As described in the above example embodiments, the pre-driver circuit 702 of the gate driver system 700b, 700c may receive the PWM signals PWMA, PWMB from the power controller 720. The pre-driver circuit 702 may provide a signal to the post-driver circuit 710. The post-driver circuit 710 provides PWM signals POST-PWMA and POST-PWMB to the transistor gates G1 and G2. Figure 9A During the power transfer mode, the PWM signals POST-PWMA, POST-PWMB shown in graphs 906a, 906b are used to drive the switching of the gates G1, G2. In the protection mode, the PWM signals POST-PWMA, POST-PWMB are adjusted to latch the gates G1, G2. Figure 9B Graphs 908a and 908b illustrate PWM signals POST-PWMA and POST-PWMB, respectively, as being held at high levels (indicated by arrows 910a and 910b, respectively). This latches gates G1 and G2, respectively, and stops delivering power to the load. For example, delivered power can stop immediately after regulation or decrease over time. As a result of latching, the example rectifier output current 904 decreases to zero after time t0.

[0129] Hardware and software implementation

[0130] Figure 111100 is a block diagram of an example computer system 1100 that can be used to implement the systems and methods described herein. A general-purpose computer, network appliance, mobile device, or other electronic system may also include at least a portion of system 1100. System 1100 includes a processor 1110, memory 1120, storage device 1130, and input / output device 1140. Each of components 1110, 1120, 1130, and 1140 can be interconnected, for example, using a system bus 1150. Processor 1110 is capable of processing instructions for execution within system 1100. In some implementations, processor 1110 is a single-threaded processor. In some implementations, processor 1110 is a multi-threaded processor. Processor 1110 is capable of processing instructions stored in memory 1120 or on storage device 1130.

[0131] Memory 1120 stores information within system 1100. In some implementations, memory 1120 is a non-transitory computer-readable medium. In some implementations, memory 1120 is a volatile memory unit. In some implementations, memory 1120 is a non-volatile memory unit. In some examples, some or all of the data described above may be stored on a personal computing device, in a data store hosted on one or more centralized computing devices, or via cloud-based storage. In some examples, some data is stored in one location, while other data is stored in another location. In some examples, quantum computing may be used. In some examples, functional programming languages ​​may be used. In some examples, electronic memory, such as flash-based memory, may be used.

[0132] Storage device 1130 can provide mass storage for system 1100. In some implementations, storage device 1130 is a non-transient computer-readable medium. In various implementations, storage device 1130 can include, for example, a hard disk device, an optical disk device, a solid-state drive, a flash drive, or some other mass storage devices. For example, a storage device can store long-term data (e.g., database data, file system data, etc.). Input / output device 1140 provides input / output operations for system 1100. In some implementations, input / output device 1140 can include one or more of the following: a network interface device (e.g., an Ethernet card), a serial communication device (e.g., an RS-232 port), and / or a wireless interface device (e.g., an 802.11 card, a 3G wireless modem, or a 4G wireless modem). In some implementations, input / output device 1140 can include a drive device configured to receive input data and send output data to other input / output devices, such as a keyboard, a printer, and a display device 1160. In some examples, mobile computing devices, mobile communication devices, and other devices can be used.

[0133] In some implementations, at least a portion of the methods described above may be implemented by instructions that, when executed, cause one or more processing devices to perform the processes and functions described above. Such instructions may include, for example, interpreted instructions (such as script instructions), or executable code, or other instructions stored in a non-transitory computer-readable medium. The storage device 1130 may be implemented in a distributed manner (such as a server farm or a group of widely distributed servers) over a network, or may be implemented in a single computing device.

[0134] Although already Figure 11 An example processing system is described in the specification, but embodiments of the subject matter, functional operations, and processes described in this specification may be implemented in other types of digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or a combination of one or more thereof. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-volatile program carrier for execution by a data processing apparatus or to control its operation. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagated signal, for example, a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver device for execution by a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof.

[0135] The term "system" may encompass all kinds of devices, equipment, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. A processing system may include specialized logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, a processing system may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0136] A computer program (which may also be referred to or described as a program, software, software application, module, software module, script, or code) may be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages; and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store portions of one or more modules, subroutines, or code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0137] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0138] A computer suitable for executing a computer program may include, for example, a general-purpose microprocessor or a special-purpose microprocessor or both, or a central processing unit of any other type. Typically, the central processing unit will receive instructions and data from a read-only memory or a random access memory or both. A computer typically includes a central processing unit for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include or be operably coupled to receive data from one or more large-capacity storage devices (e.g., magnetic disks, magneto-optical disks, or optical disks) for storing data or to transmit data thereto or both. However, a computer does not need such a device. Moreover, a computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name a few.

[0139] Computer-readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media, and storage devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0140] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component (e.g., as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a client computer having a graphical user interface or a web browser through which a user can interact with implementations of the subject matter described in this specification), or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any digital data communication form or medium (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), such as the Internet.

[0141] A computing system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0142] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of what may be claimed, but rather as descriptions of features of particular embodiments. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. Moreover, although features may be described above as working in certain combinations and even initially claimed as such, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve a sub-combination or a variation of a sub-combination.

[0143] Equally, although in the accompanying drawings, operations are described in a particular order, this should not be understood as requiring these operations to be performed in the particular order shown or in a sequential order, or all illustrated operations are performed to obtain desired results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of each system component in the embodiment described above should not be understood as requiring this separation in all embodiments, and should be understood that described program component and system can be integrated in a single product usually, or can be packaged into multiple products.

[0144] Certain embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order or sequential order shown to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous. Additional steps or stages may be provided from the described processes, or steps or stages may be eliminated. Thus, other implementations are within the scope of the following claims.

[0145] the term

[0146] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting.

[0147] As used in the specification and claims, the term "about," the phrase "approximately equal to," and other similar phrases (e.g., "the value of X is approximately Y" or "X is approximately equal to Y") should be understood to mean that one value (X) is within a predetermined range of another value (Y). Unless otherwise specified, the predetermined range may be plus or minus 20%, 10%, 5%, 3%, 1%, 0.1%, or less than 0.1%.

[0148] Unless expressly stated to the contrary, the indefinite articles "a" and "an" as used in the specification and claims should be understood to mean "at least one". The phrase "and / or" as used in the specification and claims should be understood to mean "one or both" of the elements so combined, i.e., elements that are present in combination in some cases and separately in other cases. Multiple elements listed using "and / or" should be interpreted in the same manner, i.e., "one or more" of the elements so combined. In addition to the elements specifically identified by the "and / or" clause, other elements may optionally be present, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, when used in conjunction with open language such as "comprising", a reference to "A and / or B" may, in one embodiment, refer only to A (optionally including elements other than B); in another embodiment, to only B (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements), etc.

[0149] As used in the specification and claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" should be interpreted as being inclusive, i.e., including at least one, but also including more than one of several elements or a list of elements, and (optionally) other unlisted items. Only terms explicitly indicated to the contrary (such as "only one" or "exactly one") or the term "consisting of" when used in a claim will refer to the inclusion of one element from several elements or a list of elements. In general, the term "or" as used should only be interpreted as indicating exclusive alternatives (i.e., "one or the other but not both") if preceded by an exclusive term (such as "either," "one of," "only one," or "exactly one"). "Substantially consisting of" as used in a claim should have the ordinary meaning used in the field of patent law.

[0150] As used in the specification and claims, the phrase "at least one" when referring to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, but does not necessarily include at least one of each element specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows that elements other than the elements specifically identified in the list of elements to which the phrase "at least one" refers may optionally be present, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, in one embodiment, "at least one of A and B" (or equivalently, "at least one of A or B," or equivalently, "at least one of A and / or B") may mean at least one (optionally, including more than one) A, with no B (and optionally, including elements other than B); in another embodiment, may mean at least one (optionally, including more than one) B, with no A (and optionally, including elements other than A); in yet another embodiment, means at least one (optionally, including more than one) A and at least one (optionally, including more than one) B (and optionally, including other elements), etc.

[0151] The use of "including," "comprising," "having," "containing," "involving," and variations thereof, is meant to encompass the items listed thereafter as well as additional items.

[0152] The use of ordinal terms such as "first," "second," "third," etc. in the claims to modify claim elements does not, by itself, imply any priority, precedence, or order of one claim element with respect to another claim element, or temporal order of the acts of performing a method. Ordinal terms are used solely as labels to distinguish one claim element having a particular name from another claim element having the same name (but used using ordinal terms) to distinguish the claim elements.

Claims

1. A method for protecting one or more components of a wireless power receiver, the one or more components comprising one or more transistors, the one or more transistors being configured to be controlled by one or more gate drivers, the gate drivers being configured to be powered by an auxiliary power supply, the method comprising: generating, by a comparator, a signal indicative of a comparison of the value of the auxiliary power supply with a predetermined threshold; triggering a fault latch based on the generated signal, the triggering comprising transmitting a signal to a corresponding input of the gate driver to cause a corresponding gate of the one or more transistors to be in a latched state; disconnecting respective outputs of the gate drivers from respective transistor gates via one or more switches respectively coupled to the one or more gate drivers; as well as The latched state of the corresponding transistor gate is maintained for a period of time by one or more gate holding circuits respectively coupled to the transistor gates. 2 . The method of claim 1 , wherein the time period at least partially overlaps with a duration associated with a voltage induced on a resonator of the wireless power receiver.

3. The method of claim 1 , wherein the auxiliary power source is a voltage source and the time period at least partially overlaps with a duration during which the value of the auxiliary power source is zero volts. 4 . The method of claim 1 , wherein the one or more gate drivers are configured to drive the corresponding transistor gates of a tunable matching network of the wireless power receiver. 5 . The method of claim 1 , wherein the one or more gate drivers are configured to drive the corresponding transistor gates of a protection circuit, the protection circuit being coupled to a rectifier input or a rectifier output of the wireless power receiver. The method of claim 1 , wherein the value of the auxiliary power supply is a voltage value. 7 . The method of claim 1 , wherein the signal indicates whether the value of the auxiliary power supply is above or below the predetermined threshold.

8. The method of claim 1, wherein the one or more gate hold circuits each comprise at least one pull-up resistor. 9 . The method of claim 1 , wherein the one or more gate hold circuits each comprise at least one capacitor having a capacitance value based on the time period.

10. The method of claim 1, wherein the time period is 2 seconds or less.

11. A protection circuit for one or more components of a wireless power receiver, the one or more components comprising one or more transistors, the one or more transistors configured to be controlled by corresponding gate drivers configured to be powered by an auxiliary power supply, the circuit comprising: a comparator configured to generate a signal indicative of a comparison of a value of the auxiliary power supply to a predetermined threshold; a fault latch coupled to the comparator, the fault latch configured to be triggered based on the generated signal and transmit a signal to a corresponding input of the gate driver to cause the corresponding gate of the one or more transistors to be in a latched state; one or more switches respectively coupled to the one or more gate drivers and configured to disconnect respective outputs of the gate drivers from respective transistor gates; as well as One or more gate holding circuits are respectively coupled to the transistor gates and configured to maintain the latched state of the corresponding transistor gates for a period of time.

12. The circuit of claim 11, wherein the time period at least partially overlaps with a duration associated with a voltage induced on a resonator of the wireless power receiver.

13. The circuit of claim 11, wherein the auxiliary power source is a voltage source, and the time period at least partially overlaps with a duration during which the value of the auxiliary power source is zero volts.

14. The circuit of claim 11, wherein the one or more gate drivers are configured to drive one or more corresponding transistor gates of a tunable matching network of the wireless power receiver.

15. The circuit of claim 11, wherein the one or more gate drivers are configured to drive one or more corresponding transistor gates of a protection circuit coupled to a rectifier input or a rectifier output of the wireless power receiver.

16. The circuit of claim 11, wherein the value of the auxiliary power supply is a voltage.

17. The circuit of claim 11, wherein the signal indicates whether the value of the auxiliary power supply is above or below the predetermined threshold.

18. The circuit of claim 11, wherein the one or more gate hold circuits each comprise at least one pull-up resistor.

19. The circuit of claim 11, wherein the one or more gate hold circuits each comprise at least one capacitor having a capacitance value based on the time period.

20. The circuit of claim 12, wherein the time period is 2 seconds or longer.

21. A system for protecting one or more components of a wireless power receiver, the components including at least one transistor gate, the system comprising: a gate driver configured to provide at least one control signal to control switching of the transistor gate so that power is delivered to a load coupled to the receiver; as well as A first controller is coupled to the gate driver and configured to generate a protection signal, the protection signal comprising: (i) a fault signal indicating a fault in one or more components of the receiver; (ii) a signal indicating that the transistor gate should be latched; and / or (iii) at least one undervoltage signal indicating the presence of an undervoltage condition in a power supply of the gate driver, wherein based on the generated protection signal, the gate driver is configured to adjust the provided control signal to latch the transistor gate so that power is not delivered to the load, and Wherein the transistor gate forms part of an active rectifier, and wherein adjusting the control signal to latch the transistor gate causes a short circuit at an input of the active rectifier.

22. The system of claim 21, wherein the transistor gate is a low-side transistor of the active rectifier.

23. The system of claim 21, wherein the fault signal comprises an undervoltage signal indicating that an output voltage of a power supply of the gate driver is lower than a predetermined voltage level.

24. The system of claim 21, wherein the adjusted control signal is configured to turn on the transistor gate for a period of time.

25. The system of claim 21, wherein the power supply comprises at least one of: a DC-DC converter or energy storage.

26. The system of claim 21, wherein the control signal is a pulse width modulated (PWM) signal.

27. The system of claim 26, further comprising: A second controller is coupled to the gate driver and configured to generate the PWM signal.

28. The system of claim 27, wherein the first controller and the second controller are separate controllers.

29. The system of claim 27, wherein the load is a battery, and the system further comprises: A voltage regulator is configured to provide a signal indicative of a voltage level of the battery to the second controller.

30. The system of claim 21, wherein the first controller is configured to monitor one or more signals associated with at least one of the wireless power receiver, the gate driver, or the power supply to generate the protection signal.

31. The system of claim 21 , further comprising: a fault latch configured to be triggered based on the protection signal and transmit a signal to a corresponding input of the gate driver so that the corresponding gate of the at least one transistor is in a latched state; a switch coupled to the gate driver and configured to disconnect the output of the gate driver from the transistor gate; as well as A gate holding circuit is coupled to the transistor gate and is configured to maintain the latched state of the transistor gate for a period of time.

32. A method for protecting one or more components of a wireless power receiver, wherein the one or more components include at least one transistor gate configured to be controlled by at least one gate driver, the method comprising: providing at least one control signal via a gate driver to control switching of the transistor gate so that power is delivered to a load coupled to the receiver; as well as A protection signal is generated by a first controller coupled to the gate driver, the protection signal comprising at least one of the following: (i) a fault signal indicating a fault in one or more components of the receiver; (ii) a signal indicating that the transistor gate should be latched; and / or (iii) at least one undervoltage signal indicating the presence of an undervoltage condition in a power supply of the gate driver; adjusting, by the gate driver, a provided control signal based on the received protection signal to latch the transistor gate so that power is not delivered to the load; wherein the transistor gate forms part of an active rectifier; and Adjusting the control signal to latch the transistor gate causes a short circuit at the input of the active rectifier.

33. The method of claim 32, wherein the transistor gate is a low-side transistor of the active rectifier.

34. The method of claim 32, wherein the fault signal comprises an undervoltage signal indicating that an output voltage of a power supply of the gate driver is lower than a predetermined voltage level.

35. The method of claim 32, wherein the adjusted control signal is configured to turn on the transistor gate for a period of time.

36. The method of claim 32, wherein the power source comprises at least one of: a DC-DC converter or energy storage.

37. The method of claim 32, wherein the control signal is a pulse width modulated (PWM) signal.

38. The method of claim 37, further comprising: The PWM signal is generated by a second controller coupled to the gate driver.

39. The method of claim 32, wherein the gate driver latches the transistor gate by: triggering a fault latch based on the protection signal, the triggering comprising transmitting a signal to a corresponding input of the at least one gate driver to cause a corresponding gate of the at least one transistor to be in a latched state; disconnecting respective outputs of the gate drivers from respective transistor gates via one or more switches respectively coupled to the at least one gate driver; as well as The locked state of the corresponding transistor gate is maintained for a period of time by at least one gate holding circuit respectively coupled to the at least one transistor gate.

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