Power stage and signal processing method

Abstract

Certain aspects of the present disclosure generally relate to a power stage (100). The power stage generally includes a first transistor (122); a second transistor (120) having a drain coupled to a drain of the first transistor; a first gate drive circuit (102) coupled between an input node of the power stage (105) and a gate of the first transistor (122); and a second gate drive circuit (104) having a first signal path (slow path: 140) coupled between the input node and a gate of the second transistor. In certain aspects, the second gate drive circuit includes a plurality of buffers (180, 182, 184, 186) in the first signal path; and a plurality of electronic devices (170, 172, 196, 198) coupled to the plurality of buffers and configured to impose a delay associated with driving the gate of the second transistor (120) to track a delay associated with driving the gate of the first transistor (122) via the first gate drive circuit (102).

Description

[0001] CLAIM

[0002] This patent application claims priority to non-provisional application number 16 / 752,412, filed January 24, 2020, entitled “Area Efficient Non-Overlapping Signal Generator,” which is assigned to the assignee of the present application and is hereby expressly incorporated by reference herein. TECHNICAL FIELD

[0003] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to a gate drive circuitry for a power stage. BACKGROUND

[0004] As the minimum feature size of integrated circuits (ICs) continues to shrink and the demand for reduced power consumption persists, core logic sections of digital circuits are supplied by ever-decreasing voltages, such as down to 1.0 V or lower. However, power supply voltages for other sections of the IC can remain at higher voltage levels. Accordingly, voltage level shifters (e.g., level shifting circuits) can be used to shift signals from a relatively lower power supply voltage level to a relatively higher power supply voltage. SUMMARY

[0005] Certain aspects of the present disclosure generally relate to a power stage. The power stage generally includes a first transistor; a second transistor having a drain coupled to a drain of the first transistor; a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor; a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor, wherein the second gate drive circuit includes a plurality of buffers in the first signal path; and a plurality of electronic devices coupled to the plurality of buffers and configured to impose a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor by the first gate drive circuit.

[0006] Certain aspects of the present disclosure generally relate to a method for signal processing. The method generally includes driving a gate of a first transistor based on an input signal via a first gate drive circuit; driving a gate of a second transistor based on the input signal via a second gate drive circuit; and imposing, by a plurality of electronic devices coupled to a plurality of buffers in a first signal path of the second gate drive circuit, a delay associated with driving the gate of the second transistor, wherein the delay tracks a delay associated with driving the gate of the first transistor. BRIEF DESCRIPTION OF DRAWINGS

[0007] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description can be had by reference to certain aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description can admit to other equally effective aspects.

[0008] FIG. 1 FIGURE 1 illustrates a half H-bridge circuit having a p-type metal oxide semiconductor (PMOS) drive circuit and an n-type metal oxide semiconductor (NMOS) drive circuit, in accordance with certain aspects of the present disclosure.

[0009] FIG. 2 is a flow diagram of example operations for signal processing, in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0010] Various aspects of the disclosure are more fully described below with reference to the figures. The disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of, or combined with, any other aspect of the disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein can be embodied by one or more elements of a claim.

[0011] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0012] Example Non-Overlapping Signal Generator

[0013] An H-bridge circuit in a power stage (e.g., a half-H-bridge implemented using two switches or an H-bridge implemented using four switches) can operate under a high voltage (HV) power supply (e.g., 12V and above). The H-bridge circuit can include a p-type metal-oxide-semiconductor (PMOS) transistor with a drain coupled to a drain of an n-type metal-oxide-semiconductor (NMOS) transistor. A PMOS drive voltage (PDRV) can switch between a supply voltage (e.g., a high voltage rail (VDD_HV)) and a supply-plus delta voltage, which is any voltage greater than a threshold voltage of the PMOS transistor of the power stage.

[0014] A level shifter can be used to level shift a ground reference signal to PDRV to control a high-side PMOS transistor of the H-bridge circuit. To implement a break-before-make (BBM) operation, a low-side control voltage (e.g., generated via an NMOS drive voltage (NDRV) circuit) can be generated using the same type of high voltage level converter that has approximately the same amount of delay as the PDRV circuit. The high voltage level converter occupies a large area due to the inclusion of high voltage protection devices therein. Certain aspects of the present disclosure relate to an NDRV circuit implemented using an area-efficient BBM generator that tracks the delay of the PDRV circuit over process, voltage, and temperature (PVT) variations.

[0015] FIG. 1 A half-H-bridge circuit 100 with a PDRV circuit 102 and an NDRV circuit 104 (also referred to as a “non-overlapping signal generator” or a “BBM generator”) is illustrated in accordance with certain aspects of the present disclosure. As shown in block 103, an input signal at an input node 105 can transition from a low voltage (LV) to a medium voltage (MV). The half-H-bridge circuit 100 includes at least a PMOS transistor 122 and an NMOS transistor 120 coupled between a high voltage (HV) power supply node 130 (VDD_HV) and a reference potential node 132 (e.g., electrical ground). As illustrated, the drains of the PMOS transistor 122 and the NMOS transistor 120 can be coupled together.

[0016] The PDRV circuit 102 includes transistors 106, 108 having gates coupled to a gate drive node 110. The transistors 106, 108 are coupled to a latch circuit 112. The delay associated with the PDRV circuit 102 can be dominated by the latching characteristics of the latch circuit 112. The latch circuit 112 includes cross-coupled transistors 114, 116. In other words, the gate of the transistor 114 is coupled to the drain of the transistor 116, and the gate of the transistor 116 is coupled to the drain of the transistor 114, as illustrated. The sources of the transistors 114, 116 are coupled to a high voltage supply node 130 (VDD_HV). In certain aspects, the gate drive node 110 can receive a voltage equal to VDD_HV - 3VGS, where VGS is the gate-source voltage of the transistor 114 or the transistor 116. A buffer 118 (e.g., an inverter) can be coupled between the gate of a PMOS transistor 122 and the drain of the transistor 116. For example, the input of the buffer 118 can be coupled to the drain of the transistor 116, and the output of the buffer 118 can be coupled to the gate of the PMOS transistor 122. In certain aspects, the PDRV circuit 102 can also include logic and protection circuitry 124, as illustrated.

[0017] The NDRV circuit 104 includes various delay elements to implement a BBM generator for driving the NMOS transistor 120 in a manner that prevents the PMOS transistor 122 and the NMOS transistor 120 from turning on at the same time. In other words, the NDRV circuit 104 can ensure that the gate voltage of the NMOS transistor 120 changes from logic low to logic high only after the PMOS transistor has turned off, thereby turning on the NMOS transistor 120. Still further, the NDRV circuit 104 can ensure that the gate voltage of the NMOS transistor 120 changes from logic high to logic low before the PMOS transistor turns on, thereby turning off the NMOS transistor 120.

[0018] The NDRV circuit 104 includes a slow path 140 and a fast path 142 coupled between the input node 105 and inputs 160, 162 of an AND gate 150. In this manner, the delay is only applied to the slow path 140 and not the fast path 142. In other words, the output of the AND gate 150 only transitions to a logic high when both inputs of the AND gate 150 are logic high, thereby turning off the NMOS transistor 120. Thus, when the input of the NDRV circuit 104 transitions from a logic low to a logic high to turn on the NMOS transistor 120, the delay associated with the slow path 140 causes a delay in the transition from a logic low to a logic high at the input of the AND gate 150, thereby causing a delay in turning on the NMOS transistor 120. As such, the delay prevents the NMOS transistor 120 from turning on until the PMOS transistor has a chance to turn off. However, when the input of the NDRV circuit 104 transitions from a logic high to a logic low to turn off the NMOS transistor 120, the delay associated with the slow path 140 does not dictate when the output of the AND gate transitions from a logic high to a logic low. In other words, the fast path 142 sets the input 162 of the AND gate to a logic low with little to no delay, thereby causing the output of the AND gate to transition to a logic low regardless of the logic state at the input 160.

[0019] In certain aspects, certain delay elements of the slow path can be configured to track (or at least approximate) the delay associated with the PDRV circuit 102. For example, the slow path can include a plurality of buffers 180, 182, 184, 186 (e.g., inverters). Transistors 170, 172 can be coupled between a medium voltage supply node 166 (VDD_MV) and respective supply inputs of the buffers 182, 186. Also, a capacitive element 196 can be coupled between the gates of the transistors 170, 172 and the output of the buffer 182, while a capacitive element 198 can be coupled between the gates of the transistors 170, 172 and the output of the buffer 186. Each of the capacitive elements 196, 198 can be implemented using a transistor (e.g., a PMOS transistor) having its drain and source terminals coupled together.

[0020] In some aspects, transistors 170, 172 can be replicas of transistors 106, 108. Also, the gate-source voltage applied to each of transistors 170, 172 can be equal to the gate-source voltage applied to each of transistors 106, 108. For example, the gate-source voltage applied to transistor 170 can be equal to (VDD_MV - 2 x VGS) - VDD_MV, which is equal to 2 x VGS. The voltage applied to the gate of transistor 106 can be equal to VDD_HV - 3 x VGS. Also, the voltage at node 133 can be at VDD_HV - VGS. Thus, the gate-source voltage of transistor 106 can be equal to (VDD_HV - 3 x VGS) - (VDD_HV - VGS), which is equal to 2 x VGS. Thus, the gate-source voltages of transistors 170, 106 can be the same, resulting in the source-drain impedances of transistors 106, 170 being at least approximately the same.

[0021] Also, capacitance elements 196, 198 can be configured to be the same as the junction capacitances associated with transistors 114, 116. For example, to transition the voltage at node 135 from a logic high to a logic low to turn off PMOS transistor 122, transistor 116 can turn off by charging the junction capacitance of transistor 116. In other words, the delay associated with the transition from a logic high to a logic low at node 135 can be a function of a resistance-capacitance (RC) time constant associated with the source-drain impedance of transistor 106 and the junction capacitance of transistor 116. This RC time constant can be tracked by an RC time constant associated with the source-drain impedance of transistor 170 and the capacitance of capacitance element 196 in order to track the delay associated with PDRV circuit 102 for the delay associated with slow path 140.

[0022] The variation in the drain-source impedance of transistors 170, 172 can track the variation in the impedance of transistors 106, 108 across PVT. Also, the variation in the capacitance of capacitance elements 196, 198 can track the variation in the junction capacitance of transistors 106, 108. Thus, NDRV circuit 104 can implement BBM functionality across PVT. In other words, the delay associated with slow path 140 is implemented by PVT tracking circuitry (e.g., transistors 170, 172 and capacitance elements 196, 198) that tracks the delay associated with PDRV circuit 102.

[0023] While the example half-H bridge circuit 100 uses a BBM generator for the NDRV circuit 104 to drive the NMOS transistor 120, in certain implementations, the PDRV circuit to drive the PMOS transistor 122 can be implemented using a BBM generator. In other words, the PDRV circuit to drive the PMOS transistor 122 can be implemented using a BBM generator configured to track the delay associated with the NDRV circuit to drive the NMOS transistor 120. Also, while the slow path of the NDRV circuit 104 is implemented using four buffers to facilitate understanding, any number of buffers and associated RC time constant circuitry (e.g., transistor 170 and capacitor element 196) can be used. For example, the slow path can be implemented using six buffers that track the delay associated with the PDRV circuit 102, but also implements a greater delay for the BBM function compared to using four buffers.

[0024] FIG. 2 CLAIM FIG. 1 FIG. 2 FIG. FIG. 2 is a flow diagram of example operations 200 for signal processing in accordance with certain aspects of the present disclosure. The operations 200 can be performed by a power stage circuit, such as the half-H bridge circuit 100.

[0025] The operations 200 begin, at block 202, with the circuit driving a gate of a first transistor (e.g., the PMOS transistor 122) based on an input signal (e.g., at the input node 105) via a first gate drive circuit (e.g., the PDRV circuit 102), and at block 204, driving a gate of a second transistor (e.g., the NMOS transistor 120) based on the input signal via a second gate drive circuit (e.g., the NDRV circuit 104). At block 206, the circuit applies a delay associated with driving the gate of the second transistor via a plurality of electronic devices of a first signal path (e.g., the slow path 140) coupled to the plurality of buffers (e.g., buffers 180, 182, 184, 186) in the second gate drive circuit. In certain aspects, the delay tracks a delay associated with driving the gate of the first transistor.

[0026] In certain aspects, the delay is applied only for a transition from a logic low to a logic high at the gate of the second transistor. In certain aspects, the plurality of electronic devices includes a replica of an electronic device of the first gate drive circuit. In certain aspects, the plurality of electronic devices can include a third transistor (e.g., transistor 170) coupled between a voltage rail (e.g., the voltage supply node 166) and a supply node of a buffer (e.g., buffer 182) of the plurality of buffers, and a first capacitor element (e.g., capacitor element 196) coupled to an output of the buffer of the plurality of buffers. The first capacitor element can be configured to replicate a capacitor element associated with the first gate drive circuit.

[0027] The various operations or methods described above can be performed by any suitable means enabled to perform the corresponding functions. The means can include various hardware and / or software components and / or modules, including, but not limited to a circuit, an application-specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations can have corresponding counterpart means-plus-function components with similar numbering.

[0028] As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Also, “determining” can include resolving, selecting, choosing, establishing and the like.

[0029] As used herein, the phrase “at least one of’ a list of items refers to any combination of those items, including single members. For example, “at least one of a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination of items from among a, b, and c (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0030] The methods disclosed herein comprise one or more steps or actions for achieving the methods. The method steps and / or actions can be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order is specified, the order and / or use of terms can be modified without departing from the scope of the claims.

[0031] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations can be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A power stage, comprising: a first transistor; a second transistor having a drain coupled to a drain of the first transistor; a first gate drive circuit coupled between an input node of the power stage and a gate of the first transistor; and a second gate drive circuit having a first signal path coupled between the input node and a gate of the second transistor, wherein the second gate drive circuit comprises: a plurality of buffers in the first signal path; and a plurality of electronic devices coupled to the plurality of buffers and configured to impose a delay associated with driving the gate of the second transistor to track a delay associated with driving the gate of the first transistor via the first gate drive circuit, wherein the plurality of electronic devices comprises: a third transistor coupled between a first voltage rail and a power supply node of a first buffer of the plurality of buffers; and a first capacitive element coupled to an output of the first buffer.

2. The power stage of claim 1, wherein the plurality of electronic devices comprises a replica of electronic devices of the first gate drive circuit.

3. The power stage of claim 1, wherein a voltage of the first voltage rail is lower than a voltage of a second voltage rail of the first gate drive circuit.

4. The power stage of claim 1, wherein the first capacitive element is coupled between the output of the first buffer and the gate of the third transistor.

5. The power stage of claim 1, wherein the first capacitive element comprises a fourth transistor, wherein a drain of the fourth transistor is coupled to a source of the fourth transistor and the output of the first buffer.

6. The power stage of claim 1, wherein the first gate drive circuit comprises: a latch circuit coupled to the gate of the first transistor; and a fourth transistor coupled to the latch circuit, wherein the third transistor is a replica of the fourth transistor.

7. The power stage of claim 6, wherein a gate-source voltage of the third transistor is the same as a gate-source voltage of the fourth transistor.

8. The power stage of claim 1, wherein the first capacitive element is configured to replicate a capacitive element associated with the first gate drive circuit.

9. The power stage of claim 8, wherein the first gate drive circuit comprises: a fourth transistor coupled to the gate of the first transistor, the capacitive element associated with the first gate drive circuit comprises a junction capacitance of the fourth transistor.

10. The power stage of claim 9, wherein the first gate drive circuit comprises a latch circuit having the fourth transistor and a fifth transistor, wherein a gate of the fourth transistor is coupled to a drain of the fifth transistor, and wherein a gate of the fifth transistor is coupled to a drain of the fourth transistor.

11. The power stage of claim 1, wherein the plurality of electronic devices comprises: a fourth transistor coupled between the first voltage rail and a power supply node of a second buffer of the plurality of buffers; and a fifth transistor coupled between the first voltage rail and a power supply node of a third buffer of the plurality of buffers. ​ ​ a second capacitive element coupled to an output of the second buffer.

12. The power stage of claim 1, wherein the second gate drive circuit comprises: a second signal path; and an AND gate, wherein a first input of the AND gate is coupled to the first signal path, wherein a second input of the AND gate is shorted to the input node via the second signal path, and wherein an output of the AND gate is coupled to the gate of the second transistor.

13. The power stage of claim 1, wherein the plurality of buffers comprises a plurality of inverters.

14. The power stage of claim 1, wherein the delay is configured to only apply to a transition from a logic low to a logic high at the gate of the second transistor.

15. A method for signal processing performed by the power stage of claim 1, comprising: driving the gate of the first transistor based on an input signal via the first gate drive circuit; driving the gate of the second transistor based on the input signal via the second gate drive circuit; and applying the delay associated with driving the gate of the second transistor via the plurality of electronics of the plurality of buffers in the first signal path coupled to the second gate drive circuit.

16. The method of claim 15, wherein the delay only applies to a transition from a logic low to a logic high at the gate of the second transistor.

17. The method of claim 15, wherein the plurality of electronics are a replica of the electronics of the first gate drive circuit.

18. The method of claim 15, wherein the capacitive element is configured to replicate a capacitive element associated with the first gate drive circuit.

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