Multi-core processor task scheduling method, device and equipment, and storage medium

Abstract

The present invention discloses a multi-core processor task scheduling method, apparatus, device, and storage medium. The method comprises: obtaining a target task to be executed; selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information comprises: binding relationship information and priority information, the binding relationship information being used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information being used to describe the priority of the target task; scheduling the target task to the target processor; and running the target task on the target processor. The present invention solves the technical problem that existing multi-core scheduling algorithms cannot accurately determine the target processor on which to run the task to be executed.

Description

Technical Field

[0001] The present invention relates to the field of processor task scheduling, and in particular to a multi-core processor task scheduling method, device and equipment, and storage medium. Background Art

[0002] On a machine running a multi-core processor, each processor has its own cache area, in which the data used to execute tasks is stored. If the task in the processor is scheduled to another processor by the operating system, since the processor cache area does not have such data, the data in the memory or hard disk needs to be loaded into the cache area, and the cache memory hit rate becomes low, which in turn affects the performance of the system.

[0003] For example, the multi-processor task scheduling algorithms provided in the prior art all have the problem of frequently scheduling tasks between multiple processors, increasing the number of unnecessary task scheduling times; and cannot accurately determine which processor the new task to be executed will run on, resulting in poor affinity of the new task to the cache memory.

[0004] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0005] Embodiments of the present invention provide a multi-core processor task scheduling method, apparatus, device, and storage medium to at least solve the technical problem that existing multi-core scheduling algorithms cannot accurately determine the target processor for running a task to be executed.

[0006] According to one aspect of an embodiment of the present invention, a multi-core processor task scheduling method is provided, including: obtaining a target task to be executed; selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; scheduling the target task to the target processor; and running the target task on the target processor.

[0007] According to another aspect of an embodiment of the present invention, a multi-core processor task scheduling device is also provided, including: an acquisition module for acquiring a target task to be executed; a selection module for selecting a target processor from a multi-core processor based on the attribute information of the above-mentioned target task, wherein the above-mentioned attribute information includes: binding relationship information and priority information, the above-mentioned binding relationship information is used to describe whether the above-mentioned target task needs to be run on a processor with a binding relationship, and the above-mentioned priority information is used to describe the priority of the above-mentioned target task; a scheduling module for scheduling the above-mentioned target task to the above-mentioned target processor; and a running module for running the above-mentioned target task on the above-mentioned target processor.

[0008] According to another aspect of an embodiment of the present invention, a non-volatile storage medium is further provided, wherein the non-volatile storage medium includes a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute any one of the multi-core processor task scheduling methods mentioned above.

[0009] According to another aspect of an embodiment of the present invention, a multi-core processor task scheduling device is also provided, including: a processor; and a memory, connected to the above-mentioned processor, for providing the above-mentioned processor with instructions for processing the following processing steps: obtaining a target task to be executed; selecting a target processor from a multi-core processor based on the attribute information of the above-mentioned target task, wherein the above-mentioned attribute information includes: binding relationship information and priority information, the above-mentioned binding relationship information is used to describe whether the above-mentioned target task needs to be run on a processor with a binding relationship, and the above-mentioned priority information is used to describe the priority of the above-mentioned target task; scheduling the above-mentioned target task to the above-mentioned target processor; and running the above-mentioned target task on the above-mentioned target processor.

[0010] In an embodiment of the present invention, a target task to be executed is obtained; a target processor is selected from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; the target task is scheduled to the target processor; and the target task is run on the target processor.

[0011] It is easy to notice that the embodiment of the present application treats all processors in a multi-core processor as a whole resource that can be used for unified scheduling. Based on the binding relationship information and priority information of the target task to be executed, the target processor is selected from the multi-core processor, and the target task is only scheduled to the target processor to run the target task on the target processor. As a result, the embodiment of the present application achieves the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of task scheduling times of the multi-core processor and improving the overall performance of the system, thereby solving the technical problem that the existing multi-core scheduling algorithm cannot accurately determine the target processor for running the task to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0013] Figure 1 A hardware structure block diagram of a computer terminal (or mobile device) for implementing a multi-core processor task scheduling method is shown;

[0014] Figure 2 is a flowchart of a multi-core processor task scheduling method according to an embodiment of the present invention;

[0015] Figure 3 is a flowchart of an optional multi-core processor task scheduling method according to an embodiment of the present invention;

[0016] Figure 4 This is a structural diagram of a multi-core processor task scheduling device according to an embodiment of the present application;

[0017] Figure 5 It is a structural block diagram of another computer terminal according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0019] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0020] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following interpretations:

[0021] Multi-core processor: refers to the integration of two or more complete computing engines (cores) in one processor. In this case, the processor can support multiple processors on the system bus, and all bus control signals and command signals are provided by the bus controller. Processors may include but are not limited to: central processing unit (CPU), graphics processing unit (GPU), digital signal processing (DSP) chip, microprocessor (MCU), programmable logic device (FPGA), neural network processor (NPU), tensor processing unit (TPU), artificial intelligence (AI) type processor and other processing devices. The optional embodiments mentioned below will be explained using the CPU as an example, but it does not constitute an undue limitation to this application, and these optional embodiments can also be applied to other types of processors.

[0022] Task scheduling: refers to the process of selecting target tasks to run on the processor.

[0023] Inter-core interrupt: refers to the processor currently running a task in a multi-core processor sending an interrupt signal to the target processor, triggering the program to execute task scheduling on the target processor.

[0024] Ready queue: refers to the queue of tasks waiting to be executed by the processor.

[0025] Task binding processor: means that a specified task only runs on a certain processor.

[0026] The first multi-processor task scheduling algorithm offered in the prior art typically has only a single global ready queue. Before executing a task, each CPU sends an inter-core interrupt to other CPUs, triggering the execution of the scheduler on those CPUs. Each time a task is scheduled, all CPUs must execute the scheduler. This approach has the following drawbacks: tasks may be frequently scheduled across multiple CPUs, increasing the number of unnecessary task scheduling attempts; and it fails to consider which core a new task previously ran on, resulting in poor CPU cache affinity.

[0027] The second multi-processor task scheduling algorithm provided in the prior art also has a global ready queue and adds a ready queue for core-bound tasks for each core. If the ready task is a core-bound task, only the corresponding CPU is selected. However, if it is bound to the current CPU, no inter-core interrupt is issued. If the ready task is not a core-bound task, all other cores other than the current core are selected. However, this algorithm has the following disadvantages: after an interrupt is issued to all other cores, all cores trigger a scheduling operation, which increases the number of unnecessary scheduling operations. The algorithm also does not consider which core the new task was previously running on, resulting in poor CPU cache affinity.

[0028] The third multi-processor task scheduling algorithm offered in the prior art assigns a ready task queue to each CPU, performing periodic load balancing. It also adds a task migration thread for migrating tasks between CPUs. However, this approach has the following drawbacks: Each CPU has a ready task queue, which can easily lead to task imbalance across CPUs, necessitating the implementation of an additional load balancing algorithm. Furthermore, supporting various complex CPU topologies increases code complexity.

[0029] From the above analysis, it can be seen that the multi-processor task scheduling algorithm provided in the prior art sends an inter-core interrupt to other CPUs when executing each scheduling, triggering other CPUs to execute the scheduling program together. Since task switching is uncontrollable, the problem of frequent task switching between different CPUs will occur, resulting in many unnecessary schedulings. At the same time, the CPU cache hit rate is low, affecting system performance.

[0030] In addition, the multi-processor task scheduling algorithm provided in the prior art is still unable to accurately determine which CPU the new task to be executed will run on. In order to solve the above technical problems, the inventors of this application provide a multi-core processor task scheduling method, which regards all CPUs in the multi-core processor as usable overall resources for unified scheduling, improves the affinity of the CPU cache, reduces the number of scheduling times and improves system performance. Compared with the above-mentioned Linux scheduling algorithm, the embodiment of this application is more concise and clear and is more suitable for Internet of Things (IOT) devices.

[0031] Example 1

[0032] According to an embodiment of the present invention, an embodiment of a multi-core processor task scheduling method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0033] The method embodiment provided in Example 1 of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 A hardware structure block diagram of a computer terminal (or mobile device) for implementing a multi-core processor task scheduling method is shown. Figure 1 As shown, the computer terminal 10 (or mobile device 10) may include one or more processors 102 (shown as 102a, 102b, ..., 102n in the figure), a memory 104 for storing data, and a transmission module 106 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply and / or a camera. It will be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0034] It should be noted that the one or more processors 102 and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry". The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. In addition, the data processing circuitry may be a single independent processing module, or may be incorporated in whole or in part into any of the other components of the computer terminal 10 (or mobile device). As described in the embodiments of the present application, the data processing circuitry serves as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0035] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the multi-core processor task scheduling method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned multi-core processor task scheduling method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0036] The transmission device 106 is configured to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by the communications provider of the computer terminal 10. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is configured to communicate with the Internet wirelessly.

[0037] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 (or mobile device).

[0038] Under the above operating environment, this application provides Figure 2 A multi-core processor task scheduling method is shown. Figure 2 FIG. 1 is a flow chart of a multi-core processor task scheduling method according to an embodiment of the present invention. Figure 2 As shown, the multi-core processor task scheduling method includes:

[0039] Step S202, obtaining the target task to be executed;

[0040] Step S204: selecting a target processor from the multi-core processors based on the attribute information of the target task, wherein the attribute information includes binding relationship information and priority information, wherein the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task;

[0041] Step S206, dispatching the target task to the target processor;

[0042] Step S208: running the target task on the target processor.

[0043] In an embodiment of the present invention, a target task to be executed is obtained; a target processor is selected from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; the target task is scheduled to the target processor; and the target task is run on the target processor.

[0044] It is easy to notice that the embodiment of the present application treats all processors in a multi-core processor as a whole resource that can be used for unified scheduling. Based on the binding relationship information and priority information of the target task to be executed, the target processor is selected from the multi-core processor, and the target task is only scheduled to the target processor to run the target task on the target processor. As a result, the embodiment of the present application achieves the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of task scheduling times of the multi-core processor and improving the overall performance of the system, thereby solving the technical problem that the existing multi-core scheduling algorithm cannot accurately determine the target processor for running the task to be executed.

[0045] It should be noted that the technical problem that the multi-core scheduling algorithm focuses on solving is to select the next target task to be run and determine the target processor for running the target task. The multi-core processor task scheduling method provided in the embodiment of the present application mainly solves the technical problem of how to accurately determine the target processor for running the target task.

[0046] In an embodiment of the present application, all processors in a multi-core processor can be regarded as a whole resource that can be used and scheduled uniformly. In a specific embodiment, by obtaining or selecting a target task to be executed, for example, a new task to be executed; determining the binding relationship information and priority information of the target task to be executed, selecting a target processor from the multi-core processor, and only scheduling the target task to the target processor to run the target task on the target processor.

[0047] Optionally, in an embodiment of the present application, it is first determined whether the target task needs to be run on a processor with a binding relationship based on the binding relationship information of the target task, and then it is determined which one or several processors in the multi-core processor have a binding relationship with the target task.

[0048] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0049] Step S302: determining, based on the binding relationship information, whether there is a first processor in the multi-core processor that has a binding relationship with the target task;

[0050] Step S304, comparing the priority of the target task with the priority of the current task on the first processor;

[0051] Step S306 : When the priority of the target task is higher than the priority of the current task and the first processor is the processor currently scheduling the target task, the first processor is determined as the target processor.

[0052] Optionally, in the embodiment of the present application, Figure 3 FIG. 1 is a flow chart of an optional multi-core processor task scheduling method according to an embodiment of the present invention. Figure 3 As shown, if it is determined based on the above-mentioned binding relationship information that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task, that is, it indicates that the target task (that is, the new task to be executed) has a binding relationship with the first processor, then the priority of the target task and the priority of the current task running on the first processor are compared; when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task, it is checked whether the first processor is the processor currently scheduling the above-mentioned target task. If the above-mentioned first processor is the processor currently scheduling the above-mentioned target task, the above-mentioned first processor is determined as the above-mentioned target processor, and the scheduler is executed on the first processor.

[0053] Optionally, in an embodiment of the present application, if the priority of the target task is lower than the priority of the current task running on the first processor, it indicates that the target task cannot preempt the first processor with a binding relationship, so there is no need to perform task scheduling.

[0054] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0055] Step S402: determining, based on the binding relationship information, whether there is a first processor in the multi-core processor that has a binding relationship with the target task;

[0056] Step S404: comparing the priority of the target task with the priority of the current task on the first processor;

[0057] Step S406, when the priority of the target task is higher than the priority of the current task and the first processor is not the processor currently scheduling the target task, an inter-core interrupt is sent to the first processor through the processor currently scheduling the target task, and the first processor is determined as the target processor.

[0058] Optionally, in an embodiment of the present application, if it is determined based on the above-mentioned binding relationship information that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task, that is, it indicates that the target task (that is, the new task to be executed) has a binding relationship with the first processor, then the priority of the target task is compared with the priority of the current task running on the first processor.

[0059] Still Figure 3 As shown, when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task, it is checked whether the first processor is the processor currently scheduling the above-mentioned target task. If the above-mentioned first processor is not the processor currently scheduling the above-mentioned target task, an inter-core interrupt is sent to the above-mentioned first processor through the processor currently scheduling the above-mentioned target task, the above-mentioned first processor is determined as the above-mentioned target processor, and the scheduling program is executed on the first processor.

[0060] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0061] Step S502: determining, based on the binding relationship information, that there is no first processor having a binding relationship with the target task;

[0062] Step S504, comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor;

[0063] Step S506: When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are the same, selecting a second processor from the multi-core processor that has previously run the target task;

[0064] Step S508: When the second processor is the processor currently scheduling the target task, the second processor is determined as the target processor.

[0065] Optionally, in the embodiment of the present application, Figure 3As shown, if it is determined based on the above binding relationship information that there is no first processor in the above multi-core processor that has a binding relationship with the above target task, that is, there is no processor in the multi-core processor that has a binding relationship with the target task (that is, the new task to be executed), then the priority of the target task is compared with the priority of the current task on each processor in the above multi-core processor.

[0066] When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor, it is checked whether the priorities of the current tasks on each processor in the multi-core processor are the same. If the priorities of the current tasks on each processor are the same, a second processor that has run the target task is selected from the multi-core processor, for example, the processor that ran the target task last time, the processor that ran the target task the day before last, and so on.

[0067] After selecting the above-mentioned second processor, it is detected whether the processor currently scheduling the above-mentioned target task is the above-mentioned second processor. If so, the above-mentioned second processor is determined as the above-mentioned target processor, and the scheduling program is executed on the second processor, which can significantly improve the affinity of the target task to the target processor in the multi-core processor.

[0068] Optionally, in an embodiment of the present application, if the priority of the above-mentioned target task is lower than the priority of the current task on each processor in the multi-core processor, it indicates that the target task cannot preempt the first processor with a binding relationship, so there is no need to perform task scheduling.

[0069] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0070] Step S602: determining, based on the binding relationship information, that there is no first processor having a binding relationship with the target task;

[0071] Step S604: comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor;

[0072] Step S606: When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are the same, selecting a second processor from the multi-core processor that has previously run the target task;

[0073] Step S608 : When the second processor is not the processor currently scheduling the target task, the processor currently scheduling the target task sends an inter-core interrupt to the second processor, and determines the second processor as the target processor.

[0074] Optionally, in an embodiment of the present application, if it is determined based on the above-mentioned binding relationship information that there is no first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task, that is, it indicates that there is no processor in the multi-core processor that has a binding relationship with the target task (that is, the new task to be executed), then the priority of the target task is compared with the priority of the current task on each processor in the above-mentioned multi-core processor.

[0075] When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor, it is checked whether the priorities of the current tasks on each processor in the multi-core processor are the same. If the priorities of the current tasks on each processor are the same, a second processor that has run the target task is selected from the multi-core processor, for example, the processor that ran the target task last time, the processor that ran the target task the day before last, and so on.

[0076] Still Figure 3 As shown, after selecting the above-mentioned second processor, it is detected whether the processor currently scheduling the above-mentioned target task is the above-mentioned second processor. If the above-mentioned second processor is not the processor currently scheduling the above-mentioned target task, an inter-core interrupt is sent to the above-mentioned second processor through the processor currently scheduling the above-mentioned target task, and the above-mentioned second processor is determined as the above-mentioned target processor. The scheduling program is executed on the second processor, which can significantly improve the affinity of the target task to the target processor in the multi-core processor.

[0077] Optionally, in an embodiment of the present application, a ready queue (i.e., a queue of tasks waiting to be executed by the CPU) can be pre-set for each processor in the multi-core processor, and load balancing operations can be performed periodically. Furthermore, by recording the identification information of the CPU where the target task last ran, the target task is likely to run on the same CPU next time, significantly improving the CPU cache hit rate.

[0078] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0079] Step S702: determining based on the binding relationship information that there is no first processor having a binding relationship with the target task;

[0080] Step S704, comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor;

[0081] Step S706: When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are different, selecting a third processor with the lowest priority of the current task from the multi-core processor;

[0082] Step S708: When the third processor is the processor currently scheduling the target task, the third processor is determined as the target processor.

[0083] Optionally, in an embodiment of the present application, if it is determined based on the above-mentioned binding relationship information that there is no first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task, that is, it indicates that there is no processor in the multi-core processor that has a binding relationship with the target task (that is, the new task to be executed), then the priority of the target task is compared with the priority of the current task on each processor in the above-mentioned multi-core processor.

[0084] Still Figure 3 As shown, when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor, it is checked whether the priority of the current task on each processor in the multi-core processor is the same. If the priority of the current task on each processor is different, the third processor with the lowest current task priority is selected from the above-mentioned multi-core processor.

[0085] After selecting the above-mentioned third processor, it is detected whether the processor currently scheduling the above-mentioned target task is the above-mentioned third processor. If so, the above-mentioned third processor is determined as the above-mentioned target processor, and the scheduling program is executed on the third processor, which can significantly improve the affinity of the target task to the target processor in the multi-core processor.

[0086] Optionally, in an embodiment of the present application, if the priority of the above-mentioned target task is lower than the priority of the current task on each processor in the multi-core processor, it indicates that the target task cannot preempt the first processor with a binding relationship, so there is no need to perform task scheduling.

[0087] In an optional embodiment, selecting the target processor from the multi-core processor based on the attribute information of the target task includes:

[0088] Step S802: determining, based on the binding relationship information, that there is no first processor having a binding relationship with the target task;

[0089] Step S804: comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor;

[0090] Step S806: When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are different, selecting a third processor with the lowest priority of the current task from the multi-core processor;

[0091] Step S808 : When the third processor is not the processor currently scheduling the target task, the processor currently scheduling the target task sends an inter-core interrupt to the third processor, and determines the third processor as the target processor.

[0092] Optionally, in an embodiment of the present application, if it is determined based on the above-mentioned binding relationship information that there is no first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task, that is, it indicates that there is no processor in the multi-core processor that has a binding relationship with the target task (that is, the new task to be executed), then the priority of the target task is compared with the priority of the current task on each processor in the above-mentioned multi-core processor.

[0093] Still Figure 3 As shown, when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor, it is checked whether the priority of the current task on each processor in the multi-core processor is the same. If the priority of the current task on each processor is different, the third processor with the lowest current task priority is selected from the above-mentioned multi-core processor.

[0094] After selecting the above-mentioned third processor, it is detected whether the processor currently scheduling the above-mentioned target task is the above-mentioned third processor. If the above-mentioned third processor is not the processor currently scheduling the above-mentioned target task, an inter-core interrupt is sent to the above-mentioned third processor through the processor currently scheduling the above-mentioned target task, and the above-mentioned third processor is determined as the above-mentioned target processor. The scheduling program is executed on the third processor, which can significantly improve the affinity of the target task to the target processor in the multi-core processor.

[0095] The present application scheme schedules multi-core CPUs as unified system resources, selects target processors based on the binding relationship information and priority information of the target tasks, and only schedules the CPUs that need to be scheduled, reducing the number of unnecessary scheduling times for other CPUs. This can improve the CPU cache hit rate, take into account load balancing, and improve the overall system performance.

[0096] It should be noted that for the aforementioned method embodiments, for simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0097] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a non-volatile storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the above methods of each embodiment of the present invention.

[0098] Example 2

[0099] According to an embodiment of the present application, there is also provided an embodiment of a device for implementing the above multi-core processor task scheduling method. Figure 4 FIG. 1 is a structural diagram of a multi-core processor task scheduling device according to an embodiment of the present application. Figure 4 As shown, the apparatus includes: an acquisition module 400, a selection module 402, a scheduling module 404 and an operation module 406, wherein:

[0100] An acquisition module 400 is used to acquire a target task to be executed; a selection module 402 is used to select a target processor from a multi-core processor based on the attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; a scheduling module 404 is used to schedule the target task to the target processor; and an operation module 406 is used to run the target task on the target processor.

[0101] In an embodiment of the present invention, a target task to be executed is obtained; a target processor is selected from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; the target task is scheduled to the target processor; and the target task is run on the target processor.

[0102] It is easy to notice that the embodiment of the present application treats all processors in a multi-core processor as a whole resource that can be used for unified scheduling. Based on the binding relationship information and priority information of the target task to be executed, the target processor is selected from the multi-core processor, and the target task is only scheduled to the target processor to run the target task on the target processor. As a result, the embodiment of the present application achieves the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of task scheduling times of the multi-core processor and improving the overall performance of the system, thereby solving the technical problem that the existing multi-core scheduling algorithm cannot accurately determine the target processor for running the task to be executed.

[0103] It should be noted that the acquisition module 400, selection module 402, scheduling module 404, and execution module 406 correspond to steps S202 to S208 in Example 1. The examples and application scenarios implemented by the four modules and the corresponding steps are the same, but are not limited to the contents disclosed in Example 1. It should be noted that the above modules, as part of the device, can be run in the computer terminal 10 provided in Example 1.

[0104] It should be noted that the preferred implementation of this embodiment can be found in the relevant description in Method Example 1, which will not be repeated here.

[0105] Example 3

[0106] According to an embodiment of the present application, an embodiment of a multi-core processor task scheduling device is also provided. The multi-core processor task scheduling device can be any computing device in a computing device group. The multi-core processor task scheduling device includes: a processor and a memory, wherein:

[0107] A processor; and a memory, connected to the above-mentioned processor, used to provide the above-mentioned processor with instructions for processing the following processing steps: obtaining a target task to be executed; selecting a target processor from a multi-core processor based on attribute information of the above-mentioned target task, wherein the above-mentioned attribute information includes: binding relationship information and priority information, the above-mentioned binding relationship information is used to describe whether the above-mentioned target task needs to be run on a processor with a binding relationship, and the above-mentioned priority information is used to describe the priority of the above-mentioned target task; scheduling the above-mentioned target task to the above-mentioned target processor; and running the above-mentioned target task on the above-mentioned target processor.

[0108] In an embodiment of the present invention, a target task to be executed is obtained; a target processor is selected from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; the target task is scheduled to the target processor; and the target task is run on the target processor.

[0109] It is easy to notice that the embodiment of the present application treats all processors in a multi-core processor as a whole resource that can be used for unified scheduling. Based on the binding relationship information and priority information of the target task to be executed, the target processor is selected from the multi-core processor, and the target task is only scheduled to the target processor to run the target task on the target processor. As a result, the embodiment of the present application achieves the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of task scheduling times of the multi-core processor and improving the overall performance of the system, thereby solving the technical problem that the existing multi-core scheduling algorithm cannot accurately determine the target processor for running the task to be executed.

[0110] It should be noted that the preferred implementation of this embodiment can be found in the relevant description in Example 1 and will not be repeated here.

[0111] Example 4

[0112] According to an embodiment of the present application, a computer terminal embodiment is also provided, which can be any computer terminal device in a computer terminal group. Optionally, in this embodiment, the computer terminal can also be replaced by a terminal device such as a mobile terminal.

[0113] Optionally, in this embodiment, the computer terminal may be located in at least one network device among a plurality of network devices of a computer network.

[0114] In this embodiment, the above-mentioned computer terminal can execute the program code of the following steps in the multi-core processor task scheduling method: obtaining the target task to be executed; selecting the target processor from the multi-core processor based on the attribute information of the above-mentioned target task, wherein the above-mentioned attribute information includes: binding relationship information and priority information, the above-mentioned binding relationship information is used to describe whether the above-mentioned target task needs to be run on a processor with a binding relationship, and the above-mentioned priority information is used to describe the priority of the above-mentioned target task; scheduling the above-mentioned target task to the above-mentioned target processor; and running the above-mentioned target task on the above-mentioned target processor.

[0115] Optionally, Figure 5 is a structural block diagram of another computer terminal according to an embodiment of the present application, such as Figure 5 As shown, the computer terminal may include: one or more (only one is shown in the figure) processors 502 , a memory 504 , and a peripheral interface 506 .

[0116] Among them, the memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the multi-core processor task scheduling method and device in the embodiment of the present invention. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, realizing the above-mentioned multi-core processor task scheduling method. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely located relative to the processor, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include but are not limited to the Internet, corporate intranet, local area network, mobile communication network and combinations thereof.

[0117] The processor can call the information and application stored in the memory through the transmission device to perform the following steps: obtain the target task to be executed; select the target processor from the multi-core processor based on the attribute information of the above target task, wherein the above attribute information includes: binding relationship information and priority information, the above binding relationship information is used to describe whether the above target task needs to be run on a processor with a binding relationship, and the above priority information is used to describe the priority of the above target task; schedule the above target task to the above target processor; and run the above target task on the above target processor.

[0118] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on the above-mentioned first processor; when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task and the above-mentioned first processor is the processor currently scheduling the above-mentioned target task, determine the above-mentioned first processor as the above-mentioned target processor.

[0119] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on the above-mentioned first processor; when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task and the above-mentioned first processor is not the processor currently scheduling the above-mentioned target task, send an inter-core interrupt to the above-mentioned first processor through the processor currently scheduling the above-mentioned target task, and determine the above-mentioned first processor as the above-mentioned target processor.

[0120] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is no first processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is the same, select a second processor from the above-mentioned multi-core processor that has run the above-mentioned target task; when the above-mentioned second processor is the processor currently scheduling the above-mentioned target task, determine the above-mentioned second processor as the above-mentioned target processor.

[0121] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is no first processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is the same, select a second processor from the above-mentioned multi-core processor that has run the above-mentioned target task; when the above-mentioned second processor is not the processor currently scheduling the above-mentioned target task, send an inter-core interrupt to the above-mentioned second processor through the processor currently scheduling the above-mentioned target task, and determine the above-mentioned second processor as the above-mentioned target processor.

[0122] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is no first processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is different, select the third processor with the lowest current task priority from the above-mentioned multi-core processor; when the above-mentioned third processor is the processor currently scheduling the above-mentioned target task, determine the above-mentioned third processor as the above-mentioned target processor.

[0123] Optionally, the above-mentioned processor can also execute the program code of the following steps: based on the above-mentioned binding relationship information, determine that there is no first processor that has a binding relationship with the above-mentioned target task; compare the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is different, select a third processor with the lowest current task priority from the above-mentioned multi-core processor; when the above-mentioned third processor is not the processor currently scheduling the above-mentioned target task, send an inter-core interrupt to the above-mentioned third processor through the processor currently scheduling the above-mentioned target task, and determine the above-mentioned third processor as the above-mentioned target processor.

[0124] An embodiment of the present invention provides a method for scheduling tasks on a multi-core processor. The method comprises obtaining a target task to be executed; selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information includes binding relationship information and priority information, the binding relationship information being used to describe whether the target task needs to be executed on a processor with a binding relationship, and the priority information being used to describe the priority of the target task; scheduling the target task to the target processor; and executing the target task on the target processor.

[0125] It is easy to notice that the embodiment of the present application treats all processors in a multi-core processor as a whole resource that can be used for unified scheduling. Based on the binding relationship information and priority information of the target task to be executed, the target processor is selected from the multi-core processor, and the target task is only scheduled to the target processor to run the target task on the target processor. As a result, the embodiment of the present application achieves the purpose of accurately determining the target processor for running the task to be executed, thereby achieving the technical effect of reducing the number of task scheduling times of the multi-core processor and improving the overall performance of the system, thereby solving the technical problem that the existing multi-core scheduling algorithm cannot accurately determine the target processor for running the task to be executed.

[0126] It can be understood by those skilled in the art that Figure 5 The structure shown is for illustration only, and the computer terminal may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a handheld computer, a mobile Internet device (MID), a PAD, or other terminal devices. Figure 5 It does not limit the structure of the above electronic device. For example, the computer terminal may also include Figure 5 More or fewer components (such as network interfaces, display devices, etc.) shown in, or with Figure 5 Different configurations shown.

[0127] A person skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable non-volatile storage medium. The non-volatile storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0128] Example 5

[0129] According to an embodiment of the present application, an embodiment of a non-volatile storage medium is also provided. Optionally, in this embodiment, the non-volatile storage medium can be used to store the program code executed by the multi-core processor task scheduling method provided in the above embodiment 1.

[0130] Optionally, in this embodiment, the non-volatile storage medium may be located in any computer terminal in a computer terminal group in a computer network, or in any mobile terminal in a mobile terminal group.

[0131] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for performing the following steps: obtaining a target task to be executed; selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task; scheduling the target task to the target processor; and running the target task on the target processor.

[0132] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: determining, based on the above-mentioned binding relationship information, that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on the above-mentioned first processor; when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task and the above-mentioned first processor is the processor currently scheduling the above-mentioned target task, determining the above-mentioned first processor as the above-mentioned target processor.

[0133] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: determining, based on the above-mentioned binding relationship information, that there is a first processor in the above-mentioned multi-core processor that has a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on the above-mentioned first processor; when the priority of the above-mentioned target task is higher than the priority of the above-mentioned current task and the above-mentioned first processor is not the processor currently scheduling the above-mentioned target task, sending an inter-core interrupt to the above-mentioned first processor through the processor currently scheduling the above-mentioned target task, and determining the above-mentioned first processor as the above-mentioned target processor.

[0134] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: based on the above-mentioned binding relationship information, determining that there is no first processor having a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is the same, selecting a second processor from the above-mentioned multi-core processor that has run the above-mentioned target task; when the above-mentioned second processor is the processor currently scheduling the above-mentioned target task, determining the above-mentioned second processor as the above-mentioned target processor.

[0135] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: determining based on the above-mentioned binding relationship information that there is no first processor having a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is the same, selecting a second processor from the above-mentioned multi-core processor that has run the above-mentioned target task; when the above-mentioned second processor is not the processor currently scheduling the above-mentioned target task, sending an inter-core interrupt to the above-mentioned second processor through the processor currently scheduling the above-mentioned target task, and determining the above-mentioned second processor as the above-mentioned target processor.

[0136] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: based on the above-mentioned binding relationship information, determining that there is no first processor having a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is different, selecting a third processor with the lowest priority of the current task from the above-mentioned multi-core processor; when the above-mentioned third processor is the processor currently scheduling the above-mentioned target task, determining the above-mentioned third processor as the above-mentioned target processor.

[0137] Optionally, in this embodiment, the non-volatile storage medium is configured to store program code for executing the following steps: determining based on the above-mentioned binding relationship information that there is no first processor having a binding relationship with the above-mentioned target task; comparing the priority of the above-mentioned target task with the priority of the current task on each processor in the above-mentioned multi-core processor; when the priority of the above-mentioned target task is higher than the priority of the current task on each processor in the above-mentioned multi-core processor and the priority of the current task on each processor in the above-mentioned multi-core processor is different, selecting a third processor with the lowest current task priority from the above-mentioned multi-core processor; when the above-mentioned third processor is not the processor currently scheduling the above-mentioned target task, sending an inter-core interrupt to the above-mentioned third processor through the processor currently scheduling the above-mentioned target task, and determining the above-mentioned third processor as the above-mentioned target processor.

[0138] The serial numbers of the above embodiments of the present invention are for description only and do not represent the advantages or disadvantages of the embodiments.

[0139] In the above embodiments of the present invention, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0140] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0141] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0142] In addition, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0143] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable non-volatile storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a non-volatile storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned non-volatile storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, and other media that can store program code.

[0144] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A multi-core processor task scheduling method, characterized in that: include: Get the target task to be executed; Selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information being used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information being used to describe a priority of the target task; Dispatching the target task to the target processor; Running the target task on the target processor; Among them, the selecting of the target processor from the multi-core processor based on the attribute information of the target task includes: determining that there is no first processor having a binding relationship with the target task based on the binding relationship information; comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor; when the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priority of the current task on each processor in the multi-core processor is the same, selecting a second processor from the multi-core processor that has run the target task as the target processor.

2. The multi-core processor task scheduling method according to claim 1, characterized in that: Selecting the target processor from the multi-core processor based on the attribute information of the target task includes: Determining, based on the binding relationship information, that there is a first processor in the multi-core processor that has a binding relationship with the target task; comparing the priority of the target task with the priority of the current task on the first processor; When the priority of the target task is higher than the priority of the current task and the first processor is the processor currently scheduling the target task, the first processor is determined as the target processor.

3. The multi-core processor task scheduling method according to claim 1, characterized in that: Selecting the target processor from the multi-core processor based on the attribute information of the target task includes: Determining, based on the binding relationship information, that there is a first processor in the multi-core processor that has a binding relationship with the target task; comparing the priority of the target task with the priority of the current task on the first processor; When the priority of the target task is higher than the priority of the current task and the first processor is not the processor currently scheduling the target task, an inter-core interrupt is sent to the first processor by the processor currently scheduling the target task, and the first processor is determined as the target processor.

4. The multi-core processor task scheduling method according to claim 1, characterized in that: The selecting a second processor that has run the target task from the multi-core processor as the target processor includes: When the second processor is the processor currently scheduling the target task, the second processor is determined as the target processor.

5. The multi-core processor task scheduling method according to claim 1, characterized in that: The selecting a second processor that has run the target task from the multi-core processor as the target processor includes: When the second processor is not the processor currently scheduling the target task, the processor currently scheduling the target task sends an inter-core interrupt to the second processor, and the second processor is determined as the target processor.

6. The multi-core processor task scheduling method according to claim 1, characterized in that: Selecting the target processor from the multi-core processor based on the attribute information of the target task includes: Determining based on the binding relationship information that there is no first processor having a binding relationship with the target task; Comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor; When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are different, selecting a third processor with the lowest priority of the current task from the multi-core processor; When the third processor is the processor currently scheduling the target task, the third processor is determined as the target processor.

7. The multi-core processor task scheduling method according to claim 1, characterized in that: Selecting the target processor from the multi-core processor based on the attribute information of the target task includes: Determining based on the binding relationship information that there is no first processor having a binding relationship with the target task; Comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor; When the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are different, selecting a third processor with the lowest priority of the current task from the multi-core processor; When the third processor is not the processor currently scheduling the target task, the processor currently scheduling the target task sends an inter-core interrupt to the third processor, and the third processor is determined as the target processor.

8. A multi-core processor task scheduling device, characterized in that: include: The acquisition module is used to obtain the target task to be executed; A selection module is used to select a target processor from a multi-core processor based on the attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information is used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information is used to describe the priority of the target task. The selection of the target processor from the multi-core processor based on the attribute information of the target task includes: determining based on the binding relationship information that there is no first processor with a binding relationship with the target task; comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor; when the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priorities of the current tasks on each processor in the multi-core processor are the same, selecting a second processor from the multi-core processor that has run the target task as the target processor; A scheduling module, configured to schedule the target task to the target processor; A running module is used to run the target task on the target processor.

9. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored program, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the multi-core processor task scheduling method according to any one of claims 1 to 7.

10. A multi-core processor task scheduling device, characterized in that: include: processor; as well as A memory, connected to the processor, configured to provide the processor with instructions for processing the following processing steps: Get the target task to be executed; Selecting a target processor from a multi-core processor based on attribute information of the target task, wherein the attribute information includes: binding relationship information and priority information, the binding relationship information being used to describe whether the target task needs to be run on a processor with a binding relationship, and the priority information being used to describe a priority of the target task; Dispatching the target task to the target processor; Running the target task on the target processor; Among them, the selecting of the target processor from the multi-core processor based on the attribute information of the target task includes: determining that there is no first processor having a binding relationship with the target task based on the binding relationship information; comparing the priority of the target task with the priority of the current task on each processor in the multi-core processor; when the priority of the target task is higher than the priority of the current task on each processor in the multi-core processor and the priority of the current task on each processor in the multi-core processor is the same, selecting a second processor from the multi-core processor that has run the target task as the target processor.

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