An abnormality detection device based on the mechanism of the cerebral neocortex

Abstract

The present invention relates to the field of data anomaly detection technology, specifically an anomaly detection device based on the cerebral neocortex mechanism. The anomaly detection device comprises a multi-core controller, a cortical column component, and a neuron component, and is connected to a PC motherboard via a PCIe interface. The present invention is a computer accessory that uses a PCIe interface to connect to a computer and access various data through a network to perform anomaly detection. This device is a general anomaly detection device that can be used in equipment operation and maintenance, alarms, and other application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of data anomaly detection, and in particular to an anomaly detection device based on the mechanism of the cerebral neocortex. Background Art

[0002] Detecting anomalies in various data types is a critical task in maintaining various business operations. However, existing anomaly detection technologies typically utilize machine learning algorithms (such as ES, MA, ARIMA, and SVM) or deep learning algorithms (such as LSTM-AD and LSTM-ED). These methods have significant drawbacks. For example, machine learning solutions suffer from low accuracy and poor robustness, making them suitable only for specific scenarios. Deep learning solutions are complex to train, requiring extensive data training, large models, and high computing power. This leads to high costs and makes implementation difficult using inexpensive embedded hardware. Summary of the Invention

[0003] The purpose of the present invention is to provide an abnormality detection device based on the cerebral neocortex mechanism to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] An anomaly detection device based on the cerebral neocortex mechanism includes a multi-core controller, a cortical column component, and a neuron component. The anomaly detection device is connected to a PC motherboard via a PCIe interface.

[0006] Furthermore, the multi-core controller includes an instruction register, a register, a counting register and a decoding register,

[0007] The output terminals of the counting register and the register are both connected to the second input terminal of the first data selector,

[0008] The output terminal of the instruction register is connected to the first input terminal of the first data selector,

[0009] The output terminal of the decoding register is connected to the input terminal of the second data selector,

[0010] The two output terminals of the second data selector are respectively connected to the data input terminal of the bit overlap array and the bit data input terminal of the winning neuron storage component.

[0011] The data output terminals of the bit overlapping array are linked to the input terminals of the sorting component,

[0012] The output terminal of the sorting component is connected to the bit data input terminal of the winning cortical column storage component,

[0013] The data output terminal of the winning cortical column storage component is connected to the fourth input terminal of the first data selector,

[0014] The data output terminal of the winning neuron storage component is connected to the third input terminal of the first data selector,

[0015] The bit data input terminals of the winning neuron storage component and the bit overlap array are respectively connected to the two output terminals of the second data selector.

[0016] The output terminal of the second data selector is linked to the input terminal of the cortical column data.

[0017] Further, the cortical column assembly includes a main bus,

[0018] The main bus output terminal is connected to the second input terminal and the third input terminal of the first data selector,

[0019] The fourth input terminal of the first data selector is connected to the input terminal of the first synaptic permanent value register.

[0020] The output terminal of the first data selector is connected to the bit data input terminal of the partition 1 part of the 64-byte memory, and the output terminal of the first data selector is also output to the neuron.

[0021] The data output terminal of the partition 2 of the 64-byte memory is connected to the input terminal of the third data selector.

[0022] The first output terminal of the third data selector is connected to the input terminal of the second synaptic permanent value register.

[0023] The second output terminal of the third data selector is connected to the input terminal of the synaptic address register.

[0024] The third and fourth output terminals of the third data selector are commonly connected to the input terminal of the activation address 8-bit register.

[0025] The output terminal of the synaptic address register is linked to the input terminal of the activation address 8-bit register through the first data distributor,

[0026] The activation address 8-bit register is linked to the overlap count register through a logic operation.

[0027] The second synaptic permanent value register is linked to the second data distributor,

[0028] The first output terminal of the second data distributor is linked to the input terminal of the overlap count register through a sorting operation.

[0029] The second output terminal of the second data distributor outputs data through an inversion operation, and the inversion operation output data is linked to the first input terminal of the first data selector linked to the partition 1 part of the 64-byte memory.

[0030] The information carried by the overlap count register and the neuron is linked to the pipeline register through the first data selector, and the output terminal of the pipeline register is linked to the multi-core controller.

[0031] Furthermore, the 64-byte memory also includes a partition 3 part, and the partition 3 part is linked to a counting register, and the counting register is respectively linked to four input terminals of an address counting register, a synaptic permanent value counting register, a bit register and a synaptic address register through a first data selector.

[0032] Furthermore, the neuronal assembly includes multi-phase information of multiple cortical columns,

[0033] The multi-phase information of the plurality of cortical columns is linked to the neuronal time series storage through logical operations,

[0034] The neuron time series storage interactive link controller,

[0035] Each unit of the controller is connected to the neuron time series storage at the previous moment from the input terminal of the decoding register.

[0036] Furthermore, the neuron component also includes an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition, and the multi-phase information of the multiple cortical columns is also linked to the controller through the cortical column status register.

[0037] Furthermore, the amplification processing module includes a synaptic permanent value register and a neuron register. The synaptic permanent value register is linked to the counting register through a sorting operation with a defined threshold.

[0038] The output terminal of the counting register is linked to the learning channel, and the output terminal of the neuron register is linked to the learning channel.

[0039] The output terminals of the learning channels are linked to cortical columns.

[0040] Furthermore, the learning processing module includes a segment register, a segment update register and a synaptic permanent value register.

[0041] The segment register and the segment update register are output to the controller and the synaptic comparison vector register through a sorting operation.

[0042] Furthermore, the prediction processing module includes a current value register and a segment register,

[0043] The previous value register and the segment register are linked to the count register through logical operation.

[0044] The counting register is linked to each cell of the neuron state register by a sorting operation with a defined threshold,

[0045] The identifier of each cell of the neuron state register includes a learning state flag and a neuron state.

[0046] Furthermore, the segment storage partition is divided into a segment update storage partition, a previous content storage partition and a permanent value storage partition.

[0047] The previous content storage partition is respectively linked to the segment permanent value address register, the segment address register, the segment update address register and the previous segment address register via a first data selector;

[0048] The output terminal of the first data selector is linked to the bit data input terminal of the segment storage partition.

[0049] The first input terminal of the first data selector is connected to the initial synaptic permanent value register,

[0050] The second input terminal of the first data selector links the multi-phase information of the plurality of cortical columns and the multi-phase information of the plurality of cortical columns is also linked to the controller through a logic operation output.

[0051] The third input terminal of the first data selector is connected to the synaptic comparison vector register and the synaptic permanent value register in the learning processing module.

[0052] The fourth input terminal of the first data selector is connected to the memory buffer register;

[0053] The permanent value storage partition outputs the link memory buffer register, the synaptic permanent value register in the amplification processing module, the segment register in the prediction processing module, the neuron register in the amplification processing module, the synaptic permanent value register in the learning processing module, the segment register in the learning processing module, the current value register in the prediction processing module, and the segment update register in the learning processing module through the data output of the fourth data selector.

[0054] Compared with the existing technology, the beneficial effects of the present invention are: the present invention is essentially a smart hardware card with a PCIe interface, which is a hardware and software integrated device, similar to FPGA. Some functions are completed by hardware, and some functions can be implemented programmably. The entire device is presented as a hardware device, which is plug-and-play. However, data input and result return are performed through SDK, which can realize a general algorithm for various types of data anomaly detection. It can perform anomaly detection for various types of services according to different input data, such as: sensor type, human behavior type, and vehicle trajectory type.

[0055] The present invention implements the algorithm in hardware by designing a device based on a spatiotemporal anomaly detection algorithm that simulates the cognitive system mechanism of part of the human brain's neocortex. The design has high prediction accuracy, effectively suppresses noise in real-time data, enables continuous learning, and continuously enhances its adaptability to scenarios. It requires a small amount of training data, has fast hardware computing speed, and is universal in all scenarios. Compared with the commonly used GPU card implementation method, it has a low cost to implement similar functions and does not require the development of anomaly detection software. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is the RTL design diagram of the multi-core main controller in the present invention;

[0057] Figure 2 It is the RTL representation design diagram of the cortical column in the present invention;

[0058] Figure 3 This is the design diagram of the neuron RTL representation in the present invention.

[0059] In the figure: PRG: instruction register, Register: register, Counter: counter register, Decoder: decoding register; DMUX: data distributor (1-to-2 DMUX is the second data distributor); Overlap Array: bit overlap array; Din: bit data input; Dout: data output; en: data input; Winning cells RAM: winning neuron storage component; Sorting Unit: sorting component; Winning Col. RAM: Winning cortical column storage component; MainBus: Main bus PipelineRegister: Pipeline register; OverlapCNT: Overlap count register; ActiAddr (8-bit): Activation address 8-bit register; SynpAddr: Synapse address register; PermV: Second synapse permanent value register (used for cortical column permanent value information storage); PermTh: Synapse permanent value threshold input; RAM (64 bytes): 64 bytes memory; CNT: Count register; AddrCNT: Address count register; PermCNT: Synapse permanent value count register; InBITCNT: Bit register; SynpAddr [7:3]: Synapse address register; MUX: Data selector; Initial.Perm.: Initial synapse permanent value register; CellsTimeLine: Neuron time series storage; Cells Status Register: Neuron status register; Burst_Block: Amplification processing module; Learning_Block: Learning processing module; Prediction_Block: Prediction processing module; Segment: Segment register; Counter: Count register; Current: Current value register; Ch_learn: Learning channel; SynpMatchVec: Synaptic comparison vector register; SynpPerm: Synaptic permanent value register; Cell / Segm.: Neuron register; Segm.Up.: Segment update register; M.Buffer: Memory buffer register; ColStatus: Cortical column status register; SegPermAddr: Segment permanent value address register; SegAddr: Segment address register; SegUpAddr: Segment update address register; PriorAddr: Previous segment address register; CNT: Count register; SegPartition: Segment storage partition; SegmentUp.Partition: Segment update storage partition; PriorMemPartition: Previous content storage partition; Permanence Partition: Permanent value storage partition, CCU: Communication Controller; Cell: Neuron; MCU: Multi-core Controller; CU: Controller; Learning Flag: Learning status flag; Cells Status: Neuron status flag; Column: Cortical column; First data selector: Data selector for 4 input terminals and 1 output terminal; Second data selector: Data selector for 1 input terminal and 2 output terminals; Third data selector: Data selector for 1 input terminal and 4 output terminals; Fourth data selector: Data selector for 1 input terminal and 8 output terminals; First data distributor: Data distributor for 1 input terminal and 8 output terminals; Second data distributor: Data distributor for 1 input terminal and 2 output terminals. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0061] See also Figure 1-3 , an anomaly detection device based on the brain's neocortex layer mechanism, the anomaly detection device includes a multi-core controller, a cortical column component and a neuron component, and the anomaly detection device is connected to the PC motherboard through a PCIe interface.

[0062] Specifically, the multi-core main controller is used to control and coordinate the calculations of the cortical column component and the neuron component; the anomaly detection device is composed of the multi-core controller, the cortical column component, and the neuron component, and anomaly detection is achieved through hardware. This device can communicate with other computer software and hardware by plugging into the PCIe interface of the PC motherboard.

[0063] Furthermore, the multi-core main controller is used to perform logical control of the entire system and schedule data.

[0064] See also Figure 1, an RTL representation of a multi-core controller obtained from an anomaly detection device based on the brain's neocortical layer mechanism, the multi-core controller includes an instruction register, a register, a counting register, and a decoding register, wherein the register stores the original input data from the acquisition encoder; the counting register is used to calculate the number of processing times, that is, the number of network layers; the decoding register receives the result data processed by the cortical column area of ​​the previous layer; the counting register and the register are combined into the same input terminal and connected to the second input terminal of the first data selector, the output of the instruction register is connected to the first input terminal of the first data selector, the decoding register is connected to the input terminal of a second data selector, and the two output terminals of the second data selector are respectively connected to the data input of the bit overlapping array and the bit data input terminal of the winning neuron storage component. The bit overlapping array is a storage component with corresponding identical values ​​in two arrays. The winning neuron storage component is used to store the information of the neurons that won the competition. The data output of the bit overlapping array is connected to the sorting component. The sorting component consists of a comparator and a register, compares and sorts the overlapping arrays, and selects the top 20%. The overlapping array is transmitted to the winning cortical column storage component, which is used to store the winning cortical column information. During the learning stage, the data will be transmitted to the cortical column component through MUX. The output of the sorting component is connected to the bit data input terminal of the winning cortical column storage component to store the neuron information that won the competition. The data output of the winning cortical column storage component is connected to the fourth input terminal of the first data selector, and the data output of the winning neuron storage component is connected to the third input terminal of the first data selector. The data inputs of the winning neuron storage component and the bit overlapping array are respectively connected to the two output terminals of a second data selector, and the input terminal of the second data selector is connected to the cortical column data.

[0065] Furthermore, the cortical column component mainly processes the competitive winning status of the cortical column and coordinates the control of neurons within the cortical column, communicating with neurons through the bus.

[0066] See also Figure 2The invention discloses an RTL representation of a cortical column component obtained by an abnormality detection device based on the mechanism of the cerebral neocortex layer. The cortical column component includes a main bus, which transmits addresses of various data, such as synaptic data address (SynpAddr) and winning address (WinnerAddr); the main bus output is connected to the second input terminal and the third input terminal of the first data selector, the fourth input terminal of the first data selector is connected to the synaptic permanent value register, one output terminal of the first data selector is connected to the bit data input terminal of the partition 1 part of the 64-byte memory and output to the neuron, the data output of the partition 2 part of the 64-byte memory is connected to a third data selector, the first output terminal of the third data selector is connected to the synaptic permanent value register, the second output terminal of the third data selector is connected to the synaptic address register, the synaptic address register stores the dendrite address, the third and fourth output terminals of the third data selector are commonly connected to the activation address 8-bit register, the activation address 8-bit register stores the activated cortical column address, and the synaptic address register is connected to the activation address 8 through a first data distributor. bit register, the activation address 8-bit register is linked to the overlap count register through a logic operation, the synaptic permanent value register stores the cortical column permanent value information, the synaptic permanent value register is linked to a second data distributor, the data distributor (1 input terminal and 2 output terminals) is used to distribute data to the bit overlap array storage component and the winner storage component; the first output terminal of the second data distributor is linked to the overlap count register through a sorting operation, the second output terminal of the second data distributor is linked to the first input terminal of the first data selector linked to the partition1 part of the 64-byte memory through a negation operation, the overlap count register and neuron information are both linked to the pipeline register through a first data selector, the pipeline register is used to store processing step information, the overlap count register stores the overlap count, and the pipeline register output is linked to the multi-core controller.

[0067] Furthermore, the 64-byte memory includes partition 3, which is linked to a counter register. The counter register is linked to four input terminals: an address counter register, a synapse permanent value counter register, a bit register, and a synapse address register, via a first data selector. It should be noted that the three partitions of the 64-byte memory respectively store the synapse permanent value, the synapse address in the input space, and the winner's address (Active Bits / WinnersAddr).

[0068] See also Figure 3, an RTL representation of a neuron component obtained by an anomaly detection device based on the mechanism of the cerebral neocortex layer, the neuron component includes multi-phase information of multiple cortical columns, the multi-phase information of multiple cortical columns is linked to the neuron time series storage through logical operation output, the neuron time series storage is interactively linked to the controller, each unit of the controller is linked to the neuron time series storage at the previous moment from the decoding register input, the neuron component also includes an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition, and the cortical column information is also linked to the controller through a cortical column status register.

[0069] Specifically, the previous moment refers to the discrete timing sequence t corresponding to moment t-1, t-1 corresponding to moment t-2, and so on.

[0070] Furthermore, an RTL representation of a neuron component obtained by an anomaly detection device based on the mechanism of the cerebral neocortex layer is provided, wherein the amplification processing module includes a synaptic permanent value register and a neuron register, the synaptic permanent value register is linked to the counting register through a sorting operation with a limited threshold, the counting register output is linked to a learning channel, the neuron register is also output to the learning channel, and the learning channel outputs to the cortical column; the learning processing module includes a segment register, a segment update register and a synaptic permanent value register, the segment register and the segment update register are output to the controller and the synaptic comparison vector register through a sorting operation; the prediction processing module includes a current value register and a segment register, the previous value register and the segment register are linked to the counting register through a logical operation output, the counting register is linked to each cell of the neuron state register through a sorting operation with a limited threshold, and the identifiers of each cell of the neuron state register include a learning state flag and a neuron state.

[0071] It is further explained that the neuron status register is used to store the status of the neuron, and the learning status flag (Learning Flag) and neuron status (Cells Status) indicate whether the neuron is in the active, inactive, or prediction state.

[0072] Furthermore, an RTL representation of a neuron component obtained by an anomaly detection device based on a cerebral neocortical layer mechanism, wherein a segment storage partition is divided into a segment update storage partition, a previous content storage partition, and a permanent value storage partition, and the previous content storage partition is respectively linked to a segment permanent value address register, a segment address register, a segment update address register, and a previous segment address register via a first data selector;

[0073] The segment storage partition is connected to the bit data input terminal of the segment storage partition via an output terminal of a first data selector, the first input terminal of the first data selector is connected to the initial synaptic permanent value register, the second input terminal of the first data selector is connected to the information of the cortical column, and the information of the cortical column is also connected to the controller through a logic transport output, the third input terminal of the first data selector is connected to the sorting transport result of the synaptic comparison vector register and the synaptic permanent value register in the learning processing module, and the fourth input terminal of the first data selector is connected to the memory buffer register;

[0074] The permanent value storage partition outputs the data of the permanent value storage partition through a fourth data selector to respectively output the link memory buffer register, the synaptic permanent value register in the amplification processing module, the segment register in the prediction processing module, the neuron register in the amplification processing module, the synaptic permanent value register in the learning processing module, the segment register in the learning processing module, the current value register in the prediction processing module, and the segment update register in the learning processing module.

[0075] Furthermore, the neuron component primarily handles neuron activation, learning state transitions, and neuron excitation and inhibition. The system is initially initialized by the value of the initial synaptic permanent value register. After initialization, the neurons are in the idle state. When a cortical column is activated, the column notifies the neurons. Upon receiving the notification, the neurons in the predicted state within the column are selected as input representations. If no neurons in the column are activated, all neurons are activated, and bursting is performed. The comparison is performed based on the previous information stored in the neuron's time series. If a neuron in the predicted state exists in the column, the neuron is activated. If a neuron in the column is in the learning state, the neuron is updated to the learning state. If no neurons in the predicted state exist, all neurons are updated to the activated state. The neuron with the best match is then selected as the input to the burst processing module (Burst_Block). The address of the activated neuron is then transferred from the prior content storage partition (PriorMemPartition) to the segment update storage partition (SegmentUp.Partition) via the memory buffer register (M.Buffer). The number of activated neurons in the cortical column is then transmitted to the multicore main controller (MCU) via the Cortical Column component's PipelineRegister. The MCU then updates the distribution of activated neurons. If the selected neuron is a winner, a new segment storage is created. If it is not a winner, and the neuron is inactive but has an active segment, the prediction block (Prediction_Block) is triggered. The prediction block compares the segment register with the current register. If the match is greater than 50%, the neuron is updated to the predicted state. Otherwise, the current state is checked to see if it is the predicted state. If it is and is active, the synaptic permanent value is enhanced; otherwise, it is weakened and inhibited. This stage triggers the learning block (Learning_Block). This block compares the contents of the segment register (Segment) with the segment update register (Segm.Up.). If there is an address that matches the synaptic compare vector register (SynpMatchVec), the synaptic link is enhanced. Otherwise, the synaptic link is forwarded to the segment storage partition (SegmentPartition).

[0076] It should be noted that sorting operation refers to rearranging the input values ​​according to certain sorting rules, and then outputting them into a new input value sequence to enter another operation area; sorting operation with limited threshold refers to sorting the input values ​​within the threshold value, and then outputting them in sequence; logical operation refers to operating on the input values ​​through logical methods such as AND and NOT.

[0077] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention. Such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.

Claims

1. An anomaly detection device based on the neocortex mechanism, characterized by: The anomaly detection device includes a multi-core controller, a cortical column component and a neuron component, and the anomaly detection device is connected to a PC motherboard via a PCIe interface; The multi-core controller includes an instruction register, a register, a counter register and a decoding register, The output terminals of the counter register and the register are both connected to the second input terminal of the first data selector, The output terminal of the instruction register is connected to the first input terminal of the first data selector, The output terminal of the decoding register is connected to the input terminal of the second data selector, The two output terminals of the second data selector are respectively connected to the data input terminal of the bit overlap array and the bit data input terminal of the winning neuron storage component. The data output terminals of the bit overlapping array are linked to the input terminals of the sorting component, The output terminal of the sorting component is connected to the bit data input terminal of the winning cortical column storage component, The data output terminal of the winning cortical column storage component is connected to the fourth input terminal of the first data selector, The data output terminal of the winning neuron storage component is connected to the third input terminal of the first data selector, The bit data input terminals of the winning neuron storage component and the bit overlap array are respectively connected to the two output terminals of the second data selector. The output terminal of the second data selector is connected to the input terminal of the cortical column data; The cortical column assembly includes a main bus, The main bus output terminal is connected to the second input terminal and the third input terminal of the first data selector, The fourth input terminal of the first data selector is connected to the input terminal of the first synaptic permanent value register. The output terminal of the first data selector is connected to the bit data input terminal of the partition 1 part of the 64-byte memory, and the output terminal of the first data selector is also output to the neuron. The data output terminal of the partition 2 of the 64-byte memory is connected to the input terminal of the third data selector. The first output terminal of the third data selector is connected to the input terminal of the second synaptic permanent value register. The second output terminal of the third data selector is connected to the input terminal of the synaptic address register. The third and fourth output terminals of the third data selector are commonly connected to the input terminal of the activation address 8-bit register. The output terminal of the synaptic address register is linked to the input terminal of the activation address 8-bit register through the first data distributor, The activation address 8-bit register is linked to the overlap count register through a logic operation. The second synaptic permanent value register is linked to the second data distributor, The first output terminal of the second data distributor is linked to the input terminal of the overlap count register through a sorting operation. The second output terminal of the second data distributor outputs data through an inversion operation, and the inversion operation output data is linked to the first input terminal of the first data selector linked to the partition 1 part of the 64-byte memory. The information carried by the overlap count register and the neuron is linked to the pipeline register through the first data selector, and the output terminal of the pipeline register is linked to the multi-core controller.

2. The anomaly detection device based on the neocortex mechanism according to claim 1, characterized in that: The 64-byte memory further includes a partition 3 part, which is linked to a counting register. The counting register is linked to four input terminals of an address counting register, a synaptic permanent value counting register, a bit register and a synaptic address register through a first data selector.

3. The anomaly detection device based on the neocortex mechanism according to claim 1, characterized in that: The neuronal assembly comprises multiphasic information from multiple cortical columns, The multi-phase information of multiple cortical columns is linked to the neuronal time series storage through logical operations. The neuron time series storage interactive link controller, Each unit of the controller is connected to the neuron time series storage at the previous moment from the input terminal of the decoding register.

4. The anomaly detection device based on the neocortex mechanism according to claim 3, characterized in that: The neuron component further includes an amplification processing module, a learning processing module, a prediction processing module and a segment storage partition, and the multi-phase information of the plurality of cortical columns is also linked to the controller via a cortical column status register.

5. The anomaly detection device based on the neocortex mechanism according to claim 4, characterized in that: The amplification processing module includes a synaptic permanent value register and a neuron register. The synaptic permanent value register is linked to the counting register through a sorting operation with a defined threshold. The output terminal of the counting register is linked to the learning channel, and the output terminal of the neuron register is linked to the learning channel. The output terminals of the learning channels are linked to cortical columns.

6. The anomaly detection device based on the neocortex mechanism according to claim 4, characterized in that: The learning processing module includes a segment register, a segment update register and a synaptic permanent value register, The segment register and the segment update register are output to the controller and the synaptic comparison vector register through a sorting operation.

7. The anomaly detection device based on the neocortex mechanism according to claim 4, characterized in that: The prediction processing module includes a current value register and a segment register, The previous value register and the segment register are linked to the counter register through logical operation output. The counter register is linked to each cell of the neuron state register by a sorting operation with a defined threshold, The identifier of each cell of the neuron state register includes a learning state flag and a neuron state.

8. The anomaly detection device based on the neocortex mechanism according to claim 4, characterized in that: The segment storage partition is divided into a segment update storage partition, a previous content storage partition and a permanent value storage partition. The previous content storage partition is respectively linked to the segment permanent value address register, the segment address register, the segment update address register and the previous segment address register via a first data selector; The output terminal of the first data selector is linked to the bit data input terminal of the segment storage partition. The first input terminal of the first data selector is connected to the initial synaptic permanent value register, The second input terminal of the first data selector links the multi-phase information of the plurality of cortical columns and the multi-phase information of the plurality of cortical columns is also linked to the controller through a logic operation output. The third input terminal of the first data selector is connected to the synaptic comparison vector register and the synaptic permanent value register in the learning processing module. The fourth input terminal of the first data selector is connected to the memory buffer register; The permanent value storage partition outputs the link memory buffer register, the synaptic permanent value register in the amplification processing module, the segment register in the prediction processing module, the neuron register in the amplification processing module, the synaptic permanent value register in the learning processing module, the segment register in the learning processing module, the current value register in the prediction processing module, and the segment update register in the learning processing module through the data output of the fourth data selector.

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