A programmable memory built-in self-test method based on finite state machine

Abstract

The present invention relates to a programmable memory built-in self-test method based on a finite state machine, and the method is implemented by a programmable Mbist control module driven by three counters, an algorithm module, a comparison and analysis module, and a BRAM to be tested. In the present invention, the algorithm module integrates 8 test algorithms and generates characteristic signals according to the characteristics of each test algorithm, thereby improving the coverage of faults. Secondly, the programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters, thereby improving the flexibility of the test. The present invention provides a new programmable memory built-in self-test method based on a finite state machine, which replaces the conventional test method. When the test algorithm needs to be replaced, the proposed test method does not need to reset the Mbist circuit, effectively reducing manpower and configuration time, thereby reducing the test cost.

Description

Technical Field

[0001] The invention relates to an embedded memory testing technology, in particular to a programmable memory built-in self-test method based on a finite state machine. Background Art

[0002] With the advancement of semiconductor technology, embedded storage occupies most of the chip area in current SoC products and has become a key factor affecting the reliability of SoC chips. BRAM is one of the most commonly used IP cores. Testing BRAM plays an important role in the chip manufacturing process, so how to efficiently test the correctness of its functions is particularly important.

[0003] The common memory built-in self-test (Mbist) method is based on the FSM controller to fix a certain test algorithm into the chip. If a new algorithm needs to be implemented or an existing algorithm needs to be changed, the Mbist circuit design needs to be changed, so it has low flexibility. At present, many scholars have proposed a variety of BRAM test algorithms, but no matter which test algorithm is used, it cannot fully cover all faults. Any undetected fault will affect the reliability of the product. Therefore, it is necessary to design a programmable Mbist for SoC that can improve flexibility, have high fault coverage, and have low area overhead. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the problems of poor flexibility and low fault coverage of the common method of embedding BRAM in SoC type FPGA in the prior art, thereby providing a new built-in self-test method for programmable memory based on finite state machine.

[0005] To solve the above technical problems, the present invention provides a programmable memory built-in self-test method based on a finite state machine, the method is implemented by a programmable Mbist control module driven by three counters, an algorithm module, a comparison and analysis module and a BRAM to be tested, and comprises the following steps:

[0006] Step S1: The BRAM module to be tested sets the working state of the BRAM, and the algorithm module selects the first test algorithm according to the order of the test algorithms and generates a characteristic signal of the test algorithm;

[0007] Step S2: the programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters;

[0008] Step S3: After the first algorithm is executed, the test algorithm module generates a characteristic signal of the second test algorithm and starts testing the second test algorithm, and so on.

[0009] In one embodiment of the present invention, the algorithm module integrates multiple test algorithms and generates characteristic signals of the test algorithms according to the selected test algorithms; the programmable Mbist control module is driven by three counters and uses FSM to generate test vectors, addresses and various control signals; the comparison and analysis module compares whether the output vector of the memory is consistent with the reference vector generated by the programmable Mbist control module; the BRAM module to be tested can be set to different working states.

[0010] In one embodiment of the present invention, the algorithm module integrates eight test algorithms and generates characteristic signals according to the characteristics of each test algorithm, thereby improving the coverage of faults.

[0011] In one embodiment of the present invention, the programmable Mbist control module receives a characteristic signal of a test algorithm generated by an algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters, thereby improving the flexibility of the test.

[0012] In one embodiment of the present invention, the three counters are used to generate appropriate st, cant and addr; taking the March X algorithm (algorithm 0) as an example, the March X algorithm is selected from the algorithm module by setting cant to 0, including the following steps:

[0013] Step S1: Mbist_control is set to 1 to start the built-in self-test. Initially, the st value is 0, the N-st value is 0, the addr value is 0, and the cant value is 0;

[0014] Step S2: Therefore, to execute the ↑w0 March element, the FSM enters the w0 state, and operation w0 is completed at address 0;

[0015] Step S3: When operation w0 is completed at the first address location, N-st becomes 1, addr increases, and N-st is reset;

[0016] Step S4: After performing w0 operation on all address bits, the value of st is increased by 1;

[0017] Step S5: The value of st is 1, the FSM executes the ↑(r0,w1) March element, and the FSM enters the ↑(r0,w1) state.

[0018] In one embodiment of the present invention, the ↑(r0,w1) March element contains two operations, and the number of operations in the test element generated by the algorithm module is 2. These two operations must be completed at an address location, N-st will be set to 1, addr will increase, and the value of N-st will be reset; all its March elements are executed in the above manner; until the value of st reaches the maximum value of st generated by the algorithm module and N-st is set to 1, et will be set to 1, indicating the completion of a March algorithm, the cant value is increased from 0 to 1, and test algorithm 1 is selected in the algorithm module for execution, and so on.

[0019] In one embodiment of the present invention, the method is a BRAM testing method, which is applied to the testing of BRAM in other types of FPGAs.

[0020] The above-mentioned technical scheme of the present invention has the following advantages over the prior art: the programmable memory built-in self-test method based on a finite state machine described in the present invention improves fault coverage and flexibility through a programmable Mbist control module driven by three counters and an algorithm module integrating eight test algorithms; this method can accurately locate the fault position by testing the block memory, the fault detection rate is improved by 28.75%, and the problem of poor flexibility is also greatly improved; and when the test algorithm needs to be replaced, there is no need to reset the Mbist circuit, which effectively reduces manpower and configuration time and thus reduces testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0022] Figure 1 It is a structural diagram of a programmable Mbist circuit proposed by the present invention;

[0023] Figure 2 It is a block diagram of the programmable Mbist control module of the present invention;

[0024] Figure 3 It is the flow chart of the Mbist controller proposed by the present invention;

[0025] Figure 4 It is the fault location diagram of March X of the present invention;

[0026] Figure 5 This is the fault injection simulation interface diagram of the common Mbist test method;

[0027] Figure 6 This is a fault injection simulation interface diagram of the Mbist test method proposed in the present invention. DETAILED DESCRIPTION

[0028] This embodiment provides a new programmable memory built-in self-test method based on a finite state machine. The method integrates eight test algorithms through a programmable Mbist control module and an algorithm module driven by three counters to improve fault coverage and flexibility. Figure 1 As shown, the Mbist circuit takes Mbist_clk, Mbist_rst and Mbist_control signals as inputs to generate addresses, read and write control signals, test vectors, err_count, Mbist_done and Mbist_fial signals as outputs.

[0029] The programmable Mbist control module uses FSM to generate test vectors, addresses and various control signals, such as Figure 2 The purpose of the diagram is to achieve the transition between four states, namely r0, r1, w0 and w1. The transition between these states depends on four factors:

[0030] The first is the value of cant, which indicates the serial number of the test algorithm in Table 1; the second is st, which indicates M0-M5 in Table 1, used to execute the March elements specified in the test algorithm; the third is N-st, which indicates the completion signal of executing all operations in each March element; the fourth is et, which indicates that all March elements of a test algorithm execute the completion signal at all addresses of the memory, where the March algorithm table is shown in the following table:

[0031]

[0032] The three counters are used to generate appropriate st, cant and addr; taking the March X algorithm (algorithm 0) as an example, the March X algorithm is selected from the algorithm module by setting cant to 0, including the following steps:

[0033] Step S1: Mbist_control is set to 1 to start the built-in self-test. Initially, the st value is 0, the N-st value is 0, the addr value is 0, and the cant value is 0;

[0034] Step S2: Therefore, to execute the ↑w0 March element, the FSM enters the w0 state, and operation w0 is completed at address 0;

[0035] Step S3: When operation w0 is completed at the first address location, N-st becomes 1, addr increases, and N-st is reset;

[0036] Step S4: After performing w0 operation on all address bits, the value of st is increased by 1;

[0037] Step S5: The value of st is 1, the FSM executes the ↑(r0,w1) March element, and the FSM enters the ↑(r0,w1) state.

[0038] Furthermore, since this ↑(r0,w1) March element contains two operations, the number of operations in the test element generated by the algorithm module is 2. These two operations must be completed at an address location before N-st is set to 1, addr is increased, and the value of N-st is reset. Similarly, all March elements are executed in the above manner. Until the value of st reaches the maximum value of st generated by the algorithm module and N-st is set to 1, et will be set to 1, indicating the completion of a March algorithm, the cant value is increased from 0 to 1, and test algorithm 1 is selected in the algorithm module for execution, and so on.

[0039] The algorithm module determines the test algorithm to be executed according to the value of cant, generates the maximum value of st, and the number of operations and address execution direction required for each test element. The flowchart for implementing the 8 test algorithms is as follows Figure 2 As shown on the left, the specific flow chart of a single test algorithm is as follows Figure 2 Shown on the right.

[0040] The comparison analysis module takes the output vector of the memory and the reference vector generated by the FSM as input. If the reference vector and the output vector of the memory do not match, the Mbist_fial output given by the comparator unit will be 1 (high), indicating that there is a fault at the corresponding address location. And in order to facilitate the counting of the number of faults, a fault counter is designed at the output end of the comparator.

[0041] According to the proposed test method, the proposed circuit design is implemented by Verilog HDL language programming, and the 36*1024 BRAM is simulated and tested by the modelsim simulation tool. In order to verify the fault detection capability of the proposed programmable Mbist controller, a fixed "0" fault is injected into the "0101101001" address of the BRAM, and a write 1 operation is performed on all addresses. The simulation results of the March X test algorithm are shown in the figure. Figure 3 As shown, it shows that the fault can be accurately detected and located.

[0042] Furthermore, this paper conducts a set of comparative simulation experiments, using Verilog HDL language to artificially inject 32 faults when designing the BRAM to be tested, and then uses the proposed Mbist test method and the common Mbist test method to test the BRAM after the faults are injected. The simulation results of the common Mbist test method are shown in Figure 2. Figure 4As shown in Figure 2, the number of detected faults is 26, and the fault detection rate is 81.25%. The fault injection simulation of the proposed Mbist test method is shown in Figure 2. Figure 5 As shown, the number of faults detected is 32 and the fault detection rate is 100%.

[0043] Compared with the common Mbist test method, the present invention has the characteristics of higher fault coverage and higher flexibility, and the method can also be applied to the test of BRAM in other types of FPGA.

[0044] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A programmable memory built-in self-test method based on a finite state machine, the method is implemented by a programmable Mbist control module driven by three counters, an algorithm module, a comparison and analysis module and a BRAM to be tested, It is characterized in that The steps include: Step S1: The BRAM module to be tested sets the working state of the BRAM, and the algorithm module selects the first test algorithm according to the order of the test algorithms and generates a characteristic signal of the test algorithm; Step S2: the programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, address and control signal to test the BRAM under the control of three counters; Step S3: After the first algorithm is executed, the test algorithm module generates a characteristic signal of the second test algorithm, and starts testing the second test algorithm, and so on; The algorithm module integrates multiple test algorithms and generates a characteristic signal of the test algorithm according to the selected test algorithm; The programmable Mbist control module is driven by three counters and uses FSM to generate test vectors, addresses and various control signals; the comparison and analysis module compares whether the output vector of the memory is consistent with the reference vector generated by the programmable Mbist control module; the BRAM module to be tested can be set to different working states.

2. The programmable memory built-in self-test method based on a finite state machine according to claim 1, Features: The algorithm module integrates eight test algorithms and generates characteristic signals according to the characteristics of each test algorithm.

3. The programmable memory built-in self-test method based on a finite state machine according to claim 1, Features: The programmable Mbist control module receives the characteristic signal of the test algorithm generated by the algorithm module, and generates a test vector, an address and a control signal under the control of three counters to test the BRAM.

4. The programmable memory built-in self-test method based on a finite state machine according to claim 1, Features: The three counters are used to generate appropriate st, cant and addr; the March X algorithm is selected from the algorithm module by setting cant to 0, including the following steps: Step S1: Mbist_control is set to 1 to start the built-in self-test. Initially, the st value is 0, the N-st value is 0, the addr value is 0, and the cant value is 0; Step S2: Therefore, to execute the ↑w0 March element, the FSM enters the w0 state, and operation w0 is completed at address 0; Step S3: When operation w0 is completed at the first address location, N-st becomes 1, addr increases, and N-st is reset; Step S4: After performing w0 operation on all address bits, the value of st is increased by 1; Step S5: The value of st is 1, the FSM executes the ↑(r0,w1) March element, and the FSM enters the ↑(r0,w1) state.

5. The programmable memory built-in self-test method based on a finite state machine according to claim 4, Features: The ↑(r0,w1)March element contains two operations. The number of operations in the test element generated by the algorithm module is 2. These two operations must be completed at an address location before N-st is set to 1, addr is increased, and the value of N-st is reset; all March elements are executed in the above manner; until the value of st reaches the maximum value of st generated by the algorithm module and N-st is set to 1, et will be set to 1, indicating the completion of a March algorithm, the cant value is increased from 0 to 1, and test algorithm 1 is selected in the algorithm module for execution, and so on.

6. The programmable memory built-in self-test method based on a finite state machine according to claim 1, Features: The method is a BRAM testing method.

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