Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a pixel circuit, the pixel circuit comprising a driving module, a leakage suppression module, a first reset module and a compensation module; the first reset module and the compensation module are connected to the control end of the driving module through the leakage suppression module; the compensation module comprises a first submodule and a second submodule, and the second submodule is connected to the leakage suppression module through the first submodule; the leakage suppression module comprises an eighth transistor, the first submodule comprises a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are connected to the same signal line, the active layer of the eighth transistor and the active layer of the ninth transistor are connected through a first connecting part, and the first connecting part, the active layer of the eighth transistor and the active layer of the ninth transistor are located in the same film layer. According to the embodiment of the application, the problem of low-frequency flicker can be solved.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202110800273.4, filed on July 15, 2021, entitled “Pixel Circuit, Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0004] With the development of display technology, variable frequency drive technology is gradually being applied to display panels. For example, a higher refresh rate drive is used to drive the display of dynamic images (such as sports events or game scenes) to ensure the smoothness of the displayed image; a lower refresh rate drive is used to drive the display of slow-motion images or static images to reduce power consumption. In low frequency mode, the display panel is more prone to flickering. Summary of the Invention

[0005] This application provides a display panel and display device to solve the problem that the display panel is more prone to flickering in low-frequency mode.

[0006] In a first aspect, embodiments of this application provide a display panel, including a pixel circuit, the pixel circuit including a driving module, a leakage current suppression module, a first reset module, and a compensation module;

[0007] Both the first reset module and the compensation module are connected to the control terminal of the drive module through the leakage current suppression module. The compensation module includes a first sub-module and a second sub-module. The second sub-module is connected to the leakage current suppression module through the first sub-module.

[0008] The leakage current suppression module includes an eighth transistor, and the first sub-module includes a ninth transistor. The gates of the eighth transistor and the ninth transistor are connected to the same signal line. The active layer of the eighth transistor and the active layer of the ninth transistor are connected through a first connection portion, and the first connection portion, the active layer of the eighth transistor, and the active layer of the ninth transistor are located in the same film layer.

[0009] In one possible implementation of the first aspect, the first reset module includes a fourth transistor, the fourth transistor including a dual-gate transistor;

[0010] Preferably, the pixel circuit further includes a seventh transistor connected to the first electrode of the light-emitting element of the display panel;

[0011] The active layer of the seventh transistor in the pixel circuit of row i and column j is connected to the active layer of the fourth transistor in the pixel circuit of row i+1 and column j+1, where i and j are both positive integers greater than or equal to 1.

[0012] In one possible implementation of the first aspect, the display panel further includes a shift register, which includes cascaded light-emitting control circuitry.

[0013] The pixel circuit also includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power line and the first end block of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first electrode of the light-emitting element of the display panel.

[0014] The control terminals of the first and second light-emitting control modules are both connected to the light-emitting control signal line, and the signal line connected to the gates of the eighth and ninth transistors is the leakage control signal line.

[0015] Preferably, the signals on the light emission control signal line and the signals on the leakage current control signal line are opposite signals, and the light emission control signal line and the leakage current control signal line connected to the same row of pixel circuits are connected to the same light emission control circuit.

[0016] Preferably, the drive module includes a first transistor, and the first connection portion is located on the side of the leakage control signal line away from the first transistor;

[0017] Preferably, the eighth transistor is connected to the gate of the first transistor through the second connection portion, and the connection via between the eighth transistor and the second connection portion is located on the side of the leakage control signal line closer to the first transistor;

[0018] Preferably, the first connecting part is a semiconductor connecting part.

[0019] In one possible implementation of the first aspect, the ninth transistor includes a dual-gate transistor, and the first reset module includes a fourth transistor and a tenth transistor, with the fourth transistor connected to the leakage current suppression module via the tenth transistor.

[0020] Preferably, the active layer of the eighth transistor is located between the active layers of the ninth transistor and the tenth transistor, the active layers of the eighth transistor and the ninth transistor are connected by a first connection portion, and the active layers of the eighth transistor and the tenth transistor are connected by a third connection portion.

[0021] Preferably, the first connecting portion, the third connecting portion, the active layer of the eighth transistor, the active layer of the fourth transistor, and the active layer of the ninth transistor are located in the same film layer.

[0022] Preferably, both the first connecting portion and the third connecting portion are semiconductor connecting portions.

[0023] In one possible implementation of the first aspect, the gate of the fourth transistor is connected to the first scan signal line, and the gate of the tenth transistor is connected to the leakage control signal line.

[0024] Preferably, the leakage control signal line extends along a first direction, and the gates of the eighth transistor, the tenth transistor, and the ninth transistor are connected to the same leakage control signal line.

[0025] In one possible implementation of the first aspect, the operation of the pixel circuit includes a data frame and a hold frame, wherein the data frame includes a reset phase.

[0026] During the reset phase, both the fourth and tenth transistors are turned on;

[0027] During the hold frame, the tenth transistor is turned off.

[0028] Preferably, the gate of the fourth transistor is connected to the first scan signal line, and the gate of the tenth transistor is connected to the leakage control signal line.

[0029] In one possible implementation of the first aspect, the first reset module includes a fourth transistor, and the pixel circuit further includes a seventh transistor connected to a first electrode of the light-emitting element of the display panel.

[0030] The active layer of the seventh transistor in the pixel circuit of row i and column j is connected to the active layer of the fourth transistor in the pixel circuit of row i+1 and column j, where i and j are both positive integers greater than or equal to 1.

[0031] In one possible implementation of the first aspect, the driving module includes a first transistor, an eighth transistor is connected to the gate of the first transistor via a second connection portion, and a connection via between the eighth transistor and the second connection portion is located on the side of the leakage control signal line away from the first transistor.

[0032] Preferably, the first connection portion and the third connection portion are located on the side of the leakage control signal line closer to the first transistor.

[0033] In one possible implementation of the first aspect, the first terminal of the eighth transistor is connected to the control terminal of the driving module, the eighth transistor includes a dual-gate transistor, and the pixel circuit further includes a first capacitor and a second capacitor.

[0034] The first terminal of the first capacitor is connected to the dual-gate node of the eighth transistor, and the second terminal of the first capacitor is connected to the first power supply line or the reference signal line.

[0035] The first terminal of the second capacitor is connected to the second terminal of the eighth transistor, and the second terminal of the second capacitor is connected to the first power supply line or the reference signal line.

[0036] The capacitance of the first capacitor is 10F to 60F, and the capacitance of the second capacitor is 10F to 60F.

[0037] Preferably, the pixel circuit further includes a data writing module, a storage module, a first light-emitting control module, and a second light-emitting control module;

[0038] The data writing module is connected between the data signal line and the first end of the driving module, the storage module is connected between the control end of the driving module and the first power line, the first light-emitting control module is connected between the first power line and the first end block of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first electrode of the light-emitting element of the display panel.

[0039] Preferably, the driving module includes a first transistor, the data writing module includes a second transistor, the second sub-module includes a third transistor, the first reset module includes a fourth transistor, the first light-emitting control module includes a fifth transistor, and the second light-emitting control module includes a sixth transistor.

[0040] The gate of the fourth transistor is connected to the first scan signal line, the gates of the second and third transistors are both connected to the second scan signal line, the gates of the fifth and sixth transistors are both connected to the light emission control signal line, and the gates of the eighth and ninth transistors are both connected to the leakage control signal line.

[0041] Secondly, embodiments of this application provide a display device, including a display panel as described in any embodiment of the first aspect.

[0042] According to the display panel and display device provided in the embodiments of this application, by setting a leakage current suppression module between the first reset module and the compensation module and the control terminal of the driving module, the leakage current path of the control terminal of the driving module is reduced, so that there is only one leakage current path at the control terminal of the driving module. Compared with the case where there are multiple leakage current paths at the control terminal of the driving module, the potential of the control terminal of the driving module can be more stable, and the problem of flickering in the display panel can be improved. On the other hand, the first node and the second terminal of the driving module are not directly connected, but a compensation module is also provided. Compared with the direct connection between the first node and the second terminal of the driving module, the compensation module has a larger resistance, which can prevent the first node and the second terminal of the driving module from flickering during the light emission stage. The equal potentials prevent a large potential difference between the control terminal of the drive module and the first node, thus avoiding a large leakage current through the leakage current suppression module at the control terminal of the drive module. This further improves the stability of the control terminal potential of the drive module and further alleviates the flickering problem in the display panel. On the other hand, the active layers of the eighth and ninth transistors are connected by the first connection part, and the first connection part, the active layers of the eighth and ninth transistors are located on the same film layer. This allows for electrical connection between the leakage current suppression module and the first sub-module without the need for vias in the layout design. This reduces the number of vias in the layout design, thereby improving space utilization and facilitating the formation of a high-resolution display panel. Attached Figure Description

[0043] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0044] Figure 1 This illustration shows a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0045] Figure 2 Show Figure 1 A schematic diagram of a cross-sectional structure along the AA direction;

[0046] Figure 3 Show Figure 1 A schematic diagram of a cross-sectional structure along the BB direction;

[0047] Figure 4 This illustration shows a schematic diagram of the pixel circuit in a display panel according to an embodiment of this application;

[0048] Figure 5 This invention provides a schematic diagram of the structure of a pixel circuit in a display panel according to another embodiment of the present application.

[0049] Figure 6 This diagram illustrates the timing of a pixel circuit in a display panel according to an embodiment of this application.

[0050] Figure 7 This illustration shows a partial structural diagram of a display panel provided in one embodiment of the present application;

[0051] Figure 8 Show Figure 7 A schematic diagram of a cross-sectional structure along the CC direction;

[0052] Figure 9 A schematic diagram of a pixel circuit structure is shown as a comparative example;

[0053] Figure 10 A schematic diagram of the pixel circuit structure is shown as another comparative example;

[0054] Figure 11 A schematic diagram of the pixel circuit structure is shown as yet another comparative example;

[0055] Figure 12 A partial structural schematic diagram of a display panel in a comparative example is shown;

[0056] Figure 13 Show Figure 12 A schematic diagram of a cross-sectional structure along the DD direction;

[0057] Figure 14 This illustration shows a schematic diagram of the pixel circuit in a display panel according to another embodiment of the present application;

[0058] Figure 15 A partial structural schematic diagram of a display panel provided in another embodiment of this application is shown;

[0059] Figure 16 , Figure 17 This application provides schematic diagrams illustrating the structure of pixel circuits in a display panel according to further embodiments.

[0060] Figure 18 This illustration shows a partial structural diagram of a display panel provided in another embodiment of this application;

[0061] Figure 19 Show Figure 18 A schematic diagram of a cross-sectional structure along the EE direction;

[0062] Figure 20 This illustration shows a timing diagram of a pixel circuit in a display panel according to another embodiment of the present application;

[0063] Figure 21 This illustration shows a partial structural diagram of a display panel provided in another embodiment of this application;

[0064] Figure 22 This illustration shows a schematic diagram of the pixel circuit in a display panel according to another embodiment of the present application;

[0065] Figure 23 This is a schematic diagram of the structure of a display device provided in one embodiment of this application. Detailed Implementation

[0066] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0067] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0068] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0069] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0070] In the embodiments of this application, the term "connection" can refer to two components being directly connected, or it can refer to two components being connected via one or more other components.

[0071] In the embodiments of this application, the first node, the second node, the third node, and other nodes are defined only for the convenience of describing the circuit structure, and the first node, the second node, the third node, and other nodes are not actual circuit units.

[0072] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0073] This application provides a display panel and a display device. The display panel and display device provided in this application will be described below with reference to the accompanying drawings.

[0074] like Figure 1 As shown, this application embodiment provides a display panel 100, including pixel circuits 10. Multiple pixel circuits 10 can be arranged in an array; for example, multiple pixel circuits 10 can be arranged in an array along intersecting first direction X and second direction Y. Exemplarily, the first direction X can be a row direction, and the second direction Y can be a column direction. Of course, the first direction X can also be a column direction, and the second direction Y can also be a row direction.

[0075] For example, the display panel and display device provided in the embodiments of this application can support low-frequency mode and high-frequency mode. For example, low-frequency mode may include a refresh rate of less than 60Hz, such as 30Hz, 15Hz, etc. High-frequency mode may include a refresh rate of greater than or equal to 60Hz, such as 60Hz, 90Hz, 120Hz, 144Hz, etc.

[0076] In some alternative embodiments, such as Figure 1As shown, the display panel 100 may include a shift register VSR2, which may include a multi-stage cascaded light-emitting control circuit E-VSR. In some examples below, when the signals on the light-emitting control signal line EM and the leakage control signal line EMB are opposite signals, the light-emitting control signal line EM and the leakage control signal line EMB electrically connected to the same row of pixel circuits 10 can be electrically connected to the same light-emitting control circuit E-VSR. That is, the same light-emitting control circuit E-VSR can generate two control signals. For example, the same light-emitting control circuit E-VSR generates a light-emitting control signal, and the light-emitting control signal outputs a leakage control signal through a connected inverter module. This can save the number of light-emitting control circuits E-VSR and achieve a narrow bezel.

[0077] For example, the light-emitting control circuit E-VSR may include a first output terminal, an inverter module, and a second output terminal electrically connected to the inverter module. The first output terminal may be electrically connected to the light-emitting control signal line EM and the inverter module, while the second output terminal may be electrically connected to the leakage current control signal line EMB. Through the inversion function of the inverter module, the signal at the first output terminal can be inverted and output to the second output terminal. The above is merely an example and is not intended to limit this application. In some examples below, the signal on the leakage current control signal line EMB and the signal on the light-emitting control signal line EM may be unrelated; for example, their signals may be generated by their respective independent circuits. In this case, the leakage current control signal line EMB and the light-emitting control circuit E-VSR may not be connected.

[0078] Please continue to refer to this. Figure 1 The display panel 100 may also include a shift register VSR1, which is used to generate scan signals. The shift register VSR1 may include multiple cascaded scan drive circuits S-VSR, which are electrically connected to the pixel circuit 10 via scan signal lines S(n-1), Sn, and S(n+1). The driver chip IC can be mounted on the display panel 100, or it can be mounted on a display module including the display panel. The first power supply line VDD, data signal line Vdata, and reference signal line Vref can be electrically connected to the driver chip IC. Additionally, the second power supply line VSS (… Figure 1 (Not shown) can be arranged at least partially around the display area of ​​the display panel, and the second power line VSS can also be electrically connected to the driver chip IC.

[0079] The driver IC provides the first start signal STV1 to the shift register VSR1. Additionally, as... Figure 1As shown, among the multiple cascaded scan drive circuits S-VSR, except for the first and last scan drive circuits S-VSR, the remaining scan drive circuits S-VSR can provide scan signals for two adjacent rows of pixel circuits 10.

[0080] The driver chip IC provides a second start signal STV2 for the shift register VSR2.

[0081] In addition, a clock signal line (not shown in the figure), a high-level signal line (VGH) (not shown in the figure), and a low-level signal line (VGL) (not shown in the figure) can be connected between shift register VSR1 and driver chip IC, and between shift register VSR2 and driver chip IC. The driver chip IC provides clock signals, high-level signals, and low-level signals to shift register VSR1 and shift register VSR2.

[0082] For example, such as Figure 1 As shown, the display panel 100 may include a shift register VSR1 and a shift register VSR2. The shift register VSR1 and the shift register VSR2 may be located on opposite sides of the display panel 100 in the second direction Y, or they may be located on the same side.

[0083] For example, the display panel 100 may also include two shift registers VSR1 and two shift registers VSR2, with each end of the scan signal line electrically connected to a shift register VSR1, and each end of the light emission control signal line EM and the leakage current control signal line EMB electrically connected to a shift register VSR2.

[0084] The above descriptions of shift registers VSR1 and VSR2 are merely examples and are not intended to limit this application.

[0085] To better understand the overall structure of the display panel provided in the embodiment, please refer to... Figures 2 to 3 .like Figure 2 As shown, the display panel may include a display area AA and a non-display area NA, and the non-display area NA may include an ink area INK. For example, the display panel includes a substrate 01 and a driving circuit layer 02 disposed on one side of the substrate 01. Figure 2 The diagram also shows a planarization layer PLN, a pixel definition layer PDL, a light-emitting element (the light-emitting element includes an anode RE, an organic light-emitting layer OM, and a cathode SE, wherein the first electrode of the light-emitting element can be the anode RE, and the second electrode of the light-emitting element can be the cathode SE), a support pillar PS, a thin film encapsulation layer (including a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2), an optical adhesive layer OCA, and a cover plate CG. Additionally, Figure 2The shift register VSR1, the first barrier Bank1, and the second barrier Bank2 are also shown. The shift register VSR1 can be set in the non-display area NA, and the shift register VSR1 can be set in the driver circuit layer 02 of the non-display area NA.

[0086] The pixel circuit 10 can be disposed within the driving circuit layer 02, and the pixel circuit 10 is connected to the anode RE of the light-emitting element. For example... Figure 3 As shown, the driving circuit layer 02 of the display panel may include a first metal layer M1, a second metal layer M2, and a third metal layer M3 stacked in the direction away from the substrate 01. A semiconductor layer b is disposed between the first metal layer M1 and the substrate 01. An insulating layer is disposed between any two adjacent metal layers. For example, a gate insulating layer GI is disposed between the first metal layer M1 and the semiconductor layer b, a capacitor insulating layer IMD is disposed between the second metal layer M2 and the first metal layer M1, and an interlayer dielectric layer ILD is disposed between the third metal layer M3 and the second metal layer M2.

[0087] Semiconductor layer b can be the semiconductor layer where the active layer of the transistor is located, the first metal layer M1 can be the metal conductive layer where the gate of the transistor is located, the second metal layer M2 can be the metal conductive layer where one of the plates of the capacitor is located, and the third metal layer M3 can be the metal conductive layer where the source and drain of the transistor are located.

[0088] For example, the scan signal lines S(n-1), Sn, S(n+1), the light emission control signal line EM, and the leakage current control signal line EMB can be disposed on the first metal layer M1. The reference signal line Vref can be disposed on the second metal layer M2, and the first power supply line VDD and the data signal line Vdata can be disposed on the third metal layer M3. Of course, the film layers containing each signal line can also be disposed in other ways, and this application does not limit this.

[0089] like Figure 4 As shown, the pixel circuit 10 includes a driving module 11, a leakage current suppression module 12, a first reset module 13, and a compensation module 14. The first reset module 13 and the compensation module 14 are both connected to the control terminal of the driving module 11 through the leakage current suppression module 12. The compensation module 14 may include a first submodule 141 and a second submodule 142. The second submodule 142 is connected to the leakage current suppression module 12 through the first submodule 141. Figure 4 The first reset module 13 and the compensation module 14 are connected to the first node N1, and one end of the leakage current suppression module 12 is connected to the control terminal of the drive module 11, and the other end of the leakage current suppression module 12 is connected to the first node N1 (illustrated). The first sub-module 141 and the second sub-module 142 are connected to the second node N2 (illustrated).

[0090] For example, such as Figure 4As shown, the pixel circuit may further include a first light-emitting control module 151 and a second light-emitting control module 152. The first light-emitting control module 151 can be connected between the first power line VDD and the first terminal of the driving module 11. The first light-emitting control module 151 can write the signal provided by the first power line VDD to the first terminal of the driving module 11 according to the signal on the light-emitting control signal line EM. The second light-emitting control module 152 can be connected between the second terminal of the driving module 11 and the light-emitting element 16. The second light-emitting control module 152 can transmit the driving current of the driving module 11 to the light-emitting element 16 according to the signal on the light-emitting control signal line EM, so that the light-emitting element 16 emits light.

[0091] The first reset module 13 can transmit the signal of the reference signal line Vref to the first node N1 according to the signal on the first scan signal line S(n-1). The second sub-module 142 can perform threshold compensation on the drive module 11 according to the signal on the second scan signal line Sn.

[0092] For example, such as Figure 5 As shown, the pixel circuit may further include a data writing module 17, a second reset module 18, and a storage module 19. The data writing module 17 can be connected between the data signal line Vdata and the first terminal of the driving module 11. The data writing module 17 can be turned on or off according to the signal on the second scan line Sn. When on, the data voltage provided by the data signal line Vdata is written to the control terminal of the driving module 11 through the transmission path of the driving module 11, the compensation module 14, and the leakage current suppression module 12. The first terminal of the second reset module 18 is connected to the reset signal line Vref, and the second terminal of the second initialization module 18 is connected to the first terminal of the light-emitting element 16. The second reset module 18 can be used to write the reset signal provided by the reset signal line Vref to the first terminal of the light-emitting element 16 according to the signal on the first scan signal line S(n-1) or the second scan signal line Sn.

[0093] The storage module 19 is connected between the first power line VDD and the control terminal of the drive module 11. The storage module 19 is used to store the charge written to the control terminal of the drive module 11.

[0094] As an example, such as Figure 6As shown, the operation of the pixel circuit can include a reset stage, a data writing stage, and a light emission stage. In the reset stage, the signal on the first scan line S(n-1) controls the first reset module 13 to turn on. The signal provided by the reset signal line Vref is written to the control terminal of the drive module 11 through the first reset module 13 and the leakage current suppression module 12, thus resetting the control terminal of the drive module 11. In the data writing stage, the signal transmitted by the first scan line S(n-1) controls the first reset module 13 to turn off, and the signal on the second scan line Sn controls the data writing module 17 and the second sub-module 142 to turn on. The data voltage provided by the data signal line Vdata is written to the control terminal of the drive module 11 through the data writing module 17, the drive module 11, the second sub-module 142, the first sub-module 141, and the leakage current suppression module 14. Since the second sub-module 142 can compensate for the threshold voltage of the drive module 11, the voltage at the control terminal of the drive module 11 can include voltages associated with the data voltage and the threshold voltage, thus realizing the writing of the data voltage and threshold compensation of the drive module 11. Optionally, the second reset module 18 can be controlled by a signal on the second scan line Sn. During the data writing phase, the signal on the second scan line Sn controls the second reset module 18 to be turned on. The signal provided by the reset signal line Vref is written to the first end of the light-emitting element 16 through the second reset module 18, thereby resetting the first end of the light-emitting element 16 during the data writing phase and preventing the residual charge at the first end of the light-emitting element 16 from affecting the display effect. During the light-emitting phase, the signal on the first scan line S(n-1) controls the first reset module 13 to be turned off, the signal on the second scan line Sn controls the data writing module 17 and the second sub-module 142 to be turned off, the signal on the second scan line Sn controls the second reset module 18 to be turned off, the signal on the light-emitting control signal line EM controls the first light-emitting control module 151 and the second light-emitting control module 152 to be turned on, and the voltage on the first power line VDD is transmitted to the first end of the drive module 11. The drive module 11 outputs a drive current to drive the light-emitting element 16 to emit light. Figure 6 This is merely an example and is not intended to limit this application.

[0095] like Figure 4 As shown, the leakage current suppression module 12 may include an eighth transistor T8, and the first submodule 141 may include a ninth transistor T9. The gates of the eighth transistor T8 and the ninth transistor T9 are connected to the same signal line. In this document, the signal line connecting the gates of the eighth transistor T8 and the ninth transistor T9 is referred to as the leakage current control signal line EMB.

[0096] like Figure 7 and Figure 8As shown, the active layer b8 of the eighth transistor T8 and the active layer b9 of the ninth transistor T9 are connected by a first connection portion 21, and the first connection portion 21, the active layer b8 of the eighth transistor T8, and the active layer b9 of the ninth transistor T9 are located in the same film layer. For example, the first connection portion 21 can be a semiconductor connection portion.

[0097] like Figure 8 As shown, taking the eighth transistor T8 as an example, in the direction perpendicular to the light-emitting surface of the display panel, the portion where the leakage control signal line EMB overlaps with the active layer b8 of the eighth transistor T8 is multiplexed as the gate g8 of the eighth transistor T8. The active layer b8 of the eighth transistor T8 may include a lightly doped region PD and heavily doped regions CHD located on both sides of the lightly doped region PD. In the direction perpendicular to the light-emitting surface of the display panel, the lightly doped region PD overlaps with the gate g8 of the eighth transistor T8, while the heavily doped region CHD does not overlap with the gate g8 of the eighth transistor T8. The lightly doped region PD can be understood as the channel region of the active layer b8 of the eighth transistor T8, and the heavily doped region CHD can be understood as the source and drain regions of the active layer b8 of the eighth transistor T8. The source and drain regions of the active layer b8 of the eighth transistor T8 can be the source and drain of the eighth transistor T8. The direction perpendicular to the light-emitting surface of the display panel can be understood as the thickness direction of the display panel.

[0098] The first connection portion 21, the active layer b8 of the eighth transistor T8, and the active layer b9 of the ninth transistor T9 can be located at... Figure 3 The semiconductor layer b shown allows for the electrical connection between the eighth transistor T8 and the ninth transistor T9 without the need for vias.

[0099] To better understand the technical effects of the display panel provided in the embodiments of this application, please refer to the comparison. Figure 9 , Figure 9 The pixel circuit shown differs from the pixel circuit 10 provided in the embodiments of this application in that, Figure 9 The pixel circuit shown does not have a leakage current suppression module, and Figure 9 The control terminals of the two sub-modules 141' and 142' of the compensation module 14' shown are both electrically connected to the second scan signal line Sn. Figure 9 The connection method of the driving module 11', the first reset module 13', the light-emitting element control modules 151' and 152', and the light-emitting element 16' in the pixel circuit shown is the same as... Figure 4 The corresponding modules in the pixel circuit 10 are connected in the same way. Because... Figure 9 No leakage current suppression module was installed. Figure 9The leakage path of the control terminal of the drive module 11' includes two paths: path L1 through the first reset module 13' and path L2 through the compensation module 14'. In other words, the control terminal of the drive module 11' will leak current through both the first reset module 13' and the compensation module 14'. If the potential of the control terminal of the drive module 11' is unstable, it will cause instability in the drive current generated by the drive module 11', especially in low-frequency drive mode, which can easily lead to flickering on the display panel.

[0100] In the pixel circuit 10 of the display panel provided in the embodiments of this application, both the first reset module 13 and the compensation module 14 are connected to the control terminal of the drive module 11 through the leakage current suppression module 12, compared to Figure 9 In this embodiment, the number of functional modules directly connected to the control terminal of the driving module 11 is reduced from two to one. This is equivalent to reducing the number of functional modules directly connected to the control terminal of the driving module 11. As a result, the leakage path of the control terminal of the driving module 11 must pass through the leakage suppression module 12. Compared with the case where there are multiple leakage paths of the control terminal of the driving module 11, the potential of the control terminal of the driving module 11 is more stable, which improves the problem that the display panel is prone to flickering.

[0101] To better understand another technical effect of the display panel provided in the embodiments of this application, please refer to the comparison. Figure 10 , Figure 10 The pixel circuit shown is similar to the pixel circuit 10 provided in the embodiments of this application, and will not be described again. The difference is that... Figure 10 In the pixel circuit shown, the leakage current suppression module 12' and the second terminal of the driving module 11' are directly connected without any functional module between them. The second terminal of the driving module 11' and the first reset module 13' are connected to the first node N1. Since the first node N1 and the second terminal of the driving module 11' are directly connected, their potentials are approximately equal. However, during the light-emitting phase of the pixel circuit, while the potentials of the first node N1 and the second terminal of the driving module 11' are approximately equal, the potential of the control terminal of the driving module 11' differs significantly from that of its second terminal. This results in a large potential difference between the control terminal of the driving module 11' and the first node N1. With the equivalent resistance of the leakage current suppression module 12' remaining constant, a larger potential difference across the leakage current suppression module 12' leads to a larger leakage current through the control terminal of the driving module 11', which is detrimental to the stability of the control terminal potential of the driving module 11'.

[0102] According to the pixel circuit 10 provided in the embodiment of this application, the first node N1 and the second end of the driving module 11 are not directly connected. A compensation module 14 is also provided between the first node N1 and the second end of the driving module 11. Compared with the scheme where the first node N1 and the second end of the driving module 11 are directly connected, the compensation module 14 has a larger resistance and can play the role of voltage division during the light-emitting stage, increasing the potential difference between the first node N1 and the second end of the driving module 11, thereby reducing the potential difference between the control end of the driving module 11 and the first node N1, reducing the leakage current of the control end of the driving module 11 through the leakage current suppression module 12, thereby further improving the stability of the potential of the control end of the driving module 11 and further improving the problem that the display panel is prone to flickering.

[0103] Additionally, please refer to Figure 11 , Figure 12 , Figure 13 , Figure 11 , Figure 12 , Figure 13 The pixel circuit shown is Figure 4 , Figure 7 The pixel circuit 10 shown differs in that the gate of transistor T9' is electrically connected to the second scan signal line Sn. To achieve the electrical connection between the eighth transistor T8 and the ninth transistor T9', the connection portion 21' is located on different film layers from the active layers b8 of the eighth transistor T8 and b9' of the ninth transistor T9', and is connected to the active layers b8 of the eighth transistor T8 and b9' of the ninth transistor T9' by providing vias h1 and h2. Via h1 is connected between the active layer b8 of the eighth transistor T8 and the connection portion 21', and via h2 is connected between the active layer b9' of the ninth transistor T9' and the connection portion 21'.

[0104] The display panel provided according to some embodiments of this application, see [link / reference]. Figure 7 and Figure 8 It eliminates the need for additional vias h1 and h2, resulting in higher space utilization and better layout for high-resolution display panels.

[0105] like Figure 14 As shown, the first reset module 13 of the pixel circuit 10 may include a fourth transistor T4, which may be a dual-gate transistor. For example, the fourth transistor T4 may include sub-transistors T4-1 and T4-2, such as... Figure 15 and Figure 16 As shown, the pixel circuit 10 also includes a seventh transistor T7 connected between the reference signal line Vref and the first terminal of the light-emitting module 16. For example, the gate of the seventh transistor T7 may be electrically connected to the second scan signal line Sn. Figure 15In the diagram, the gate of the seventh transistor T7 is connected to the second scan signal line Sn. The seventh transistor T7 can also be connected to the first scan signal line S(n-1). Figure 14 This is not intended to limit the scope of this application.

[0106] Figure 15 Taking the pixel circuit 10 in the i-th row, i+1-th row, j-th column, and j+1-th column as an example, where i and j can both be positive integers greater than or equal to 1. The pixel circuit in the i-th row is connected to the scan signal lines S(n-1) and Sn, and the pixel circuit in the i+1-th row is connected to the scan signal lines Sn and S(n+1). For the pixel circuit 10 in the i-th row, its corresponding first scan signal line S... (i 1) is the scan signal line S(n-1), and its corresponding second scan signal line S (i ,2) is the scan signal line Sn; for the (i+1)th row pixel circuit 10, its corresponding first scan signal line S (i+1 1) is the scan signal line Sn, and its corresponding second scan signal line S (i+1 2) is the scan signal line S(n+1). It can be understood that the scan signal line Sn can serve as both the second scan signal line S corresponding to the i-th row pixel circuit in two adjacent rows of pixel circuits. (i ,2), can also serve as the first scanning signal line S corresponding to the (i+1)th row pixel circuit. (i+1 ,1).

[0107] like Figure 15 As shown, the seventh transistor T7 of the pixel circuit 10 in the i-th row and j-th column i，j active layer b7 i，j The active layer b4 of the fourth transistor of pixel circuit 10 in row i+1 and column j+1. i+1 The active layer of the pixel circuit 10 in the i-th row and j-th column is connected to the active layer of the pixel circuit 10 in the (i+1)-th row and j+1-th column, where i and j are both positive integers greater than or equal to 1. This means the active layer of the pixel circuit 10 in the i-th row and j-th column is interconnected with the active layer of the pixel circuit 10 in the (i+1)-th row and j+1-th column, improving display uniformity. On one hand, this arrangement allows for reasonable layout of the pixel circuit to achieve high resolution; on the other hand, the fabrication of the active layer requires high-temperature processes, which generate static charge. This static charge can irreversibly affect the characteristics of the transistors. If the static charge is unevenly distributed in the active layers of each pixel circuit, it will lead to uneven display. In this embodiment, since the active layer of the pixel circuit 10 in the i-th row and j-th column is interconnected with the active layer of the pixel circuit 10 in the (i+1)-th row and j+1-th column, the static charge can be evenly distributed across these two active layers, improving display uniformity.

[0108] In some alternative embodiments, such as Figure 4 As shown, the control terminals of the first light-emitting control module 151 and the second light-emitting control module 152 are connected to the light-emitting control signal line EM. The signal line connected to the gates of the eighth transistor T8 and the ninth transistor T9 is the leakage control signal line EMB. The signal applied to the light-emitting control signal line EM is the opposite of the signal applied to the leakage control signal line EMB. For example, when EM is at a high level, EMB is at a low level, and when EM is at a low level, EMB is at a high level. Figure 1 As shown, the light emission control signal line EM and the leakage current control signal line EMB connected to the same row of pixel circuits are connected to the same light emission control circuit E-VSR. This allows for the achievement of a narrow bezel.

[0109] like Figure 16 As shown, the drive module 11 may include a first transistor T1. For example... Figure 7 As shown, the first connection portion 21 can be located on the side of the leakage control signal line EMB away from the first transistor T1.

[0110] The eighth transistor T8 can be connected to the gate of the first transistor T1 through the second connection part 31, and the connection via h8 between the eighth transistor T8 and the second connection part 31 can be located on the side of the leakage control signal line EMB close to the first transistor T1.

[0111] In this paper, the first connecting portion 21 may be a semiconductor connecting portion. The second connecting portion 31 may be a metal connecting portion.

[0112] For example, such as Figure 16 As shown, the driving module 11 may include a first transistor T1, the data writing module 17 includes a second transistor T2, the second sub-module 142 includes a third transistor T3, the first reset module 13 includes a dual-gate transistor T4, the dual-gate transistor T4 may include sub-transistors T4-1 and T4-2, the first light-emitting control module 151 includes a fifth transistor T5, and the second light-emitting control module 152 includes a sixth transistor T6. Figure 16 In the diagram, sub-transistors T4-1 and T4-2 are connected to the third node N3.

[0113] For example, the gates of sub-transistors T4-1 and T4-2 are connected to the first scan signal line S(n-1). The gates of the second transistor T2 and the third transistor T3 are both connected to the second scan signal line Sn. The gate of the fifth transistor T5 can serve as the control terminal of the first light-emitting control module 151, and the gate of the sixth transistor T6 can serve as the control terminal of the second light-emitting control module 152. The gates of both the fifth transistor T5 and the sixth transistor T6 are connected to the light-emitting control signal line EM. The gates of the eighth transistor T8 and the ninth transistor T9 are both connected to the leakage current control signal line EMB.

[0114] As an example, please refer to the reference. Figure 6 and Figure 16 Taking the example that each transistor of the pixel circuit 10 is turned on at a low level and turned off at a high level, the operation process of the pixel circuit 10 can include the following:

[0115] During the reset phase, the signals on the light emission control signal line EM and the second scan signal line Sn are at a high level, while the signals on the leakage control signal line EMB and the first scan signal line S(n-1) are at a low level. The eighth transistor T8 and its sub-transistors T4-1 and T4-2 are turned on. The signal on the reference signal line Vref is transmitted to the gate of the first transistor T1 through the sub-transistors T4-1 and T4-2 and the eighth transistor T8, thereby resetting the gate of the first transistor T1. Since the storage capacitor Cst is electrically connected to the gate of the first transistor T1, the storage capacitor Cst is also reset during the reset phase. In addition, during the reset phase, the ninth transistor T9 is turned on, while the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0116] During the data writing phase, the signals on the light emission control signal line EM and the first scan signal line S(n-1) are at a high level, while the signals on the leakage control signal line EMB and the second scan signal line Sn are at a low level. The second transistor T2, the third transistor T3, the ninth transistor T9, and the eighth transistor T8 are turned on. The data signal on the data signal line Vdata is written to the gate of the first transistor T1. In other words, the data signal provided by the data signal line Vdata is written to the gate of the first transistor T1 via the transmission path of the second transistor T2, the first transistor T1, the third transistor T3, the ninth transistor T9, and the eighth transistor T8. Furthermore, the third transistor T3 and the ninth transistor T9 perform threshold compensation on the threshold voltage of the first transistor T1. Additionally, during the data writing phase, the fifth transistor T5, the sixth transistor T6, and the sub-transistors T4-1 and T4-2 are turned off.

[0117] During the light-emitting stage, the signal on the light-emitting control signal line EM is at a low level, while the signals on the leakage control signal line EMB, the first scan signal line S(n-1), and the second scan signal line Sn are at a high level. The fifth transistor T5 and the sixth transistor T6 are turned on, and the driving current generated by the first transistor T1 is transmitted to the light-emitting diode D, which is then lit and begins to emit light. Additionally, during the light-emitting stage, the second transistor T2, the third transistor T3, the ninth transistor T9, the eighth transistor T8, and the sub-transistors T4-1 and T4-2 are turned off.

[0118] Understandably, when the gate of the seventh transistor T7 is electrically connected to the first scan signal line S(n-1), the seventh transistor T7 is turned on during the reset phase. When the gate of the seventh transistor T7 is electrically connected to the second scan signal line Sn, the seventh transistor T7 is turned on during the data writing phase. When the seventh transistor T7 is turned on, the signal on the reference signal line Vref is transmitted to the first electrode of the light-emitting diode D via the seventh transistor T7, resetting the first electrode of the light-emitting diode D.

[0119] In some alternative embodiments, such as Figure 17 As shown, the first reset module 13 may include a third submodule 131 and a fourth submodule 132, with the fourth submodule 132 connected to the leakage current suppression module 12 via the third submodule 131. For example, the connection node between the fourth submodule 132 and the third submodule 131 is considered as the fourth node N4. The fourth submodule 132 includes a dual-gate transistor T4, which may include sub-transistors T4-1 and T4-2. The third submodule 131 includes a tenth transistor T10, and the ninth transistor T9 may include a dual-gate transistor or a multi-gate transistor, meaning the ninth transistor T9 may include at least two sub-transistors connected in series, with the gates of the at least two series-connected sub-transistors connected to the same signal line.

[0120] like Figure 18 As shown, the active layer b8 of the eighth transistor T8 is located between the active layer b9 of the ninth transistor T9 and the active layer b10 of the tenth transistor T10. The active layer b8 of the eighth transistor T8 and the active layer b9 of the ninth transistor T9 are connected by a first connection portion 21, and the active layer b8 of the eighth transistor T8 and the active layer b10 of the tenth transistor T10 are connected by a third connection portion 23. The first connection portion 21, the third connection portion 23, the active layer b8 of the eighth transistor T8, the active layer b10 of the tenth transistor T10, and the active layer b9 of the ninth transistor T9 are located in the same film layer.

[0121] like Figure 19 As shown, the third connecting part 23 ( Figure 19 (Not shown), the active layer b8 of the eighth transistor T8, and the active layer b10 of the tenth transistor T10 ( Figure 19 (Not shown), the active layer b9 of the ninth transistor T9 and the first connection portion 21 can be located at Figure 3 The semiconductor layer b shown allows for electrical connection between the eighth transistor T8 and the ninth transistor T9 and the tenth transistor T10 without the need for vias.

[0122] In this article, the third connecting part 23 may be a semiconductor connecting part.

[0123] The display panel can support a low-frequency mode to reduce power consumption, for example, such as Figure 20 As shown, in low-frequency mode, the operation of the pixel circuitry in the display panel may include data frames and hold frames. For example, one or more hold frames may follow a data frame. In high-frequency mode, the operation of the pixel circuitry in the display panel may consist only of data frames.

[0124] For example, the frequency of the scanning signal can be the same in both high-frequency and low-frequency modes. Thus, even if the display panel is displayed in low-frequency mode, the user can still experience the visual effect of high-frequency mode. In low-frequency mode, such as... Figure 20 As shown, the signal applied on the first scan signal line S(n-1) can be the same in the data frame and the hold frame, and the signal applied on the second scan signal line Sn can be the same in the data frame and the hold frame.

[0125] In some alternative embodiments, such as Figure 17 and Figure 20 As shown, the data frame may include a reset phase t1; in the reset phase t1, the fourth transistor T4 (including sub-transistors T4-1 and T4-2) and the tenth transistor T10 are both turned on; in the hold frame, the tenth transistor T10 is turned off. The gate of the fourth transistor T4 may be connected to the first scan signal line S(n-1), and the gate of the tenth transistor T10 is connected to the leakage control signal line EMB.

[0126] For example, in a data frame, the data signal can be transmitted to the control terminal of the drive module, while in a hold frame, the data signal may not be transmitted to the control terminal of the drive module. The light-emitting element 16 can be reset in the hold frame, thereby reducing flickering.

[0127] For example, such as Figure 17 As shown, the pixel circuit 10 may further include a second reset module 18, which is used to transmit the signal of the reference signal line Vref to the first electrode of the light-emitting element 16 under the control of the scan signal Sn. For example, in a hold frame, the second reset module 18 may be turned on for a period of time to transmit the signal of the reference signal line Vref to the first electrode of the light-emitting element 16, thereby resetting the first electrode of the light-emitting element 16.

[0128] The inventor discovered that, as Figure 17 and Figure 20As shown, the fourth transistor T4 and the second reset module 18 can be turned on or off by a scan signal, such as the scan signals S(n-1) and Sn generated by the gate drive circuit of the display panel. The second reset module 18 can be turned on for a period of time during the holding frame, and the fourth sub-module 132 can also be turned on for a period of time during the holding frame. The signal of the reference signal line Vref will be transmitted to the fourth point N4 during the holding frame. If the tenth transistor T10 is not set, the signal of the reference signal line Vref will be directly transmitted to the first node N1 during the holding frame. For example, the signal of the reference signal line Vref is a constant negative voltage, and the potential of the control terminal of the driving module 11 in the holding frame is a positive potential. This will cause a large potential difference between the potential of the control terminal of the driving module 11 in the holding frame and the potential of the first node N1, thereby increasing the leakage current through the leakage current suppression module 12, causing the potential of the control terminal of the driving module 11 in the holding frame to be unstable, resulting in flickering. In this embodiment, by setting the tenth transistor T10 and turning off the tenth transistor T10 in the holding frame, the signal of the reference signal line Vref can be prevented from being directly transmitted to the first node N1 in the holding frame. This makes the potential difference between the control terminal of the driving module 11 and the first node N1 smaller in the holding frame, which means that the potential difference between the two ends of the leakage current suppression module 12 is smaller, thereby reducing the leakage current through the leakage current suppression module 12, stabilizing the potential of the control terminal of the driving module 11, and thus avoiding the flickering problem.

[0129] like Figure 17 and Figure 20 As shown, the data frame may also include a data writing phase t2. During the data writing phase t2, a low level on the leakage control signal line EMB can control the first submodule 141 to turn on, and a low level on the second scan signal line Sn can control the second submodule 142 to turn on. In the hold frame, the leakage control signal line EMB can always be at a high level, so that a high level on the leakage control signal line EMB can control the first submodule 141 to always remain off.

[0130] The inventors also discovered that, such as Figure 17 As shown, the second submodule 142 can also be controlled by a scan signal, which can be generated by the scan signal generated by the gate drive circuit of the display panel. The second reset module 18 can be turned on for a period of time during the holding frame, and the second submodule 142 can also be turned on for a period of time during the holding frame. Since the second submodule 142 can also be turned on for a period of time during the holding frame, the pixel circuits in the same column can be connected to the same data signal line. The data signals required by other pixel circuits in the same column as pixel circuit 10 will be transmitted to the second node N2 of pixel circuit 10 during the holding frame, such as... Figure 17As shown, the data signal is transmitted to the second node N2 of the pixel circuit 10 via the data writing module 17, the driving module 11, and the second sub-module 142 in the holding frame. If the first sub-module 141 is not provided, the data signals required by other pixel circuits in the same column of pixel circuits will be directly transmitted to the first node N1 via the data writing module 17, the driving module 11, and the second sub-module 142 in the holding frame. Since the data signals required by the same column of pixel circuits in the same frame are different and significantly different, this results in a large difference between the potential of the control terminal of the driving module 11 and the potential of the first node N1 within the holding frame. This leads to an increase in the leakage current of the leakage current suppression module 12, causing instability in the potential of the control terminal of the driving module 11 within the holding frame, resulting in flickering. However, in this embodiment, by providing the first sub-module 141 and ensuring that it is turned off in the holding frame, the data signals required by other pixel circuits are prevented from being transmitted to the first node N1 in the holding frame. This reduces the potential difference between the control terminal of the driving module 11 and the first node N1 within the holding frame, further stabilizing the potential of the control line of the driving module 11 and thus avoiding flickering.

[0131] In some alternative embodiments, such as Figure 17 As shown, taking the second reset module 18 including the seventh transistor T7 as an example, please refer to... Figure 21 The seventh transistor T7 of pixel circuit 10 in row i and column j i，j active layer b7 i，j The dual-gate transistor T4 of pixel circuit 10 in row i+1 and column j i+1，j active layer b4 i+1，j The connection is made where i and j are both positive integers greater than or equal to 1. Connecting the active layers of pixel circuits in the same column simplifies the layout and is more conducive to achieving high resolution.

[0132] For example, the seventh transistor T7 of the pixel circuit 10 in the i-th row and j-th column i，j The gate of the pixel circuit 10 in the (i+1)th row and the jth column is a dual-gate transistor T4. i+1，j The gates are connected to the same scan line Sn. By sharing scan lines, the number of scan lines required can be reduced, which is more conducive to achieving high resolution.

[0133] like Figure 18 As shown, the leakage control signal line EMB can extend along the first direction X, and the gates of the eighth transistor T8, the tenth transistor T10, and the ninth transistor T9 are connected to the same leakage control signal line EMB. This reduces the number of leakage control signal lines EMB, which is more conducive to achieving high resolution.

[0134] Please refer to Figure 18The driving module 11 may include a first transistor T1, the gate g1 of which is connected to the second connection portion 31. The gate g1 of the first transistor T1 serves as the control terminal of the driving module. An eighth transistor T8 is connected to the second connection portion 31 via an eighth via h8, which may be located on the side of the leakage control signal line EMB away from the first transistor T1. For example, the lower plate of the storage capacitor Cst can be reused as the gate g1 of the first transistor T1. To improve the potential stability of the gate g1 of the first transistor T1, the area of ​​the gate g1 can be set to be large enough. By placing the eighth via h8 on the side of the leakage control signal line EMB away from the first transistor T1, sufficient space can be provided to set a gate g1 with a large area without reducing pixel density.

[0135] like Figure 22 As shown, the first terminal of the eighth transistor T8 is connected to the gate of the first transistor T1. The eighth transistor T8 may include a dual-gate transistor. The pixel circuit 10 also includes a first capacitor C1 and / or a second capacitor C2. The first terminal of the first capacitor C1 is connected to the connection node N5 between the two sub-transistors of the eighth transistor T8, which may also be called the dual-gate node N5. The second terminal of the first capacitor C1 is connected to a constant voltage signal line, which includes a first power supply line VDD or a reference signal line Vref. The first terminal of the second capacitor C2 is connected to the second terminal of the eighth transistor T8. The second terminal of the second capacitor C2 is connected to a constant voltage signal line, which includes a first power supply line VDD or a reference signal line Vref. The capacitance of the first capacitor C1 is 10F to 60F. The capacitance of the second capacitor C2 is 10F to 60F. Since the signal on the first power line VDD or the reference signal line Vref is a constant voltage signal, both the first capacitor C1 and the second capacitor C2 play a voltage stabilizing role. The larger the capacitance of the first capacitor C1 and the second capacitor C2, the stronger the voltage stabilizing ability. Since the capacitance of the first capacitor and the second capacitor are relatively large, they can better stabilize the potential of the dual gate node N5 of the eighth transistor T8 and the second terminal of the eighth transistor T8.

[0136] For example, one of the first and second terminals of the eighth transistor T8 can be the source, and the other can be the drain.

[0137] As another example, please refer to the reference. Figure 22 and Figure 20 Taking the example where each transistor of pixel circuit 10 is turned on at a low level and turned off at a high level, the data frame may include a reset phase t1, a data writing phase t2, and a first light-emitting phase t3. The holding frame may include a non-light-emitting phase t4 and a second light-emitting phase t5. The non-light-emitting phase t4 may include a first phase t41 and a second phase t42.

[0138] During the reset phase t1, the signals on the light emission control signal line EM and the second scan signal line Sn are at a high level, while the signals on the leakage control signal line EMB and the first scan signal line S(n-1) are at a low level. The eighth transistor T8, the fourth transistor T4, and the tenth transistor T10 are turned on. The signal on the reference signal line Vref is transmitted to the gate of the first transistor T1, thereby resetting the gate of the first transistor T1. Since the storage capacitor Cst is electrically connected to the gate of the first transistor T1, the storage capacitor Cst is also reset during the reset phase. Additionally, during the reset phase t1, the ninth transistor T9 is turned on, while the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0139] During the data writing phase t2, the signals on the light-emitting control signal line EM and the first scan signal line S(n-1) are at a high level, while the signals on the leakage control signal line EMB and the second scan signal line Sn are at a low level. The second transistor T2, the third transistor T3, the ninth transistor T9, and the eighth transistor T8 are turned on. The data signal on the data signal line Vdata is written to the gate of the first transistor T1 via the second transistor T2, the first transistor T1, the third transistor T3, the ninth transistor T9, and the eighth transistor T8. The third transistor T3 and the ninth transistor T9 perform threshold compensation on the threshold voltage of the first transistor T1. Additionally, during the data writing phase t2, the seventh transistor T7 is turned on, and the signal on the reference signal line Vref is transmitted to the first electrode of the light-emitting element D, thereby resetting the light-emitting element D. Furthermore, during the data writing phase t2, the fifth transistor T5, the sixth transistor T6, and the dual-gate transistor T4 are turned off.

[0140] During the first light-emitting phase t3 of the data frame and the second light-emitting phase t5 of the holding frame, the signal on the light-emitting control signal line EM is at a low level, while the signals on the leakage control signal line EMB, the first scan signal line S(n-1), and the second scan signal line Sn are at a high level. The fifth transistor T5 and the sixth transistor T6 are turned on, and the driving current generated by the first transistor T1 is transmitted to the light-emitting diode D, which is then lit and begins to emit light. Additionally, during light-emitting phases t3 and t5, the second transistor T2, the third transistor T3, the ninth transistor T9, the eighth transistor T8, the fourth transistor T4, and the tenth transistor T10 are turned off.

[0141] In the first stage t41, the signals on the light emission control signal line EM, the leakage current control signal line EMB, and the second scan signal line Sn are at a high level, while the signal on the first scan signal line S(n-1) is at a low level. The fourth transistor T4 is turned on, and the signal on the reference signal line Vref is transmitted to the fourth node N4, while the tenth transistor T10 is turned off, so the signal on the reference signal line Vref is not transmitted to the first node N1. In addition, the second transistor T2, the third transistor T3, the ninth transistor T9, the eighth transistor T8, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0142] In the second stage t42, the signals on the light-emitting control signal line EM, the leakage control signal line EMB, and the first scan signal line S(n-1) are at a high level, while the signal on the second scan signal line Sn is at a low level. The seventh transistor T7 is turned on, and the signal on the reference signal line Vref is transmitted to the first terminal of the light-emitting element D, resetting the first terminal of the light-emitting element D. The second transistor T2 and the third transistor T3 are turned on, and the signal on the data signal line Vdata is transmitted to the second node N2. Because the ninth transistor T9 is turned off, the signal on the data signal line Vdata is not transmitted to the first node N1. Additionally, the eighth transistor T8, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, and the fourth transistor T4 are turned off.

[0143] In this document, for example, the first power line VDD can be used to transmit a positive voltage, such as +4.6V. The second power line VSS can be used to transmit a negative voltage, such as -2.5V. The first scan signal line S(n-1) and the second scan signal line Sn are used to transmit scan signals. The light emission control signal line EM and the leakage control signal line EMB are used to transmit light emission control signals and leakage control signals, respectively. The scan signal, light emission control signal, and leakage control signal can be pulse signals, and their high level can be +7V and their low level can be -7V. The reference signal line Vref is used to transmit a negative voltage, such as -3.5V. The above values ​​are merely examples and are not intended to limit this application.

[0144] Furthermore, in the partial structural schematic diagram of the display panel provided in this application, via h3 can be understood as a connection hole between the pixel circuit 10 and the first electrode of the light-emitting diode D. Via h4 can be understood as a connection hole between the second transistor T2 and the data signal line Vdata. Via h5 can be understood as a connection hole between the fifth transistor T5 and the first power line VDD. Via h6 can be understood as a connection hole between the upper plate of the storage capacitor Cst and the first power line VDD. The lower plate of the storage capacitor Cst can be reused as the gate of the first transistor T1. The gate of the first transistor T1 and the eighth transistor T8 are connected through the second connection portion 31. Via h7 can be understood as a connection hole between the second connection portion 31 and the gate of the first transistor T1, and via h8 can be understood as a connection hole between the second connection portion 31 and the eighth transistor T8. The reference signal line Vref is connected to the seventh transistor T7 and the sub-transistors T4-1 and T4-2 through the connection part 41. The via h9 can be understood as the connection hole between the connection part 41 and the reference signal line Vref, and the via h10 can be understood as the connection hole between the connection part 41 and the seventh transistor T7 and the sub-transistors T4-1 and T4-2.

[0145] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 23 , Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 23 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 23 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0146] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that, The pixel circuit includes a driving module, a leakage current suppression module, a first reset module, and a compensation module. Both the first reset module and the compensation module are connected to the control terminal of the drive module through the leakage current suppression module. The compensation module includes a first sub-module and a second sub-module, and the second sub-module is connected to the leakage current suppression module through the first sub-module. The leakage current suppression module includes an eighth transistor, and the first sub-module includes a ninth transistor. The gates of the eighth transistor and the ninth transistor are both connected to the leakage current control signal line. The active layers of the eighth transistor and the ninth transistor are connected through a first connection portion, and the first connection portion, the active layers of the eighth transistor and the ninth transistor are located in the same film layer. The first connection portion is a semiconductor connection portion. The eighth transistor and the ninth transistor are turned off during the light-emitting phase.

2. The display panel according to claim 1, characterized in that, The first reset module includes a fourth transistor, which is a dual-gate transistor.

3. The display panel according to claim 2, characterized in that, The pixel circuit also includes a seventh transistor connected to the first electrode of the light-emitting element of the display panel; The active layer of the seventh transistor of the pixel circuit in the i-th row and j-th column is connected to the active layer of the fourth transistor of the pixel circuit in the (i+1)-th row and j+1-th column, where i and j are both positive integers greater than or equal to 1.

4. The display panel according to claim 1, characterized in that, The display panel also includes a shift register, which includes a multi-stage cascaded light-emitting control circuit. The pixel circuit further includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting module is connected between the second end of the driving module and the first electrode of the light-emitting element of the display panel. The control terminals of both the first and second light-emitting control modules are connected to the light-emitting control signal line.

5. The display panel according to claim 4, characterized in that, The drive module includes a first transistor, and the first connection portion is located on the side of the leakage control signal line away from the first transistor.

6. The display panel according to claim 5, characterized in that, The eighth transistor is connected to the gate of the first transistor via the second connection portion, and the connection via between the eighth transistor and the second connection portion is located on the side of the leakage control signal line closer to the first transistor.

7. The display panel according to claim 4, characterized in that, The signal on the light emission control signal line is the opposite of the signal on the leakage current control signal line. The light emission control signal line and the leakage current control signal line connected to the pixel circuit in the same row are connected to the same light emission control circuit.

8. The display panel according to claim 1, characterized in that, The ninth transistor includes a dual-gate transistor, and the first reset module includes a fourth transistor and a tenth transistor, with the fourth transistor connected to the leakage current suppression module through the tenth transistor.

9. The display panel according to claim 8, characterized in that, The active layer of the eighth transistor is located between the active layers of the ninth transistor and the tenth transistor. The active layer of the eighth transistor and the active layer of the ninth transistor are connected through the first connection portion, and the active layer of the eighth transistor and the active layer of the tenth transistor are connected through the third connection portion.

10. The display panel according to claim 9, characterized in that, The first connecting portion, the third connecting portion, the active layer of the eighth transistor, the active layer of the fourth transistor, and the active layer of the ninth transistor are located in the same film layer.

11. The display panel according to claim 9, characterized in that, The third connection part is a semiconductor connection part.

12. The display panel according to claim 9, characterized in that, The gate of the fourth transistor is connected to the first scan signal line, and the gate of the tenth transistor is connected to the leakage control signal line.

13. The display panel according to claim 12, characterized in that, The leakage control signal line extends along a first direction, and the gates of the eighth transistor, the tenth transistor, and the ninth transistor are connected to the same leakage control signal line.

14. The display panel according to claim 12, characterized in that, The operation of the pixel circuit includes a data frame and a hold frame, and the data frame includes a reset phase. During the reset phase, both the fourth transistor and the tenth transistor are turned on; During the holding frame, the tenth transistor is turned off.

15. The display panel according to claim 1, characterized in that, The first reset module includes a fourth transistor, and the pixel circuit further includes a seventh transistor connected to a first electrode of the light-emitting element of the display panel; The active layer of the seventh transistor of the pixel circuit in the i-th row and j-th column is connected to the active layer of the fourth transistor of the pixel circuit in the (i+1)-th row and j-th column, where i and j are both positive integers greater than or equal to 1.

16. The display panel according to claim 12, characterized in that, The driving module includes a first transistor, and an eighth transistor is connected to the gate of the first transistor via a second connection portion. The connection via between the eighth transistor and the second connection portion is located on the side of the leakage control signal line away from the first transistor.

17. The display panel according to claim 16, characterized in that, The first connection portion and the third connection portion are located on the side of the leakage control signal line close to the first transistor.

18. The display panel according to claim 1, characterized in that, The first terminal of the eighth transistor is connected to the control terminal of the driving module. The eighth transistor includes a dual-gate transistor. The pixel circuit also includes a first capacitor and a second capacitor. The first terminal of the first capacitor is connected to the dual-gate node of the eighth transistor, and the second terminal of the first capacitor is connected to the first power supply line or the reference signal line. The first terminal of the second capacitor is connected to the second terminal of the eighth transistor, and the second terminal of the second capacitor is connected to the first power supply line or the reference signal line.

19. The display panel according to claim 18, characterized in that, The capacitance of the first capacitor is 10F to 60F, and the capacitance of the second capacitor is 10F to 60F.

20. The display panel according to claim 1, characterized in that, The pixel circuit also includes a data writing module, a storage module, a first light emission control module, and a second light emission control module; The data writing module is connected between the data signal line and the first end of the driving module, the storage module is connected between the control end of the driving module and the first power line, the first light-emitting control module is connected between the first power line and the first end block of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first electrode of the light-emitting element of the display panel.

21. The display panel according to claim 20, characterized in that, The driving module includes a first transistor, the data writing module includes a second transistor, the second sub-module includes a third transistor, the first reset module includes a fourth transistor, the first light-emitting control module includes a fifth transistor, and the second light-emitting control module includes a sixth transistor. The gate of the fourth transistor is connected to the first scan signal line, the gates of the second transistor and the third transistor are both connected to the second scan signal line, the gates of the fifth transistor and the sixth transistor are both connected to the light emission control signal line, and the gates of the eighth transistor and the ninth transistor are both connected to the leakage control signal line.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 21.

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