A phase change memory operation method, phase change memory and memory system

Abstract

An embodiment of the present invention provides an operation method of a phase change memory, a phase change memory and a memory system. The operation method comprises: when resetting a selected memory block from the plurality of memory blocks, resetting the lower phase change memory unit of the selected memory block based on a first reset current; resetting the upper phase change memory unit of the selected memory block based on a second reset current; wherein the first reset current is less than or greater than the second reset current.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to an operating method of a phase change memory, a phase change memory and a memory system. Background Art

[0002] Phase change memory is a memory element used to store information by using the conductivity or impedance difference between the crystalline and amorphous states of a specific phase change material. When setting the operation of the phase change material of the phase change memory to switch between the crystalline and amorphous states, different pulses can be used to control the heating of the phase change material. At present, the operating method used generates a relatively large surge current, which has a relatively serious impact on the life of the phase change memory. Summary of the invention

[0003] In view of this, the main purpose of the present invention is to provide an operation method of a phase change memory, a phase change memory and a memory system. By adopting a two-stage reset method and making the reset current provided to the phase change memory unit in the T2 stage smaller than the reset current provided to the phase change memory unit in the T3 stage, the surge current of performing a reset operation on a phase change memory unit of the phase change memory is reduced, thereby improving the life of the phase change memory.

[0004] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0005] In a first aspect, an embodiment of the present invention provides an operating method of a phase change memory, comprising:

[0006] The phase change memory includes a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block includes a lower phase change memory unit and an upper memory unit; the operation method includes:

[0007] When resetting a selected storage block among the plurality of storage blocks, a reset operation is performed on a lower phase-change memory cell of the selected storage block based on a first reset current; and a reset operation is performed on an upper phase-change memory cell of the selected storage block based on a second reset current;

[0008] Wherein, the first reset current is smaller than or larger than the second reset current.

[0009] Optionally, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first reset current is less than the second reset current; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first reset current is greater than the second reset current.

[0010] Optionally, the first reset current and the second reset current are controlled by a current mirror coupled to a bit line of the selected memory block.

[0011] Optionally, the duration of the first reset current and the second reset current are both not greater than the duration of a set current provided when the phase change memory unit is set.

[0012] Optionally, the operation method further includes:

[0013] Applying a first voltage to a first word line coupled to a lower phase-change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase-change memory cell of the selected memory block;

[0014] When the first selector of the lower phase change memory cell of the selected memory block is turned on by the first voltage and the second voltage, a reset operation is performed on the lower phase change memory cell of the selected memory block based on the first reset current.

[0015] Optionally, the operation method further includes:

[0016] Applying a third voltage to a second word line coupled to an upper phase-change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase-change memory cell of the selected memory block;

[0017] When the second selector of the upper phase change memory cell of the selected memory block is turned on under the action of the third voltage and the fourth voltage, a reset operation is performed on the upper phase change memory cell of the selected memory block based on the second reset current.

[0018] Optionally, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

[0019] Optionally, when the first voltage is less than the third voltage, the operating method further includes: adjusting the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value, wherein the second value is greater than the first value;

[0020] Alternatively, when the first voltage is greater than the third voltage, the operating method further includes:

[0021] The ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value.

[0022] Optionally, the first voltage and the third voltage are positive voltages; and the second voltage and the fourth voltage are negative voltages.

[0023] Optionally, the operating method also includes: applying a fifth voltage to a word line coupled to phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block, and applying a sixth voltage to a bit line coupled to phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block; under the action of the fifth voltage and the sixth voltage, selectors applied to all unselected phase change memory cells in the memory array block are in a non-conducting state.

[0024] In a second aspect, a phase change memory provided by an embodiment of the present invention comprises: a plurality of memory arrays; each memory array comprises a plurality of memory blocks, each memory block comprises a lower phase change memory unit and an upper memory unit;

[0025] and a peripheral circuit coupled to the plurality of storage arrays and used to control the plurality of storage arrays; wherein,

[0026] The peripheral circuit is configured to: when resetting a selected storage block among the plurality of storage blocks, perform a reset operation on a lower phase-change memory cell of the selected storage block based on a first reset current; and perform a reset operation on an upper phase-change memory cell of the selected storage block based on a second reset current;

[0027] Wherein, the first reset current is smaller than or larger than the second reset current.

[0028] Optionally, the peripheral circuit includes a current mirror coupled to a bit line of the selected storage block and configured to control the first reset current and the second reset current.

[0029] Optionally, the peripheral circuit also includes a word line driver configured to: apply a first voltage to a first word line coupled to a lower phase change memory cell of the selected storage block; apply a second voltage to a first bit line coupled to a lower phase change memory cell of the selected storage block; apply a third voltage to a second word line coupled to an upper phase change memory cell of the selected storage block; and apply a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected storage block.

[0030] Optionally, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

[0031] Optionally, the peripheral circuit further includes a voltage regulator, and the voltage regulator is configured to: when the first voltage is less than the third voltage, adjust the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

[0032] Alternatively, when the first voltage is greater than the third voltage, the ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value.

[0033] Optionally, the peripheral circuit is also configured to: apply a fifth voltage to the word line coupled to the phase change memory cells contained in all unselected storage blocks in the phase change memory that belong to the same storage array block as the selected storage block, and apply a sixth voltage to the bit line coupled to the phase change memory cells contained in all unselected storage blocks in the phase change memory that belong to the same storage array block as the selected storage block; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the storage array block are in a non-conducting state.

[0034] In a third aspect, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described above and a memory controller coupled to the phase change memories and used to control the phase change memories.

[0035] The embodiment of the present invention provides an operation method of a phase change memory, a phase change memory and a memory system. The phase change memory includes a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block includes a lower phase change memory unit and an upper memory unit; the operation method includes: when resetting a selected memory block among the plurality of memory blocks, resetting the lower phase change memory unit of the selected memory block based on a first reset current; resetting the upper phase change memory unit of the selected memory block based on a second reset current; wherein the first reset current is less than or greater than the second reset current. That is, different reset currents are used for two phase change memory units in a memory block. For example, in one case, the lower phase change memory unit in the selected memory block uses a first reset current, and the upper phase change memory unit uses a second reset current greater than the first reset current, thereby reducing the instantaneous current (surge current plus reset current) applied to the selector of the lower phase change memory unit when it is turned on, reducing the damage to the lower phase change memory unit, and thus improving the life of the phase change memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of various pulses during the operation of a phase change memory unit provided by an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of threshold voltage distributions of set and reset states of a phase change memory cell provided by an embodiment of the present invention;

[0038] Figure 3 A block diagram of an exemplary system of a memory including a phase change memory cell provided for an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of an exemplary memory including a peripheral circuit provided for an embodiment of the present invention;

[0040] Figure 5 A schematic diagram of a structure of an implementation of a phase change memory array 401 provided in an embodiment of the present invention;

[0041] Figure 6 A partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0042] Figure 7 Another partial three-dimensional schematic diagram of a phase change memory unit provided by an embodiment of the present invention;

[0043] Figure 8 A block diagram of an exemplary memory including a memory array and peripheral circuits provided for an embodiment of the present invention;

[0044] Fig. 9A schematic diagram of a circuit structure for resetting a phase change memory unit provided by an embodiment of the present invention;

[0045] Fig.10 A schematic diagram of a flow chart of a method for operating a phase change memory provided by an embodiment of the present invention;

[0046] Fig.11 A schematic diagram of a circuit structure for performing a reset operation on a phase change memory unit provided by an embodiment of the present invention;

[0047] Fig.12 The embodiment of the present invention provides Fig.11 The timing diagram of each voltage signal of the circuit structure schematic diagram shown;

[0048] Fig.13 A relationship diagram of the current-voltage characteristics of the OTS when the selector provided in the embodiment of the present invention is the OTS;

[0049] Fig.14 A schematic diagram of a reset current provided when a reset operation is performed on a selected phase change memory cell according to an embodiment of the present invention;

[0050] Fig.15 A timing diagram for implementing a reset operation provided in an embodiment of the present invention.

[0051] Fig.16 A schematic diagram of a circuit structure for controlling a first reset current and a second reset current using a current mirror is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0052] Although specific configurations and arrangements have been discussed, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be very practical without departing from the scope of the present invention. In addition, the present invention may also be used for various other applications. The functions and structural features as described in the present invention may be combined, adjusted and modified with each other and in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the disclosure of the present invention.

[0053] Typically, a term can be understood, at least in part, from usage in context. For example, the term "one or more," as used herein, can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a feature, structure, or combination of features in a plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" can also be understood to express singular usage or to express plural usage, depending at least in part on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of other factors that are not necessarily explicitly described, again depending at least in part on the context.

[0054] Phase Change Memory (PCM) is a non-volatile memory device that uses phase change materials to store data. PCM can be based on heating and quenching the phase change material in an electrothermal manner, using the difference between the resistivity of the amorphous state and the crystalline state in the phase change material (e.g., a chalcogenide alloy). The phase change material in the PCM cell can be located between two electrodes, and a current can be applied to repeatedly switch the material (or at least a portion of it blocking the current path) between the two phases to store data. The set state is a low resistance state of the PCM cell, which can be obtained by generating a crystalline region in the chalcogenide material. When the chalcogenide material is heated at a crystallization temperature for a sufficient time, crystallization occurs. Conversely, the reset state is a high resistance state of the PCM cell, which can be obtained by generating a non-crystalline region in the chalcogenide material. When the chalcogenide material is heated to above its melting temperature and then rapidly quenched to form an amorphous state, an amorphous state can be generated. Among them, the set state can be referred to as the on state; and the reset state can be referred to as the off state.

[0055] As described above, when the phase change material in the PCM switches between the crystalline state and the amorphous state, different pulses (such as light pulses, electric pulses) can be used to control the heating of the phase change material. Figure 1 As shown, when a long and medium-intensity programming pulse (also called Set Pulse) is applied to raise the temperature of the phase change material layer of the phase change memory unit to below the melting temperature Tm and above the crystallization temperature Tx, and is maintained for a period of time to promote the growth of the crystal nucleus, the phase change material layer of the phase change memory unit can be transformed from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state). The process of realizing the transformation of the phase change material of the phase change memory unit from a high state (0 state) to a low resistance state (1 state) is usually called a set (Set) process, or a write operation process; after applying a short and strong reset pulse (also called Reset Pulse) to raise the temperature of the phase change material layer of the phase change memory unit to above the melting temperature Tm, and then undergoing rapid cooling (Cooling Down), the phase change material layer of the phase change memory unit can be transformed from a crystalline state to an amorphous state. The process of realizing the transformation of the phase change material layer of the phase change memory unit from a low resistance state (1 state) to a high state (0 state) is usually called a reset (Reset) process, or an erase operation process. The Reset process and the Set process are mutually reversible processes, so that the phase change memory cell can use the crystalline state to represent the unit binary data 1, and use the amorphous state to represent the binary data 0. In some embodiments, the phase change memory may include multiple memory arrays, and the threshold voltage distribution of the phase change memory cells included in each memory array may be as follows: Figure 2As shown. It should be noted that the threshold voltage distributions corresponding to the phase change memory cells in different storage arrays may be somewhat different, that is, the shapes of the threshold voltage distributions calculated for different numbers of phase change memory cells may be slightly different, but the general shapes are similar. In addition, after applying a very weak read pulse that does not affect the phase change material layer, the resistance value of the phase change memory cell is measured to achieve the reading of the data stored in the phase change memory cell.

[0056] At present, in the related technical solutions, during the reset process of the phase change memory unit, the reset pulse applied will introduce a relatively large inrush current spike, wherein the inrush current spike is the main factor affecting the life of the phase change memory unit. It should be noted that the reset pulse can be a voltage or a current. This article is an improved method for operating a phase change memory unit based on a current pulse test system, so the pulse used here is a current pulse. Therefore, unless otherwise specified, the pulses used in the set process or the reset process are all current pulses.

[0057] In order to solve the above problems, an embodiment of the present invention provides an operating method for a phase change memory, which uses different reset current pulses for phase change memory cells at different positions in the same storage block to reduce the inrush current spike during the reset operation, thereby extending the life of the phase change memory cells.

[0058] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Figure 3 Block diagram of an exemplary system of a memory including a phase change memory cell provided by an embodiment of the present invention. System 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 3As shown, the system 300 may include a host 308 and a memory system 302, wherein the memory system 302 has one or more memories 304 and a memory controller 306; the host 308 may be a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), wherein the system on a chip may be, for example, an application processor (AP). The host 308 may be configured to send data to the memory 304 or receive data from the memory 304.

[0060] Specifically, the memory 304 may be any memory device disclosed in the present invention, as disclosed in detail below, the memory 304, for example, a phase change random access memory (PCRAM); the memory 304 may also refer to a three-dimensional phase change memory.

[0061] According to some embodiments, the memory controller 306 is coupled to the memory 304 and the host 308. And is configured to control the memory 304. The memory controller 306 can manage the data stored in the memory 304 and communicate with the host 308. In some embodiments, the memory controller 306 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices with low duty cycle environments such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 306 is designed to operate in a high duty cycle environment, such as a solid state drive (SSD) or an embedded multimedia card (eMMC), wherein the SSD or eMMC is used as a data storage device for a mobile device with a high duty cycle environment such as a smart phone, a tablet computer, a laptop computer, and an enterprise storage array. The memory controller 306 can be configured to control the operation of the memory 304, such as read, erase, and program operations. The memory controller 306 may also be configured to manage various functions regarding data stored or to be stored in the memory 304, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 306 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 304. The memory controller 306 may also perform any other suitable functions, such as formatting the memory 304. The memory controller 306 may communicate with an external device (e.g., a host 308) according to a specific communication protocol.For example, the memory controller 306 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0062] The memory controller 306 and one or more memories 304 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 302 can be implemented and packaged into different types of terminal electronic products. In one example, the memory controller 306 and the single memory 304 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card that connects the memory card to a host (e.g., Figure 3 In another example, the memory controller 306 and the plurality of memories 304 may be integrated into the SSD. The SSD may also include a memory card connector that couples the SSD to a host (e.g., Figure 3 The memory controller 306 may be configured to control the erase, read, and write operations of the memory 304.

[0063] Figure 4Schematic diagram of an exemplary memory including peripheral circuits provided for an embodiment of the present invention. The memory 304 may be a three-dimensional phase change memory, which may include a phase change memory array 401 and a peripheral circuit 402 coupled to the phase change memory array 401. The phase change memory array 401 may include a word line 4011, a bit line 4012, and a phase change memory cell 4013 formed between the word line 4011 and the bit line 4012. In some embodiments, each phase change memory cell 4013 may include a PCM element (including a phase change material, not shown in the figure) connected in series with a selector (not shown in the figure). In some embodiments, the phase change memory cell 4013 may include a DRAM cell of a paired transistor and a capacitor. In order to operate the phase change memory array 401, a word line voltage (Vw) may be applied to a selected word line 4011, and a bit line voltage (Vb) may be applied to a selected bit line 4012.

[0064] Regarding the structure of the phase change memory array 401, in some embodiments, as Figure 5 As shown, it is a schematic diagram showing a structure of an implementation method of a phase change memory array 401 provided in an embodiment of the present invention. Figure 5 It can be seen that the phase change memory array 401 is a three-dimensional memory array, which is composed of a plurality of small memory array blocks with a single bit line, a word line and a phase change memory cell. A three-dimensional phase change memory generally includes a top bit line, a word line, a bottom bit line and a memory cell located at the intersection of the bit line and the word line. In practical applications, the word line, the top bit line and the bottom bit line are usually formed by a 20nm / 20nm equal width line (L / S, Line / Space) pattern formed after a patterning process. Among them, the structure of the phase change memory cell 4013, such as Figure 6 As shown, it shows a partial three-dimensional schematic diagram of a phase change memory cell 4013 provided in an embodiment of the present invention. The phase change memory cell 4013 includes: a stacked PCM element 602, a selector 604, and a plurality of electrodes 601, 603, and 605. The PCM element 602 can utilize the difference between the resistivity of the amorphous phase (i.e., amorphous state) and the crystalline phase (i.e., crystalline state) in the phase change material based on the heating and quenching of the phase change material in an electrothermal manner. A current can be applied to cause the phase change material of the PCM element 602 (or at least a portion thereof that blocks the current path) to repeatedly switch between two phases to store data. A single bit of data can be stored in each storage cell 4013, and a single bit of write operation or read operation can be performed by changing the voltage applied to the corresponding selector 604.

[0065] In some embodiments, the material of the PCM element 602 includes a chalcogenide-based alloy (chalcogenide glass), such as a GST (Ge-Sb-Te) alloy, or any other suitable phase change material; the material of the selector 604 may include any suitable bidirectional threshold switch (OTS) material, such as ZnxTey, GexTey, NbxOy, SixAsyTez, etc. The electrodes 601, 603, and 605 may include a conductive material, including but not limited to W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the material of the electrodes 601, 603, and 605 includes carbon, such as amorphous carbon.

[0066] It should be noted that the upper and lower phase change memory cells in the phase change memory array 401 may also share a word line, for example, Figure 7 shown.

[0067] Figure 8 A block diagram of an exemplary memory including a memory array and peripheral circuits provided for an embodiment of the present invention. Figure 8 As shown, the memory 304 includes a phase change memory array 401 and a peripheral circuit 402, wherein the memory array has been described above. The peripheral circuit 402 includes: a control logic 4021, an address register 4022, a voltage generator 4023, a row decoder / word line driver 4024, a page buffer / sense amplifier circuit 4025, a column decoder / bit line driver / data latch 4026, and a data register / data I / O 4027, wherein;

[0068] The page buffer / sense amplifier circuit 4025 can be configured to read data from the phase-change memory array 401 and program (write) data to the phase-change memory array 401 according to the control signal from the control logic 4021. In one example, the page buffer / sense amplifier 4025 can store data to be programmed into the phase-change memory array 401 (e.g., Figure 4In another example, the page buffer / sense amplifier 4025 can perform a program verification operation to ensure that the data has been correctly programmed into the phase change memory cell 4013 coupled to the selected word line 4011. In yet another example, the page buffer / sense amplifier 4025 can also sense a low-power signal from the selected bit line 4012 representing the data bit stored in the phase change memory cell 4013, and amplify the small voltage swing to a recognizable logic level in a read operation. In some embodiments, the page buffer / sense amplifier 4025 may include a comparator (e.g., a voltage comparator) to compare a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). The column decoder / bit line driver / data latch 4026 can be configured to be controlled by the control logic 4021 and select one or more phase change memory cells 4013 and bit lines 4012. Column decoder / bit line driver / data latch 4026 may be further configured to drive selected bit line 4012. Column decoder / bit line driver / data latch 4026 may be further configured to drive bit line 4012 using a bit line voltage generated from voltage generator 4023. Column decoder / bit line driver / data latch 4026 may be a temporary binary data storage device for storing bits. In some embodiments, column decoder / bit line driver / data latch 4026 may include a read data latch to temporarily store read data.

[0069] The data register / data I / O 416 can be coupled to the page buffer / sense amplifier 4025 and / or the column decoder / bit line driver / data latch 4026, and is configured to direct (route) data input from the data bus 4028 to the desired phase change memory cell 4013 of the phase change storage array 401, and to direct (route) data output from the desired memory cell to the data bus 4028.

[0070] The row decoder / word line driver 4024 may be configured to be controlled by the control logic 4021 and select one or more phase change memory cells 4013 and word lines 4011 of the phase change memory array 401. The row decoder / word line driver 4024 may be further configured to drive the selected word line 4011. The row decoder / word line driver 4024 may be further configured to drive the word line 4011 using the word line voltage generated from the voltage generator 4023.

[0071] The voltage generator 4023 can be configured to be controlled by the control logic 4021 according to a control signal from the control logic 4021, and generate a word line voltage (e.g., a read voltage, a programming voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the phase change memory array 401.

[0072] The control logic 4021 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The control logic 4021 is configured to be received from a host (eg, Figure 3 308 in the figure) receives clock signals, command signals, address signals and data signals, wherein the command signals are received via the command bus 4029; and the data signals are received via the data bus 4028. In some embodiments, the control logic 4021 can be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU, Micro Controller Unit)), a digital signal processor (DSP, Digital Signal Processor), an application specific integrated circuit (ASIC, Application Specific Integrated Circuit), a field programmable gate array (FPGA, Field Programmable Gate Array), a programmable logic device (PLD, Programmable Logic Device), a state machine, a gating logic, a discrete hardware circuit and other appropriate hardware, firmware and / or software configured to perform the various functions described.

[0073] Fig. 9 The structure diagram of the reset operation of the phase change memory unit provided by the embodiment of the present invention is as follows. Fig. 9 As shown, once the control logic 4021 determines that the command signal is a reset command, the control logic 4021 triggers the reset operation, and the word line voltage (Vhh) is led to the word line of the selected phase change memory cell through the word line driver, and the bit line voltage (-VII) is led to the bit line of the selected phase change memory through the bit line driver, and then under the action of the word line voltage and the bit line voltage, the selector of the selected phase change memory cell is turned on, and then, the selected phase change memory is provided with a current for resetting (transforming into an amorphous state) to perform a reset operation on the selected phase change memory cell. It should be noted that the voltages applied to the bit lines described below are all bit line voltages, only because different names are selected in different scenarios for distinction, which does not limit the present invention. Similarly, the voltages applied to the word lines described below are all word line voltages, only because different names are selected in different scenarios for distinction, which does not limit the present invention.

[0074] Based on the above three-dimensional phase change memory, in order to solve the technical problems described above, an embodiment of the present invention provides an operation method of a phase change memory, such as Fig.10 As shown, it shows a schematic diagram of the structure of an operation method of a phase change memory provided by an embodiment of the present invention. Specifically, the phase change memory includes a plurality of memory arrays; each memory array includes a plurality of memory blocks, and each memory block includes a lower phase change memory unit and an upper memory unit; based on this, as Fig.10 As shown, the operation method may include:

[0075] S1001: When resetting a selected storage block from the multiple storage blocks, a reset operation is performed on a lower phase change memory cell of the selected storage block based on a first reset current; a reset operation is performed on an upper phase change memory cell of the selected storage block based on a second reset current; wherein the first reset current is less than or greater than the second reset current.

[0076] It should be noted that the structure of the phase change memory described in the embodiment of the present invention can be Figure 6 or Figure 7 The structure shown in FIG. 1 is that the lower phase-change memory cell and the upper phase-change memory cell share a bit line or a word line.

[0077] Among them, the operating method provided by the embodiment of the present invention can be understood as: when performing a reset operation on a selected storage block, a reset operation is performed on the lower phase change memory unit based on a first reset current; and a reset operation is performed on the upper phase change memory unit based on a second reset current; wherein, the first reset current is smaller than the second reset current, or the second reset current is smaller than the first reset current.

[0078] Among them, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first reset current is less than the second reset current; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first reset current is greater than the second reset current.

[0079] It should be noted that, through research, it is found that the closer the phase change memory unit is to the peripheral circuit, when performing a reset operation on it, because the loss of the voltage applied from the voltage source is relatively small at this time, and because the resistance of the phase change memory unit in the set state is relatively small at this time, when the OTS is turned on, the surge current generated will be relatively large, and the instantaneous current flowing through the phase change memory unit at this time will be relatively large, that is, the phase change memory unit closer to the peripheral circuit is more affected by the surge current. At this time, in order to reduce the instantaneous current passing through the phase change memory unit when performing a reset operation, due to the characteristics of the OTS, the current generated is not easy to control. At this time, the reset current provided to the phase change memory unit externally can be reduced, that is, when the peripheral circuit for controlling the selected storage block contained in the phase change memory is arranged on the side of the lower phase change memory unit close to the selected storage block, the reset current provided to the lower phase change memory unit is smaller than the reset current provided to the upper phase change memory unit, that is, the first reset current is smaller than the second reset current. Similarly, if the peripheral circuit included in the phase change memory for controlling the selected memory block is arranged on a side of the upper phase change memory unit close to the selected memory block, the first reset current is greater than the second reset current.

[0080] That is, when the upper and lower phase change memory cells included in the selected storage block are reset, different reset currents are used to reset the upper and lower phase change memory cells included in the selected storage block. For example, in an optional manner, a second reset current is provided to the upper phase change memory cell included in the selected storage block, and a first reset current is provided to the lower phase change memory cell included in the selected storage block, wherein the first reset current is less than the second reset current, or the first reset current is greater than the second reset current. In this way, the instantaneous current (surge current plus reset current) applied to the lower phase change memory cell when the selector is turned on is reduced, thereby reducing damage to the lower phase change memory cell, thereby improving the life of the phase change memory.

[0081] The following takes the example of setting the peripheral circuit on the lower phase change memory cell side close to the selected storage block to explain how to reduce the instantaneous current flowing through the phase change memory cell by changing the reset current of the phase change memory cell at different positions to improve the life of the phase change memory cell.

[0082] In related technologies, such as Fig.11 As shown, it shows a schematic diagram of a circuit structure for applying voltage to the bit line and word line of a phase change memory cell; Fig.12 As shown, it is shown based on Fig.11 The circuit diagram of FIG. 1 is a graph of the voltage applied to the word line and the bit line of the phase change memory cell. Fig.11In the above, WL_Driver represents the voltage source of the word line voltage applied to the word line; BL_Driver represents the voltage source of the bit line voltage applied to the bit line; Ireset current source represents the reset current source provided by the user. V2 represents the voltage value; V1 represents the voltage value, where V2 is greater than V1. Based on this, in Fig.12 In the figure, the curve corresponding to IBL represents the instantaneous current curve for resetting that flows through the selected phase change memory cell in the selected storage block; the curve corresponding to VWL represents the voltage curve applied to the word line coupled to the selected phase change memory cell; the curve corresponding to VBL represents the voltage curve applied to the bit line coupled to the selected phase change memory cell, and the voltage can be provided by the bit line driver BL_driver through the corresponding selection transistor; the curve corresponding to BL_driver represents the voltage curve applied to the bit line driver; the curve corresponding to Ireset is the reset current curve provided by the user.

[0083] It should be noted that in Fig.12 In the process of resetting the lower phase change memory cell of the selected storage block, the T2 stage corresponds to the process of resetting the upper phase change memory cell of the selected storage block; the T3 stage corresponds to the process of resetting the upper phase change memory cell of the selected storage block. During the reset operation, whether it is the T2 stage or the T3 stage of the reset operation, the instantaneous current IBL flowing through the selected phase change memory cell for reset includes two parts, one part is the Ireset provided by the user, and the other part is the inrush current introduced by the applied voltage mutation, among which the peak value of the inrush current is relatively large, which has a serious impact on the life of the phase change memory cell.

[0084] Specifically, based on the above description of the structure of the phase change memory cell, the phase change memory cell includes a PCM element 602 and a selector 604, wherein the selector 604 is an OTS, and the OTS is a bidirectional threshold switch, and its current-voltage characteristic is as follows: Fig.13As shown. Based on this, when performing a reset operation on the phase change memory cell, once the voltage difference between the word line voltage applied to the word line coupled to the selected phase change memory cell and the bit line voltage applied to the bit line coupled to the selected phase change memory cell is greater than the threshold voltage Vt of the OTS, the voltage across the OTS will drop from Vt to its holding voltage Vhold instantly, and a relatively large inrush current is introduced to flow through the selected phase change memory cell due to the voltage mutation. Due to the characteristics of the OTS device, the magnitude of the inrush current introduced is uncontrollable, and since the current flowing through the selected phase change memory cell is the sum of the Ireset provided by the user and the inrush current introduced based on the voltage change on the OTS, then, in order to reduce the maximum peak value of the instantaneous current flowing through the selected phase change memory cell, the reset current provided by the user can be used as a starting point, that is: reduce the reset current provided by the user to reduce the instantaneous current flowing through the entire phase change memory cell. Since the peripheral circuit is relatively close to the lower phase-change memory cell of the selected storage block, the lower phase-change memory cell has a relatively large impact during the reset operation. Therefore, when performing the reset operation on the selected storage block, only the reset current used when resetting the lower phase-change memory cell can be reduced to ensure that the time for resetting the entire selected storage block does not need to be too long. That is, during the original entire reset operation, the T2 stage and the T3 stage use the same Ireset, which is adjusted to use the first reset current in the T2 stage and the second reset current in the T3 stage, wherein the first reset current is less than the second reset current. That is, by reducing the Ireset provided by the user in the T2 stage, the maximum peak value of the instantaneous current flowing through the selected phase-change memory cell in the T2 stage of the reset operation is reduced, thereby improving the life of the phase-change memory cell.

[0085] That is, the reset operation of the phase change memory cell provided by the embodiment of the present invention is as follows: Fig.14 As shown, Ireset is the reset current provided by the user, wherein Ireset1 is the first reset current; and Ireset2 is the second reset current. In this way, based on the superposition characteristics of the current, by reducing the Ireset provided by the user in the T2 stage, the instantaneous current flowing through the selected phase change memory cell in the T2 stage can be quickly reduced, thereby reducing the peak value of the instantaneous current flowing through the selected phase change memory cell in the T2 stage of the reset operation, thereby reducing the damage to the selected phase change memory cell, thereby improving the life of the phase change memory cell; and also accelerating the stabilization of the current flowing through the selected phase change memory cell in the T2 stage, thereby reducing the reset time of the phase change memory.

[0086] Based on the operation method provided in the embodiment of the present invention, an optional implementation method is as follows: Fig.15As shown, it shows a timing diagram for implementing the reset operation provided by an embodiment of the present invention. Among them, the curve corresponding to IBL represents the current curve for resetting flowing through the selected phase change memory cell; the curve corresponding to VWL represents the voltage curve applied to the word line coupled to the selected phase change memory cell; the curve corresponding to VBL represents the voltage curve applied to the bit line coupled to the selected phase change memory cell, and the voltage can be provided by the bit line driver BL_driver through the corresponding selection transistor; the curve corresponding to BL_driver represents the voltage curve applied to the bit line driver. The curve corresponding to I1 is the aforementioned Fig.14 The Ireset1 shown in the figure is the first reset current; the curve corresponding to Ireset is the reset current curve provided by the user, which is the second reset current. Fig.15 In the timing diagram provided in , in the T2 stage, the first reset current provided by the user is smaller than before; in the T3 stage, the second reset current provided by the user is the same as before and does not need to be changed, so that the first reset current can be smaller than the second reset current, so as to reduce the current for resetting flowing through the selected phase change memory unit in the T2 stage.

[0087] In some embodiments, the duration of the first reset current and the second reset current can be set according to actual conditions. There is no special correlation between the two, but the duration of the two is on the same order of magnitude, that is, the duration of the two is similar.

[0088] In some embodiments, the durations of the first reset current and the second reset current are not greater than the duration of a set current provided when the selected phase-change memory cell is set.

[0089] It should be noted that based on Figure 1 It can be seen from the time relationship diagram of the set process and the reset process described in that the duration of the reset process should be shorter than the duration of the set process, that is, the duration of the first reset current and the second reset current are both shorter than the duration of the set current provided when the selected phase change memory unit is set.

[0090] In some embodiments, the first reset current and the second reset current are controlled by a current mirror coupled to a bit line of the selected memory block.

[0091] Here, the amplitudes of the first reset current and the second reset current may be controlled by a current mirror coupled to the bit line of the selected memory block.

[0092] As a way to achieve this, Fig.16 As shown, it shows a schematic diagram of a circuit structure using a current mirror to control the first reset current and the second reset current. Fig.16 In other structures Fig.11 The structure is the same as in Fig.16 The current mirror is used to realize Fig.11 The Ireset current source in the current mirror is used to control the reset current provided by the user in the T2 stage or the T3 stage. It should be noted that this is only an exemplary description, and the parameters and structure of the specific current mirror can be designed according to specific needs, and its specific structure is not limited here.

[0093] According to the above description, when performing a reset operation on the phase change memory unit, it is necessary to turn on the selector of the phase change memory unit. Therefore, in some embodiments, the operation method further includes:

[0094] Applying a first voltage to a first word line coupled to a lower phase-change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase-change memory cell of the selected memory block;

[0095] When the first selector of the lower phase change memory cell of the selected memory block is turned on by the first voltage and the second voltage, a reset operation is performed on the lower phase change memory cell of the selected memory block based on the first reset current.

[0096] In some other embodiments, the operation method further includes:

[0097] Applying a third voltage to a second word line coupled to an upper phase-change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase-change memory cell of the selected memory block;

[0098] When the second selector of the upper phase change memory cell of the selected memory block is turned on under the action of the third voltage and the fourth voltage, a reset operation is performed on the upper phase change memory cell of the selected memory block based on the second reset current.

[0099] It should be noted that according to the above Figure 6 and Figure 7 In the structure of the phase change memory cell shown, the upper phase change memory cell and the lower memory cell may share a word line or a bit line, so the first word line and the second word line appearing here may be the same word line, or the first line or the second bit line may be the same bit line.

[0100] In some embodiments, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

[0101] It should be noted that the phase change memory cell far away from the peripheral circuit may require a higher voltage to ensure that the voltage applied to the phase change memory cell can turn on the selector. Figure 6 In the phase-change memory array structure shown, the voltage applied to the word line coupled to the phase-change memory cell on the side to which the peripheral circuit is close can be smaller. For example, when the peripheral circuit is close to the lower phase-change memory cell of the selected memory block, the first voltage applied to the first word line coupled to the lower phase-change memory cell can be smaller than the third voltage applied to the second word line coupled to the upper phase-change memory cell. Conversely, when the peripheral circuit is close to the side of the upper phase-change memory cell, the first voltage is greater than the third voltage.

[0102] Based on this, since the selected phase change memory cell is in a set state during the reset operation, at this time, the resistance of the selected phase change memory cell is in a low resistance state, from the T2 stage, the first voltage on the word line rises to the T3 stage, the second voltage on the word line, at this time, since the resistance of the selected phase change memory cell is in a low resistance state, then, based on the change from the first voltage to the third voltage, the current flowing through the selected phase change memory cell will be relatively large in a short time. Therefore, in order to reduce the peak value of this current, in some embodiments, in some embodiments, when the first voltage is less than the third voltage, the operation method further includes: adjusting the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value;

[0103] Alternatively, when the first voltage is greater than the third voltage, the operating method further includes:

[0104] The ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value.

[0105] For example, assuming that the first voltage is less than the third voltage, the above adjustment is as follows: Fig.13 and Fig.15 As shown, in Fig.13 In the example, it is assumed that the ramp pulse width of the third voltage is the first value; Fig.15 In the example, the ramp pulse width of the third voltage is the second value, which is Fig.13 middle, Fig.15 In the T3 stage shown, since it takes a long time for the voltage to rise from the first voltage to the third voltage, that is, the voltage change time is long, the instantaneous current flowing through the selected phase change memory cell will be reduced, thereby reducing the damage to the phase change memory cell, thereby increasing the life of the phase change memory cell.

[0106] In some embodiments, the first voltage and the third voltage are positive voltages; and the second voltage and the fourth voltage are negative voltages.

[0107] In some embodiments, the operating method further includes:

[0108] A fifth voltage is applied to the word lines coupled to the phase change memory cells included in all unselected memory blocks that belong to the same memory array block as the selected memory block in the phase change memory, and a sixth voltage is applied to the bit lines coupled to the phase change memory cells included in all unselected memory blocks that belong to the same memory array block as the selected memory block in the phase change memory; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the memory array block are in a non-conducting state.

[0109] It should be noted that, here, a reset operation is described for only the selected phase change memory cell, and a fifth voltage is applied to the word line and a sixth voltage is applied to the bit line of the unselected phase change memory cell in the same storage array block. Under the action of the fifth voltage and the sixth voltage, the voltage difference between the bit line and the word line corresponding to all the unselected phase change memory cells in the storage array block is equal to the threshold voltage of the selector of the unselected phase change memory cell, and is not turned on, so that the reset operation is not performed on the unselected phase change memory cell.

[0110] The operating method of the phase change memory provided by the embodiment of the present invention reduces the instantaneous maximum value of the current flowing through the phase change memory unit in the T2 stage by making the first reset current used in the T2 stage smaller than the second reset current used in the T3 stage in the two-stage reset operation, thereby improving the life of the phase change memory.

[0111] Based on the same inventive concept, an embodiment of the present invention further provides a phase change memory, a plurality of memory arrays; each memory array includes a plurality of memory blocks, each memory block includes a lower phase change memory unit and an upper memory unit;

[0112] and a peripheral circuit coupled to the plurality of storage arrays and used to control the plurality of storage arrays; wherein,

[0113] The peripheral circuit is configured to: when resetting a selected storage block among the plurality of storage blocks, perform a reset operation on a lower phase-change memory cell of the selected storage block based on a first reset current; and perform a reset operation on an upper phase-change memory cell of the selected storage block based on a second reset current;

[0114] Wherein, the first reset current is smaller than or larger than the second reset current.

[0115] In some embodiments, the peripheral circuit includes a current mirror coupled to a bit line of the selected memory block and configured to control the first reset current and the second reset current.

[0116] In some embodiments, the peripheral circuit also includes a word line driver configured to: apply a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; apply a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block; apply a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; and apply a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block.

[0117] In some embodiments, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

[0118] In some embodiments, the peripheral circuit further includes a voltage regulator, and the voltage regulator is configured to: when the first voltage is less than the third voltage, adjust the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

[0119] Alternatively, when the first voltage is greater than the third voltage, the ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value.

[0120] It should be noted that the voltage regulator is any circuit structure that can be used to adjust the ramp pulse width of the third voltage or the first voltage.

[0121] In some embodiments, the peripheral circuit is further configured to: apply a fifth voltage to the word lines coupled to the phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block, and apply a fifth voltage to the bit lines coupled to the phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the memory array block are in a non-conducting state.

[0122] It should be noted that the phase change memory here and the aforementioned operating method belong to the same inventive concept, and the terms and operations appearing here have been described in detail above and will not be repeated here.

[0123] Based on the same inventive concept, an embodiment of the present invention further provides a memory system, comprising: one or more phase change memories as described in any of the foregoing items and a memory controller coupled to the phase change memories and used to control the phase change memories.

[0124] In some embodiments, the peripheral circuit is configured to: in response to a received reset instruction, perform a reset operation on a selected phase change memory cell in the phase change memory, wherein the reset operation includes: when resetting a selected storage block among the plurality of storage blocks, performing a reset operation on a lower phase change memory cell of the selected storage block based on a first reset current; performing a reset operation on an upper phase change memory cell of the selected storage block based on a second reset current;

[0125] Wherein, the first reset current is smaller than or larger than the second reset current.

[0126] In some embodiments, the peripheral circuit includes a current mirror coupled to a bit line of the selected memory block, and configured to control the first reset current and the second reset current.

[0127] In some embodiments, the peripheral circuit also includes a word line driver configured to: apply a first voltage to a first word line coupled to a lower phase change memory cell of the selected memory block; apply a second voltage to a first bit line coupled to a lower phase change memory cell of the selected memory block; apply a third voltage to a second word line coupled to an upper phase change memory cell of the selected memory block; and apply a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected memory block.

[0128] In some embodiments, when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

[0129] In some embodiments, the peripheral circuit further includes a voltage regulator, and the voltage regulator is configured to: when the first voltage is less than the third voltage, adjust the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value;

[0130] Alternatively, when the first voltage is greater than the third voltage, the ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value.

[0131] In some embodiments, the peripheral circuit is further configured to: apply a fifth voltage to the word lines coupled to the phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block, and apply a fifth voltage to the bit lines coupled to the phase change memory cells contained in all unselected memory blocks in the phase change memory that belong to the same memory array block as the selected memory block; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the memory array block are in a non-conducting state.

[0132] Here, the reset instruction is transmitted by the memory controller to the peripheral circuit via a communication interface connected to the peripheral circuit, so that the peripheral circuit performs a reset operation on the selected phase change memory unit in the phase change memory in response to the received reset instruction.

[0133] The memory system here belongs to the same inventive concept as the aforementioned operating method and phase change memory. The terms and operations appearing here have been described in detail above and will not be repeated here.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A method for operating a phase change memory, characterized in that: The phase change memory comprises a plurality of memory arrays; each memory array comprises a plurality of memory blocks, each memory block comprises a lower phase change memory cell and an upper phase change memory cell; the lower phase change memory cell and the upper phase change memory cell share a bit line, and the bit line shared by the lower phase change memory cell and the upper phase change memory cell is located between the lower phase change memory cell and the upper phase change memory cell; or, the lower phase change memory cell and the upper phase change memory cell share a word line, and the word line shared by the lower phase change memory cell and the upper phase change memory cell is located between the lower phase change memory cell and the upper phase change memory cell; the operation method comprises: When resetting a selected storage block among the plurality of storage blocks, a reset operation is performed on a lower phase-change memory cell of the selected storage block based on a first reset current; and a reset operation is performed on an upper phase-change memory cell of the selected storage block based on a second reset current; Wherein, the first reset current is smaller than or larger than the second reset current.

2. The operating method according to claim 1, characterized in that: When the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first reset current is less than the second reset current; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first reset current is greater than the second reset current.

3. The operating method according to claim 1, characterized in that: The first reset current and the second reset current are controlled by a current mirror coupled to a bit line of the selected memory block.

4. The operating method according to claim 1, characterized in that: The duration of the first reset current and the second reset current are both no longer than the duration of the set current provided when the phase change memory cell is set.

5. The operating method according to claim 1, characterized in that: The operation method also includes: Applying a first voltage to a first word line coupled to a lower phase-change memory cell of the selected memory block; applying a second voltage to a first bit line coupled to a lower phase-change memory cell of the selected memory block; When the first selector of the lower phase change memory cell of the selected memory block is turned on by the first voltage and the second voltage, a reset operation is performed on the lower phase change memory cell of the selected memory block based on the first reset current.

6. The operating method according to claim 5, characterized in that: The operation method also includes: Applying a third voltage to a second word line coupled to an upper phase-change memory cell of the selected memory block; applying a fourth voltage to a second bit line coupled to an upper phase-change memory cell of the selected memory block; When the second selector of the upper phase change memory cell of the selected memory block is turned on under the action of the third voltage and the fourth voltage, a reset operation is performed on the upper phase change memory cell of the selected memory block based on the second reset current.

7. The operating method according to claim 6, characterized in that: When the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

8. The operating method according to claim 7, characterized in that: When the first voltage is less than the third voltage, the operating method further includes: adjusting the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value, wherein the second value is greater than the first value; Alternatively, when the first voltage is greater than the third voltage, the operating method further includes: The ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value.

9. The operating method according to claim 6, characterized in that: The first voltage and the third voltage are positive voltages; the second voltage and the fourth voltage are negative voltages.

10. The operating method according to claim 1, characterized in that: The operation method also includes: A fifth voltage is applied to the word lines coupled to the phase change memory cells included in all unselected memory blocks that belong to the same memory array block as the selected memory block in the phase change memory, and a sixth voltage is applied to the bit lines coupled to the phase change memory cells included in all unselected memory blocks that belong to the same memory array block as the selected memory block in the phase change memory; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the memory array block are in a non-conducting state.

11. A phase change memory, characterized in that: include: A plurality of memory arrays; each memory array comprising a plurality of memory blocks, each memory block comprising a lower phase change memory cell and an upper phase change memory cell; The lower phase change memory unit and the upper phase change memory unit share a bit line, and the bit line shared by the lower phase change memory unit and the upper phase change memory unit is located between the lower phase change memory unit and the upper phase change memory unit; or, the lower phase change memory unit and the upper phase change memory unit share a word line, and the word line shared by the lower phase change memory unit and the upper phase change memory unit is located between the lower phase change memory unit and the upper phase change memory unit; and a peripheral circuit coupled to the plurality of storage arrays and used to control the plurality of storage arrays; wherein, The peripheral circuit is configured to: when resetting a selected storage block among the plurality of storage blocks, perform a reset operation on a lower phase-change memory cell of the selected storage block based on a first reset current; and perform a reset operation on an upper phase-change memory cell of the selected storage block based on a second reset current; Wherein, the first reset current is smaller than or larger than the second reset current.

12. The phase change memory according to claim 11, characterized in that: The peripheral circuit includes a current mirror coupled to a bit line of the selected memory block and configured to control the first reset current and the second reset current.

13. The phase change memory according to claim 12, characterized in that: The peripheral circuit also includes a word line driver, which is configured to: apply a first voltage to a first word line coupled to a lower phase change memory cell of the selected storage block; apply a second voltage to a first bit line coupled to a lower phase change memory cell of the selected storage block; apply a third voltage to a second word line coupled to an upper phase change memory cell of the selected storage block; and apply a fourth voltage to a second bit line coupled to an upper phase change memory cell of the selected storage block.

14. The phase change memory according to claim 13, characterized in that: When the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the lower phase change memory unit close to the selected storage block, the first voltage is less than the third voltage; when the peripheral circuit included in the phase change memory for controlling the selected storage block is arranged on the side of the upper phase change memory unit close to the selected storage block, the first voltage is greater than the third voltage.

15. The phase change memory according to claim 14, characterized in that: The peripheral circuit further includes a voltage regulator, and the voltage regulator is configured to: when the first voltage is less than the third voltage, adjust the ramp pulse width of the third voltage so that the ramp pulse width of the third voltage is adjusted from a first value to a second value; Alternatively, when the first voltage is greater than the third voltage, the ramp pulse width of the first voltage is adjusted so that the ramp pulse width of the first voltage is adjusted from the first value to the second value, wherein the second value is greater than the first value.

16. The phase change memory according to claim 11, characterized in that: The peripheral circuit is also configured to: apply a fifth voltage to the word lines coupled to the phase change memory cells included in all unselected storage blocks in the phase change memory that belong to the same storage array block as the selected storage block, and apply a sixth voltage to the bit lines coupled to the phase change memory cells included in all unselected storage blocks in the phase change memory that belong to the same storage array block as the selected storage block; under the action of the fifth voltage and the sixth voltage, the selectors applied to all unselected phase change memory cells in the storage array block are in a non-conducting state.

17. A memory system, characterized in that: include: A phase change memory as claimed in any one of one or more claims 11 to 16, and a memory controller coupled to the phase change memory and used to control the phase change memory.

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