Memory device and operation method thereof

Abstract

The present invention discloses a memory device and an operation method thereof. The memory device comprises: a memory array having a plurality of memory cells; a plurality of bit lines coupled to the memory array; a plurality of word lines coupled to the memory array; and a plurality of conductance controllable cells coupled to the memory array, wherein a memory cell group of the memory cells and at least one conductance controllable cell of the conductance controllable cells form a logic operation unit, and a logic operation function of the logic operation unit is determined by an equivalent conductance of the at least one conductance controllable cell.

Description

Technical Field

[0001] The invention relates to a memory device with a computing in memory function and an operation method thereof. Background Art

[0002] Computing in Memory technology can be applied to artificial intelligence (AI) accelerator architecture. Data is computed in memory, and the results are sent to the processor. Therefore, in comparison, computing in memory technology can perform AI functions on terminal devices in a low-power and high-efficiency manner.

[0003] In order to further reduce power consumption and improve integration, resistive switches are now used as logic operation units of CIM. Currently, different voltages have been applied to switch the logic operation functions of the logic operation unit. However, the multi-voltage operation architecture will increase the complexity of the calculation process and peripheral circuits. Summary of the invention

[0004] According to an example of the present invention, a memory device is provided, comprising: a memory array having a plurality of memory cells; a plurality of bit lines coupled to the memory array; a plurality of word lines coupled to the memory array; and a plurality of conductivity-controllable cells coupled to the memory array, wherein a memory cell group of the memory cells and at least one conductivity-controllable cell of the conductivity-controllable cells form a logic operation unit, and a logic operation function of the logic operation unit is determined by an equivalent conductance of the at least one conductivity-controllable cell.

[0005] According to an example of the present invention, a method for operating a memory device is proposed, comprising: selecting a memory cell group of multiple memory cells of the memory device and at least one conductivity-controllable unit to form a logic operation unit; and controlling an equivalent conductance of the at least one conductivity-controllable unit to determine a logic operation function of the logic operation unit.

[0006] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B FIG. 4 is a circuit diagram of a logic operation unit of a memory device according to two embodiments of the present invention.

[0008] Figure 2A graph showing the voltage-current characteristics of a resistive switch.

[0009] FIG. 3A to FIG. 3E Multiple possible implementations of the conductivity controllable unit C according to the embodiments of the present invention are shown respectively.

[0010] Figure 4 A voltage waveform diagram according to an embodiment of the present invention is shown.

[0011] Figure 5 A circuit diagram showing a logic operation unit of a memory device according to an embodiment of the present invention is shown.

[0012] Figure 6 Displays the signal waveform diagram for NOR operation.

[0013] Fig. 7A Display logical operations Circuit architecture diagram of the logic operation unit of S; Figure 7B Display logical operations Schematic diagram of the logic gate of S; Figure 7C Display logical operations Signal waveform diagram of S.

[0014] FIG. 8A to FIG. 8G Circuit diagrams of memory devices according to various embodiments of the present invention are shown.

[0015]

Explanation of symbols

[0016] 100A, 100B: Logic operation unit

[0017] A, B and Y: Resistive switches

[0018] C: Conductivity controllable unit

[0019] WL1~WL6:Word lines

[0020] BL: Bit Line

[0021] Taccess: access transistor

[0022] T1~T5: Transistor

[0023] RW: Resistive switch

[0024] S: Selector

[0025] T A 、T B 、T Y 、T C 、T Y1 、T Y2 、T S :transistor

[0026] P1~P6: Timing

[0027] 800A~800G:Memory device

[0028] 810: Memory Array

[0029] BL1~BLN: bit line

[0030] WL1~WLM:word line

[0031] 820: Memory unit

[0032] GCL, GCL1~GCLP, GWL, GTL, GTL1~GTLP: control line DETAILED DESCRIPTION

[0033] The technical terms of the present invention refer to the customary technical terms in the art. If the present invention explains or defines some of the terms, the interpretation of these terms shall be based on the explanation or definition of the present invention. Each embodiment of the present invention has one or more technical features. Under the premise of possible implementation, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0034] Please refer to Figure 1A and Figure 1B , which illustrates a circuit architecture diagram of a logic operation unit of a memory device according to two embodiments of the present invention.

[0035] exist Figure 1A In the embodiment, the logic operation unit 100A includes resistive switches A, B and Y, and a conductivity controllable unit C.

[0036] Resistive switches A, B and Y are connected in parallel. One end of resistive switch A is coupled to word line WL1, and the other end is coupled to bit line BL. One end of resistive switch B is coupled to word line WL2, and the other end is coupled to bit line BL. One end of resistive switch Y is coupled to word line WL3, and the other end is coupled to bit line BL. One end of conductivity controllable unit C is coupled to bit line BL, and the other end is grounded.

[0037] exist Figure 1B In the embodiment of the present invention, the logic operation unit 100B includes: resistive switches A, B and Y, a conductance controllable unit C, and an access transistor Taccess. The access transistor Taccess is a selective element in the embodiment of the present invention.

[0038] One end (e.g., drain end) of the access transistor Taccess is coupled to the bit line BL, the other end (e.g., source end) thereof is coupled to a sense amplifier (not shown), and the control end (e.g., gate end) thereof receives a gate control voltage (not shown). The access transistor Taccess is used to provide a read current / read voltage to read or change the conductance state of the resistive switch.

[0039] In the embodiment of the present invention, Figure 1A and Figure 1B As shown, by changing the equivalent conductance of the controllable conductance unit C, the operating functions of the logic operation units 100A and 100B can be controlled. Here, the operating functions of the logic operation units 100A and 100B having NAND logic operations and NOR logic operations are used as examples for illustration, but it should be understood that the present invention is not limited to this.

[0040] In the embodiment of the present invention, when the conductivity controllable unit C has a first equivalent conductance value, the operation functions of the logic operation units 100A and 100B are controlled to be a first logic operation (e.g., a NAND logic operation); and when the conductivity controllable unit C has a second equivalent conductance value, the operation functions of the logic operation units 100A and 100B are controlled to be a second logic operation (e.g., a NOR logic operation), wherein the first equivalent conductance value is higher than the second equivalent conductance value. For example, but not limited to, the first equivalent conductance value is twice the second equivalent conductance value.

[0041] In the embodiment of the present invention, the resistive switches A and B may also be referred to as input units, which store input data before the logic operation; and the resistive switch Y may also be referred to as an output unit, which stores output data after the logic operation.

[0042] In addition, the resistive switches A, B, and the conductivity controllable unit C can be regarded as forming a voltage dividing unit, which determines the bit line voltage Vint on the bit line BL and also determines the final state of the resistive switch Y. The details will be described below.

[0043] Figure 2 Displays the voltage-current characteristics of a resistive switch. Figure 2 As shown, when the voltage across the resistive switch is higher than a set voltage VSET, the resistive switch changes from a high resistance state (HRS) to a low resistance state (LRS); conversely, when the reverse voltage across the resistive switch is higher than a reset voltage, the resistive switch changes from a low resistance state to a high resistance state.

[0044] In the embodiment of the present invention, the low impedance state and the high impedance state of the resistive switch are set to logic 1 and logic 0 respectively. HRS With GLRS are the conductance values ​​of the resistive switch in the high impedance state and the low impedance state, respectively, where G HRS <<G LRS .

[0045] exist Figure 1A and Figure 1B , the input voltage Vi is applied to the word lines WL1 and WL2, that is, the input voltage Vi is applied to the resistive switches A and B. The output voltage Vo is applied to the word line WL3, that is, the output voltage Vo is applied to the resistive switch Y. In addition, the initial state of the resistive switch Y is a high impedance state.

[0046] According to the voltage division law, the bit line voltage Vint can be expressed as follows.

[0047] When the resistive switches A and B are both in the low impedance state, the bit line voltage Vint can be expressed as: Vint = Vi × (G LRS ) / (G LRS +0.5G L ), where G L Represents the conductivity value of the conductivity controllable unit C.

[0048] When one of the resistive switches A and B is in a low impedance state and the other is in a high impedance state, the bit line voltage Vint can be expressed as: Vint = Vi × (G LRS ) / (G LRS +G L ).

[0049] When the resistive switches A and B are both in a high impedance state, the bit line voltage Vint can be expressed as: Vint=0V.

[0050] If the resistive switch Y is to be programmed, the voltage across the resistive switch Y must be greater than the set voltage VSET. That is, when the difference between the output voltage Vo and the set voltage VSET (Vo-VSET) is higher than the bit line voltage Vint, the resistive switch Y can be programmed (changed from a high impedance state to a low impedance state).

[0051] NAND logic operation

[0052] In the embodiment of the present invention, when the difference between the output voltage Vo and the set voltage VSET (Vo-VSET) is between Vi×(G LRS ) / (G LRS +0.5G L ) and Vi×(G LRS ) / (G LRS +G L), then (1) when at least one of the resistive switches A and B is in a high impedance state, the resistive switch Y will be programmed (the state of the resistive switch Y is a low impedance state (Y=0)); and (2) when both the resistive switches A and B are in a low impedance state, the resistive switch Y will not be programmed (the state of the resistive switch Y is a high impedance state (Y=1)).

[0053] That is, in this case, the relationship between the logic states of the resistive switches A, B and Y (as shown in Table 1 below) can be expressed as follows:

[0054] A B Y 0 0 1 0 1 1 1 0 1 1 1 0

[0055] Table 1

[0056] Therefore, in this case, the operation function of the logic operation units 100A and 100B has a NAND logic operation.

[0057] NOR logic operation

[0058] In another case, in the embodiment of the present invention, when the difference between the output voltage Vo and the set voltage VSET (Vo-VSET) is between Vi×(G LRS ) / (G LRS +G L ) and 0, then (1) when both resistive switches A and B are in a high impedance state, resistive switch Y will be programmed (the state of resistive switch Y is a low impedance state (Y=0)); (2) when one of resistive switches A and B is in a high impedance state and the other is in a low impedance state, resistive switch Y will not be programmed (the state of resistive switch Y is a high impedance state (Y=1)); and (3) when both resistive switches A and B are in a low impedance state, resistive switch Y will not be programmed (the state of resistive switch Y is a high impedance state (Y=1)).

[0059] That is, in this case, the relationship between the logic states of the resistive switches A, B and Y (as shown in Table 2 below) can be expressed as follows:

[0060] A B Y 0 0 1 0 1 0 1 0 0 1 1 0

[0061] Table 2

[0062] Therefore, in this case, the operation function of the logic operation units 100A and 100B has a NOR logic operation.

[0063] In addition, in order to make Vi×(G LRS ) / (G LRS +0.5G L ) and Vi×(G LRS ) / (G LRS +GL ) to obtain the best result, the conductivity value G of the conductivity controllable unit C L Can be set to However, it should be understood that the present invention is not limited thereto. The conductivity value G of the conductivity controllable unit C L It can be set to other appropriate values.

[0064] In summary, it can be seen that in the embodiment of the present invention, when Time (G L is its optimal value), Vo-VSET=(1 / 2)×Vi (but it should be understood that the present invention is not limited to this), then when at least one of the resistive switches A and B is in a high impedance state, the resistive switch Y will be programmed, that is, at this time, the operation function of the logic operation units 100A and 100B has NAND logic operation.

[0065] If the conductivity value G of the controllable conductivity unit C is controlled L Half of its optimal value When both the resistive switches A and B are in the high impedance state, the resistive switch Y will be programmed, that is, the operation functions of the logic operation units 100A and 100B are switched to the NOR logic operation.

[0066] That is, in the embodiment of the present invention, by controlling the conductivity value G of the conductivity controllable unit C L , the operation functions of the logic operation units 100A and 100B can be switched between NAND logic operation and NOR logic operation.

[0067] Please refer to FIG. 3A to FIG. 3E , which respectively show a plurality of possible implementations of the conductivity controllable unit C according to an embodiment of the present invention.

[0068] exist Figure 3A In the embodiment, the conductivity controllable unit C is composed of transistor T1. Figure 3A In the embodiment, the transistor T1 is placed in a linear region to adjust the equivalent conductance value of the controllable conductivity unit C. Applying a larger gate voltage to the gate of the transistor T1 can reduce the equivalent conductance value of the controllable conductivity unit C, and vice versa.

[0069] exist Figure 3B In the embodiment, the conductivity controllable unit C is composed of a floating-gate transistor T2 and a transistor T3. The transistor T3 can provide a drain current to program or erase the floating-gate transistor T2, thereby changing the equivalent conductance value of the floating-gate transistor T2 in the linear region. In addition, during the logic operation, the transistor T3 will be turned off.

[0070] exist Figure 3CIn the embodiment, the conductivity controllable unit C is composed of a resistive switch RW and a transistor T4. The transistor T4 provides a current or a voltage to control the electrical property value of the resistive switch RW. Similarly, during the logic operation, the transistor T4 will be turned off.

[0071] exist Figure 3D In the embodiment, the conductivity controllable unit C is composed of a multi-terminal transistor T5, wherein one terminal of the multi-terminal transistor T5 is not necessarily grounded.

[0072] exist Figure 3E In the embodiment of the present invention, the conductivity controllable unit C is composed of a resistive switch RW and a selector S connected in series. In the embodiment of the present invention, the selector can be implemented as a unipolar diode, a bipolar diode, octadecyltrichlorosilane (OTS), a metal-insulator-metal-film (the insulator can be aluminum oxide (Al2O3), transition metal oxides (transition metal oxides), etc.), a metal-insulator transition material (VO x , NbO x )wait.

[0073] Depend on FIG. 3A to FIG. 3E It can be seen that in the embodiment of the present invention, the conductivity controllable unit C can be a volatile element or a non-volatile element. The conductivity controllable unit C can be a single transistor, a floating gate transistor, a ferroelectric random access memory (FeRAM or FRAM), etc.

[0074] Furthermore, in a possible embodiment of the present invention, the conductivity controllable unit C may be a 2-terminal element or a multi-terminal element, one end of which is not necessarily grounded.

[0075] Figure 4 A voltage waveform diagram according to an embodiment of the present invention is shown. Figure 4 In FIG. 1 , Vread represents the read voltage to be applied to the word lines WL1 to WL3 when reading the resistive switch Y. The pulse width of the input voltage Vi must be sufficient to charge the bit line BL, and the application time of the output voltage Vo is within the application time of the input voltage Vi. The read voltage Vread and the input voltage Vi must be small enough to avoid changing the states of the resistive switches A, B, and Y.

[0076] In a possible embodiment of the present invention, the set voltage VSET may be between 0.5V and 3V, the input voltage Vi may be between 0.1V and 2V, the output voltage Vo may be between 0.3V and 5V, and the read voltage Vread may be between 0.02V and 1V. This is for illustration only and is not intended to limit the present invention.

[0077] Figure 5A circuit diagram showing a logic operation unit of a memory device according to an embodiment of the present invention. Figure 5 In the example, the logic operation unit also includes a transistor T A , T B With T Y . Transistor T A is coupled between the word line WL1 and the resistive switch A. The transistor TR is coupled between the word line WL2 and the resistive switch B. The transistor TY is coupled between the word line WL3 and the resistive switch Y. The conductance controllable unit C is composed of the transistor T C Implemented.

[0078] Below, an example of performing a NOR logic operation (Y=NOR(A, B)) on the logic states of the resistive switches A and B is used for explanation, wherein A=1 and B=0 are used for explanation.

[0079] Figure 6 Displays the signal waveform diagram for NOR operation.

[0080] exist Figure 6 In the timing P1, the transistor T is turned on. A A high voltage is applied to the word line WL1, so that the resistive switch A (A=1) can be programmed; the transistor T is turned off. B , so the resistive switch B is not programmed (B=0); the transistor T is turned off Y , turning on the transistor Taccess to charge the bit line BL.

[0081] In timing P2, the transistor T is turned on. A , T B With T Y ; A high level voltage is applied to the word lines WL1-WL3, and the initial conductance of the controllable conductance unit C is adjusted to a low conductance value to perform a NOR logic operation. At the timing P2, the state of the resistive switch Y will be: Y=NOR(A, B)=NOR(1,0)=0.

[0082] In the timing sequence P3, the state of the resistive switch Y is read. Therefore, in the timing sequence P3, the transistor T is turned off. A , T B ; Turn on transistor T Y and Taccess; and adjusting the conductivity of the conductivity controllable unit C to a high conductivity value G L (G L >>G HRS ); applying a small read voltage Vread to the word line WL3 to read out the current through the access transistor Taccess to obtain the logic state of the resistive switch Y.

[0083] In one embodiment of the present invention, the logic operation unit can be expanded by adding more resistive switches to perform user-defined logic operations. S is used as an example for illustration, but it should be understood that the present invention is not limited thereto.

[0084] Fig. 7A Display logical operations Circuit architecture diagram of the logic operation unit of S; Figure 7B Display logical operations Schematic diagram of the logic gate of S; Figure 7C Display logical operations The signal waveform of S. S, can be divided into 3 steps: the first step is to perform Y1 = NOR (A, B); the second step is to perform Y2 = NOR (Y1, S); the third step is to perform Y = NAND (Y1, Y2). Fig. 7A In the figure, S, Y1 and Y2 are resistive switches.

[0085] In the timing P4, the transistor T is turned on. A 、T B 、T Y1 A high level voltage is applied to the bit lines WL1, WL2 and WL4, and the conductivity value of the conductivity controllable unit C is set to a low conductivity value, so that Y1 = NOR (A, B) can be performed.

[0086] In the timing sequence P5, the transistor T is turned on. Y1 、T Y2 、T S A high level voltage is applied to the bit lines WL3, WL4 and WL5, and the conductivity value of the conductivity controllable unit C is set to a low conductivity value, so that Y2 = NOR (Y1, S) can be performed.

[0087] In the timing sequence P6, the transistor T is turned on. Y1 、T Y2 、T Y A high level voltage is applied to the bit lines WL4, WL5 and WL6, and the conductivity value of the conductivity controllable unit C is set to a high conductivity value, so that Y=NAND(Y1, Y2) can be performed.

[0088] Through the above description, the embodiments of the present invention can combine required logic operation units to perform user-defined logic operations.

[0089] Please refer to FIG. 8A to FIG. 8G , which shows a circuit diagram of a memory device according to multiple embodiments of the present invention.

[0090] like Fig. 8AAs shown, the memory device 800A includes a memory array 810, a plurality of bit lines BL1-BLN (N is a positive integer), a plurality of word lines WL1-WLM (M is a positive integer), and at least one conductivity controllable unit C. The memory array 810 is coupled to these bit lines BL1-BLN, these word lines WL1-WLM, and at least one conductivity controllable unit C. The memory array 810 includes a plurality of memory cells 820, wherein these memory cells 820 can be implemented by the above-mentioned resistive switches (such as resistive switches A, B and Y). That is, a memory cell group of these memory cells 820 (such as resistive switches A, B and Y) and the at least one conductivity controllable unit can form a logic operation unit. Alternatively, in other possible embodiments of the present invention, each of these memory cells 820 can be implemented by the above-mentioned resistive switches (such as resistive switches A, B and Y) connected in series with a selector or a transistor. Fig. 8A In the embodiment, a plurality of control lines (not shown) controlling the selectors or transistors of the memory cells 820 may be connected in parallel to the bit lines BL1 ˜BLN or to the word lines WL1 ˜WLM, thereby forming a semi-crossbar array.

[0091] like Figure 8B As shown, the memory device 800B includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductivity controllable cell C. Figure 8B In the embodiment, the conductance values ​​of these controllable conductivity cells C are controlled by the same conductance control line GCL to synchronously adjust the conductance of these controllable conductivity cells C; the conductance control line GCL is connected in parallel to the bit lines BL1 ˜BLN or the word lines WL1 ˜WLM to form a semi-crossbar array.

[0092] like Figure 8C As shown, the memory device 800C includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductance controllable cell C. Figure 8C In the embodiment, the conductivity control lines GCL1-GCLP (P is a positive integer) for controlling the conductivity controllable units C are independent of each other (i.e., not connected) to independently adjust the conductance of the conductivity controllable units C; the conductivity control lines GCL1-GCLP are connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM, thereby forming a semi-crossbar array.

[0093] like Fig.8D As shown, the memory device 800D includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductivity controllable cell C. Fig.8D In the embodiment, the conductance values ​​of the conductivity controllable cells C are controlled by the same conductance control line GCL to synchronously adjust the conductance of the conductivity controllable cells C; the conductance control line GCL is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM, thereby forming a semi-crossbar array. In addition, the memory device 800D further includes a conductance word line GWL, and the drain conductance word line GWL connected to the transistors of the conductivity controllable cells C is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM.

[0094] like Fig. 8E As shown, the memory device 800E includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductivity controllable cell C. Fig. 8E In the embodiment, the conductance control lines GCL1-GCLP for controlling the conductance controllable cells C are independent of each other (i.e., not connected) to independently adjust the conductance of the conductance controllable cells C; the conductance control lines GCL1-GCLP are connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM, thereby forming a semi-crossbar array. In addition, the memory device 800E further includes a conductance word line GWL connected to the drains of the transistors of the conductance controllable cells C, and the conductance word line GWL is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM.

[0095] like Figure 8F As shown, the memory device 800F includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductivity controllable cell C. Figure 8F In the embodiment, the conductance values ​​of the conductivity controllable cells C are controlled by a single conductivity control line GCL to synchronously adjust the conductance of the conductivity controllable cells C; the conductivity control line GCL is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM, thereby forming a semi-crossbar array. In addition, the memory device 800F further includes a conductivity word line GWL connected to the drains of the transistors of the conductivity controllable cells C, the conductivity word line GWL is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM. In addition, the memory device 800F further includes a conductivity tuning line GTL connected to the gates of the floating gate transistors of the conductivity controllable cells C, the conductivity tuning line GTL is connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM.

[0096] like Figure 8GAs shown, the memory device 800G includes a memory array 810, bit lines BL1-BLN, word lines WL1-WLM, and at least one conductivity controllable cell C. Figure 8G In the embodiment, the conductance control lines GCL1-GCLP controlling the conductance controllable cells C can be independent (not connected). The memory device 800G further includes a plurality of conductance adjustment lines GTL1-GTLP connected to the gates of the floating gate transistors of the conductance controllable cells C. The conductance control lines GCL1-GCLP are connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM, thereby forming a semi-crossbar array. The conductance adjustment lines GTL1-GTLP are connected in parallel to the bit lines BL1-BLN or in parallel to the word lines WL1-WLM. Thus, the conductance of the conductance controllable cells C can be adjusted independently. In addition, the memory device 800G further includes a conductance word line GWL connected to the drains of the transistors of the conductance controllable cells C, and the conductance word line GWL is connected in parallel to the bit lines BLI-BLN or in parallel to the word lines WL1-WLM.

[0097] In a possible embodiment of the present invention, the resistive switch may be a resistive random-access memory (RRAM, including metal oxide resistive memory (OxRAM), conductive-bridging RAM (CBRAM), etc.), a phase change memory (PCM), a spin-transfer torque MRAM (STT-MRAM), a spin-orbit torque MRAM (SOT-RAM), etc., all of which are within the spirit of the present invention.

[0098] In one possible embodiment of the present invention, the computing in memory logic operation unit can be repeatedly arranged to expand into a large area array. In fact, the array can be manufactured in a 2D or 3D structure. The operation of the array can depend on the customer's specific requirements, the resistive switch (optionally including selectors and / or transistors), and the circuit type (crossbar or semi-crossbar), etc., all of which are within the spirit of the present invention.

[0099] The above embodiment of the present invention discloses a memory device with in-memory computing function and an operation method using the same, which uses a resistive switch as a memory unit. The logical computing function (NAND and NOR) that the memory device can perform can be switched by controlling the conductance of these conductance controllable units. Therefore, the above embodiment of the present invention has the advantage of simplifying the computational complexity and the complexity of the peripheral circuits.

[0100] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0101] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, wherein: include: a memory array having a plurality of memory cells; a plurality of bit lines coupled to the memory array; a plurality of word lines coupled to the memory array; as well as A plurality of conductance controllable units are coupled to the memory array, Among them, a memory cell group of these memory cells and at least one conductivity-controllable unit of these conductivity-controllable units form a logic operation unit, and a logic operation function of the logic operation unit is determined by an equivalent conductance of the at least one conductivity-controllable unit; multiple input units of the memory cell group of the logic operation unit store input data of the logic operation function, and the output units of the memory cell group of the logic operation unit store output data of the logic operation function.

2. The memory device according to claim 1, wherein: The memory cells are multiple resistive switches; The plurality of input units of the memory cell group and the at least one conductivity controllable unit form a voltage dividing unit to determine a bit line voltage of a coupled bit line of the bit lines and determine a logic state of an output unit of the memory cell group; When the at least one conductivity controllable unit has a first equivalent conductivity value, the logic operation function of the logic operation unit is a first logic operation; as well as When the at least one conductivity controllable unit has a second equivalent conductivity value, the logic operation function of the logic operation unit is a second logic operation, wherein the first equivalent conductivity value is higher than the second equivalent conductivity value.

3. The memory device according to claim 2, wherein: The first logic operation is a NAND logic operation, and the second logic operation is a NOR logic operation.

4. The memory device according to claim 1, wherein: The logic operation unit also includes: An access transistor is coupled to the memory cell group and is used to provide a read current or a read voltage to read a state of an output cell of the memory cell group.

5. The memory device according to claim 1, wherein: The conductivity controllable unit is composed of any combination of the following: a transistor, a floating gate transistor, a resistive switch, a multi-terminal transistor and a selector.

6. The memory device according to claim 1, wherein: The conductance controllable units are controlled synchronously; or These conductance-controllable units are independently controlled.

7. A method for operating a memory device, wherein: include: Selecting a memory cell group of the plurality of memory cells of the memory device and at least one conductance controllable unit to form a logic operation unit; as well as Controlling an equivalent conductance of the at least one conductance controllable unit to determine a logic operation function of the logic operation unit; The plurality of input units of the memory unit group of the logic operation unit store input data of the logic operation function, and the output units of the memory unit group of the logic operation unit store output data of the logic operation function.

8. The method for operating a memory device according to claim 7, wherein: Each of these memory cells is a resistive switch; Controlling the equivalent conductance of the at least one conductance controllable unit to have a first equivalent conductance value so as to perform the logic operation function of the logic operation unit as a first logic operation; as well as The equivalent conductance of the at least one conductivity controllable unit is controlled to have a second equivalent conductance value to execute the logic operation function of the logic operation unit as a second logic operation, wherein the first equivalent conductance value is higher than the second equivalent conductance value.

9. The method for operating a memory device according to claim 8, wherein: The first logic operation is a NAND logic operation, and the second logic operation is a NOR logic operation; and The conductance controllable units are synchronously controlled, or the conductance controllable units are independently controlled.

10. The method for operating a memory device according to claim 8, wherein: The method further comprises: providing a read current or a read voltage by an access transistor of the logic operation unit to read a state of an output unit of the memory unit group.

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