Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of the invention relate to an integrated circuit (IC) device and a method of manufacturing the same, the IC device including a first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and a second plurality of active regions extending in the first direction and offset from the first direction. The first plurality of active regions is in the first direction and has a second pitch in the second direction. A ratio of the second pitch to the first pitch is 3:2.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] Integrated circuits (ICs) typically comprise multiple semiconductor devices, also known as IC devices. One way to represent an IC device is using a planar diagram called a layout or IC layout. IC layouts are hierarchical and include modules that perform high-level functions according to the IC device design specifications. Modules are typically composed of combinations of cells that may include standard and custom cells, each cell representing one or more semiconductor structures fabricated based on the IC layout.

[0003] The cell is configured to provide common, low-level functions, typically performed by transistors based on the gate region, which intersects with the active region, sometimes referred to as the oxide-defined (OD) region. The cell's elements are arranged within the cell boundary and electrically connected to other cells via interconnect structures. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, an integrated circuit device is provided, comprising: a first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction; and a second plurality of active regions extending in the first direction, offset from the first plurality of active regions in the first direction and having a second pitch in the second direction, wherein the ratio of the second pitch to the first pitch is 3:2.

[0005] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a first power rail and a second power rail extending in a first direction; a first plurality of active regions extending in the first direction; and a second plurality of active regions extending in the first direction and offset from the first plurality of active regions in the first direction, wherein the first power rail is electrically connected to a first active region in the first plurality of active regions and a first active region in the second plurality of active regions, the second power rail is electrically connected to a second active region in the first plurality of active regions and a second active region in the second plurality of active regions, the first plurality of active regions includes a third active region located between the first active region and the second active region and electrically connected to the second power rail, and the first active region and the second active region in the second plurality of active regions are adjacent active regions of the second plurality of active regions.

[0006] According to another aspect of the present invention, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction; and forming a second plurality of active regions extending in a first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction, wherein the ratio of the second pitch to the first pitch is 3:2. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A and Figure 1B This is a schematic diagram of an IC device according to some embodiments.

[0009] Figures 2A-2C These are diagrams of IC devices according to some embodiments.

[0010] Figure 3 This is a schematic diagram of an IC device according to some embodiments.

[0011] Figures 4A-4E This is a schematic diagram of an IC device according to some embodiments.

[0012] Figure 5 This is a flowchart of a method for manufacturing an IC device according to some embodiments.

[0013] Figure 6 This is a flowchart of a method for generating an IC layout diagram according to some embodiments.

[0014] Figure 7 It is a block diagram of a system generated based on IC layout diagrams of some embodiments.

[0015] Figure 8 This is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, operations, arrangements, etc., are also contemplated. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0018] In various embodiments, the IC device based on the IC layout includes a first region and a second region. In the first region, cell rows have a first pitch based on a first cell height, and in the second region, cell rows are aligned with the cell rows in the first region and have a second pitch based on a second cell height, thus being taller and having greater speed and power than the cells in the first region. Circuit designs that include relatively tall cells in the critical path and relatively short cells in the non-critical paths can therefore achieve higher speeds more effectively than designs that do not include relatively tall and short cells.

[0019] In various embodiments, the ratio of the second pitch to the first pitch is 3:2. Compared to methods that do not include adjacent regions with a 3:2 pitch ratio, the various embodiments are able to include relatively taller cell groups stacked in multiple rows, separate from relatively shorter cell groups stacked in multiple rows, thereby further improving circuit efficiency.

[0020] The following discussion Figures 1A-2C Floor plans of some embodiments are depicted. Figure 3 Cross-sectional views of some embodiments are depicted. Figures 4A-4E A non-restrictive example of cell configuration is depicted, and Figures 5-8 Features related to manufacturing-related embodiments are described.

[0021] The following discussion Figures 1A-4E Each of these is a structure / layout diagram, where reference numerals denote IC structural components and IC layout components. These IC structural components and IC layout components are used to at least partially define the corresponding IC structural components in a manufacturing process, such as the process described below. Figure 5 The methods discussed are 500 and / or related to the following. Figure 8 The IC manufacturing process associated with the IC manufacturing system 800 discussed. In some embodiments, Figures 1A-4E One or more of them are achieved by executing the following about Figure 6 The discussed method 600 involves some or all of the operations that generate some or all of the IC layout diagrams. Therefore, Figures 1A-4E Each of the diagrams represents the IC layout, plan view, or cross-sectional view of the corresponding structure as viewed from the corresponding perspective.

[0022] For illustrative purposes, each figure in this document (e.g.) Figures 1A-4E The figures are simplified. These figures are views of IC structures and devices that include and exclude various components for the purpose of facilitating the discussion below. In various embodiments, except... Figures 1A-4E The depicted components, IC structures, devices, and / or layout diagrams include one or more components corresponding to power distribution structures, metal interconnects, contacts, vias, gate structures or other transistor elements, isolation structures, etc.

[0023] Figure 1A and Figure 1B This is a schematic diagram of an IC device 100 according to some embodiments. Figure 1A A top-level planar view of IC device 100 is depicted, including the X and Y directions. Figure 1B A plan view of a portion of the IC device 100, along with its X and Y directions, and corresponding to the following... Figure 3 The lines A-A' and B-B' in the cross-sectional view are discussed.

[0024] IC device 100 includes regions 100A and 100B. Region 100A includes cell rows having cell height CHA (also referred to as pitch CHA in some embodiments) in the Y direction. Figure 1A and Figure 1B (Not shown independently), and region 100B includes a row of cells having a cell height CHB (also referred to as pitch CHB in some embodiments) in the Y direction. Figure 1A and Figure 1BIn the depicted embodiments, region 100A is adjacent to region 100B in the X direction, such that a subset or all of the cell rows in region 100A are aligned with a subset or all of the cell rows in region 100B in the X direction along at least one boundary (e.g., boundary 100AB) extending in the Y direction. In some embodiments, a subset or all of the cell rows in region 100A are aligned with a subset or all of the cell rows in region 100B in the X direction and are separated by a third region (e.g., an isolation structure) of the IC device 100.

[0025] The total height of the three cell rows in region 100A, 3 × cell height CHA, is equal to the total height of the two cell rows in region 100B, 2 × cell height CHB. Therefore, the ratio of cell height CHB to cell height CHA, also referred to in some embodiments as the pitch ratio of pitch CHB to pitch CHA, is equal to 3:2. In embodiments where the IC layout includes a pitch ratio equal to 3:2, the pitch ratio of the IC device 100 manufactured according to the IC layout has a value within a manufacturing tolerance of 3:2, also referred to in some embodiments as approximately equal to 3:2.

[0026] For the purpose of explanation, Figure 1A The illustrated embodiment of the IC device 100 is simplified. Figure 1A In the illustrated embodiment, a single instance of region 100A comprises a total of eight cell rows and surrounds a single instance of region 100B, which comprises two cell rows. In various embodiments, IC device 100 includes multiple instances of one or both of regions 100A or 100B, and / or an instance of one of regions 100A or 100B surrounds zero or more instances of the other of regions 100A or 100B. In various embodiments, a given instance of region 100A or 100B comprises a total number of cell rows equal to one, two, three, or more.

[0027] exist Figure 1A In the depicted embodiments, the entirety of IC device 100 and each of regions 100A and 100B includes cell rows. In various embodiments, one or more of IC device 100, region 100A, or region 100B include one or more unused portions, such as the gap between cells in a given cell row in the X direction or the gap in the Y direction being equal to half the cell height CHA and corresponding to an odd-numbered row of cells in region 100B. In some embodiments, IC device 100 includes one or more gaps corresponding to one or more components other than regions 100A and 100B, such as an IC structure having a configuration independent of cell rows, such as capacitor elements.

[0028] Figure 1BA portion of each of regions 100A and 100B along boundary 100AB is depicted. A portion of region 100A includes cell rows CA1-CA3 (indicated by the dashed boundary), each having a cell height CHA, and a portion of region 100B includes cell rows CB1 and CB2, each having a cell height CHB. In various embodiments, one or more of cell rows CA1-CA3 include a single cell or more than one cell, and / or one or more of cell rows CB1 or CB2 include a single cell or more than one cell.

[0029] Cell row CA1 includes active regions AA1 and AA2; cell row CA2 includes active regions AA3 and AA4; cell row CA3 includes active regions AA5 and AA6; cell row CB1 includes active regions AB1 and AB2; cell row CB2 includes active regions AB3 and AB4.

[0030] Active regions (areas), such as active regions AA1-AA6 or AB1-AB4, are included as part of the semiconductor substrate (e.g., as described below). Figure 3 The active region (structure, also referred to as active region AA1-AA6 or AB1-AB4) (also referred to as oxide diffusion or definition (OD)) is a region in the manufacturing process of the substrate 100 discussed, defined in an IC layout (e.g., an IC layout corresponding to IC device 100), forming one or more IC device components (e.g., source / drain regions) in the semiconductor substrate. In some embodiments, the active region is an n-type or p-type active region of a planar transistor, a FinFET, or a gate-all-around (GAA) transistor. In various embodiments, the active region (structure) includes one or more of the following: semiconductor materials, such as silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.; or dopant materials, such as potassium silicate, boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials.

[0031] In some embodiments, the active region is a region included in an IC layout diagram in a fabrication process that defines a nanosheet structure, such as a continuous volume of one or more layers of semiconductor material having n-type or p-type doping. In various embodiments, individual nanosheet layers comprise a single monolayer or multiple monolayers of a given semiconductor material.

[0032] Each of the active regions AA1, AA4, AA5, AB1, and AB3 is either n-type or p-type, and each of the active regions AA2, AA3, AA6, AB2, and AB4 is either n-type or p-type. At boundary 100AB, active region AA1 is continuous with active region AB1, active region AA3 is continuous with active region AB2, active region AA4 is continuous with active region AB3, active region AA6 is continuous with active region AB4, and each of active regions AA2 and AA5 is discontinuous.

[0033] exist Figure 1B In the illustrated embodiment, each of the continuous active region pairs AA1 / AB1, AA3 / AB2, AA4 / AB3, and AA6 / AB4 includes one of a top or bottom edge aligned in the X direction at boundary 100AB, such that the edge is continuous at boundary 100AB, and the other of the bottom or top edges is not aligned in the X direction, such that the other edge has discontinuity at boundary 100AB. In some embodiments, one or more of the continuous active region pairs AA1 / AB1, AA3 / AB2, AA4 / AB3, or AA6 / AB4 do not include a top or bottom edge aligned in the X direction at boundary 100AB, and each of the top and bottom edges thus includes discontinuity at boundary 100AB.

[0034] In some embodiments, as described below Figures 2A-2C The n-type active region is located in the p-well (as discussed). Figure 1B (not shown in the diagram) and / or the p-type active region is located in the n-well. In some embodiments, one or both of regions 100A or 100B of the IC device 100 do not include an n-well or a p-well.

[0035] Power rails PR1-PR4 extend across boundary 100AB in the X direction. Figure 2B In the illustrated embodiment, power rail PR1 extends along the top boundary of cell rows CA1 and CB1 and covers active regions AA1 and AB1; power rail PR2 extends along the boundary between cell rows CA1 and CA2, covering active regions AA2 and AA3, and enters cell row CB1, covering active region AB2; power rail PR3 extends along the boundary between cell rows CA2 and CA3, covering active regions AA4 and AA5, and enters cell row CB2, covering active region AB3; power rail PR4 extends along the bottom boundary of cell rows CA3 and CB2, covering active regions AA6 and AB4. In some embodiments, one or more of power rails PR1-PR4 do not cover one or more corresponding active regions AA1-AA4, AB1, or AB4, for example, they are adjacent to one or more corresponding active regions AA1-AA4, AB1, or AB4 in the Y direction.

[0036] Power rails (e.g., power rails PR1-PR4) are regions included in an IC layout diagram (e.g., an IC layout diagram corresponding to IC device 100) within a manufacturing process that defines a portion of the conductive structure. The conductive structure includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals, and / or one or more other materials suitable for providing a low-resistance path for a power supply or reference (e.g., ground) voltage. In some embodiments, the power rails correspond to a first metal layer of the manufacturing process, such as a metal zero layer or a metal layer.

[0037] In embodiments where each of active regions AA1, AA4, AA5, AB1, and AB3 is n-type and each of active regions AA2, AA3, AA6, AB2, and AB4 is p-type, power rails PR1 and PR3 are configured to carry a reference voltage, and power rails PR2 and PR4 are configured to carry a supply voltage. In embodiments where each of active regions AA1, AA4, AA5, AB1, and AB3 is p-type and each of active regions AA2, AA3, AA6, AB2, and AB4 is n-type, power rails PR1 and PR3 are configured to carry a supply voltage, and power rails PR2 and PR4 are configured to carry a reference voltage.

[0038] Based on the configurations discussed above and the following... Figures 2A-4E In a further discussed configuration, IC device 100 includes cell rows CA1-CA3 in region 100A, adjacent to cell rows CB1 and CB2 in region 100B, and the pitch ratio CHB to CHA is 3:2. Therefore, IC device 100 is capable of including relatively taller cell groups stacked in multiple rows, separate from relatively shorter cell groups stacked in multiple rows, resulting in improved circuit efficiency compared to methods excluding adjacent regions with a 3:2 pitch ratio.

[0039] Figures 2A-2C This is a partial diagram of an IC device 100 according to some embodiments. Figures 2A-2C Each of the diagrams depicts cell rows CA1 and CA2 of region 100A along boundary 100AB and in the X and Y directions, and portions of cell rows CB1 and CB2 of region 100B adjacent to region 100A. Figures 2A-2C In each of the depicted embodiments, the continuous active regions AA1 of cell row CA1 and AB1 of cell row CB1 are located in a well W1 that continuously crosses the boundary 100AB, and each of the active regions AA2 of cell row CA1 and the active regions AA3 of continuous cell row CA2 and AB2 of cell row CB1 are located in a well W2 that continuously crosses the boundary 100AB.

[0040] Well W1 is one of an n-type well or a p-type well, corresponding to the opposite p-type or n-type active regions AA1 and AB1. Well W2 is the other of an n-type well or a p-type well, corresponding to the opposite p-type or n-type active regions AA2, AA3, and AB2. In some embodiments, one of the n-type wells W1 or W2 corresponds to the other of the p-type substrate or epitaxial layer wells W1 or W2, or one of the p-type wells W1 or W2 corresponds to the other of the n-type substrate or epitaxial layer wells W1 or W2.

[0041] For the purpose of explanation, Figures 2A-2C Each of the following describes a single instance of each of wells W1 and W2. In various embodiments, IC device 100 includes one or more additional instances of well W1, such as instances where the consecutive active regions AA4 of cell row CA2 and AB3 of cell row CB2 are located, and / or one or more additional instances of well W2. See below for more details. Figures 2A-2C In each of the embodiments discussed, the width WWA of the well W2 in region 100A in the Y direction is greater than the width WWB in region 100B.

[0042] Wells W1 and W2, and in some embodiments, active regions AB1-AB3, have configurations at boundary 100AB corresponding to various embodiments of IC device 100, as follows regarding Figures 2A-2C The discussion is ongoing. In some embodiments, the configuration is based on a layout design of the IC device 100 that conforms to one or more minimum spacing rules, which apply to one or both of the wells W1 or W2 and one or more of the active regions AA1, AA2, AB1 or AB2.

[0043] Figures 2A-2C Each of the regions includes active regions AA1-AA4 with a width WA in the Y direction, and active regions AB1-AB3 with a width WB in the Y direction, where the width WB is greater than the width WA. As the width of the active region increases, the overall transistor channel width can increase, resulting in increased current, power, and speed. Therefore, the width WB being greater than the width WA corresponds to the transistors included in region 100B being larger, faster, and capable of handling greater power and generating more heat than the transistors included in region 100A.

[0044] In some embodiments, the width WB is 1.5 to 10 times larger than the width WA. In some embodiments, the width WB is 2 to 5 times larger than the width WA. In some embodiments, the width WA has a value ranging from 10 nanometers (nm) to 30 nm. In some embodiments, the width WB has a value ranging from 30 nm to 60 nm.

[0045] exist Figures 2A-2CIn the depicted embodiments, each active region in region 100A, such as active regions AA1-AA4, has the same width WA value, and each active region in region 100B, such as active regions AB1-AB3, has the same width WB value. In various embodiments, one or more active regions in region 100A have values ​​different from one or more values ​​of one or more other active regions 100A, and / or one or more active regions in region 100B have values ​​different from one or more values ​​of one or more other active regions 100B.

[0046] exist Figure 2A In the illustrated embodiment, wells W1 and W2 share a boundary (unmarked) extending along the X direction between active regions AA1 and AA2 in region 100A and between active regions AB1 and AB2 in region 100B, and include a discontinuity at boundary 100AB. Overall well W1 is positioned above active region AA2 in the Y direction, and overall well W2 is positioned below active region AB1 in the Y direction.

[0047] exist Figure 2A In the illustrated embodiment, the boundary in region 100A is positioned higher in the Y direction than the boundary in region 100B, such that width WWA is greater than width WWB and offset O1 in the Y direction corresponds to a discontinuity. In some embodiments, offset O1 corresponds to the boundary in region 100B positioned higher in the Y direction than the boundary in region 100A, such that width WWB is greater than width WWA.

[0048] In some embodiments, the boundary does not include discontinuities at boundary 100AB, the width WWA is equal to the width WWB, and the offset O1 has a zero value. In various embodiments, the offset O1 has a value that makes each of wells W1 and W2 a continuous well, the continuous wells conforming to the minimum spacing rule of the distance between the boundary in region 100A and active regions AA1 and AA2, and between the boundary and active regions AB1 and AB2 in region 100B. In some embodiments, the offset O1 has a value ranging from greater than 0 nm to 20 nm. In some embodiments, the offset O1 has a value ranging from greater than 0 nm to 10 nm.

[0049] exist Figure 2B In the embodiment shown, the boundary between wells W1 and W2 in region 100A is aligned with the bottom edge of active region AB1 in the X direction, and the boundary between wells W1 and W2 in region 100B is aligned with active region AA2 in the X direction, such that a portion of well W1 is lower than a portion of active region AA2 in the Y direction, and the width WWA is greater than the width WWB.

[0050] exist Figure 2BIn the illustrated embodiment, the offset O2 in the Y direction corresponds to a discontinuity in the boundary and includes portions of each of the well W2 and active regions AA2 in region 100A, which are partially aligned with the well W1 in region 100B in the X direction. In some embodiments, the offset O2 includes the entire active region AA2 in region 100A, which is partially aligned with the well W1 in region 100B in the X direction.

[0051] In various embodiments, offset O2 has a value that makes each of the wells W1 and W2 a consecutive well, the consecutive wells conforming to a minimum spacing rule between the boundary in region 100A and the active regions AA1 and AA2, and between the boundary and regions AB1 and AB2 in region 100B. In some embodiments, offset O2 has a value that allows the width WB to adapt to the target component size (e.g., the number of fins). In some embodiments, offset O2 has a value ranging from 5 nm to 50 nm. In some embodiments, offset O2 has a value ranging from 10 nm to 30 nm.

[0052] exist Figure 2C In the depicted embodiment, the middle portion of each active region AB1-AB3 has a width WB, and the ends of each active region AB1-AB3 have a width WA. Each active region AA1 / AB1, AA3 / AB2, and AA4 / AB3 thus includes each of a top edge and a bottom edge aligned in the X direction at boundary 100AB, such that each edge is continuous at boundary 100AB.

[0053] The ends of the active regions AB1-AB3 with width WA extend offset O3 from boundary 100AB in the X direction. Figure 2C In the depicted embodiment, each active region (e.g., active regions AB1-AB3) in region 100B has the same offset O3 value. In some embodiments, the value of one or more active regions in region 100B differs from one or more offset O3 values ​​of one or more other active regions in region 100B.

[0054] In some embodiments, the value of offset O3 is equal to half the gate pitch of IC device 100, which is also referred to as cell polysilicon pitch (CPP) in some embodiments. The gate pitch corresponds to the spacing between adjacent gate structures of IC device 100, and an offset O3 value equal to half the gate pitch is beneficial for uniformity between regions 100A and 100B, thereby supporting manufacturability in some embodiments.

[0055] exist Figure 2C In the depicted embodiment, the IC device 100 includes wells W1 and W2 in regions 100A and 100B whose boundaries are aligned in the X direction, as described above. Figure 2BThe discussion focuses on the boundary in region 100B being offset from boundary 100AB in the X direction by a distance less than offset O3. The trap W2 thus comprises a first portion in region 100B adjacent to boundary 100AB with a width WWA and a second portion in region 100B with a width WWB. The overall active region AA2 is thus aligned in the X direction with the first portion of trap W2 in region 100B.

[0056] exist Figures 2A-2C In each of the depicted embodiments, well W2 and another well (not shown) located below well W2 in the Y direction, such as a second instance of well W1 inverted in the Y direction, share a boundary that extends in the X direction and is continuous at boundary 100AB. In some embodiments, the shared boundary includes a discontinuity at boundary 100AB, such that there is an offset (not shown) in the Y direction.

[0057] Based on the above... Figures 2A-2C In the configuration discussed, IC device 100 can include cell rows CA1-CA3 in region 100A, with cell rows CA1-CA3 adjacent to cell rows CB1 and CB2 in region 100B, as described above, thereby enabling the implementation of the above-mentioned... Figure 1A and Figure 1B Benefits of the discussion.

[0058] Figure 3 This is a schematic diagram of an IC device 100 according to some embodiments. Figure 3 Includes the Y and Z directions, and depicts cross-sectional views corresponding to the following two YZ planes: corresponding to Figure 1B The YZ plane at the X-coordinate position XA of cell row CA1 and line A-A' in the depicted area 100A corresponds to... Figure 1B The depicted region 100B is defined by the cell row CB1 and the line B-B' in the YZ plane at the X-coordinate position XB. The two YZ planes are therefore defined by the boundary 100AB ( Figure 3 (Not shown in the image) Separation.

[0059] The cross-sectional view of region 100A includes element height CHA, the cross-sectional view of region 100B includes element height CHB, and each cross-sectional view includes power rails PR1 and PR2, each with a height of CHB. Figure 1A and Figure 1BThe following were discussed. Each cross-sectional view also includes an example of a via VD located below power rails PR1 and PR2 in the Z direction, an example of a conductive region MD located below the example of via VD in the Z direction, and a substrate 100S. The cross-sectional view of region 100A includes examples of epitaxial structures EA1-EA3 between the example of conductive region MD and the substrate 100S, and the cross-sectional view of region 100B includes examples of epitaxial structures EB1 and EB2 between the example of conductive region MD and the substrate 100S.

[0060] In some embodiments, the epitaxial layers, such as EA1-EA3, EB1, or EB2, are also referred to as source / drain (S / D) regions, which include one or more semiconductor material volumes having a crystal structure different from that of the substrate 100S, for example, by including one or more materials having a doping type and / or orientation different from that of the substrate 100S.

[0061] A conductive region (MD) is a region included in the IC layout diagram during the manufacturing process as a portion of a defined metal-like segment. Also referred to as a conductive segment, MD segment, or MD conductive line or trace, it is located within and / or on a semiconductor substrate (e.g., substrate 100S) and / or an S / D structure (e.g., epitaxial layers EA1-EA3, EB1, or EB2). In some embodiments, the MD segment includes a portion of at least one metal layer (e.g., a contact layer) that covers and contacts the substrate and has a sufficiently small thickness to allow an insulating layer to be formed between the MD segment and an overlying metal layer (e.g., a first metal layer). In various embodiments, the MD segment includes copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or other metallic materials or materials suitable for providing low-resistance electrical connections between IC structural elements. In various embodiments, the MD segment includes an epitaxial layer having a doping level (e.g., based on an implantation process) sufficient to give the segment a low resistance level. In various embodiments, the doped MD segment includes one or more of Si, SiGe, SiC, B, P, As, Ga, metals, or other materials suitable for providing a low resistance level. In various embodiments, the conductive region MD at least partially defines part or all of the MD segment corresponding to one or more S / D structures included in one or more transistors.

[0062] A via (e.g., via VD) is a region included in an IC layout (e.g., an IC layout corresponding to IC device 100) within a manufacturing process that defines a via structure. This via structure includes one or more conductive materials as discussed above with respect to power rails PR1-PR4. The via structure is configured to provide an electrical connection between an upper conductive structure (e.g., a power rail) and a lower conductive structure (e.g., a conductive region MD).

[0063] exist Figure 3 In the depicted embodiment, cell row CA1 includes an epitaxial layer EA1 electrically connected to power rail PR1 via a first instance of conductive region MD and via VD, and an epitaxial layer EA2 electrically connected to power rail PR2 via a second instance of conductive region MD and via VD. A first portion of power rail PR1 covers epitaxial layer EA1, and a second portion of power rail PR1 extends out of cell row CA1 in the Y direction and is disposed on substrate 100S. A first portion of power rail PR2 covers epitaxial layer EA2, and a second portion of power rail PR2 extends out of cell row CA1 in the Y direction and is disposed on substrate 100S between epitaxial layers EA2 and EA3. Cell row CA1 thus does not include the entire width of either power rail PR1 or PR2 in the Y direction, and does not include the portion of power rail PR1 or PR2 located on substrate 100S between epitaxial layers EA1 and EA2.

[0064] Cell row CB1 includes an epitaxial layer EB1 electrically connected to power rail PR1 via a third instance of conductive region MD and via VD, and an epitaxial layer EB2 electrically connected to power rail PR2 via a fourth instance of conductive region MD and via VD. A first portion of power rail PR1 is disposed on epitaxial layer EB1, and a second portion of power rail PR1 extends out of cell row CB1 in the Y direction and is disposed on substrate 100S. A first portion of power rail PR2 is disposed on epitaxial layer EB2, and a second portion of power rail PR2 extends in the Y direction within cell row CB1 and is disposed on substrate 100S between epitaxial layers EB1 and EB2. Cell row CB1 thus includes the entire width of power rail PR2 in the Y direction and includes the second portion of power rail PR2 disposed on substrate 100S between epitaxial layers EB1 and EB2.

[0065] Based on the above... Figure 3 In the configuration discussed, IC device 100 can include cell rows CA1-CA3 in region 100A, with cell rows CA1-CA3 adjacent to cell rows CB1 and CB2 in region 100B, as described above, thereby enabling the implementation of the above-mentioned... Figure 1A and Figure 1B Benefits of the discussion.

[0066] Figures 4A-4E These are diagrams of IC devices 400A-400C according to some embodiments. Figure 4A The depicted IC device 400A is a non-limiting example of a single-cell height inverter array that can be included in either region 100A or 100B. Figure 4BThe depicted IC device 400B is a non-limiting example of a dual-cell height inverter array that can be included in either region 100A or 100B. Figures 4C-4E The depicted IC device 400C is a non-limiting example of a three-cell height trigger that can be included in region 100A.

[0067] exist Figure 4A In the non-limiting example shown, IC device 400A either includes active regions AA1 and AA2 and has a cell height CHA corresponding to region 100A, or includes active regions AB1 and AB2 and has a cell height CHB corresponding to region 100B. IC device 400A includes six instances of three conductive regions MD disposed on active regions AA1 or AB1, three conductive regions MD disposed on active regions AA2 or AB2, two conductive regions MD disposed on active regions AA1 and AA2 or AB1 and AB2, and a gate G disposed on active regions AA1 and AA2 or AB1 and AB2.

[0068] A gate (e.g., gate G) is a region included in an IC layout (e.g., an IC layout corresponding to IC device 100) in a manufacturing process that defines a portion of the gate structure. The gate structure is a volume comprising one or more conductive segments (e.g., gate electrodes) including one or more conductive materials (e.g., polysilicon) substantially surrounded by one or more insulating materials, one or more metals, and / or one or more other suitable materials, wherein the one or more conductive segments are thereby configured to control the voltage supplied to the underlying gate dielectric layer.

[0069] A dielectric layer (e.g., a gate dielectric layer) is a volume comprising one or more insulating materials (e.g., silicon dioxide) and / or one or more other suitable materials (e.g., low-k materials with a k value less than 3.8 or high-k materials with a k value greater than 3.8), wherein the one or more insulating materials are suitable for providing high resistance between IC structural elements, i.e., resistance levels higher than a predetermined threshold corresponding to one or more tolerance levels based on the impact of resistance on circuit performance.

[0070] Apart from Figure 4A In addition to the components depicted, IC device 400A includes conductive components (e.g., examples of vias, such as those mentioned above). Figure 3 The discussed via (VD) is configured to provide electrical connections between instances of conductive regions MD and power rails PR1 and PR2, and between instances of gates G configured to propagate one or more electrical signals and conductive regions MD, as well as one or more conductive segments. IC device 400A includes... Figure 4A The depicted components and additional components arranged as an array of four inverters.

[0071] exist Figure 4BIn the non-limiting example shown, IC device 400B either includes active regions AA1-AA4 and has twice the cell height CHA corresponding to region 100A, or includes active regions AB1-AB4 and has twice the cell height CHB corresponding to region 100B. IC device 400B includes two instances of conductive regions MD placed on active regions AA1 or AB1, two instances of conductive regions MD placed on active regions AA2 or AB2, two instances of conductive regions MD placed on active regions AA3 or AB3, two instances of conductive regions MD placed on active regions AA3 or AB3, two instances of conductive regions MD placed on active regions AA4 or AB4, one instance of conductive regions MD placed on active regions AA1 and AA2 or AB1 and AB2, one instance of conductive regions MD placed on active regions AA3 and AA4 or AB3 and AB4, two instances of gates G placed on active regions AA1 and AA2 or AB1 and AB2, two instances of gates G placed on active regions AA3 and AA4 or AB3 and AB4, and two instances of gates G placed on each of active regions AA1-AA4 or AB1-AB4.

[0072] Apart from Figure 4B In addition to the components depicted, IC device 400B includes conductive components (e.g., examples of vias, such as those mentioned above). Figure 3 The discussed via (VD) is configured to provide electrical connections between instances of conductive regions MD and subsets of power rails PR1-PR4, and between a gate G configured to propagate one or more electrical signals and instances of one or more conductive regions MD. IC device 400B includes... Figure 4B The depicted components and additional features are arranged as an array of four inverters.

[0073] With the above configuration, each of the IC devices 400A and 400B includes some or all of the active regions AA1-AA4 of region 100A of IC device 100, or some or all of the active regions AB1-AB4 of region 100B of IC device 100. The IC device 400A implemented in region 100A is thus configured to have device performance equivalent to that of the IC device 400B implemented in region 100A, and the IC device 400A implemented in region 100B is thus configured to have device performance equivalent to that of the IC device 400B implemented in region 100B.

[0074] IC device 400A has a width in the X direction corresponding to five times the gate pitch of the gate G, and a height in the Y direction equal to the height of a single cell CHA or CHB. IC device 400B has a width in the X direction corresponding to three times the gate pitch, and a height in the Y direction equal to twice the height of a cell CHA or CHB. IC device 400A can thus have a smaller area than IC device 400B. Because IC device 400B includes a total of ten instances of conductive regions MD and IC device 400A includes a total of eight instances of conductive regions MD, IC device 400B can have greater wiring flexibility than IC device 400A.

[0075] IC devices based on a design process that includes IC devices capable of being included in regions 100A and / or 100B (e.g., one or more instances of IC devices 400A and / or 400B) (e.g., the IC devices mentioned above) Figures 1A-3 The discussed IC device 100 enables a more efficient combination of area and performance design goals compared to IC devices based on other design methods. IC devices 400A and 400B are non-limiting examples provided for illustrative purposes. In various embodiments, one or more IC devices having configurations different from those of IC devices 400A and 400B can be included in regions 100A and / or 100B of IC device 100, thereby enabling a more efficient combination of area and performance design goals compared to IC devices based on other design methods.

[0076] exist Figures 4C-4E In the depicted non-limiting example, IC device 400C includes active regions AA1-AA6 and power rails PR1-PR4, each of which is above IC device 100 and Figures 1A-3 The discussion took place. IC device 400C corresponds to... Figure 4C The diagram depicted Figure 4D The layout of back-end process (BEOL) components is depicted. Figure 4E The trigger circuits depicting the arrangement of intermediate process (MEOL) and / or front-end process (FEOL) components.

[0077] like Figure 4CAs shown in the schematic diagram, IC device 400C includes circuit sections P1-P7, each of which includes one or more PMOS transistors (unlabeled) and one or more NMOS transistors (unlabeled). Section P1 is a selection circuit configured to receive external signals SI, SE, and D, and signal SEB from section P5, and output signals mx1 and mx2 in response to signals SI, SE, SEB, and D. Section P2 is a main switch configured to receive signals mx1 and mx2 from section P1, signal mlb from section P3, clock signal cb from section P6, and clock signal cbb from section P7, and output signal mxx in response to signals mx1 and mx2 and clock signals cb and cbb. Part P3 is a switch configured to receive signal mxx from part P2, signal slbx from part P4, clock signal cb from part P6, and clock signal cbb from part P7, and output signals mlb and sla in response to signals mxx and slbx and clock signals cb and cbb. Part P4 is an output circuit configured to receive signal sla and output signals slbx and Q in response to signal sla. Part P5 is an inverter configured to receive signal SE and output signal SEB in response to signal SE; part P6 is an inverter configured to receive clock signal CP and output clock signal cb in response to clock signal CP; part P7 is an inverter configured to receive clock signal cb and output clock signal cbb in response to clock signal cb.

[0078] like Figure 4D As depicted, portions P1 and P7 of IC device 400C are positioned adjacent to each other between power rails PR4 and PR3, portions P2 and P6 are positioned adjacent to each other between power rails PR3 and PR2, portions P3 and P5 are positioned adjacent to each other between power rails PR2 and PR1, and portion P4 is positioned adjacent to portions P2 and P3 between power rails PR3 and PR1.

[0079] In addition to the corresponding portions including power rails PR1-PR4, each of portions P1-P7 of IC device 400C includes the above-mentioned... Figure 4A and Figure 4B The discussion refers to part or all of one or more instances of each of the gate G, metal segment M1, via V1, and metal segment M2. For clarity, individual instances of each of the gate G, via V1, and metal segments M1 and M2 are labeled.

[0080] Metal segment M1 is a conductive structure located in the same layer as the power rails PR1-PR4, such as a first metal layer or a zero metal layer. Metal segment M2 is a conductive structure located in a metal layer above metal segment M1 and power rails PR1-PR4, such as a second metal layer or a first metal layer. Through-hole V1 is a through-hole structure located between metal segments M1 and M2, and is configured to electrically connect metal segments M1 and M2 to each other.

[0081] like Figure 4E The described IC device 400C also includes the above-mentioned... Figure 3 Examples of conductive segments MD and vias VD, as well as gate vias VG, are discussed. For clarity, a single example of each of the conductive segments MD, vias VD, and gate vias VG is labeled.

[0082] A gate via VG is a via structure located between the gate G and the metal section M1 and configured to electrically connect the gate electrode of the gate G and the metal section M1 to each other.

[0083] IC device 400C has a width in the X direction that is seven times the gate pitch corresponding to the gate G and a height in the Y direction that is three times the cell height CHA. Therefore, IC device 400C can have a smaller area than flip-flop circuits in other methods (e.g., methods where the height in the Y direction is equal to one or two times the cell height). IC device 400C is a non-limiting example provided for illustrative purposes. In various embodiments, one or more IC devices having a configuration different from IC device 400C include a height greater than twice the cell height, and are therefore able to have a smaller area than methods that do not include a height greater than twice the cell height.

[0084] Based on, such as, those that can be included in area 100A Figures 4C-4E The design process of IC device 400C is described (e.g., the IC device mentioned above). Figures 1A-3 The IC device 100 discussed can therefore have a smaller area than IC devices based on other design methods (e.g., methods where the height in the Y direction is limited to a multiple of one or two).

[0085] Figure 5 This is a flowchart of a method 500 for manufacturing an IC device according to some embodiments. Method 500 can be used to form the above-mentioned... Figures 1A-3 The IC device 100 discussed and / or the above reference Figures 4A-4E The IC devices discussed are 400A-400C.

[0086] In some embodiments, the operation of method 500 is as follows: Figure 5 The described order of execution. In some embodiments, the operation of method 500 is different from... Figure 5The operations are performed sequentially. In some embodiments, one or more additional operations are performed before, during, and / or after the operation of method 500.

[0087] In some embodiments, performing some or all of the operations of method 500 includes performing the following operations regarding IC manufacturing system 800 and Figure 8 One or more operations are being discussed.

[0088] At operation 510, in some embodiments, a first well is formed in the semiconductor substrate. Forming the first well includes performing one or more fabrication operations, such as deposition, implantation, or other processes suitable for forming a doped region in the substrate.

[0089] In various embodiments, forming a first well includes forming an n-well in a p-type substrate or epitaxial layer, or forming a p-well in an n-type substrate or epitaxial layer. In some embodiments, forming a first well includes forming a first well and a second well in a substrate or epitaxial layer, the first well and the second well comprising an n-well and a p-well.

[0090] In some embodiments, forming the first well includes forming a first well having a first width in a first region and a second width in a second region adjacent to the first region, wherein the first width is greater than the second width. In some embodiments, forming the first well includes forming a well W1 having a width WWA in region 100A and a width WWWB in region 100B, as described above. Figures 2A-2C Discussed. In some embodiments, forming the first well includes forming each of wells W1 and W2 in regions 100A and 100B, as discussed above. Figures 2A-2C Discussed.

[0091] In some embodiments, forming a first well includes forming a first portion in a first region and forming a second portion in a second region, the first portion and the second portion being separated by an IC structure (e.g., an isolation structure).

[0092] At operation 520, a first plurality of active regions and a second plurality of active regions are formed in the substrate. Forming the first plurality of active regions and the second plurality of active regions includes forming one or more active regions (e.g., as described above regarding...). Figures 1A-4E The active regions AA1-AA6 and AB1-AB4 discussed perform one or more manufacturing operations, such as deposition and / or injection processes.

[0093] The formation of the first plurality of active regions includes the first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and the formation of the second plurality of active regions includes the second plurality of active regions extending in the first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction. The ratio of the second pitch to the first pitch is 3:2.

[0094] In some embodiments, forming the first plurality of active regions and the second plurality of active regions includes forming active regions AA1-AA6 with pitch CHA and active regions AB1-AB4 with pitch CHB, as described above. Figures 1A-3 Discussed.

[0095] In some embodiments, forming the first plurality of active regions includes forming first and second active regions in a well, such as forming active regions AA2 and AA3 in well W1, as described above. Figures 2A-2C The discussion focuses on the formation of a second plurality of active regions, including the first active region of the second plurality of active regions formed in the well and continuous with the first active region of the first plurality of active regions. For example, active region AB2 is formed in well W1, as discussed above. Figures 2A-2C Discussed.

[0096] At operation 530, in some embodiments, a first plurality of transistors including a first plurality of active regions are formed, and a second plurality of transistors including a second plurality of active regions are formed. Forming the first and second plurality of transistors includes performing one or more of a plurality of fabrication operations, such as photolithography, diffusion, deposition, etching, planarization, or other operations suitable for constructing a gate structure adjacent to and disposed on the active regions of a semiconductor wafer. In various embodiments, forming the first and second plurality of transistors includes forming planar transistors, FinFET transistors, GAA transistors, or other suitable IC devices.

[0097] In various embodiments, forming the first and second plurality of transistors includes forming an S / D structure in and / or on the first and second plurality of active regions (e.g., as mentioned above). Figure 3 The discussed epitaxial structures EA1-EA3, EB1, and EB2), and the conductive structures on the S / D structure (e.g., those mentioned above) Figures 3-4E The conductive region (MD) discussed, and the gate structure (e.g., the one mentioned above) Figures 4A-4E The gate (G) discussed and via structures (e.g., those mentioned above) Figures 3-4E The discussion focuses on through-holes (VD and VG) to perform one or more manufacturing operations.

[0098] At operation 540, in some embodiments, an electrical connection is constructed to each of the first and second plurality of transistors, the electrical connection including a plurality of power rails. Constructing the electrical connection includes constructing a plurality of conductive structures configured to propagate one or more electrical signals and / or power levels.

[0099] Forming a conductive structure (e.g., gate or drain via, signal line, metal line, power rail, etc.) includes performing multiple fabrication operations (including depositing and patterning one or more photoresist layers), performing one or more etching processes, and performing one or more deposition processes, thereby configuring one or more conductive materials to form a continuous low-resistance structure surrounded by one or more continuous dielectric layers, whereby the continuous low-resistance structure is selectively electrically connected to or electrically isolated from various adjacent components. In some embodiments, forming the conductive structure includes performing a damascene or dual damascene process.

[0100] In some embodiments, constructing an electrical connection includes constructing the above reference. Figures 3-4E The discussion includes one or more of the through holes VD, VG, or V1 and the metal segments MD, M1, or M2.

[0101] In some embodiments, constructing an electrical connection including multiple power rails includes constructing the above-mentioned... Figures 1B-4E The power rails PR1-PR4 are discussed. In some embodiments, constructing multiple power rails includes constructing power rails that are placed on the first and second active regions of the first plurality of first active regions and the first active region of the second plurality of active regions, for example, constructing power rails as described above. Figure 1B The power rail PR2 is placed on the active regions AA2, AA3 and AB2.

[0102] By performing some or all of the operations of method 500, an IC device comprising a first region is manufactured, the first region comprising a first plurality of active regions having a first pitch, the first plurality of active regions being offset from a second plurality of active regions having a second pitch, thereby obtaining the benefits discussed above with respect to IC devices 100 and 400A-400C.

[0103] Figure 6 This is a flowchart of a method 600 for generating an IC layout diagram corresponding to an IC device according to some embodiments, such as the one mentioned above. Figures 1A-4E The IC layout diagram / device 100 or 400A-400C is discussed.

[0104] In some embodiments, some or all of method 600 is executed by a computer processor, such as processor 702 of IC design system 700, as described below. Figure 7 Discussed.

[0105] Some or all of the operations of method 600 can be performed in the design room (e.g., as described below). Figure 8 The portion of the design procedure executed in the design room 820 (discussion design room) is executed.

[0106] In some embodiments, the operation of method 600 is as follows: Figure 6The operations of method 600 are executed sequentially. In some embodiments, the operations of method 600 are performed simultaneously and / or in a manner different from those described above. Figure 6 The operations are performed sequentially in the order described in the instructions. In some embodiments, one or more operations are performed before, between, during, and / or after one or more operations of method 600.

[0107] At operation 610, in some embodiments, a first well is defined in the IC layout diagram. In various embodiments, defining the first well includes defining an n-well in a p-type substrate or epitaxial layer, or defining a p-well in an n-type substrate or epitaxial layer. In some embodiments, defining the first well includes defining a first well and a second well in a substrate or epitaxial layer, the first well and the second well comprising an n-well and a p-well.

[0108] In some embodiments, defining the first well includes defining a first portion and a second portion of the first well in corresponding first and second regions of the IC layout diagram, such as those mentioned above. Figures 1A-4E Regions 100A and 100B of the IC device 100 under discussion.

[0109] In some embodiments, defining the first well includes defining a first well having a first width in a first region and a second width in a second region adjacent to the first region, wherein the first width is greater than the second width. In some embodiments, defining the first well includes defining a well W1, which has a width WWA in region 100A and a width WWB in region 100B, as described above. Figures 2A-2C Discussed.

[0110] In some embodiments, defining the first well includes defining each of wells W1 and W2 in regions 100A and 100B, as described above. Figures 2A-2C Discussed.

[0111] In some embodiments, defining a first well includes a first portion defining a first region and a second portion defining a second region, the first portion and the second portion being separated by a region defining an IC structure, such as an isolation structure defining an IC structure.

[0112] At operation 620, a first plurality of active regions are arranged in the first region of the IC layout diagram, and a second plurality of active regions are arranged in the second region of the IC layout diagram. The ratio of the second pitch of the second plurality of active regions to the first pitch of the first plurality of active regions is 3:2.

[0113] Arranging a first plurality of active regions includes the first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction, and arranging a second plurality of active regions includes the second plurality of active regions extending in a first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction.

[0114] In some embodiments, arranging the first plurality of active regions and the second plurality of active regions includes arranging the first plurality of active regions and the second plurality of active regions in corresponding first and second regions of the IC layout diagram, such as the above regarding... Figures 1A-4E Regions 100A and 100B of the IC device 100 under discussion.

[0115] In some embodiments, arranging the first plurality of active regions and the second plurality of active regions includes arranging active regions AA1-AA6 having a pitch CHA and forming active regions AB1-AB4 having a pitch CHB, as described above. Figures 1A-3 Discussed.

[0116] In some embodiments, arranging the first plurality of active regions includes a first active region and a second active region defining the first plurality of active regions in a well, for example, defining active regions AA2 and AA3 in well W1, as described above. Figures 2A-2C The discussion focuses on arranging a second plurality of active regions, which includes a first active region defining the second plurality of active regions within a well and being continuous with the first active region of the first plurality of active regions. For example, an active region AB2 is defined within well W1, as described above. Figures 2A-2C As discussed.

[0117] At operation 630, a first plurality of units having a first unit height equal to the first pitch are placed in the first region, and a second plurality of units having a second unit height equal to the second pitch are placed in the second region.

[0118] In some embodiments, placing a first plurality of cells having a first cell height in a first region and placing a second plurality of cells having a second cell height in a second region includes placing one or more of cell rows CA1-CA3 having cell height CHA in region 100A and placing one or both of cell rows CB1 and CB2 having cell height CHB in region 100B, as described above regarding Figures 1A-3 Discussed.

[0119] In various embodiments, placing a first plurality of cells having a first cell height in a first region includes placing one or more cells with a total height equal to or twice the cell height, such as IC devices 400A and / or 400B based on cell height CHA, as per [reference to...]. Figure 4A and Figure 4B The discussed, and / or one or more cells having a height greater than twice the cell height, for example, regarding Figures 4C-4E The IC device under discussion is 400C.

[0120] In various embodiments, placing a second plurality of cells having a second cell height in a second region includes placing one or more cells with a total height equal to or twice the cell height, such as IC devices 400A and / or 400B based on cell height CHB, as described below. Figure 4A and Figure 4B The discussed cells, and / or one or more cells, have a cell height greater than twice that of the cell height, such as multiple times the cell height CHB.

[0121] In some embodiments, placing a first plurality of cells having a first cell height in a first region and placing a second plurality of cells having a second cell height in a second region includes determining that one or more of the second plurality of cells are included in the timing critical path of the IC device corresponding to the IC layout diagram.

[0122] A timing-critical cell is a part of the timing-critical path of an IC device. One or more transistors within the timing-critical cell have a significant impact on the performance of timing-dependent cells. The significance of this impact on performance is based on one or more predetermined criteria, such as rise time, fall time, switching speed, and circuit bandwidth.

[0123] In various embodiments, determining that a cell is part of the timing-critical path of an IC device is performed by receiving user input and / or by executing one or more algorithms (e.g., one or more circuit simulations) based on a layout design that corresponds to some of the total IC layout diagram of the IC device including the cell.

[0124] In various embodiments, determining that a cell is a timing-critical path of an IC device is partly based on one or more manufacturing recipe parameters, one or more circuit performance specifications, and / or one or more circuit configuration criteria, such as parallel or series transistor arrangements.

[0125] In some embodiments, placing a first plurality of units having a first unit height in a first region and placing a second plurality of units having a second unit height in a second region includes defining a plurality of power rails that overlap with each of the first and second regions, for example, defining the above regarding Figures 1A-4E The power rails PR1-PR4 are discussed.

[0126] At operation 640, an IC layout diagram is generated, and in some embodiments, the IC layout diagram is stored in a storage device. In some embodiments, generating the IC layout diagram includes using an IC design system (e.g., IC design system 700, as described below). Figure 7 (Discussion) To generate electronic files in GDSII, DFII or other suitable formats.

[0127] In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile computer-readable storage medium or a cell library (e.g., a database), and / or includes storing the IC layout diagram via a network. In some embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in the IC design memory 707 or via the network 714 of the IC design system 700, as described below. Figure 7 Discussed.

[0128] At operation 650, in some embodiments, at least one or more components of one or more semiconductor masks are fabricated in a layer of the semiconductor IC based on an IC layout diagram. (See below for reference.) Figure 8 Discuss fabricating one or more semiconductor masks or at least one component in a layer of a semiconductor IC.

[0129] At operation 660, in some embodiments, one or more manufacturing operations are performed based on an IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more photolithography exposures based on an IC layout diagram. Performing one or more manufacturing operations based on an IC layout diagram, such as one or more photolithography exposures, will be discussed below regarding... Figure 8 Let's have a discussion.

[0130] By performing some or all of the operations of method 600, an IC layout diagram is generated corresponding to the IC device including a first region, the first region including a first plurality of active regions having a first pitch offset from a second plurality of active regions, thereby obtaining the benefits discussed above regarding IC devices 100 and 400A-400C.

[0131] Figure 7 This is a block diagram of an IC design system 700 according to some embodiments. According to some embodiments, such as using the IC design system 700, the methods described herein for designing IC layout diagrams according to one or more embodiments are implementable. In some embodiments, the IC design system 700 is an APR system that can be used to perform APR methods, including an APR system or a portion thereof.

[0132] In some embodiments, the IC design system 700 is a general-purpose computing device including a hardware processor 702 and a non-transitory computer-readable storage medium 704. The storage medium 704 is encoded (i.e., stored) with computer program code 706, a set of executable instructions, among other things. Execution (at least partially) of the instructions 706 by the hardware processor 702 represents an EDA tool that implements part or all of a method, such as the method 600 for generating the IC layout diagram described above (the process and / or method mentioned below).

[0133] Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708. Processor 702 is also electrically coupled to I / O interface 710 via bus 708. Network interface 712 is also electrically connected to processor 702 via bus 708. Network interface 712 is connected to network 714, enabling processor 702 and computer-readable storage medium 704 to be connected to external components via network 714. Processor 702 is configured to execute computer program code 706 encoded in computer-readable storage medium 704 to make IC design system 700 available for performing some or all of the processes and / or methods. In one or more embodiments, processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0134] In one or more embodiments, the computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 704 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0135] In one or more embodiments, storage medium 704 stores computer program code 706 configured to enable IC design system 700 (where such execution (at least partially) represents EDA tools) to perform part or all of the processes and / or methods. In one or more embodiments, storage medium 704 also stores information that facilitates the execution of part or all of the processes and / or methods. In one or more embodiments, storage medium 704 includes IC design memory 707 configured to store one or more IC layout diagrams, such as those described above. Figures 1A-4E The IC layout diagrams to be discussed are 100 or 400A-400C.

[0136] IC design system 700 includes an I / O interface 710. The I / O interface 710 is coupled to external circuitry. In one or more embodiments, the I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 702.

[0137] The IC design system 700 also includes a network interface 712 coupled to the processor 702. The network interface 712 allows the IC design system 700 to communicate with a network 714 to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface, such as BlueTooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethereum, USB, or IEEE-1364. In one or more embodiments, some or all of the mentioned processes and / or methods are implemented in two or more IC design systems 700.

[0138] The IC design system 700 is configured to receive information via I / O interface 710. The information received via I / O interface 710 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters, for processing by processor 702. The information is transmitted to processor 702 via bus 708. The IC design system 700 is also configured to receive UI (user interface) related information via I / O interface 710. This information is stored as a user interface (UI) 742 in computer-readable medium 704.

[0139] In some embodiments, some or all of the mentioned processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application as part of an additional software application. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application as part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as a software application used by an IC design system 700. In some embodiments, the layout diagram including standard cells is obtained using, for example, from CADENCE DESIGN SYSTEMS, Inc. It is generated by tools such as other suitable layout generation tools.

[0140] In some embodiments, processing is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as optical discs like DVDs, magnetic disks like hard disks, and one or more semiconductor memories (such as ROM, RAM, memory cards, etc.).

[0141] Figure 8This is a block diagram of an IC manufacturing system 800 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on an IC layout diagram, the manufacturing system 800 is used to manufacture at least one of the following in layers of a semiconductor integrated circuit: (A) one or more semiconductor masks or (B) at least one component.

[0142] like Figure 8 As shown, the IC manufacturing system 800 includes entities that interact with each other throughout the design, development, and manufacturing cycles, such as design room 820, mask room 830, and IC fab 850, and / or services related to the manufacture of IC devices 860. The entities in system 800 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 820, mask room 830, and IC fab 850 are owned by a single, larger company. In some embodiments, two or more of the design room 820, mask room 830, and IC fab 850 coexist in a shared facility and use shared resources.

[0143] Design room (or design team) 820 generates IC design layout 822. IC design layout 822 includes various geometric patterns, such as the IC layout discussed above. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 860 to be manufactured. The layers are combined to form various IC components. For example, portions of IC design layout 822 include various IC components, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, that will be formed in a semiconductor substrate (e.g., a silicon wafer) and disposed in various material layers on the semiconductor substrate. Design room 820 implements appropriate design procedures to form IC design layout 822. Design procedures include one or more of logic design, physical design, or place-and-route. IC design layout 822 is presented in one or more data files containing geometric pattern information. For example, IC design layout 822 may be represented in GDSII or DFII file format.

[0144] Mask chamber 830 includes data preparation 832 and mask fabrication 844. Mask chamber 830 uses an IC design layout 822 to fabricate one or more masks 845 for fabricating various layers of an IC device 860 according to the IC design layout 822. Mask chamber 830 performs mask data preparation 832, where the IC design layout 822 is translated into a representative data file (RDF). Mask data preparation 832 provides the RDF to mask fabrication 844. Mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate (such as a mask (mask plate) 845 or a semiconductor wafer 853). The design layout 822 is manipulated by mask data preparation 832 to conform to the requirements of the mask writer and / or IC fab 850. Figure 8 In this embodiment, mask data preparation 832 and mask manufacturing 844 are shown as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 may be collectively referred to as mask data preparation.

[0145] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0146] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that examines an IC design layout 822, which has been processed in an OPC using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margin to accommodate variability in semiconductor manufacturing processes. In some embodiments, the MRC modifies the IC design layout 822 to compensate for constraints during mask fabrication 844, which can reverse some modifications performed by the OPC to satisfy the mask creation rules.

[0147] In some embodiments, mask data preparation 832 includes a lithography process check (LPC), which simulates a process to be implemented by an IC wafer fab 850 to manufacture an IC device 860. The LPC simulates this process based on an IC design layout 822 to create simulated processing parameters in the LPC simulation. These parameters may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, or combinations thereof. In some embodiments, after the LPC creates a simulated fabricated device, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the IC design layout 822.

[0148] It should be understood that, for clarity, the above description of mask data preparation 832 has been simplified. In some embodiments, data preparation 832 includes additional features, such as logic operations (LOPs), to modify the IC design layout 822 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 822 during data preparation 832 can be performed in various different sequences.

[0149] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 is fabricated based on a modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more photolithographic exposures based on the IC design layout 822. In some embodiments, a mechanism of electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or mask stencil) 845 based on the modified IC design layout 822. The mask 845 can be formed using various techniques. In some embodiments, the mask 845 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) or EUV beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and pass through the transparent regions. In one example, a binary mask version of the mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form mask 845. In the phase-shifting mask (PSM) version of mask 845, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask produced by mask fabrication 844 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 853, in etching processes to form various etched regions in semiconductor wafer 853, and / or in other suitable processes.

[0150] IC Fab 850 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 850 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnects and packages of IC products, and a third manufacturing plant that can provide other services for foundry operations.

[0151] IC fab 850 includes wafer fabrication tool 852, which is configured to perform various fabrication operations on a semiconductor wafer 853 to fabricate an IC device 860 according to a mask (e.g., mask 845). In various embodiments, fabrication tool 852 includes a wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0152] IC wafer fab 850 uses a mask 845, fabricated by mask chamber 830, to manufacture IC device 860. Therefore, IC wafer fab 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, IC manufacturing plant 850 uses mask 845 to manufacture semiconductor wafer 853 to form IC device 860. In some embodiments, IC manufacturing includes at least indirectly performing one or more photolithographic exposures based on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 853 also includes one or more of various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0153] Regarding IC manufacturing systems (e.g.) Figure 8 Details of the system 800 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Patent No. 20150278429, published October 1, 2015; U.S. Patent No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of each of which are incorporated herein by reference.

[0154] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0155] For example, in U.S. Patent Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations within the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing the primary design pattern and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. This auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0156] For example, in Pre-License No. 20140040838, the IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. The IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, the openings being formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0157] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results. The controller also monitors the operating conditions of the processing tool and adjusts the manufacturing model of the processing tool during processing.

[0158] In some embodiments, the IC device includes: a first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction; and a second plurality of active regions extending in the first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction, wherein the ratio of the second pitch to the first pitch is 3:2. In some embodiments, the first plurality of active regions includes pairs of adjacent p-type active regions alternating with pairs of adjacent n-type active regions, and the second plurality of active regions includes one or more subsets, each subset including a total of four adjacent active regions arranged as independent p-type active regions alternating with independent n-type active regions. In some embodiments, the active regions in the first plurality of active regions have a first width in the second direction, and the active regions in the second plurality of active regions have a second width greater than the first width in the second direction. In some embodiments, each active region in the first plurality of active regions has the same first width, and each active region in the second plurality of active regions has the same second width. In some embodiments, the IC device includes a plurality of power rails extending in a first direction, wherein each of the plurality of power rails is located between adjacent p-type active regions or adjacent n-type active regions in a first plurality of active regions, and the first to fourth adjacent power rails of the plurality of power rails are aligned with a subset of one or more subsets of a second plurality of active regions. In some embodiments, a second power rail among the first to fourth adjacent power rails of the plurality of power rails covers an independent p-type active region of the second plurality of active regions, and a third power rail among the first to fourth adjacent power rails of the plurality of power rails covers an independent n-type active region of the second plurality of active regions. In some embodiments, the first plurality of active regions are adjacent to the second plurality of active regions at a boundary extending in a second direction, a continuous well extends across the boundary, a pair of adjacent active regions in the first plurality of active regions is located in a continuous well, and a single active region in the second plurality of active regions is located in a continuous well and is continuous with a first active region in a pair of adjacent active regions in the first plurality of active regions. In some embodiments, a first portion of a continuous well corresponding to the position of a pair of adjacent active regions in a first plurality of active regions has a first width in a second direction, and a second portion of a continuous well corresponding to the position of a single active region in a second plurality of active regions has a second width in the second direction, and the first width is greater than the second width. In some embodiments, the second portion of the continuous well is aligned in a first direction with a second active region in a pair of adjacent active regions in the first plurality of active regions. In some embodiments, the continuous well is an n-type well, and each of the active regions in the pair of adjacent active regions in the first plurality of active regions and the single active region in the second plurality of active regions is a p-type active region.

[0159] In some embodiments, the IC device includes: a first power rail and a second power rail extending in a first direction; a first plurality of active regions extending in the first direction; and a second plurality of active regions extending in the first direction and offset from the first plurality of active regions in the first direction. The first power rail is electrically connected to a first active region in the first plurality of active regions and a first active region in the second plurality of active regions, the second power rail is electrically connected to a second active region in the first plurality of active regions and a second active region in the second plurality of active regions, the first plurality of active regions includes a third active region located between the first active region and the second active region and electrically connected to the second power rail, and the first active region and the second active region in the second plurality of active regions are adjacent active regions of the second plurality of active regions. In some embodiments, the first active region in the first plurality of active regions is continuous with the first active region in the second plurality of active regions, and the second active region in the first plurality of active regions is continuous with the second active region in the second plurality of active regions. In some embodiments, the IC device includes a well, wherein each of the second active region and the third active region in the first plurality of active regions and each of the second active region in the second plurality of active regions is located in the well. In some embodiments, a first power rail covers each of the first active regions in a first plurality of active regions and each of the first active regions in a second plurality of active regions, and a second power rail covers each of the second active regions in the first plurality of active regions and each of the second active regions in the second plurality of active regions. In some embodiments, each of the first plurality of active regions and the second plurality of active regions covers a substrate, and the second power rail covers the substrate between the second and third active regions in the first plurality of active regions and between the first and second active regions in the second plurality of active regions. In some embodiments, each of the first plurality of active regions has a first width in a second direction perpendicular to the first direction, and each of the second plurality of active regions has a second width in the second direction that is greater than the first width.

[0160] In some embodiments, a method of manufacturing an IC device includes: forming a first plurality of active regions, the first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction; forming a second plurality of active regions, the second plurality of active regions extending in the first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction. The ratio of the second pitch to the first pitch is 3:2. In some embodiments, the method includes forming a well, wherein forming the first plurality of active regions includes forming a first active region and a second active region located within the well, and forming the second plurality of active regions includes forming a first active region located within the well and continuous with the first active region in the first plurality of active regions. In some embodiments, forming a well includes forming a well having a first width corresponding to the first and second active regions in the first plurality of active regions in the second direction and a second width corresponding to the first active regions in the second plurality of active regions in the second direction, and the first width is greater than the second width. In some embodiments, the method includes: forming a first plurality of transistors including a first plurality of active regions and a second plurality of transistors including a second plurality of active regions, and constructing an electrical connection to each of the first plurality of transistors and the second plurality of transistors, the electrical connection including a plurality of power rails, wherein a power rail of the plurality of power rails covers a first and a second active region of the first plurality of active regions and a first active region of the second plurality of active regions.

[0161] Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: The first plurality of active regions extend in a first direction and have a first pitch in a second direction perpendicular to the first direction; as well as A second plurality of active regions extend in the first direction, are offset from the first plurality of active regions in the first direction, and have a second pitch in the second direction. The first plurality of active regions includes one or more pairs of adjacent p-type active regions, which alternate with one or more pairs of adjacent n-type active regions. Each p-type active region and each n-type active region of the first plurality of active regions is thus adjacent to both the p-type and n-type active regions. The ratio of the second pitch to the first pitch is 3:

2.

2. The integrated circuit device according to claim 1, wherein... The second plurality of active regions includes one or more subsets, each subset including a total of four adjacent active regions, the four adjacent active regions being arranged as independent p-type active regions alternating with independent n-type active regions.

3. The integrated circuit device according to claim 2, wherein... The active region in the first plurality of active regions has a first width in the second direction, and The active region in the second plurality of active regions has a second width in the second direction that is greater than the first width.

4. The integrated circuit device according to claim 3, wherein Each of the first plurality of active regions has a first width, and the first width is the same for all of them. Each of the second plurality of active regions has a second width, which is the same second width.

5. The integrated circuit device of claim 2, further comprising a plurality of power rails extending in the first direction, wherein Each of the plurality of power rails is located between adjacent p-type active regions or adjacent n-type active regions in the plurality of first active regions, and The first to fourth adjacent power rails of the plurality of power rails are aligned with a subset of one or more subsets of the second plurality of active regions.

6. The integrated circuit device according to claim 5, wherein The second power rail among the first to fourth adjacent power rails of the plurality of power rails covers the independent p-type active region of the second plurality of active regions, and The third power rail among the first to fourth adjacent power rails of the plurality of power rails covers the independent n-type active region of the second plurality of active regions.

7. The integrated circuit device according to claim 2, wherein The first plurality of active regions are adjacent to the second plurality of active regions at the boundary extending along the second direction. The continuous traps extend across the boundary. The pairs of adjacent active regions in the first plurality of active regions are located in the consecutive wells, and A single active region in the second plurality of active regions is located in the continuous trap and is continuous with the first active region in the pair of adjacent active regions in the first plurality of active regions.

8. The integrated circuit device according to claim 7, wherein The first portion of the continuous well corresponding to the position of the pair of adjacent active regions in the first plurality of active regions has a first width in the second direction. The second portion of the consecutive wells corresponding to the location of the individual active region in the second plurality of active regions has a second width in the second direction, and The first width is greater than the second width.

9. The integrated circuit device according to claim 8, wherein, The second portion of the continuous trap is aligned in the first direction with the second active region in the pair of adjacent active regions of the first plurality of active regions.

10. The integrated circuit device according to claim 7, wherein The continuous traps are n-type traps, and Each of the pairs of adjacent active regions in the first plurality of active regions and each of the active regions in the individual active regions in the second plurality of active regions is a p-type active region.

11. An integrated circuit device, comprising: The first power rail and the second power rail extend in the first direction; The first plurality of active regions extend in the first direction; as well as The second plurality of active regions extend in the first direction and are offset from the first plurality of active regions in the first direction. in The first power rail is electrically connected to the first active region in the first plurality of active regions and the first active region in the second plurality of active regions. The second power rail is electrically connected to the second active region in the first plurality of active regions and the second active region in the second plurality of active regions. The first plurality of active regions includes a third active region located between the first active region and the second active region and electrically connected to the second power rail, and The first active region and the second active region in the second plurality of active regions are adjacent active regions of the second plurality of active regions.

12. The integrated circuit device according to claim 11, wherein The first active region in the first plurality of active regions is continuous with the first active region in the second plurality of active regions, and The second active region in the first plurality of active regions is continuous with the second active region in the second plurality of active regions.

13. The integrated circuit device according to claim 12, further comprising a well, wherein, The second active region and the third active region in the first plurality of active regions, and each of the second active regions in the second plurality of active regions, are located in the trap.

14. The integrated circuit device according to claim 11, wherein The first power rail covers each of the first active regions in the first plurality of active regions and each of the first active regions in the second plurality of active regions, and The second power rail covers each of the second active regions in the first plurality of active regions and each of the second active regions in the second plurality of active regions.

15. The integrated circuit device according to claim 14, wherein Each of the first plurality of active regions and the second plurality of active regions covers a substrate, and The second power rail covers the substrate between the second and third active regions in the first plurality of active regions and between the first and second active regions in the second plurality of active regions.

16. The integrated circuit device according to claim 11, wherein Each of the first plurality of active regions has a first width in a second direction perpendicular to the first direction, and Each of the second plurality of active regions has a second width in the second direction that is greater than the first width.

17. A method for manufacturing an integrated circuit device, the method comprising: A first plurality of active regions are formed, the first plurality of active regions extending in a first direction and having a first pitch in a second direction perpendicular to the first direction; as well as A second plurality of active regions are formed, extending in the first direction, offset from the first plurality of active regions in the first direction, and having a second pitch in the second direction. The formation of the first plurality of active regions includes forming one or more pairs of adjacent p-type active regions, which alternate with one or more pairs of adjacent n-type active regions. Each p-type active region and each n-type active region of the first plurality of active regions is thus adjacent to both p-type and n-type active regions. The ratio of the second pitch to the first pitch is 3:

2.

18. The method of claim 17, further comprising forming a trap, wherein Forming the first plurality of active regions includes forming a first active region and a second active region located within the trap; and Forming the second plurality of active regions includes forming a first active region of the second plurality of active regions located in the trap and continuous with the first active region in the first plurality of active regions.

19. The method of claim 18, wherein Forming the trap includes forming the trap having a first width corresponding to the first plurality of active regions and the second active regions in the second direction, and a second width corresponding to the first active region in the second direction. The first width is greater than the second width.

20. The method of claim 17, further comprising: Forming a first plurality of transistors including the first plurality of active regions and a second plurality of transistors including the second plurality of active regions; and Construct electrical connections to each of the first plurality of transistors and the second plurality of transistors, the electrical connections including a plurality of power rails. The power rails of the plurality of power rails cover the first and second active regions of the first plurality of active regions and the first active region of the second plurality of active regions.

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