A power factor correction circuit and a compensation method thereof

Abstract

The application provides a power factor correction circuit and a compensation method thereof. The power factor correction circuit comprises a PFC main circuit and a control circuit. The control circuit obtains the conduction time of the negative inductive output current in the PFC main circuit and the fixed conduction time of the switch tube in the PFC main circuit, and controls the conduction time of the switch tube to be the sum of the conduction time of the negative inductive output current and the fixed conduction time, so that the relationship between the input current and the input voltage still satisfies a linear relationship, and the influence of the valley crossover distortion on THD is greatly optimized.

Description

Technical Field

[0001] This invention relates to the field of power converter technology, specifically, but not limited to, a power factor correction circuit and its compensation method. Background Technology

[0002] Figure 1 This is the main circuit for power factor correction (PFC). In traditional critical operating mode, PFC function can usually be achieved by simply controlling the on-time of the switching transistor. Ideally, PFC function should control the input current and input voltage to have a linear relationship. Figure 2 The waveform at the top is the driving voltage of Q1, and the waveform at the bottom is the current IL through the inductor Lm. If the fixed on-time is set to Ton (i.e., square wave pulse width), then the peak inductor current Ipk = Vin * Ton / Lm. However, when the system is operating in critical mode, the average inductor current Iin = Ipk / 2 = Vin * Ton / (2 * Lm). Obviously, for fixed Ton and Lm, Iin and Vin have a linear relationship, which can meet the requirements of PFC.

[0003] However, the above calculations neglect the non-zero portion of the inductor current resonance. For a large Ipk, ignoring the non-zero portion of the inductor current has little impact on the calculation of Iin. However, when operating at the input voltage trough, this negative current has a significant impact on Ipk, directly causing a deterioration in total harmonic distortion (THD). The closer to the trough, the greater the impact of the negative resonant current on Iin, even to the point that the negative resonant current is almost the same as the peak current Ipk, making the actual operating current close to 0 instead of the ideal Ipk / 2, thus causing severe distortion and affecting the THD waveform.

[0004] In existing technologies, a minimum peak current limit is usually added directly to prevent the peak current at the valley from being too low, thereby increasing the input current at the valley. Due to the minimum peak current limit, the inductor current IL at the valley will not decrease due to the decrease in input voltage. At the same time, the input current Iin is clearly calibrated at the valley. This compensation method can optimize THD under certain conditions. However, since the minimum peak current is fixed, it is equivalent to open-loop compensation. The compensation effect is related to the actual operating current. If the actual operating current is large, the compensation effect will be weak. If the actual operating current is small, it may lead to overcompensation.

[0005] In view of this, there is a need to provide a new structure or control method in order to solve at least some of the above problems. Summary of the Invention

[0006] Addressing at least one or more problems in the background art, this invention proposes a power factor correction circuit and its compensation method, which can feed back the negative current information output by the inductor from the PFC main circuit and compensate the positive current of the inductor according to the negative current information, so that the PFC main circuit satisfies the linear relationship between the input current and the input voltage, and optimizes the impact of valley crossover distortion on THD.

[0007] According to a first aspect of the present invention, a power factor correction circuit includes:

[0008] The PFC main circuit includes inductors and switching transistors; and

[0009] A control circuit, coupled to the PFC main circuit, is used to obtain the on-time of the negative current output by the inductor and the fixed on-time of the switching transistor, and to control the on-time of the switching transistor to be twice the sum of the on-time of the negative current and the fixed on-time.

[0010] Optionally, the control circuit includes: a feedback circuit having an input terminal and an output terminal, the input terminal of the feedback circuit being coupled to the inductor for obtaining the conduction time of the negative current, the output terminal of the feedback circuit being coupled to a drive circuit for outputting a feedback signal to the drive circuit when the conduction time of the switch is twice the conduction time of the negative current; and a drive circuit having an output terminal, the output terminal of the drive circuit being coupled to the switch, the drive circuit calculating a fixed conduction time of the switch after receiving the feedback signal and driving the switch to turn off after the fixed conduction time.

[0011] Optionally, the feedback circuit includes: a timing circuit having an input terminal and an output terminal, the input terminal of the timing circuit being coupled to the inductor, and the timing circuit detecting the start point and the end point of the negative current after the inductor outputs a negative current; and a gain circuit having an input terminal and an output terminal, the input terminal of the gain circuit being coupled to the output terminal of the timing circuit, for obtaining a conduction time of twice the negative current based on the start point and the end point of the negative current; the output terminal of the gain circuit being coupled to the drive circuit, for outputting a feedback signal to the drive circuit when the conduction time of the switching transistor is twice the conduction time of the negative current.

[0012] Optionally, the timing circuit includes: a demagnetization detection circuit having an input terminal and an output terminal, the input terminal of the demagnetization detection circuit being coupled to the inductor for detecting the starting point of the negative current, and the output terminal of the demagnetization detection circuit being coupled to the set terminal of a trigger for outputting a first detection signal to the set terminal of the trigger after detecting the starting point of the negative current; a zero-crossing detection circuit having an input terminal and an output terminal, the input terminal of the zero-crossing detection circuit being coupled to the inductor for detecting the ending point of the negative current, and the output terminal of the zero-crossing detection circuit being coupled to the reset terminal of the trigger for outputting a second detection signal to the reset terminal of the trigger after detecting the ending point of the negative current; and a trigger having a set terminal, a reset terminal, and an output terminal, the output terminal of the trigger being coupled to the input terminal of the gain circuit, wherein when the trigger receives the first detection signal, the trigger outputs a high level, and when the trigger receives the second detection signal, the trigger outputs a low level.

[0013] Optionally, the gain circuit includes: a capacitor; a first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to a high-level voltage, and the second terminal of the first switch is coupled to the capacitor, and when the output terminal of the trigger outputs a high level, the first switch is turned on, and the capacitor is charged; a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the capacitor, and the second terminal of the second switch is coupled to a reference ground, and when the first switch is turned off, the second switch is turned on, and the capacitor is discharged; a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the comparator is coupled to the capacitor, the second input terminal of the comparator is coupled to a reference ground, and the output terminal of the comparator is coupled to the driving circuit, and when the voltage of the capacitor is zero, the comparator outputs the feedback signal to the driving circuit.

[0014] According to a second aspect of the present invention, another power factor correction circuit includes:

[0015] The PFC main circuit includes inductors and switching transistors; and

[0016] The control circuit, coupled to the PFC main circuit, is used to obtain the extreme value of the negative current output of the inductor, the positive current value corresponding to the extreme value of the negative current, and the fixed conduction time of the switching transistor, and to control the conduction time of the switching transistor to be the sum of the conduction time from the extreme value of the negative current output of the inductor to the positive current value and the fixed conduction time.

[0017] Optionally, the control circuit includes: a feedback circuit having an input terminal and an output terminal, the input terminal of the feedback circuit being coupled to the inductor for obtaining the negative current extreme value output by the inductor, the output terminal of the feedback circuit being coupled to a drive circuit for outputting a feedback signal to the drive circuit when the inductor outputs a positive current value corresponding to the negative current extreme value; and a drive circuit having an output terminal, the output terminal of the drive circuit being coupled to the switching transistor, the drive circuit calculating a fixed on-time of the switching transistor after receiving the feedback signal and driving the switching transistor to turn off after the fixed on-time.

[0018] According to a third aspect of the present invention, a compensation method for a power factor correction circuit includes the following steps: obtaining the on-time of the negative current output by the inductor in the PFC main circuit and the fixed on-time of the switch in the PFC main circuit; and controlling the on-time of the switch to be twice the sum of the on-time of the negative current and the fixed on-time.

[0019] According to a fourth aspect of the present invention, another compensation method for a power factor correction circuit includes the following steps: obtaining the extreme negative current output of an inductor in the PFC main circuit, the positive current value corresponding to the extreme negative current value, and the fixed on-time of a switching transistor in the PFC main circuit; and controlling the on-time of the switching transistor to be the sum of the on-time from the extreme negative current output of the inductor to the positive current value and the fixed on-time.

[0020] The present invention proposes a power factor correction circuit and its compensation method. By adding a control circuit, the on-time of the negative current output by the inductor in the PFC main circuit and the fixed on-time of the switching transistor in the PFC main circuit are obtained. The on-time of the switching transistor is controlled to be twice the sum of the on-time of the negative current and the fixed on-time, so that the relationship between the input current and the input voltage still satisfies the linear relationship, which greatly optimizes the impact of valley crossover distortion on THD. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and, together with the description, serve to explain embodiments of the invention, but do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 This is a structural diagram of the PFC main circuit;

[0023] Figure 2 It shows the waveforms of the input voltage and inductor current;

[0024] Figure 3 A schematic diagram of a power factor correction circuit structure according to an embodiment of the present invention is shown;

[0025] Figure 4 A schematic diagram of a feedback circuit structure according to an embodiment of the present invention is shown;

[0026] Figure 5 A schematic diagram of a driving circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0027] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0028] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0029] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar function, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "Multiple" or "more" indicates two or more.

[0030] Reference Figure 3 One embodiment of the present invention provides a power factor correction circuit, including a PFC main circuit 100 and a control circuit 200.

[0031] Reference Figure 1 The PFC main circuit 100 includes an inductor 110 and a switching transistor 120. When the switching transistor 120 is turned on, the inductor 110 stores energy, and the positive current output by the inductor 110 gradually increases. When the switching transistor 120 is turned off, the inductor 110 releases energy, and the positive current output by the inductor 110 gradually decreases. After the switching transistor 120 has been off for a period of time, the energy stored in the inductor 110 is exhausted, and the positive current output by the inductor 110 decreases to zero, or even the inductor 110 begins to output a negative current. Figure 2 For example, negative current in Figure 2 The representation in the figure is the waveform portion where the current IL of the inductor Lm is less than 0. Correspondingly, the forward current in Figure 2The representation in the figure is the waveform portion where the current IL of inductor Lm is greater than 0. The PFC main circuit 100 in this embodiment is at least one of an active PFC circuit or a passive PFC circuit.

[0032] Reference Figure 3 The control circuit 200 includes a feedback circuit 210 and a drive circuit 220. Specifically, the feedback circuit 210 has an input terminal and an output terminal. The input terminal of the feedback circuit 210 is coupled to both ends of the inductor 110, thereby enabling real-time acquisition of the current signal output by the inductor 110. The feedback circuit 210 can obtain the conduction time of the negative current output by the inductor 110 through the input terminal. In addition, the output terminal of the feedback circuit 210 is coupled to the drive circuit 220. When the conduction time of the switching transistor 120 is twice the conduction time of the negative current, a feedback signal is output to the drive circuit 220. The driving circuit 220 has an output terminal, which is coupled to the switching transistor 120 of the PFC main circuit 100. The driving circuit 220 can calculate the fixed on-time (i.e. the on-time of the switching transistor 120 in the PFC main circuit 100 in the prior art) through its internal circuit structure. After receiving the feedback signal from the feedback circuit 210 and after the fixed on-time, it drives the switching transistor 120 of the PFC main circuit 100 to turn off.

[0033] The control circuit controls the switching transistor 120 to conduct for a time equal to twice the negative current conduction time t1 and the fixed conduction time Ton, i.e., Ton_real = Ton + 2 * t1. Based on the input current and inductor current relationship described earlier, Iin = (Vin * (t1 + Ton) / Lm - Vin * t1 / Lm) / 2 = Vin * Ton / 2 * Lm, which still satisfies the linear relationship between input current and input voltage, greatly optimizing the impact of valley crossover distortion on THD.

[0034] In one embodiment, the feedback circuit 210 includes a timing circuit 211 and a gain circuit 212.

[0035] The timing circuit 211 has an input terminal and an output terminal. The input terminal of the timing circuit 211 is coupled to the inductor 110 and is used to detect the start and end points of the negative current output by the inductor 110. Specifically, the start point of the negative current is the critical point at which the inductor 110 changes from outputting positive current to outputting negative current, and the end point of the negative current is the critical point at which the inductor 110 changes from outputting negative current to outputting positive current. Both are represented by the voltage of the inductor 110 being zero.

[0036] The gain circuit 212 has an input terminal and an output terminal. The input terminal of the gain circuit 212 is coupled to the output terminal of the timing circuit 211 and is used to obtain the conduction time of twice the negative current based on the start and end points of the negative current. The output terminal of the gain circuit 212 is coupled to the input terminal of the driving circuit 220 and is used to output a feedback signal to the driving circuit 220 after the conduction time of twice the negative current.

[0037] Specifically, the circuit diagrams of timing circuit 211 and gain circuit 212 are as follows: Figure 4 As shown.

[0038] The timing circuit 211 includes a demagnetization detection circuit 211a, a zero-crossing detection circuit 211b, and a trigger 211c. The demagnetization detection circuit 211a has an input terminal and an output terminal. Its input terminal is coupled to an inductor 110 to detect the start of the negative current. Its output terminal is coupled to the set terminal of the trigger 211c, and upon detecting the start of the negative current, it outputs a first detection signal to the set terminal of the trigger 211c; specifically, the first detection signal is a high-level signal. The zero-crossing detection circuit 211b has an input terminal and an output terminal. Its input terminal is coupled to an inductor 110 to detect the end of the negative current. Its output terminal is coupled to the reset terminal of the trigger 211c, and upon detecting the end of the negative current, it outputs a second detection signal to the reset terminal of the trigger 211c; specifically, the second detection signal is also a high-level signal. The flip-flop 211c has a set terminal, a reset terminal, and an output terminal. The output terminal of the flip-flop 211c is coupled to the input terminal of the gain circuit 212. When the flip-flop 211c receives a first detection signal, it outputs a high level; when it receives a second detection signal, it outputs a low level. Preferably, to better match the gain circuit 212, the flip-flop 211c in this embodiment is preferably an RS flip-flop. The RS flip-flop has a first output terminal and a second output terminal. When the set terminal of the flip-flop 211c receives a high level, the first output terminal of the RS flip-flop outputs a high level, and the second output terminal outputs a low level; when the reset terminal of the flip-flop receives a high level, the first output terminal of the RS flip-flop outputs a low level, and the second output terminal outputs a high level.

[0039] The gain circuit 212 includes a capacitor 212a, a first switch 212b, a second switch 212c, and a comparator 212d. The first switch 212b has a first terminal, a second terminal, and a control terminal. The first terminal of the first switch 212b is coupled to a high-level voltage, the second terminal of the first switch 212b is coupled to the capacitor 212a, and the control terminal of the first switch 212b is coupled to the first output terminal of the aforementioned RS flip-flop. The control logic of the first switch 212b is as follows: when the first output terminal of the aforementioned RS flip-flop outputs a high level, the control terminal is also high, controlling the first switch 212b to conduct and charge the capacitor 212a; when the first output terminal of the aforementioned RS flip-flop outputs a low level, the control terminal is also low, controlling the first switch 212b to turn off, without affecting the capacitor 212a. Considering the conduction characteristics of the first switch 212b, it is preferable that the first switch 212b is a transistor. The second switch 212c has a first terminal, a second terminal, and a control terminal. The first terminal of the second switch 212c is coupled to a capacitor 212a, the second terminal is coupled to a reference ground, and the control terminal is coupled to the second output terminal of the aforementioned RS flip-flop. The control logic of the second switch 212c is as follows: when the second output terminal of the aforementioned RS flip-flop outputs a high level, the control terminal is also high, controlling the second switch 212c to conduct and discharge the capacitor 212a; when the second output terminal of the aforementioned RS flip-flop outputs a low level, the control terminal is also low, controlling the second switch 212c to turn off and not affect the capacitor 212a. Considering the conduction characteristics of the second switch 212c, it is preferable that the second switch 212c is a transistor. The comparator 212d has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator 212d is coupled to a capacitor 212a, the second input terminal is coupled to a reference ground, and the output terminal of the comparator 212d is coupled to a driver circuit 220. That is, the comparator 212d compares the voltage of capacitor 212a with zero voltage. If the voltage of capacitor 212a is equal to the zero voltage, it outputs a feedback signal to the drive circuit 220. Specifically, when the output current of inductor 110 changes from positive to negative, the demagnetizing detection circuit 211a detects the critical point where the output current of inductor 110 is zero and outputs a first detection signal to the set terminal of RS flip-flop 211c. At this time, the first switch 212b is turned on, the second switch 212c is turned off, capacitor 212a is coupled to a high-level voltage for charging, the voltage of capacitor 212a is greater than the reference ground voltage, and the comparator 212d has no output.When the output current of inductor 110 changes from negative to positive, the zero-crossing detection circuit 211b detects the critical point where the output current of inductor 110 is zero and outputs a second detection signal to the set terminal of RS flip-flop 211c. At this time, the first switch 212b is turned off, the second switch 212c is turned on, and capacitor 212a is coupled to the reference ground to discharge until the discharge time of capacitor 212a is the same as the charging time of capacitor 212a, the voltage of capacitor 212a is equal to the voltage of the reference ground, and comparator 212d outputs a feedback signal. From the point when the demagnetizing detection circuit 211a detects the critical point when the output current of inductor 110 is zero to the point when the zero-crossing detection circuit 211b detects the critical point when the output current of inductor 110 is zero, this is the conduction time when the inductor 110 outputs a negative current, which is also the charging time of capacitor 212a. From the point when the demagnetizing detection circuit 211a detects the critical point when the output current of inductor 110 is zero to the point when comparator 212d outputs a feedback signal, capacitor 212a has undergone charging and discharging operations, which is the conduction time when the inductor 110 outputs a negative current twice the current.

[0040] One embodiment of the demagnetizing detection circuit 211a involves coupling the inductor 110 through an auxiliary winding and using a DC blocking circuit to detect the point at which the current in the inductor 110 drops to zero. Another embodiment of the demagnetizing detection circuit 211a involves adding an additional capacitor between the source and gate of the switching transistor 120 and detecting the point at which the current in the inductor 110 drops to zero by detecting the discharge current on the capacitor. One embodiment of the zero-crossing detection circuit 211b is a comparator-based zero-crossing detection circuit 211b. It attenuates the inductor 110 signal to the positive input of the comparator through a voltage divider resistor. When the inductor 110 signal exceeds the zero reference voltage, the zero-crossing detection circuit 211b changes the output state of the comparator. Another embodiment of the zero-crossing detection circuit 211b is a transistor-based zero-crossing detection circuit 211b. It attenuates the AC signal to the base of the transistor through a voltage divider resistor and uses the transistor's characteristics to perform zero-crossing detection to change the output state. It should be noted that, due to space limitations, this embodiment only lists the more common demagnetization detection circuit 211a and zero-crossing detection circuit 211b. Other circuits with demagnetization detection function and zero-crossing detection function are also applicable to this invention.

[0041] In one embodiment, reference Figure 5The driving circuit 220 is a Ton control circuit. Under normal conditions, the switching transistor Q2 is in the on state, and the capacitor C is coupled to the reference ground, with zero voltage across capacitor C. When the driving circuit 220 receives a feedback signal from the feedback circuit 210, it controls the switching transistor Q2 to turn off. At this time, capacitor C is charged through the current mirror. When the voltage of capacitor C rises to be equal to the reference voltage Vref, the comparator flips, outputting the switch 120 turn-off signal ton_rst. Therefore, the time from the driving circuit 220 receiving the feedback signal to outputting the switch 120 turn-off signal ton_rst is Ton = Vref * C / I. If the parameters in the driving circuit 220 have been set, and the reference voltage, capacitor capacitance, and capacitor charging current are all constant, then Ton is a fixed time, i.e., a fixed on-time.

[0042] A common power factor correction circuit includes a PFC main circuit 100 and a drive circuit 220. When the output current of inductor 110 changes from positive to negative, switch 120 turns on, and simultaneously, capacitor C of drive circuit 220 charges. After a fixed on-time Ton, drive circuit 220 outputs a switch-off signal ton_rst to turn off switch 120. Therefore, in a common power factor correction circuit, the on-time of switch 120 is a fixed on-time. In this embodiment, a feedback circuit 210 is added to obtain the on-time t1 of twice the negative current. When the on-time of switch 120 is twice the on-time of the negative current t1, a feedback signal is output to drive circuit 220. At this time, capacitor C of drive circuit 220 charges again. Therefore, the on-time of switch 120 is the sum of the on-time t1 of twice the negative current and the fixed on-time Ton, i.e., Ton_real = Ton + 2*t1. Based on the relationship between input current and inductor current described above, the linear relationship between input current and input voltage can still be satisfied, which can greatly optimize the impact of valley crossover distortion on THD.

[0043] Reference Figure 3 One embodiment of the present invention provides a power factor correction circuit, including a PFC main circuit 100 and a control circuit. The PFC main circuit 100 in this embodiment is the same as that in the above embodiments, and the description of the PFC main circuit can be referred to the above embodiments.

[0044] The difference lies in the control circuit 200. In this embodiment, the control circuit 200 no longer acquires the conduction time of the negative current of inductor 110, but instead acquires the maximum negative current value and the corresponding positive current value. Specifically, the positive current value corresponding to the maximum negative current value refers to the positive current whose value is equal to the maximum negative current value. (Refer to...) Figure 2After switch 120 is turned off, the current in inductor 110 decreases rapidly. Therefore, the time from when the current in inductor 110 is zero to when it reaches its maximum negative current value is very short, and the impact of the negative current during this period on the PFC main circuit 100 can be ignored. After detecting the positive current value, the switch 120 is turned off, and its on-time is approximately Ton_real = Ton + 2*t1. As described above, the impact of valley crossover distortion on THD can still be optimized.

[0045] The control circuit 200 includes a feedback circuit 210 and a drive circuit 220. Specifically, the feedback circuit 210 has an input terminal and an output terminal. The input terminal of the feedback circuit 210 is coupled to both ends of the inductor 110, thereby acquiring the current signal output by the inductor 110 in real time. The maximum negative current value output by the inductor 110 can be obtained through the input terminal feedback circuit 210. In addition, the output terminal of the feedback circuit 210 is coupled to the drive circuit 220. When the inductor 110 outputs a positive current value corresponding to the maximum negative current value, it outputs a feedback signal to the drive circuit 220. The driving circuit 220 has an output terminal, which is coupled to the switching transistor 120 of the PFC main circuit 100. The driving circuit 220 can calculate the fixed on-time (i.e. the on-time of the switching transistor 120 in the PFC main circuit 100 in the prior art) through its internal circuit structure. After receiving the feedback signal from the feedback circuit 210 and after the fixed on-time, it drives the switching transistor 120 of the PFC main circuit 100 to turn off.

[0046] Based on the same inventive concept, one embodiment of the present invention provides a compensation method for a power factor correction circuit, comprising the following steps: obtaining the conduction time of the negative current output by the inductor in the PFC main circuit and the fixed conduction time of the switching transistor in the PFC main circuit; and controlling the conduction time of the switching transistor to be twice the sum of the conduction time of the negative current and the fixed conduction time.

[0047] Based on the same inventive concept, this invention provides another compensation method for a power factor correction circuit, comprising the following steps: obtaining the extreme negative current output of the inductor in the PFC main circuit, the positive current value corresponding to the extreme negative current value, and the fixed on-time of the switching transistor in the PFC main circuit; and controlling the on-time of the switching transistor to be the sum of the on-time from the extreme negative current output of the inductor to the positive current value and the fixed on-time.

[0048] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0049] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A power factor correction circuit, characterized in that, include: PFC main circuit, including inductors and switching transistors; as well as A control circuit, coupled to the PFC main circuit, is used to acquire the on-time of the negative current output by the inductor and the fixed on-time of the switching transistor, and to control the on-time of the switching transistor to be twice the sum of the on-time of the negative current and the fixed on-time. The control circuit includes: A feedback circuit has an input terminal and an output terminal. The input terminal of the feedback circuit is coupled to the inductor and is used to obtain the conduction time of the negative current. The output terminal of the feedback circuit is coupled to the drive circuit and is used to output a feedback signal to the drive circuit when the conduction time of the switch is twice the conduction time of the negative current. as well as A driving circuit has an output terminal, the output terminal of which is coupled to the switching transistor. After receiving the feedback signal, the driving circuit calculates the fixed on-time of the switching transistor and drives the switching transistor to turn off after the fixed on-time.

2. The power factor correction circuit as described in claim 1, characterized in that, The feedback circuit includes: a timing circuit having an input terminal and an output terminal, the input terminal of the timing circuit being coupled to the inductor; and after the inductor outputs a negative current, the timing circuit detecting the start point and the end point of the negative current; and A gain circuit has an input terminal and an output terminal. The input terminal of the gain circuit is coupled to the output terminal of the timing circuit and is used to obtain a conduction time of twice the negative current based on the start and end points of the negative current. The output terminal of the gain circuit is coupled to the driving circuit and is used to output a feedback signal to the driving circuit when the conduction time of the switching transistor is twice the conduction time of the negative current.

3. The power factor correction circuit as described in claim 2, characterized in that, The timing circuit includes: A demagnetizing detection circuit has an input terminal and an output terminal. The input terminal of the demagnetizing detection circuit is coupled to the inductor and is used to detect the starting point of the negative current. The output terminal of the demagnetizing detection circuit is coupled to the set terminal of a trigger and is used to output a first detection signal to the set terminal of the trigger after detecting the starting point of the negative current. A zero-crossing detection circuit has an input terminal and an output terminal. The input terminal of the zero-crossing detection circuit is coupled to the inductor and is used to detect the end point of the negative current. The output terminal of the zero-crossing detection circuit is coupled to the reset terminal of the flip-flop and is used to output a second detection signal to the reset terminal of the flip-flop after detecting the end point of the negative current. A trigger has a set terminal, a reset terminal, and an output terminal. The output terminal of the trigger is coupled to the input terminal of the gain circuit. When the trigger receives the first detection signal, the trigger outputs a high level. When the trigger receives the second detection signal, the trigger outputs a low level.

4. The power factor correction circuit as described in claim 3, characterized in that, The gain circuit includes: capacitance; A first switch has a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to a high-level voltage, and the second terminal of the first switch is coupled to the capacitor. When the output terminal of the trigger outputs a high level, the first switch is turned on, and the capacitor is charged. A second switch has a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the capacitor, and the second terminal of the second switch is coupled to a reference ground; when the first switch is off, the second switch is on, and the capacitor discharges; and A comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator is coupled to the capacitor, the second input terminal of the comparator is coupled to a reference ground, and the output terminal of the comparator is coupled to the driving circuit.

5. A power factor correction circuit, characterized in that, include: PFC main circuit, including inductors and switching transistors; as well as A control circuit, coupled to the PFC main circuit, is used to acquire the extreme negative current value of the inductor output, the positive current value corresponding to the extreme negative current value, and the fixed on-time of the switching transistor, and to control the on-time of the switching transistor to be the sum of the on-time from the extreme negative current value of the inductor output to the positive current value and the fixed on-time. The control circuit includes: A feedback circuit has an input terminal and an output terminal. The input terminal of the feedback circuit is coupled to the inductor and is used to obtain the negative current extreme value output by the inductor. The output terminal of the feedback circuit is coupled to a driving circuit and is used to output a feedback signal to the driving circuit when the inductor outputs a positive current value corresponding to the negative current extreme value. as well as A driving circuit has an output terminal, the output terminal of which is coupled to the switching transistor. After receiving the feedback signal, the driving circuit calculates the fixed on-time of the switching transistor and drives the switching transistor to turn off after the fixed on-time.

6. A compensation method for a power factor correction circuit, characterized in that, Includes the following steps: Obtain the conduction time of the inductor outputting the negative current in the PFC main circuit and the fixed conduction time of the switching transistor in the PFC main circuit; as well as The on-time of the switch is controlled to be twice the sum of the on-time of the negative current and the fixed on-time; in The input terminal of the feedback circuit is coupled to the inductor to obtain the conduction time of the negative current. The output terminal of the feedback circuit is coupled to the drive circuit to output a feedback signal to the drive circuit when the conduction time of the switch is twice the conduction time of the negative current. as well as After receiving the feedback signal, the driving circuit calculates the fixed on-time of the switching transistor and drives the switching transistor to turn off after the fixed on-time.

7. A compensation method for a power factor correction circuit, characterized in that, Includes the following steps: Obtain the extreme negative current output of the inductor in the PFC main circuit, the positive current value corresponding to the extreme negative current, and the fixed on-time of the switching transistor in the PFC main circuit; as well as The on-time of the switch is controlled to be the sum of the on-time from the extreme value of the negative current output by the inductor to the value of the positive current, and the fixed on-time. in The input terminal of the feedback circuit is coupled to the inductor to obtain the negative current extreme value output by the inductor. The output terminal of the feedback circuit is coupled to the driving circuit to output a feedback signal to the driving circuit when the inductor outputs a positive current value corresponding to the negative current extreme value. as well as After receiving the feedback signal, the driving circuit calculates the fixed on-time of the switching transistor and drives the switching transistor to turn off after the fixed on-time.

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