Link assessment for memory devices

Abstract

This application relates to link assessment for memory devices. A memory device can receive signaling via a channel and can identify logic values encoded into the signaling based on sampling the signaling for a reference voltage. The sampling can occur at a reference time within a sampling period. To assess the quality (e.g., error margin) of the channel, the memory device can adjust the reference voltage, the reference time, or both, and the memory device or a host device can determine whether the memory device is still able to correctly identify logic values encoded into signaling via the channel. In some cases, the channel quality can be assessed during a refresh cycle or at another opportunity time for the memory device.

Description

[0001] Cross-reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / US2020 / 065100, filed December 15, 2020, entitled “Link Evaluation for a Memory Device”, filed by Balb et al., claiming priority to U.S. Patent Application No. 17 / 121,314, filed December 14, 2020, entitled “Link Evaluation for a Memory Device”, and U.S. Provisional Patent Application No. 62 / 950,851, filed December 19, 2019, entitled “Link Evaluation for an Memory Device”, each of which is assigned to the assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to link evaluation for memory devices. Background Technology

[0004] The following text generally refers to one or more memory systems, and more specifically, to link evaluation for memory devices.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, vehicles, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write to or program the states in the memory device.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can retain its stored logical state for a long time, even without external power. Volatile memory devices (e.g., DRAM) lose their stored state when disconnected from external power. Summary of the Invention

[0007] Describe a method. The method may include: receiving, at a memory device, via a channel, a first signaling associated with data stored in the memory device; sampling the first signaling based on a first reference point in a time domain and a voltage domain to obtain the data; receiving, at the memory device, via the channel, a second signaling associated with a sequence of logical values; sampling the second signaling based on a second reference point in the time domain and the voltage domain to obtain a candidate sequence of logical values; and transmitting, by the memory device, third signaling based on a comparison between the candidate sequence of logical values ​​and the sequence of logical values.

[0008] Describe a method. The method may include: transmitting signaling associated with a sequence of logical values ​​to a memory device via a channel, wherein the signaling supports the determination of conditions of the channel; receiving feedback from the memory device based on the signaling associated with the sequence of logical values; and transmitting an instruction to the memory device based on the feedback.

[0009] Describe an apparatus. The apparatus may include: a memory cell array operable to store data; a channel operable to exchange data between the memory cell array and a host device of the apparatus; one or more samplers coupled to the channel and operable to determine logic values ​​based at least in part on signals received via the channel, wherein at least one of the one or more samplers is operable to use a default reference point in a time domain and a voltage domain; and a controller coupled to the memory cell array, the channel, and the one or more samplers. The controller is operable such that the apparatus: receives signaling including a sequence of logic values ​​via the channel; determines a candidate sequence of logic values ​​using the one or more samplers based on the signaling and a second reference point in the time domain and the voltage domain; and transmits feedback to the host device based on a comparison of the candidate sequence with the sequence. Attached Figure Description

[0010] Figure 1This document describes an example of a system that supports link evaluation for memory devices, based on the examples disclosed herein.

[0011] Figure 2 This document describes instances of memory dies that support link evaluation for memory devices, based on examples disclosed herein.

[0012] Figure 3 This document describes instances of memory systems that support link evaluation for memory devices, based on the examples disclosed herein.

[0013] Figure 4 This document describes an example of an eye diagram used for link evaluation of memory devices, based on the examples disclosed herein.

[0014] Figure 5 This document describes an example of a process flow for link evaluation of memory devices, based on the examples disclosed herein.

[0015] Figure 6 A block diagram of a memory device supporting link evaluation for memory devices, based on examples disclosed herein, is shown.

[0016] Figure 7 A block diagram of a host device supporting link evaluation for memory devices, based on examples disclosed herein, is shown.

[0017] Figures 8 to 11 The flowchart illustrates one or more methods for link evaluation of memory devices, based on the examples disclosed herein. Detailed Implementation

[0018] In some cases, the memory device may receive data from the host device. The host device may transmit the data via a communication channel. The data may be transmitted as a signal that can be sampled at the memory device. The memory device may sample the signal by measuring the voltage level of the signal during a unit interval (symbol period) to determine the logic state of the signal (e.g., logic '0' or logic '1') during the unit interval. The unit interval may have a duration defined by a clock associated with the transmission of the measured signal (e.g., the unit interval may have a duration equal to one cycle (circle) or half a cycle (circle) of the clock, depending on whether single data rate (SDR) or double data rate (DDR) signaling is used).

[0019] To distinguish different voltage levels when sampling a signal during a unit interval, a sampler at the memory device can compare a measured voltage level with a reference voltage at a point within the unit interval. The sampling time and reference voltage can correspond to reference points in the time and voltage domains (e.g., where the time domain corresponds to the duration of sampling, which may be aligned with or based on the unit interval, and the voltage domain corresponds to voltage fluctuations (e.g., track differences) of the signal or channel), where the reference point can be determined or configured for the memory device. The sampler can accurately determine the logical state of the signal when the reference point used for sampling falls within a data 'eye,' which can refer to the space between signal traces corresponding to different logical states in the signal. The data eye can include an associated width of time (e.g., duration) and an associated opening (e.g., height, difference) between voltage levels. It is advantageous to sample the signal at the center of the data eye to maximize the likelihood that the sampler can accurately determine the logical state of the signal during the unit interval. The center of the data eye can refer to the reference point corresponding to the reference voltage (which is the midpoint between the high voltage level associated with the first logic state (e.g., logic '1') and the low voltage level associated with the second logic state (e.g., logic '0') and the sampling time at the midpoint of the data eye.

[0020] In some instances, even if the memory device and the host device exchange data via the channel without associated transmission or sampling errors, the channel can still degrade (e.g., the boundary (segmentation, buffer) between the sampler's reference point and the edge of the data eye can shrink in the time domain, voltage domain, or both, and thus the channel's error boundary degrades). For example, voltage transitions (e.g., rising or falling edges) of signaling via the channel (and therefore the data eye) can be shifted earlier or later than the start and end of the channel's sampling period (and thus in the time domain). Alternatively, the voltage level of signaling via the channel (and thus the data eye) (e.g., maximum or minimum voltage level) can increase or decrease the voltage (and thus in the voltage domain).

[0021] Sampling the signal at a reference point different from the center of the data eye increases the likelihood of incorrect decoding (interpretation) of the received signal and therefore incorrect determination of the information encoded into the signaling (e.g., data errors), especially when the time or voltage difference between the center of the data eye and the reference point is significant (e.g., above a threshold). In some systems and apparatuses, when an error is detected, the host device or memory device may attempt to recalibrate the channel. For example, the host device may adjust the reference clock (or otherwise adjust the timing of the channel's clock signal) or recalibrate the signaling (e.g., increase or decrease the delay in the signal path or the voltage level associated with the signaling driver) before transmission to the memory device, or the memory device may adjust the sampling procedure of the received data (e.g., adjust the associated reference point). However, such techniques are reactive. To proactively avoid errors, it is advantageous to determine the state of the channel (e.g., error limits, quality, robustness) before errors or additional errors occur. For example, it is advantageous to determine the error limits associated with the configured reference point (e.g., the time domain, voltage domain, or distance between the reference point used to sample the signaling via the channel and the data eye used for signaling).

[0022] This document describes techniques that enable a memory device or a host device to determine error limits associated with a channel between the memory device and the host device. The memory device may receive signaling containing a sequence of logic values ​​from a host device via a channel. The memory device may sample the signaling at one or more reference points in the time and voltage domains to obtain candidate sequences of logic values. For example, the memory device may use reference points that are earlier and later in the time domain, higher or lower in the voltage domain, or both, to determine whether the signaling is accurately decoded at the adjusted reference point.

[0023] In some instances, the memory device may compare candidate sequences with sequences to determine error limits. For example, if the memory device can correctly decode a sequence (and thus the candidate sequence matches the sequence) using an adjusted reference point shifted relative to a reference point voltage or time shifted for decoding operational information such as user data (which may be referred to as an ideal, default, or operating reference point), then the error limit of the channel can be determined to be at least as large in the time or voltage domain as the difference between the adjusted reference point and the ideal reference point. Alternatively, the memory device may transmit candidate sequences decoded by the memory device to a host device, and the host device may compare the candidate sequences with the sequences transmitted by the host device to determine error limits. Based on the error limits, the host device may take corrective or mitigating measures, such as instructing the memory device to calibrate the sampler (e.g., adjust the reference point used by the sampler) to improve sampling of subsequent data transmissions from the host device.

[0024] Firstly, in reference Figure 1 and 2The features of this disclosure are described in the context of the memory system and the die. Then, in the references... Figures 3 to 5 The features of this disclosure are described in the context of the memory system, eye diagram, and process flow. Further details are provided in conjunction with references. Figures 6 to 11 The device diagrams and flowcharts related to link evaluation for memory devices are described, and these and other features of this disclosure are described with reference to the device diagrams and flowcharts.

[0025] Figure 1 This document describes an example of a system 100 utilizing one or more memory devices, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0026] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0027] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, or some other fixed or portable electronic device and other examples. In some examples, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0028] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation scheme of the modulation signal, various pin configurations for transmitting signals, various physical package dimensions of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0029] Memory device 110 is operable to store data of components of host device 105. In some instances, memory device 110 may be used as a slave device of host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0030] The host device 105 may include one or more of the following: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0031] Processor 125 is operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or combination of these components. In such instances, processor 125 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances. In some instances, external memory controller 120 may be implemented by or may be part of processor 125.

[0032] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0033] In some instances, system 100 or host device 105 may include an I / O controller. The I / O controller manages data communication between processor 125 and peripheral components, input devices, or output devices. The I / O controller can also manage peripheral devices not integrated into system 100 or host device 105. In some instances, the I / O controller may represent a physical connection or port to an external peripheral component.

[0034] In some instances, system 100 or host device 105 may include input components, output components, or both. An input component may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or its components. In some instances, an input component may include a user interface or interface with other devices or intersect with other devices. In some instances, an input component may be a peripheral device that interfaces with system 100 via one or more peripheral components, or may be managed by an I / O controller. An output component may represent a device or signal external to system 100 operable to receive output from any of system 100 or its components. Examples of output components may include a display, audio speaker, printing device, another processor on a printed circuit board, and others. In some instances, an output may be a peripheral device that interfaces with system 100 via one or more peripheral components, or may be managed by an I / O controller. In some instances, system 100 may include a channel between the I / O controller of host device 105 and the I / O controller of memory device 110.

[0035] Memory device 110 may include a memory controller 155 supporting a desired or specified capacity for data storage and one or more memory dies 160 (e.g., memory chips). Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory, a multi-die package, a multi-chip memory, or a multi-chip package.

[0036] Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions enabling memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information associated with components of memory device 110. Device memory controller 155 is operable to communicate with one or more of external memory controller 120, memory dies 160, or processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with local memory controller 165 of memory die 160. In some instances, device memory controller 155 may include or be coupled to an I / O controller of memory device 110.

[0037] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data in host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0038] A local memory controller 165 (e.g., local to memory die 160) is operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120, or processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0039] External memory controller 120 is operable to transfer one or more of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, the external memory controller 120, or other components of system 100 or host device 105, or its functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0040] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to serve as part of a channel.

[0041] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, information may be transmitted via channel 115 using SDR signaling or DDR signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be recorded for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be recorded for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0042] In some instances, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 are operable to transmit commands between host device 105 and memory device 110, including control information (e.g., address information) associated with the commands. For example, CA channel 186 may contain an address for reading a command and expected data. In some instances, CA channel 186 may contain any number of signal paths to decode one or more of the address or command data (e.g., 8 or 9 signal paths).

[0043] In some instances, channel 115 may include one or more clock signal channels 188 (e.g., CK channel). Clock signal channels 188 are operable to transmit one or more clock signals between host device 105 and memory device 110. Each clock signal is operable to oscillate between high and low states and may support coordination (e.g., time coordination) between host device 105 and memory device 110. In some instances, the clock signal may be single-ended. In some instances, the clock signal may provide a timing reference for command and addressing operations of memory device 110 or other system-wide operations of memory device 110. For example, signals received via other channels 115 (e.g., CA channel 186, DQ channel 190) may be edge-sampled based on the system clock signal. The clock signal may therefore be referred to as a control clock signal, command clock signal, or system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillator, crystal, logic gate, transistor).

[0044] In some instances, channel 115 may include one or more data (DQ) channels 190. Data channels 190 are operable to transfer one or more of data or control information between host device 105 and memory device 110. For example, data channel 190 may transfer information written to memory device 110 (e.g., bidirectional) or information read from memory device 110.

[0045] Channel 115 may contain signaling that can be sampled by a sampler at memory device 110. The sampler samples the signaling by measuring the voltage level of the signal during a unit interval to determine the logic state of the signal (e.g., logic '0' or logic '1') during the unit interval. The unit interval may be defined by a clock associated with the transmission of the measured signal (e.g., the unit interval may span the duration of the rising or falling edge of the clock during its occurrence). The sampler may compare the measured voltage level with a reference voltage at the sampling time, wherein the reference voltage and the sampling time may correspond to reference points in the time and voltage domains.

[0046] In some cases, memory device 110 may receive signaling containing a sequence of logic values ​​from host device 105 via evaluation channel 115. The sequence of logic values ​​may be pre-configured or otherwise include logic values ​​known a priori to memory device 110. Memory device 110 may sample the signaling at one or more reference points in the time and voltage domains to obtain candidate sequences of logic values. In some cases, memory device 110 may include multiple samplers to sample the signaling simultaneously at multiple reference points. In other cases, host device 105 may repeatedly transmit the sequence, and memory device 110 may use the same sampler but sample each example of the sequence at different (reconfigured) reference points. For each candidate sequence determined by memory device 110, memory device 110 may compare the candidate sequence with the transmitted sequence to determine an error limit. Alternatively or concurrently, memory device 110 may transmit the candidate sequence to host device 105, and host device 105 may compare the candidate sequence with the transmitted sequence to determine an error limit. Based on the error limits, the host device 105 may instruct the memory device 110 to calibrate the sampler or may take other corrective measures to improve the sampling of subsequent data transmissions from the host device 105.

[0047] Channel 115 may each contain any number of signal paths (including a single signal path). In some instances, channel 115 may contain multiple individual signal paths. For example, a channel may be x4 (e.g., containing 4 signal paths), x8 (e.g., containing 8 signal paths), x16 (e.g., containing 16 signal paths), etc.

[0048] In some instances, one or more other channels 192 may include one or more Error Detection Code (EDC) channels. EDC channels can be operated to transmit error detection signals, such as checksums, to improve system reliability. EDC channels may contain any number of signal paths.

[0049] Signals transmitted via channel 115 may be modulated using one or more different modulation schemes. In some instances, a binary symbol (or binary level) modulation scheme may be used to modulate signals transmitted between host device 105 and memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M equals 2. Each symbol of the binary symbol modulation scheme is operable to represent a digital data bit (e.g., a symbol may represent logic 1 or logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or others.

[0050] In some instances, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between host device 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme is operable to represent more than one digital data bit (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or others. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme comprising at least three levels encoding more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0051] Figure 2 This describes an example of a memory die 200 based on the examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of memory die 160 described. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each programmable to store different logical states (e.g., a set of two or more programmable states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., multilevel memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11).

[0052] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor containing a dielectric material that stores charge representing a programmable state. In other memory architectures, other memory devices and components are possible. For example, a nonlinear dielectric material may be used. Memory cell 205 may include logic storage components, such as capacitor 230 and switching components 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. Nodes of capacitor 230 may be coupled to a voltage source 240, which may be a cell board reference voltage (e.g., Vpl) or grounded (e.g., Vss).

[0053] The memory die 200 may include one or more access lines (e.g., one or more word lines 210 and one or more digital lines 215) arranged in a pattern such as a grid pattern. The access lines may be conductive lines coupled to memory cells 205 and used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. The referenced access lines, row lines, column lines, word lines, digital lines, or bit lines, or the like, may be interchanged without loss of understanding or operability. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215.

[0054] For example, read and write operations can be performed on memory cell 205 by activating or selecting one or more access lines, such as word line 210 or digital line 215. A single memory cell 205 can be accessed at its intersection by applying a bias to word line 210 and digital line 215 (e.g., applying a voltage to word line 210 or digital line 215). The intersection of word line 210 and digital line 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of memory cell 205.

[0055] The memory access unit 205 can be controlled by either row decoder 220 or column decoder 225. For example, row decoder 220 can receive a row address from local memory controller 260 and activate word line 210 based on the received row address. Column decoder 225 can receive a column address from local memory controller 260 and activate digital line 215 based on the received column address.

[0056] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 235 using word line 210. Capacitor 230 can be coupled to digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and capacitor 230 can be coupled to digital line 215 when switch assembly 235 is activated.

[0057] Sensing component 245 is operable to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. Sensing component 245 may include one or more sensing amplifiers to amplify or otherwise convert the signal caused by accessing memory cell 205. Sensing component 245 may compare the signal detected from memory cell 205 with reference 250 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., to input / output 255) and may indicate the detected logic state to another component of the memory device including memory die 200.

[0058] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 may be a reference. Figure 1 Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing component 245 may co-locate with local memory controller 260. Local memory controller 260 is operable to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. Local memory controller 260 may generate row signals and column address signals to activate target word line 210 and target digital line 215. Local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for various operations discussed when operating the memory die 200.

[0059] In some instances, the local memory controller 260 may include or be coupled to one or more samplers, each operable to sample signaling received via channel 115 to identify commands, data, or other information encoded in the signaling. The local memory controller 260 may be configured to support link evaluation by determining error limits associated with the channel between host device 105 and memory die 200. The samplers may sample signaling containing a sequence of logical values ​​received from host device 105 and thereby obtain candidate logical value sequences. In some instances, the local memory controller 260 may compare the candidate sequences with the sequence to determine error limits. Alternatively, the local memory controller 260 may transmit the candidate sequences to host device 105, and host device 105 may compare the candidate sequences with the sequence to determine error limits. Based on the error limits, host device 105 may instruct the local memory controller 260 to calibrate the samplers to improve sampling for subsequent data transfers from host device 105.

[0060] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, and others. The local memory controller 260 is operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0061] The local memory controller 260 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 to which the write operation will be performed. The local memory controller 260 can identify the target word line 210 and target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

[0062] The local memory controller 260 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 can identify the target word line 210 and target digital line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and target digital line 215 (e.g., apply a voltage to the word line 210 or digital line 215) to access the target memory cell 205. The target memory cell 205 can transmit a signal to the sensing component 245 in response to applying a bias voltage to the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., a latching sensing component) and thereby compare the signal received from the memory cell 205 with the reference 250. Based on the comparison, the sensing component 245 can determine the logic state stored in the memory cell 205.

[0063] Figure 3This document describes an example of a memory system 300 that supports link evaluation based on the examples disclosed herein. The memory system 300 may include a host device 305 and a memory device 310, which may be used as a reference. Figure 1 An example of the corresponding device described.

[0064] Components of host device 305 may exchange information with memory device 310 using one or more channels 115, where channel 315 may be an instance of the aforementioned channel 115. For example, I / O component 320 of host device 305 may transmit instructions (commands) to I / O component 325 of memory device 310 via channel 315-a. For example, channel 315-a may be a reference... Figure 1 The CA channel 186 is described. Additionally, channel 315-b is operable to support communication between the memory controller 335 at the host device 305 and the memory device 310. Channel 315-b can transfer data information between the host device 305 and the memory device 310. For example, channel 315-b may be a reference... Figure 1 The described DQ channel 190 transmits information written to or read from the memory device 310 (e.g., bidirectionally).

[0065] Memory device 310 can receive signaling containing (encoded) logic values ​​from host device 305 via channel 315-b. In some instances, memory device 310 can identify the logic values ​​(e.g., data written to the memory array or a test sequence used to evaluate the conditions of channel 315-b) based on instructions received at I / O component 325. To determine the encoded logic values, memory device 310 can use sampler 340 to sample the signaling on channel 315-b at one or more reference points in the time and voltage domains. Sampler 340 can sample the signaling on one or both of the rising and falling edges of clock signal 345 based on the type of signaling (e.g., SDR or DDR signaling). Figure 3 The description states that sampler 340 can sample the signaling at time 355 on the rising edge of clock signal 345.

[0066] At time 355, sampler 340 measures the voltage level of the signaling and compares the measured voltage level with a reference voltage to determine the logic value (e.g., logic '0' or logic '1') at time 355. During normal operation (e.g., when decoding data for storage in memory device 310 or commands issued by host device 305), time 355 via channel 315-b and the signaling can be configured such that the signaling is sampled near the middle of a unit interval (or another reference point previously corresponding to the middle of a data eye) to avoid errors in determining the logic state of the signaling. Similarly, the reference voltage can be configured such that the reference voltage is at the midpoint between a first voltage level corresponding to a first logic value and a second voltage level corresponding to a second logic value. Time 355 and the reference voltage can together include a reference point used by the sampler, and the reference point used during normal operation can be referred to as the default, ideal, or operating reference point.

[0067] Based on sampling, the memory controller 330 or other components (e.g., row or column decoders) of the memory device 310 coupled to the sampler 340 and I / O component 325 can obtain logical values; that is, the sampler 340 can output logical values ​​encoded by the host device 305 in the sampled signaling. Although Figure 3 The example shown is a sampler 340, but in some instances, such as the reference... Figure 4 As further described herein, the memory device 310 may include a plurality of samplers 340 to sample signaling simultaneously at multiple reference points.

[0068] Figure 4 This document describes an example of an eye diagram 400 for support link evaluation based on the examples disclosed herein. The eye diagram 400 can depict superimposed data transmissions from different unit intervals in the time domain corresponding to the duration of each unit interval (or other sampling period, which may alternatively be referred to as a sample period) and can illustrate references. Figures 1 to 3 The description describes the behavior or operation of aspects of system 100, memory die 200, and memory system 300. Therefore, eye diagram 400 illustrates behaviors and operations that can occur across any number of unit intervals.

[0069] For example, eye diagram 400 can indicate signal quality and represent different possible logic values ​​(e.g., logic '0' or logic '1') that can be encoded into a signal. Each logic value can be represented by different voltage amplitudes (e.g., voltage levels 405-a and 405-b). Eye diagram 400 can provide a visual indication of the health and integrity of a signal. In this example, eye diagram 400 illustrates two distinct voltage levels 405 (e.g., first voltage level 405-a and second voltage level 405-b) that can ideally be transmitted via a data channel. In some instances, eye diagram 400 can represent a memory device (e.g., a reference) that can be used for transmission. Figure 1The described memory device 110) contains binary-level signals (e.g., NRZ signals) of data. Additionally, the binary-level signaling represented by eye diagram 400 can correspond to data transmission via a non-terminal transmission line. For example, NRZ signaling can be transmitted via a channel without an active termination. Although eye diagram 400 can represent a signal (e.g., a binary-level signal) modulated according to a scheme involving two voltage levels 405, it should be understood that the principles and techniques described herein are extendable to modulation schemes using any number of voltage levels.

[0070] Eye diagram 400 may span sample periods 410 (e.g., unit intervals or bit periods). Sample periods 410 may be based on a clock definition associated with the transmission of the measured signal (e.g., sample periods 410 may span one cycle or period of a clock). Eye diagram 400 may show the voltage level of the signal over several sample periods 410 during which they are superimposed to form trace 415. Noise and other factors can cause trace 415 to deviate from a set of ideal step functions. By superimposing multiple traces 415, various characteristics of the measured signal can be illustrated. For example, eye diagram 400 may illustrate different characteristics of communication signals, such as jitter, crosstalk, distortion, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. Closing the eye may indicate noisy and / or unpredictable signals.

[0071] The 'eye' in eye diagram 400 can refer to the space between traces 415 and may include a width (e.g., width 420) and an opening (e.g., opening 430). Regarding eye diagram 400, the region between voltage levels 405-a and 405-b, lacking trace 415, as the signal converges toward one of voltage levels 405-a and 405-b, can therefore be referred to as the eye of eye diagram 400. Various encoding and decoding techniques can be used to modify the width 420 of the measured signal.

[0072] To distinguish different voltage levels 405 during signal decoding, a corresponding reference voltage 440 can be positioned between different ideal voltage levels 405 associated with trace 415. The difference between voltage level 405-b (maximum expected or ideal maximum voltage) and voltage level 405-a (minimum expected or ideal minimum voltage) can be referred to as the voltage swing of the signal. Reference voltage 440-a can be equidistant from voltage levels 405-b and 405-a, and thus can represent an instance of the ideal reference voltage corresponding to the center of the data eye. When decoding user data (for data stored in the memory array) or commands, the signal represented by trace 415 can be compared with reference voltage 440-a at sampling time 425. For example, sampling time 425-a can occur near the middle of the sampling period 410, which can correspond to the time center of the data eye. Reference point 435 in the time and voltage domains (e.g., its time domain corresponding to the sampling period 410 and its voltage domain corresponding to the voltage swing) can represent a combination of reference voltage 440 and sampling time 425. For example, reference point 435-a can be represented as the ideal reference point 435 corresponding to the center of the data eye at sampling time 425-a and therefore corresponding to the reference voltage 440-a.

[0073] The closer the reference point 435 is to the edge of the data eye, the more likely errors will occur when decoding the signal represented by the data eye. In operation, the data eye used for signaling via the channel can vary, for example, due to cross-coupling, noise, unstable voltage, and the like. For instance, if a signal conveying a logic value associated with the first voltage level 405-a is higher than the reference voltage 440 used by the sampler 340 when sampling time 425 occurs, then an error (e.g., an incorrect value) can therefore be detected. Thus, even if the logic value associated with the first voltage level 405-a is expected, the receiver can determine that a logic value associated with the second voltage level 405-b has been transmitted.

[0074] As described herein, to avoid or mitigate transmission or decoding errors (e.g., reduce the likelihood or occurrence of transmission or decoding errors), a device (e.g., a reference device) Figure 1The described memory device 110 or host device 105 can determine error limits (e.g., buffers, intervals in the time or voltage domain relative to the edges of the data eye diagram 400) associated with the operating reference point 435 used by the sampler 340. The memory device can receive signaling containing a sequence of logic values ​​(which may be referred to as test signaling containing a sequence of test logic values) from the host device via a channel. In some instances, the memory device can sample the signaling at the adjusted reference point 435 in each sample period 410 to determine the error limits. The memory device can adjust the reference point 435 by adjusting the reference voltage 440 or by adjusting the sampling time 425. For example, the memory device can adjust the phase interpolator used for the sampler, or the memory device can adjust the amount of delay in the signal path of the sampling clock. Examples of adjusted reference points 435 may include reference points 435-b, 435-c, 435-d, and 435-e. Reference point 435-b may correspond to sampling time 425-b and reference voltage 440-c, reference point 435-c may correspond to sampling time 425-c and reference voltage 440-c, reference point 435-d may correspond to sampling time 425-c and reference voltage 440-b, and reference point 435-e may correspond to sampling time 425-b and reference voltage 440-b. By sampling the test signaling at the adjusted reference point 435 and determining whether the logic value determined by this sampling matches the expected (e.g., previously indicated, pre-configured, or originally known) logic value used for the test signaling, the memory device can determine the error limits associated with the channel through which it receives the test signaling.

[0075] In a first example, the memory device may determine that the signaling represented by the eye diagram 400 is sampled at reference point 435-d. That is, in each sample period 410 spanned by the signaling, the memory device may sample the signaling at sampling time 425-c and compare the signal with a reference voltage 440-b to determine the logic value corresponding to the sample period 410. The memory device may sample the signaling at reference point 435-d during consecutive sampling periods 410 to determine a sequence of candidate logic values. In some examples, the memory device may compare the candidate sequence with a expected sequence of logic values. Alternatively or concurrently, the memory device may transmit the candidate sequence to a host device, and the host device may compare the candidate sequence with the expected sequence.

[0076] exist Figure 4In the example described, reference point 435-d is within the data eye of eye diagram 400, and therefore the candidate logic value sequence matches the expected logic value sequence. Based on the comparison, the memory device (or host device) can determine the error limits of the channel carrying signaling. The error limits can be determined to be at least as large as the difference in the time domain and the difference in the voltage domain between reference points 435-a and 435-d. For example, the difference in the time domain may correspond to the difference between sampling time 425-a and sampling time 425-c, and the difference in the voltage domain may correspond to the difference between reference voltage 440-a and reference voltage 440-b. In the example of reference point 435-d, the error limits may include a negative difference in the time domain and a positive difference in the voltage domain.

[0077] In the second example, the memory device may determine that the signaling represented by the eye diagram 400 is sampled at reference point 435-b. That is, in each sample period 410 spanned by the signaling, the memory device may sample the signaling at sampling time 425-b and compare the signal with a reference voltage 440-c to determine the logic value corresponding to the sample period 410. The memory device may sample the signaling at reference point 435-b during consecutive sampling periods 410 to determine a sequence of candidate logic values. The candidate sequence may be compared with a expected sequence.

[0078] exist Figure 4 In the example described, reference point 435-b is outside the data eye of eye diagram 400, and therefore one or more errors (e.g., incorrect decoded values, mismatches) can be detected in the candidate logic value sequence based on comparison. For example, a logic value represented by trace 415-a (e.g., logic '0') can be incorrectly detected as a logic value represented by trace 415-b (e.g., logic '1'). Based on the sequence comparison, the error limit can be determined to be less than the difference in the time domain and the difference in the voltage domain between reference point 435-a and reference point 435-b. For example, the difference in the time domain could correspond to the difference between sampling time 425-a and sampling time 425-b, and the difference in the voltage domain could correspond to the difference between reference voltage 440-a and reference voltage 440-c. In the example of reference point 435-b, the error limit could include a positive difference in the time domain and a negative difference in the voltage domain.

[0079] In some instances, the memory device may include multiple samplers that enable the memory device to sample signaling at multiple reference points 435 in each sample period 410. For example, in addition to sampling the signal at reference point 435-a, the memory device may additionally sample the signal at adjusted reference points 435-d and 435-b and adjusted reference points 435-a and 435-c as described in the first and second instances. Alternatively, the host device may transmit signaling comprising multiple repetitions (i.e., multiple examples of test signaling) of a sequence of logic values, and the memory device may sample the signaling at different reference points 435 during each repetition. Based on sampling the signaling at multiple reference points 435, the error limits of the channel can be determined using positive and negative differences in each of the time and voltage domains. It should be understood that the memory device may sample the signaling at any number of adjusted reference points 435 (not shown) to obtain estimates of the error limits at any desired granularity and in any number of directions and domains.

[0080] The memory device or host device can determine whether an error limit exceeds a threshold (e.g., whether an error limit in one or more directions and domains exceeds a corresponding threshold). If the error limit exceeds the threshold, then the error limit can be determined to be tolerable for the operation of the channel. If the error limit does not exceed the threshold (e.g., if a threshold number (e.g., 1) of the error limits in different directions and thresholds is below its corresponding threshold), then the memory device or host device can determine to take steps to improve communication on the channel. For example, the memory device or host device can determine to initiate a recalibration procedure for one or more samplers at the memory device to improve sampling of subsequent data transmissions from the host device.

[0081] Figure 5 This document describes an example of process flow 500 for supporting link evaluation based on the examples disclosed herein. In some instances, process flow 500 may be described with reference to [reference needed]. Figures 1 to 3 The described embodiments include aspects of system 100, memory die 200, and memory system 300. For example, process flow 500 may include connections to host device 505 and memory device 510 (which may be referenced). Figures 1 to 3This refers to one or more instances of transmission or operation associated with the corresponding devices described. In the following description of process flow 500, transmissions between host device 505 and memory device 510 may be transmitted in a sequence different from the order of the examples shown, or operations performed by host device 505 and memory device 510 may be performed in a different order or at different times. Some transmissions or operations may also be omitted from process flow 500, and others may be added to process flow 500. Transmissions and operations performed by host device 505 and memory device 510 may support improved operation of memory device 510 and, in some instances, may promote increased reliability of memory device 510 and other benefits.

[0082] At 515, host device 505 and memory device 510 can exchange commands and data. Commands and data can be exchanged via one or more channels (e.g., reference...). Figure 1 The described channel 115) exchanges data. Commands and data may correspond to read or write operations at memory device 510. For example, host device 505 may transmit signaling corresponding to a read or write operation to memory device 510. Memory device 510 may sample the signaling (e.g., using a sampler) to determine a logic value (e.g., logic '0' or logic '1'). For example, within a unit interval of the signaling, the memory device may measure the voltage level of the signaling at the sampling (reference) time and compare the measured voltage level with a reference voltage to determine a logic value associated with the unit interval. The sampling time may be configured such that the signaling is sampled near the middle of the unit interval to avoid errors in determining the logic value of the signaling. Similarly, the reference voltage may be configured such that the reference voltage is at the midpoint between a first voltage level corresponding to a first logic value and a second voltage level corresponding to a second logic value.

[0083] At 520, host device 505 may transmit a command to memory device 510 to initiate link evaluation. The command may be transmitted via the CA channel or another channel. In some instances, the command may be an auto-refresh command for memory device 510. For example, during a time period following the auto-refresh command, memory device 510 may refresh memory cells within the memory array at memory device 510, while simultaneously performing link evaluation on one or more channels between host device 505 and memory device 510.

[0084] In some instances, the command may indicate or include a sequence of logical values ​​to be transmitted to memory device 510 as part of a link evaluation. In other instances, the sequence of logical values ​​may be pre-configured (e.g., normalized) at memory device 510 or previously sent to memory device 510.

[0085] In some instances, the command may instruct the memory device to activate one or more samplers to perform link evaluation. In other instances, the memory device may use a single sampler to perform link evaluation, and the sequence of logical values ​​may be transmitted once or more (where different examples of the sequence are sampled one after another using different reference points).

[0086] At 525, host device 505 may transmit signaling (e.g., test signaling) containing a sequence of logical values ​​to memory device 510. In some instances, memory device 510 may identify the signaling at 525 based on a command received at 520. For example, memory device 510 may identify the signaling based on the timing relationship between the command and the signaling. The sequence of logical values ​​may include a test sequence for performing link evaluation. The sequence of logical values ​​may be transmitted one or more times.

[0087] At 530, the memory device 510 can sample the signaling to determine a corresponding candidate logical value sequence for each example of the logical value sequence. The memory device 510 can sample the signaling using one or more reference points, for example, using one or more samplers. In some instances, multiple reference points can be sampled simultaneously, or the memory device 510 can sample different repetitions of the logical value sequence at different reference points to determine multiple candidate sequences.

[0088] In some instances, at 535, memory device 510 may compare one or more candidate sequences with a sequence of logical values ​​to determine error limits (or multiple error limits, each corresponding to a corresponding orientation and domain). For example, memory device 510 may compare each of the values ​​detected at multiple reference points with a corresponding expected value. In some instances, memory device 510 may make a pass or fail determination of the error limits based on a threshold. For example, if the error limit is above the threshold, then memory device 510 may determine that the error limit is acceptable, or if the error limit is below the threshold, then memory device 510 may determine that the error limit is unacceptable. In some cases, the threshold may be equal to the difference between the adjusted reference point and the ideal reference point (e.g., in orientation and domain), and therefore any mismatch between the candidate sequence and the expected sequence based on the adjusted reference point may indicate that the error limit is below the threshold. Alternatively, the threshold may be less than the difference between the adjusted reference point and the ideal reference point (e.g., in orientation and domain). In some cases, the threshold may correspond to the estimated variability of the reference point. For example, the reference point can differ in different sampling periods based on changes in the conditions associated with the sampler or signal (e.g., using different reference voltages, different sampling times, or both). If the error limit is above a threshold, then the memory device 510 can successfully receive data without error caused by the variability of the reference point.

[0089] In some instances, memory device 510 may determine multiple error limits (e.g., in multiple domains, directions, or both) based on sampling. For example, memory device 510 may determine an error limit associated with the sampling time that is above a time threshold, but an error limit associated with the reference voltage that is below a voltage threshold. In some instances, memory device 510 may determine to adjust one or both of the sampling time and the reference voltage based on the determined error limits. Memory device 510 may perform the determined adjustment by initiating a recalibration procedure associated with one or more samplers.

[0090] At 540, memory device 510 may transmit feedback to host device 505 based on sampling of the signal. In some instances, the feedback may include one or more candidate sequences determined by the sampler to support comparison by host device 505. Alternatively or additionally, the feedback may be based on comparing one or more candidate sequences with a sequence of logic values ​​by memory device 510. For example, the feedback may include one or more error limits or indications of whether they exceed one or more relevant thresholds, indications of determined adjustments to one or both of the sampling time and reference voltage, indications of initiating a recalibration procedure, indications of the result of the recalibration procedure, or a combination thereof.

[0091] In some instances, at 545, host device 505 may compare one or more candidate sequences with a sequence of logical values ​​based on feedback from memory device 510. In some instances, host device 505 may determine an error limit based on the comparison sequence. For example, host device 505 may compare values ​​detected at multiple reference points within a unit interval with expected values ​​based on the sequence of logical values. In some instances, host device 505 may determine whether the error limit passes or fails based on a threshold. For example, if the error limit is higher than the threshold, then host device 505 may determine that the error limit is acceptable, or if the error limit is lower than the threshold, then host device 505 may determine that the error limit is unacceptable.

[0092] In some instances, host device 505 may determine multiple error limits (e.g., in multiple domains, directions, or both) based on the received candidate sequence. For example, host device 505 may determine that the error limit associated with sampling time is above a time threshold, but the error limit associated with reference voltage is below a voltage threshold. In some instances, host device 505 may determine to adjust one or both of the sampling time and reference voltage based on the determined error limits. Host device 505 may determine to perform the determined adjustment by initiating a recalibration procedure associated with one or more samplers.

[0093] In some instances, at 550, host device 505 may transmit additional signaling to memory device 510. In some instances, the signaling may include a command or instruction to initiate a recalibration procedure to perform a determined adjustment. Alternatively or additionally, the signaling may include an indication of determined adjustment or a new default reference point for the sampler at memory device 510. In some instances, the signaling may include an acknowledgment or approval message associated with the determined adjustment performed by memory device 510.

[0094] The operations performed by the host device 505 and the memory device 510 can therefore support improved data processing operations and, in some instances, promote increased reliability of the memory device 510, among other benefits. Although the process flow is described with reference to the data channel, the operations can be performed to support link checks on any channel 115. Furthermore, the actions and associated operations performed by the host device 505 and the memory device 510 can be reversed. For example, the memory device 510 can transmit signaling containing a sequence of logical values ​​to the host device 505, and the host device 505 can sample the signaling to determine candidate sequences and identify error limits.

[0095] Figure 6 A block diagram 600 illustrates a memory device 605 supporting link evaluation according to an example disclosed herein. The memory device 605 may be used as a reference. Figures 1 to 3 Examples of aspects of the memory device described in section 5. The memory device 605 may include a receiving component 610, a sampling component 615, a command identification component 620, and a sequence comparison component 625. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0096] The receiving component 610 may receive, via a channel, a first signaling associated with data stored in a memory device. In some instances, the receiving component 610 may receive, via a channel, a second signaling associated with a sequence of logical values. In some instances, the receiving component 610 may receive an indication of a sequence of logical values ​​from a host device before receiving the second signaling.

[0097] Sampling component 615 can sample first signaling based on a first reference point in the time and voltage domains to obtain data. In some instances, sampling component 615 can sample second signaling based on a second reference point in the time and voltage domains to obtain a sequence of candidate logic values. In some instances, sampling component 615 can sample second signaling based on the first reference point to obtain a sequence of logic values.

[0098] In some instances, sampling component 615 may sample the second signaling based on a third reference point in both the time and voltage domains to obtain a second candidate logic value sequence, wherein the third signaling is based on a comparison between the second candidate sequence and the logic value sequence. In some instances, sampling component 615 may sample the second signaling based on the third reference point, occurring after sampling the second signaling based on the second reference point. In some instances, sampling component 615 may sample the second signaling based on the third reference point, occurring simultaneously with sampling the second signaling based on the second reference point.

[0099] In some instances, sampling component 615 may adjust a time or voltage reference used by a sampler contained in a memory device, wherein the adjustment occurs after sampling the first signaling and before sampling the second signaling, and wherein the second reference point corresponds to the adjusted time or voltage reference. In some instances, sampling component 615 may activate a second sampler contained in a memory device after sampling the first signaling, wherein the first sampler contained in the memory device is operable to use the first reference point and the second sampler is operable to use the second reference point.

[0100] In some instances, sampling component 615 may determine that the channel's error limits are insufficient based on comparison. In some instances, the sampler is calibrated based on determining that the error limits are insufficient, wherein the third signaling contains an indication for calibration. In some cases, the second reference point is earlier or later than the first reference point in the time domain. In some cases, the second reference point is at a higher or lower voltage than the first reference point in the voltage domain.

[0101] Command identification component 620 can identify a second signaling as associated with a sequence of logical values ​​based on a command received from the memory device. In some instances, command identification component 620 can identify the second signaling as associated with a sequence of logical values ​​based on the timing relationship between the received command and the received second signaling. In some instances, command identification component 620 can receive a command from the sampler of the calibration channel at the memory device. In some cases, the command includes an automatic refresh command.

[0102] The sequence comparison component 625 can transmit third signaling based on a comparison of candidate logic value sequences with logic value sequences by a memory device. In some instances, the sequence comparison component 625 can determine a match between candidate sequences and sequences. In some instances, the sequence comparison component 625 can determine, based on a match, that the channel's error limit is greater than or equal to the difference between a second reference point and a first reference point. In some instances, the sequence comparison component 625 can determine a mismatch between candidate sequences and sequences. In some instances, the sequence comparison component 625 can determine, based on a mismatch, that the channel's error limit is less than the difference between a second reference point and a first reference point.

[0103] Figure 7 A block diagram 700 illustrates a host device 705 supporting link evaluation according to an example disclosed herein. Host device 705 may be an example of an aspect of the host device described with reference to Figures [[XX to YY]]. Host device 705 may include a feedback component 710, an instruction component 715, a command signaling component 720, and a channel condition component 725. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0104] Feedback component 710 can receive feedback from a memory device based on signaling associated with a sequence of logic values. In some instances, feedback component 710 can compare an error boundary with a threshold. In some cases, the feedback includes an indication of whether the error boundary is below a threshold.

[0105] The instruction unit 715 can transfer instructions to the memory device based on feedback.

[0106] Command signaling component 720 can transmit commands associated with indication signaling and logical value sequences to the memory device.

[0107] Channel condition component 725 can transmit signaling associated with a sequence of logical values ​​to a memory device via a channel, wherein the signaling supports the determination of conditions for the channel. In some instances, channel condition component 725 can compare candidate sequences with a sequence. In some instances, channel condition component 725 can determine conditions based on the comparison. In some cases, the conditions include an error limit for the channel in at least one of the time or voltage domains.

[0108] Figure 8 The flowchart illustrates one or more methods 800 for support link evaluation based on the examples disclosed herein. Operation of method 800 may be implemented by a memory device or its components described herein. For example, operation of method 800 may be performed by a reference... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0109] At 805, the memory device may receive, via a channel, a first signaling associated with data stored in the memory device. Operation 805 may be performed according to the methods described herein. In some instances, aspects of operation 805 may be derived from references... Figure 6 The described receiving component is executed.

[0110] In operation 810, the memory device may sample the first signaling based on a first reference point in both the time and voltage domains to obtain data. Operation 810 may be performed according to the methods described herein. In some instances, aspects of operation 810 may be derived from a reference... Figure 6The sampling component described is executed.

[0111] In operation 815, the memory device can receive a second signaling associated with a sequence of logical values ​​via a channel. Operation 815 can be performed according to the method described herein. In some instances, aspects of operation 815 may be derived from references. Figure 6 The described receiving component is executed.

[0112] In operation 820, the memory device may sample the second signaling based on a second reference point in both the time and voltage domains to obtain a sequence of candidate logic values. Operation 820 may be performed according to the method described herein. In some instances, aspects of operation 820 may be derived from a reference... Figure 6 The sampling component described is executed.

[0113] In 825, the memory device can transmit a third signaling based on a comparison of a candidate logical value sequence with a logical value sequence. Operation 825 can be performed according to the methods described herein. In some instances, aspects of operation 825 may be derived from references. Figure 6 The sequence comparison component described is executed.

[0114] In some instances, the apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, via a channel, a first signaling associated with data stored in a memory device; sampling the first signaling based on a first reference point in the time and voltage domains to obtain the data; receiving, at the memory device, via a channel, a second signaling associated with a sequence of logical values; sampling the second signaling based on a second reference point in the time and voltage domains to obtain a candidate sequence of logical values; and transmitting, by the memory device, a third signaling based on a comparison of the candidate sequence of logical values ​​with the sequence of logical values.

[0115] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: determining a match between candidate sequences and sequences; and determining an error limit for a channel based on the match that is greater than or equal to the difference between a second reference point and a first reference point.

[0116] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: determining a mismatch between candidate sequences and sequences; and determining an error limit for a channel based on the mismatch that may be less than the difference between a second reference point and a first reference point.

[0117] Some examples of the method 800 and apparatus described herein may further include methods for identifying a second signaling as an operation, feature, component, or instruction associated with a sequence of logical values ​​based on a command received from a memory device.

[0118] Some examples of the method 800 and apparatus described herein may further include methods for identifying the second signaling as an operation, feature, component, or instruction associated with a sequence of logical values, based on the timing relationship between the received command and the received second signaling.

[0119] In some instances of the method 800 and device described herein, the commands include an automatic refresh command.

[0120] In some instances of the method 800 and device described herein, the second reference point may be earlier or later than the first reference point in the time domain.

[0121] In some instances of the method 800 and apparatus described herein, the second reference point may be at a voltage higher or lower than that of the first reference point in the voltage domain.

[0122] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for receiving an indication of a sequence of logical values ​​from a host device prior to receiving a second signaling.

[0123] Some examples of the method 800 and device described herein may further include operations, features, components, or instructions for sampling a second signaling based on a first reference point to obtain a sequence of logical values.

[0124] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for sampling a second signaling based on a third reference point in the time and voltage domains to obtain a second candidate logic value sequence, wherein the third signaling may be based on a comparison of the second candidate sequence with the logic value sequence.

[0125] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for sampling the second signaling based on a third reference point, occurring after the sampling of the second signaling based on the second reference point.

[0126] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for sampling the second signaling based on a third reference point, occurring simultaneously with the sampling of the second signaling based on the second reference point.

[0127] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for adjusting a time or voltage reference used by a sampler contained in a memory device, wherein the adjustment may occur after sampling of a first signaling and before sampling of a second signaling, and wherein the second reference point corresponds to the adjusted time or voltage reference.

[0128] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for activating a second sampler contained in a memory device after sampling of a first signaling, wherein the first sampler contained in the memory device is operable to use a first reference point and the second sampler is operable to use a second reference point.

[0129] In some instances of the method 800 and apparatus described herein, the third signaling may include operations, features, components, or instructions for receiving a sampler for a calibration channel at a memory device.

[0130] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for: determining, based on comparison, that the error limits of a channel may be insufficient; and calibrating the sampler based on determining that the error limits may be insufficient, wherein a third signaling includes an indication for calibration.

[0131] Figure 9 The flowchart illustrates one or more methods 900 for support link evaluation based on the examples disclosed herein. Operation of method 900 may be implemented by a memory device or its components described herein. For example, operation of method 900 may be performed by a reference... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0132] At 905, the memory device may receive, via a channel, a first signaling associated with data stored in the memory device. Operation 905 may be performed according to the methods described herein. In some instances, aspects of operation 905 may be derived from references... Figure 6 The described receiving component is executed.

[0133] In operation 910, the memory device may sample the first signaling based on a first reference point in both the time and voltage domains to obtain data. Operation 910 may be performed according to the methods described herein. In some instances, aspects of operation 910 may be derived from a reference... Figure 6 The sampling component described is executed.

[0134] In operation 915, the memory device can adjust a time or voltage reference used by a sampler included in the memory device. Operation 915 can be performed according to the methods described herein. In some instances, aspects of operation 915 can be adjusted by a reference... Figure 6 The sampling component described is executed.

[0135] At 920, the memory device can receive a second signaling associated with a sequence of logical values ​​via a channel. Operation 920 can be performed according to the method described herein. In some instances, aspects of operation 920 may be derived from references. Figure 6 The described receiving component is executed.

[0136] In operation 925, the memory device may sample the second signaling based on a second reference point in both the time and voltage domains to obtain a sequence of candidate logic values, wherein the second reference point corresponds to an adjusted time or voltage reference. Operation 925 may be performed according to the methods described herein. In some instances, aspects of operation 925 may be derived from a reference... Figure 6 The sampling component described is executed.

[0137] In operation 930, the memory device may transmit third signaling based on a comparison of a sequence of candidate logical values ​​with a sequence of logical values. Operation 930 may be performed according to the method described herein. In some instances, aspects of operation 930 may be derived from references. Figure 6 The sequence comparison component described is executed.

[0138] Figure 10 The flowchart illustrates one or more methods 1000 for support link evaluation based on the examples disclosed herein. Operation of method 1000 may be implemented by a memory device or its components described herein. For example, operation of method 1000 may be performed by a reference... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0139] At 1005, the memory device may receive, via a channel, a first signaling associated with data stored in the memory device. Operation 1005 may be performed according to the methods described herein. In some instances, aspects of operation 1005 may be derived from references... Figure 6 The described receiving component is executed.

[0140] In operation 1010, the memory device can sample the first signaling based on a first reference point in both the time and voltage domains to obtain data, wherein a first sampler contained in the memory device is operable to use the first reference point. Operation 1010 can be performed according to the methods described herein. In some instances, aspects of operation 1010 may be derived from a reference... Figure 6 The sampling component described is executed.

[0141] At 1015, the memory device may activate a second sampler contained within the memory device. Operation 1015 may be performed according to the method described herein. In some instances, aspects of operation 1015 may be derived from references. Figure 6 The sampling component described is executed.

[0142] In operation 1020, the memory device may receive a second signaling associated with a sequence of logical values ​​via a channel. Operation 1020 may be performed according to the method described herein. In some instances, aspects of operation 1020 may be derived from references. Figure 6 The described receiving component is executed.

[0143] In operation 1025, the memory device may sample the second signaling based on a second reference point in both the time and voltage domains to obtain a sequence of candidate logic values, wherein the second sampler is operable to use the second reference point. Operation 1025 may be performed according to the methods described herein. In some instances, aspects of operation 1025 may be derived from a reference point. Figure 6 The sampling component described is executed.

[0144] In operation 1030, the memory device may transmit third signaling based on a comparison of candidate logical value sequences with logical value sequences. Operation 1030 may be performed according to the methods described herein. In some instances, aspects of operation 1030 may be derived from references. Figure 6 The sequence comparison component described is executed.

[0145] Figure 11 The flowchart illustrates one or more methods 1100 for supporting link evaluation based on the examples disclosed herein. Operation of method 1100 may be implemented by a host device or its components described herein. For example, operation of method 1100 may be performed by a reference... Figure 7 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0146] At 1105, the host device can transmit signaling associated with a sequence of logical values ​​to the memory device via the channel, wherein the signaling supports the determination of conditions of the channel. Operation 1105 can be performed according to the methods described herein. In some instances, aspects of operation 1105 may be derived from references... Figure 7 The described channel condition component is executed.

[0147] In 1110, the host device can receive feedback from the memory device based on signaling associated with a sequence of logical values. Operation 1110 can be performed according to the methods described herein. In some instances, aspects of operation 1110 may be derived from references. Figure 7 The described feedback component is executed.

[0148] In operation 1115, the host device may transmit instructions to the memory device based on feedback. Operation 1115 may be performed according to the methods described herein. In some instances, aspects of operation 1115 may be derived from references. Figure 7 The described instruction component is executed.

[0149] In some instances, the device described herein may perform one or more methods, such as method 1100. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: transmitting signaling associated with a sequence of logical values ​​to a memory device via a channel, wherein the signaling supports the determination of conditions of the channel; receiving feedback from the memory device based on the signaling associated with the sequence of logical values; and transmitting instructions to the memory device based on the feedback.

[0150] Some examples of the method 1100 and apparatus described herein may further include operations, features, components, or instructions for transmitting instructions to a memory device that can be associated with a sequence of logical values.

[0151] In some instances of the method 1100 and apparatus described herein, the conditions include error limits for the channel in at least one of the time or voltage domains.

[0152] In some instances of the method 1100 and device described herein, the feedback may include an indication of whether the error limit can be lower than a threshold.

[0153] In some instances of the method 1100 and apparatus described herein, the feedback may include operations, features, components, or instructions for comparing error limits with thresholds.

[0154] In some instances of the method 1100 and apparatus described herein, feedback may include operations, features, components, or instructions for: comparing candidate sequences with sequences; and determining conditions based on the comparison.

[0155] It should be noted that the above methods describe possible implementation schemes, and the operations and steps can be rearranged or otherwise modified, and other implementation schemes are feasible. Furthermore, portions from two or more of the methods can be combined.

[0156] Describe an apparatus. The apparatus may include: a memory cell array operable to store data; a channel operable to exchange data between the memory cell array and a host device of the apparatus; one or more samplers coupled to the channel and operable to determine logic values ​​based on signals received via the channel, wherein at least one of the one or more samplers is operable to use a default reference point in a time domain and a voltage domain; and a controller coupled to the memory cell array, the channel, and the one or more samplers, the controller operable to cause the apparatus to: receive signaling comprising a sequence of logic values ​​via the channel; determine a candidate sequence of logic values ​​using the one or more samplers based on the signaling and a second reference point in the time domain and the voltage domain; and transmit feedback to the host device based on a comparison of the candidate sequence with the sequence.

[0157] In some instances of the device, the one or more samplers may include: a first sampler operable to determine a logic value using the default reference point; and a second sampler operable to determine a logic value using the second reference point. In some instances of the device, the second reference point may be at a time different from the default reference point in the time domain; and the second reference point may be at a voltage different from the default reference point in the voltage domain.

[0158] The information and signals described herein can be represented using any of a variety of different process technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have various bit widths.

[0159] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if any conductive path exists between them that supports the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, one or more intermediate components (e.g., switches or transistors) may be used to interrupt the flow of signals between connected components for a period of time.

[0160] The term "coupling" refers to a condition that moves from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0161] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, when a switch positioned between components is turned on, the two components separated by the switch are isolated from each other. When a controller isolates two components, the controller creates a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0162] As used herein, the terms "layer" or "level" refer to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0163] As used in this article, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not need to be absolute, but is close enough to achieve the advantage of the characteristic.

[0164] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. Electrodes can comprise traces, wires, conductive lines, conductive layers, or the like that provide a conductive path between elements or components of the memory array.

[0165] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0166] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0167] The descriptions presented herein, together with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed descriptions include specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0168] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0169] The information and signals described herein can be represented using any of a variety of different process technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0170] The various specification boxes and modules described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core or any other such configuration).

[0171] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on a computer-readable medium or transmitted as one or more instructions or code via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the above-described functions can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distributed features such that portions of the functions are implemented at different physical locations. Moreover, as used herein (included in the claims), the word "or" used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on..." should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same way as the phrase "at least partially based on...".

[0172] Computer-readable media includes non-transitory computer storage media and communication media, which includes any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then the media definition includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0173] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of operating a memory device, comprising: receiving, at the memory device via a lane, first signaling associated with data stored at the memory device; sampling the first signaling based at least in part on a first reference point within a time domain and a voltage domain to obtain the data, wherein the first reference point is at a first sampling time within a sampling period; receiving, at the memory device via the lane, second signaling associated with a sequence of logic values; sampling the second signaling based at least in part on a second reference point within the time domain and the voltage domain to obtain a candidate sequence of logic values, wherein the second reference point is at a second sampling time within the sampling period; and transmitting, by the memory device, third signaling based at least in part on a comparison of the candidate sequence of logic values to the sequence of logic values.

2. The method of claim 1, further comprising: determining a match between the candidate sequence of logic values and the sequence of logic values; and determining, based at least in part on the match, that an error margin of the lane is greater than or equal to a difference between the second reference point and the first reference point.

3. The method of claim 1, further comprising: determining a mismatch between the candidate sequence of logic values and the sequence of logic values; and determining, based at least in part on the mismatch, that an error margin of the lane is less than a difference between the second reference point and the first reference point.

4. The method of claim 1, further comprising: identifying the second signaling as being associated with the sequence of logic values based at least in part on a command received by the memory device.

5. The method of claim 4, wherein identifying the second signaling as being associated with the sequence of logic values is based at least in part on a timing relationship between the received command and the received second signaling.

6. The method of claim 4, wherein the command comprises an auto-refresh command.

7. The method of claim 1, wherein the second reference point is earlier or later in the time domain than the first reference point.

8. The method of claim 1, wherein the second reference point is at a higher or lower voltage in the voltage domain than the first reference point.

9. The method of claim 1, further comprising: receiving, from a host device, an indication of the sequence of logic values prior to receiving the second signaling.

10. The method of claim 1, further comprising: sampling the second signaling based at least in part on the first reference point to obtain the sequence of logic values.

11. The method of claim 1, further comprising: adjusting a time or voltage reference used by a sampler included in the memory device, wherein the adjusting is after sampling the first signaling and before sampling the second signaling, and wherein the second reference point corresponds to the adjusted time or voltage reference.

12. The method of claim 1, further comprising: activating a second sampler included in the memory device after sampling the first signaling, wherein a first sampler included in the memory device is operable to use the first reference point and the second sampler is operable to use the second reference point.

13. The method of claim 1, wherein the third signaling comprises an indication of an error margin of the lane, the method further comprising: receiving, at the memory device, a command to calibrate a sampler of the lane.

14. The method of claim 1, further comprising: determining, based at least in part on the comparison, that an error margin of the lane is insufficient; and calibrating a sampler based at least in part on determining that the error margin is insufficient, wherein the third signaling comprises an indication of the calibration.

15. A method of operating a memory device, comprising: receiving, at the memory device via a lane, first signaling associated with data stored at the memory device; sampling the first signaling based at least in part on a first reference point within a time domain and a voltage domain to obtain the data; receiving, at the memory device via the lane, second signaling associated with a sequence of logic values; sampling the second signaling based at least in part on a second reference point within the time domain and the voltage domain to obtain a candidate sequence of logic values, and sampling the second signaling based at least in part on a third reference point within the time domain and the voltage domain to obtain a second candidate sequence of logic values; and transmitting, by the memory device, third signaling based at least in part on a comparison of the candidate sequence of logic values to the sequence of logic values and a comparison of the second candidate sequence of logic values to the sequence of logic values.

16. The method of claim 15, wherein sampling the second signaling based at least in part on the third reference point occurs after sampling the second signaling based at least in part on the second reference point.

17. The method of claim 15, wherein sampling the second signaling based at least in part on the third reference point occurs concurrently with sampling the second signaling based at least in part on the second reference point.

18. A method of operating a memory device, comprising: transmitting, to the memory device via a lane, signaling associated with a sequence of logic values, wherein the signaling supports a determination of a condition of the lane; receiving feedback from the memory device based at least in part on the signaling associated with the sequence of logic values, wherein the feedback is based on sampling the signaling, the sampling based at least in part on a first reference point within a time domain and a voltage domain, and wherein the first reference point is at a first sampling time within a sampling period; and transmitting, to the memory device, an instruction based at least in part on the feedback.

19. The method of claim 18, further comprising: transmitting, to the memory device, a command indicating that the signaling is associated with the sequence of logic values.

20. The method of claim 18, wherein the condition of the lane comprises an error margin of the lane in at least one of the time domain or the voltage domain.

21. The method of claim 20, wherein the feedback comprises an indication of whether the error margin is below a threshold.

22. The method of claim 20, wherein the feedback comprises an indication of a size of the error margin, the method further comprising: comparing the error margin to a threshold.

23. The method of claim 18, wherein the feedback comprises an indication of a candidate sequence of logic values determined by the memory device, the method further comprising: comparing the candidate sequence of logic values to the sequence of logic values; and determining the condition of the channel based at least in part on the comparison.

24. A memory device, comprising: an array of memory cells operable to store data; a channel operable to exchange data between the array of memory cells and a host device of the memory device; one or more samplers coupled with the channel and operable to determine logic values based at least in part on signals received via the channel, wherein at least one of the one or more samplers is operable to use a default reference point in a time domain and a voltage domain, and wherein the default reference point is at a first sampling time within a sampling period; and a controller coupled with the array of memory cells, the channel, and the one or more samplers, the controller operable to cause the memory device to: receive signaling comprising a sequence of logic values via the channel; determine a candidate sequence of logic values based at least in part on the signaling and a second reference point in the time domain and the voltage domain using the one or more samplers, wherein the second reference point is at a second sampling time within the sampling period; and transmit feedback to the host device based at least in part on a comparison of the candidate sequence of logic values to the sequence of logic values.

25. The memory device of claim 24, wherein the one or more samplers comprise: a first sampler operable to determine logic values using the default reference point; and a second sampler operable to determine logic values using the second reference point.

26. The memory device of claim 24, wherein: the second reference point is at a different time than the default reference point within the time domain; and the second reference point is at a different voltage than the default reference point in the voltage domain. ​

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