Enable memory access transactions to persistent storage

Abstract

The present application relates to enabling a memory access transaction for a persistent memory. A first request to initiate a memory access transaction is received by a processing device of a memory subsystem from a host system. One or more host data items are received from the host system. The one or more host data items are stored in a memory buffer on a volatile memory device resident in the memory subsystem. In response to initiating one or more operations to commit the memory access transaction, the one or more host data items are transferred from the memory buffer to a persistent memory device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly to enabling memory access transactions to persistent memory. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] In one aspect, the present application provides a method, comprising: receiving, by a processing device of a memory subsystem, a first request from a host system to initiate a memory access transaction; receiving one or more host data items from the host system; storing the one or more host data items in a memory buffer on a volatile memory device residing in the memory subsystem; and transferring the one or more host data items from the memory buffer to a persistent memory device in response to initiating one or more operations to commit the memory access transaction.

[0004] On the other hand, the present application provides a memory subsystem comprising: a first memory device comprising a memory buffer; a second memory device, wherein one or more portions of the second memory device comprise a persistent memory; and a processing device coupled to the first memory device and the second memory device, the processing device being configured to perform operations comprising: obtaining a memory access transaction identifier of a memory access transaction initiated by a host system; storing one or more host data items in a memory buffer residing on the first memory device of the memory subsystem, wherein the one or more host data items are associated with the memory access transaction identifier; and receiving a request from the host system to commit the one or more host data items associated with the memory access transaction identifier to the persistent memory, thereby transferring at least a portion of the one or more host data items from the memory buffer to the persistent memory.

[0005] In another aspect, the present application provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a first request from a host system to initiate a memory access transaction; receiving one or more host data items from the host system; storing the one or more host data items in a memory buffer residing on a volatile memory device; and transferring the one or more host data items from the memory buffer to a persistent memory device in response to initiating one or more operations to commit the memory access transaction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2A is a flow chart of an example method for storing host data at a persistent memory region of a memory subsystem using a persistent memory buffer according to some embodiments of the present disclosure.

[0009] Figure 2B is a flow chart of another example method for storing host data at a persistent memory region of a memory subsystem using a persistent memory buffer according to some embodiments of the present disclosure.

[0010] Figures 3A-3C An example of storing host data at a persistent memory area using a persistent memory buffer according to some embodiments of the present disclosure is shown.

[0011] Figure 4 is a flow chart of an example method for storing host data at a persistent memory area of ​​a memory subsystem by a host system according to some embodiments of the present disclosure.

[0012] Figure 5 is a flow chart of an example method for storing host data at a persistent memory area of ​​a memory subsystem by a host system according to some embodiments of the present disclosure.

[0013] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Various aspects of the present disclosure relate to enabling memory access transactions to persistent memory. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more memory components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0015] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. In some embodiments, the non-volatile memory devices may be provided by NAND type flash memory devices. Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. Planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. A "block" will refer to a collection of consecutive or non-consecutive memory pages in this document. An example of a "block" is an "erasable block," which is the smallest erasable unit of memory, and a "page," which is the smallest writable unit of memory. Each page contains a collection of memory cells. A memory cell is an electronic circuit that stores information.

[0016] Data operations may be performed by the memory subsystem. Data operations may be operations initiated by the host. For example, the host system may initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem. The controller at the memory subsystem may receive access requests from the host system and may perform operations according to the requests to access and / or write host data at the memory device. Data to be read or written as specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity check code), data version (e.g., for distinguishing the expiration of the written data), valid bitmap (whose LBA or logical transfer unit includes valid data), etc.

[0017] The memory subsystem may be enabled to facilitate storage of host data to a persistent memory of the memory subsystem. Persistent memory refers to a memory device or a portion of a memory device (e.g., a persistent memory area herein) that stores data so that the data can be accessed even after the process that created or last modified the data item has ended. The persistent memory device and / or area may refer to a non-volatile memory device or a power-protected volatile memory device (e.g., a power-protected dynamic random access memory (DRAM)). The host system may be coupled to the memory subsystem via, for example, a peripheral component interconnect express (PCIe) bus, and may store host data at the persistent memory by transmitting instructions to a memory subsystem controller via the PCIe bus to write the host data at an address of the persistent memory.

[0018] Although the memory subsystem can provide the host system with access to the persistent memory device and / or zone, the host system and the memory subsystem may occupy a large amount of resources in order to manage the storage of host data to the persistent memory. For example, for some memory subsystems, the cacheability and / or consistency of the host data stored at the persistent memory involve a lot of complexity for the host system using the persistent memory. Therefore, the developer of the process running at the host system can develop a custom process to enable the host system to manage the storage of host data to the persistent memory. Such a process may involve a large number of write operations and / or cache refresh operations to record each modification of the host data at the host system in the event of a power failure or system crash in the host system and / or the memory subsystem. This large amount of write and / or refresh operations may occupy a large amount of valuable space at one or more memory devices of a large number of system resources and the memory subsystem, thereby causing the overall system efficiency to be reduced and the overall system delay to be longer. Therefore, these exemplary shortcomings limit the widespread industry adoption as a solution that can utilize transaction-oriented persistent memory.

[0019] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that enables memory access transactions for persistent memory. The memory subsystem may include a volatile memory device and a persistent memory device and / or a persistent memory area (collectively referred to herein as persistent memory). In some embodiments, the volatile memory device may include a memory buffer configured to store host data before the host data is written to the persistent memory. Persistent memory refers to a non-volatile memory device or a power-protected volatile memory device, or a portion of such a device. In some embodiments, the memory subsystem may be coupled to a host system via a computing high-speed link (CXL) interface. In such embodiments, the memory subsystem may be a CXL system configured to support the CXL protocol. In additional or alternative embodiments, the memory buffer may reside in the persistent memory area and / or at another non-volatile memory device of the memory subsystem.

[0020] The host system may transmit a request to the memory subsystem to initiate a memory access transaction to store host data at a persistent memory of the memory subsystem. A memory access transaction refers to a set of operations to be performed at the memory subsystem to store host data at an address range of the persistent memory. In some embodiments, the request may include an indication of an address range and / or an indication of an amount of host data to be stored at the persistent memory for the memory access transaction. In response to receiving the request from the host system, the memory subsystem controller may obtain a transaction identifier for the memory access transaction. In some embodiments, the memory subsystem controller may use the transaction identifier to track the status of the corresponding transaction, as described below. In some embodiments, the memory subsystem controller may transmit an indication of the transaction identifier to the host system.

[0021] Upon request, the host system may transfer one or more host data items (i.e., one or more portions of host data) to the memory subsystem for storage at a specific address in an address range of the persistent memory. In response to receiving the one or more host data items, the memory subsystem controller may store the host data items in a memory buffer at a volatile memory device of the memory subsystem. In some embodiments, the memory subsystem controller may store an indication of a specific address in the address range associated with the host data item and / or an indication of a transaction identifier of a memory access transaction.

[0022] In response to determining that each host data item of the memory access transaction has been transmitted to the memory subsystem controller, the host system may transmit another request to the memory subsystem to commit the memory access transaction. For the purposes of this disclosure, committing a memory access transaction refers to the process of completing the storage of a set of host data items at an address range of a persistent memory. In response to receiving the request to commit the memory access transaction, the memory subsystem controller may transfer the host data items associated with the memory access transaction from the memory buffer to the persistent memory, and in some embodiments, may transmit a notification to the host system that the memory access transaction was successfully committed. The memory subsystem controller may be configured to complete the transfer of the host data items to the persistent memory even in the event of a power loss or system crash at the memory subsystem and / or the host system.

[0023] In additional or alternative embodiments, the memory subsystem controller may store an initial state associated with each host data item at the memory buffer. The initial state of the data item may include a copy of the data item before the host system updates the data item before transmitting a request to commit a memory access transition. The memory subsystem controller may (e.g., in response to a request or notification from the host system) restore the updated data item to the initial state using the initial state of the data item stored at the memory buffer. The host system may transmit a request to commit a memory access transaction to the memory subsystem controller, as indicated above. In response to receiving the request to commit a memory access transaction, the memory subsystem controller may discard the stored initial state associated with each host data item.

[0024] Advantages of the present disclosure include, but are not limited to, exposing persistent memory at a memory subsystem to processes running at a host system, wherein resource consumption of the host system is minimized. By maintaining a memory buffer at a volatile memory device of the memory subsystem, a memory subsystem controller is able to execute a CXL protocol enabled by a CXL interface connecting the memory subsystem to the host system, which increases the cacheability and / or consistency of host data stored at the persistent memory. Thus, no expensive processes are run at the host system to enable host data to be stored to the persistent memory, thereby reducing consumption of expensive system resources by the host system and / or the memory subsystem. By reducing resource consumption of the host system and / or the memory subsystem, overall system efficiency can be improved and overall system latency can be reduced.

[0025] Figure 1An example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure is shown. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 130), one or more non-volatile memory devices (e.g., memory device 140), or a combination of such devices. In some embodiments, the memory subsystem 110 may further include a persistent memory (PM) device 150. Persistent memory according to embodiments provided herein refers to a memory device or a portion of a memory device (i.e., a persistent memory area) that stores data items so that the data can be accessed even after the process that created or last modified the data items has ended. In some embodiments, the persistent memory device 150 may be a non-volatile memory device. In other or similar embodiments, the persistent memory device 150 may be a power-protected volatile memory device (e.g., a power-protected dynamic random access memory (DRAM) device). In some embodiments, memory subsystem 110 may not include persistent memory device 150, and instead, memory device 130 and / or memory device 140 may include one or more persistent memory areas. According to the embodiments described herein, a persistent memory area refers to a portion of a memory device that supports persistent memory storage. For example, in some embodiments, memory device 140 may be a volatile memory device rather than a non-volatile memory device, and at least a portion of memory device 140 may be a power-protected volatile memory.

[0026] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0027] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0028] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0029] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0030] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is shown as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0031] In some embodiments, the host system 120 may be coupled to the memory subsystem 110 via a compute express link (CXL) interface. In such embodiments, the memory subsystem 110 may be a CXL system configured to support the CXL protocol. The CXL interface refers to an interface that can support several protocols that can run on top of PCIe, including the CXL.io protocol, the CXL.mem protocol, and the CXL.cache protocol. The CXL.io protocol is a PCIe-like protocol and can be considered an "enhanced" PCIe protocol that can partition managed memory. The CXL interface can be used for initiation, connection, device discovery and enumeration, register access, and can provide an interface for I / O devices. The CXL.mem protocol can implement host access to the memory of an attached device using memory semantics (e.g., load and store commands). According to the embodiments described herein, this approach can support both volatile memory architectures and persistent memory architectures. The CXL.cache protocol can define host device interactions to implement efficient caching of host memory with low latency using a request and response approach. Traffic can run over the CXL.io protocol, and the CXL.mem and CXL.cache protocols can share a common link layer and transaction layer. Thus, the CXL protocol can be multiplexed and transmitted over the PCIe physical layer.

[0032] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-layer cells (MLC), triple-layer cells (TLC), quad-layer cells (QLC), and penta-layer cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-OR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic on the die (e.g., the local controller 132) and a controller for media management within the same memory device package (e.g., the memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0042] The memory subsystem 110 includes a PM manager component 113, which can be used to store host data at a persistent memory (e.g., a persistent memory device 150) of the memory subsystem 110. As described above, the host data refers to data of the host system 120 received by the memory subsystem controller 115 to be stored at a memory device of the memory subsystem 110. In some embodiments, the host data may include data associated with a process running on the host system 120. In some embodiments, the memory subsystem controller 115 includes at least a portion of the PM manager component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in a local memory 119 for performing the operations described herein. In some embodiments, the PM manager component 113 is part of the host system 110, an application, or an operating system.

[0043] In some embodiments, the PM manager component 113 may be configured to receive a request from the host system 120 to initiate a memory access transaction. A memory access transaction refers to a set of operations to be performed (e.g., by the PM manager component 113) at the memory subsystem 115 to store host data at a specific address range of the persistent memory device 150. In some embodiments, the PM manager component 113 may receive a host data item in a set of host data items and may store the received host data item in a memory buffer 137 residing on a memory device. In some embodiments, the memory buffer 137 may reside on a volatile memory device at the memory subsystem 110, such as the memory device 130. In other or similar embodiments, the memory buffer 137 may reside on a non-volatile memory device, such as the memory device 140. In yet other or similar embodiments, the buffer 137 may reside on a local memory of the memory subsystem controller 115, such as the local memory 119. The PM manager component 113 may receive a second request from the host system 120 to submit the memory access transaction to the persistent memory device. For purposes of this disclosure, committing a memory access transaction refers to completing a process to store a set of host data items at the persistent memory device 150. In response to receiving a second request from the host system 120, the PM manager component 113 may transfer the set of host data items from the memory buffer 137 to the persistent memory device 150. Additional details regarding storing host data at the persistent memory device 150 are provided herein.

[0044] Figure 2A 2 is a flowchart of an example method 200 for storing host data at a persistent memory area of ​​a memory subsystem using a persistent memory buffer according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The method 200 is performed by the PM manager component 113 of the memory subsystem controller. In other or similar embodiments, one or more operations of the method 200 are performed by another component of the memory subsystem controller. Although shown in a specific order or sequence, the order of the process may be modified unless otherwise specified. Therefore, it should be understood that the described embodiments are only examples, and the described processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0045] At operation 210, processing logic may receive a first request from a host system to initiate a memory access transaction. As described above, a memory access transaction refers to a process to store one or more host data items at a persistent memory of a memory subsystem (e.g., a persistent memory device 150 or a persistent memory area of ​​a memory device 130 or a memory device 140). It should be noted that although embodiments of the present disclosure describe storing host data items at a persistent memory device 150, these embodiments are also applicable to storing host data items at a persistent memory area at a memory subsystem 110.

[0046] Figure 3A 1 shows an example of storing host data in a persistent memory area of ​​the memory subsystem 110 according to an embodiment of the present disclosure. Figure 3A As shown, memory subsystem 110 may include persistent memory 310. Persistent memory 310 may correspond to persistent memory device 150 and / or persistent memory area, as previously described. The memory subsystem may also include buffer 137, as described above.

[0047] In some embodiments, the request from host system 120 may include an indication of a virtual address range of persistent memory device 150 at which one or more host data items for the memory access transaction are to be stored. The request may further include an indication of an amount of host data to be stored at the virtual address range of persistent memory device 150 for the memory access transaction. For example, the request may include an indication of a number of words to be stored at the virtual address range of persistent memory device 150. In other or similar embodiments, the request may include an indication of an amount of host data to be stored at persistent memory device 150 for the memory access transaction and an initial virtual address of the host data at persistent memory device 150. Processing logic may determine the virtual address range of the memory access transaction based on the initial virtual address and the indication of the amount of host data for the memory access transaction.

[0048] In response to receiving the request, processing logic may determine whether there is sufficient available space at a buffer residing on a volatile memory device of memory subsystem 110 to store host data for the memory access transaction before the host data is transferred to persistent memory device 150. In some embodiments, the buffer residing on the volatile memory device may correspond to buffer 137. In response to determining that there is insufficient available space at buffer 137, processing logic may transmit a message to host system 120 indicating that the memory access transaction cannot be completed at memory subsystem 110.

[0049] In some embodiments, processing logic may obtain a physical address range of persistent memory device 150 that is mapped to the virtual address range included in the first request. For example, processing logic may access a data structure at a local memory (e.g., local memory 119) of memory subsystem controller 115 that includes a virtual address to physical address mapping for persistent memory device 150. In some embodiments, the data structure may be a virtual (or logical) to physical address table (e.g., a V2P table or an L2P table). In some embodiments, processing logic may retrieve a mapping of each virtual address in the virtual address range to a corresponding physical address at persistent memory device 150 and store the retrieved mapping at a buffer of local memory 119.

[0050] In some embodiments, in response to receiving a first request to initiate a memory access transaction, the processing logic may store a transaction identifier associated with the memory access transaction, for example, at the local memory 119. The transaction identifier may be a unique identifier for a particular memory access transaction corresponding to the first request. In some embodiments, the processing logic may store multiple transaction identifiers for multiple memory access transactions initiated by the host system 120 or another host system coupled to the memory subsystem 110. In some embodiments, the first request from the host system 120 may include an indication of the transaction identifier associated with the memory access transaction. Therefore, the processing logic may extract the transaction identifier from the first request and store the extracted transaction identifier, for example, at the local memory 119. In other or similar embodiments, the processing logic may generate a transaction identifier in response to receiving the first request from the host system 120 and store the generated transaction identifier, for example, at the local memory 119. In response to generating the transaction identifier, the processing logic may transmit an indication of the transaction identifier to the host system 120.

[0051] In yet other or similar embodiments, a memory space (eg, local memory 119) of the memory subsystem controller 115 may store a transaction identifier data structure, such as Figure 3AThe data structure 312 shown. The transaction identifier data structure 312 may include an entry for each of a limited set of transaction identifiers that can be used for memory access transactions at the memory subsystem 110. Each entry of the data structure may include: a field 314, which includes an indication of the corresponding transaction identifier; and an additional field 316, which includes an indication of whether the transaction identifier is available for the requested memory access transaction. For example, the additional field 316 may include a flag indicating whether the corresponding transaction identifier is available. In another example, the additional field 316 for the unavailable transaction identifier may include an address (e.g., virtual address or physical address) range of the persistent memory device 150 that is currently mapped to the unavailable transaction identifier. The additional field 316 for the available transaction identifier may be empty, indicating that the transaction identifier is available. The processing logic may access the data structure to retrieve the available transaction identifier for the first requested memory access transaction, and may update the entry for the transaction identifier in response to identifying the available transaction identifier to indicate that the transaction identifier is not available. For example, the processing logic may update the flag of the entry to indicate that the transaction identifier is not available. In another example, processing logic may add an indication of a memory address (eg, virtual address or physical address) range to the entry to indicate that the transaction identifier is not available. Figure 3A As shown, processing logic may update the entry associated with transaction identifier "0" to indicate a range of memory addresses (e.g., "0X000-0X005") associated with the transaction identifier. The entry associated with transaction identifier "1" does not include an indication of a memory address range, and thus indicates that the transaction identifier is available. In some embodiments, processing logic may store the retrieved transaction identifier, for example, at local memory 119. In response to retrieving the transaction identifier, processing logic may transmit an indication of the transaction identifier to host system 120.

[0052] The first request to initiate a memory access transaction may include a transaction identifier, as described above. In some embodiments, the transaction identifier included in the first request may be a transaction identifier (referred to as a host transaction identifier) ​​generated by the host system 120 before transmitting the first request to the memory subsystem 110. In such embodiments, according to the embodiments described above, the processing logic may obtain an additional transaction identifier (referred to as a memory subsystem transaction identifier) ​​of the memory access transaction in response to receiving the first request from the host system 12. For example, the processing logic may generate a memory subsystem transaction identifier or may retrieve a memory subsystem transaction identifier from a memory subsystem transaction identifier, as described herein. The processing logic may transmit an indication of the obtained memory subsystem transaction identifier to the host system 120, as described above. In some embodiments, the processing logic may also generate a mapping between a host transaction identifier and a memory subsystem transaction identifier and store the mapping at a memory (e.g., local memory 119) of the memory subsystem controller 15. It should be noted that in some embodiments, reference to a transaction identifier as provided herein may refer to a host transaction identifier or a memory subsystem transaction identifier.

[0053] At operation 212, processing logic may receive one or more host data items from the host system. In some embodiments, processing logic may receive an instruction to write the one or more host data items to a specific virtual address of persistent memory device 150 within the previously described virtual address range. Processing logic may determine the physical address of persistent memory device 150 that is mapped to the specific virtual address, for example, using a mapping of the virtual address included in the first request to the corresponding physical address stored at local memory 119, as described above. In other or similar embodiments, processing logic may determine the physical address of persistent memory device 150 using a V2P table or an L2P table stored at local memory 119 in accordance with the embodiments provided herein.

[0054] At operation 214, processing logic may store the one or more host data items in a memory buffer 137 residing on a volatile memory device of the memory subsystem 110. In some embodiments, processing logic may store an indication of a physical address that maps to a virtual address of the one or more host data items in the memory buffer 137 along with the one or more host data items. In other or similar embodiments, processing logic may store an indication of a transaction identifier associated with the first requested memory access transaction in the memory buffer 137 along with the one or more host data items. In still other or similar embodiments, processing logic may update an entry for the transaction identifier at a transaction identifier data structure to include an indication of the address of the one or more host data items stored in the memory buffer 137. Figure 3AAs shown, processing logic may program the host data item to memory buffer 137. In some embodiments, processing logic may update the entry for the transaction identifier to include an indication of the address (eg, physical address) of the stored host data item (eg, 0X000-0X003).

[0055] In some embodiments, one or more host data items received from host system 120 may include an indication of a host transaction identifier for a memory access transaction. In such embodiments, processing logic may determine a memory subsystem transaction identifier for the memory access transaction (e.g., from a mapping stored at local memory 119) and store the indication of the memory subsystem memory access transaction identifier at memory subsystem 110, as described above.

[0056] In some embodiments, processing logic may receive a first instruction to store one or more first host data items at a particular virtual address of persistent memory device 150, as described above. Processing logic may store the one or more first host data items, the obtained physical address of persistent memory device 150, and / or a transaction identifier of a memory access transaction at buffer 137, as described above. In some embodiments, processing logic may receive a second instruction to store one or more second host data items at the same virtual address of persistent memory device 150. In response to receiving the second instruction to store the one or more second host data items, processing logic may replace the one or more first host data items and the obtained physical addresses of the one or more first host data items with the one or more second data items and / or the obtained physical addresses of the one or more second host data items. For example, processing logic may erase a first host data item, the obtained physical address and / or transaction identifier of the host data item from buffer 137 and store a second host data item, the physical address and / or transaction identifier of one or more second host data items at the same portion or a different portion of buffer 137.

[0057] In other or similar embodiments, processing logic may program the one or more second host data items to persistent memory 310, and may save the one or more first host data items at buffer 137. In such embodiments, the first host data item may correspond to an initial state of the host data associated with the virtual address, and the second host data item may correspond to an updated state of the host data associated with the virtual address. In some embodiments, processing logic may receive a request from host system 120 to restore the host data associated with the virtual address to the initial state. In such embodiments, processing logic may obtain the first host data item from buffer 137, and may replace the second host data item with the first host data item at persistent memory 310.

[0058] In some embodiments, after receiving the first request from the host system 120, the processing logic may receive a plurality of instructions from the host system 120 to store the host data items at the persistent memory device 150. In some embodiments, the processing logic does not receive the host data items to be stored at the persistent memory device 150 within a threshold time period after receiving the first request from the host system 120 or after receiving one or more initial instructions from the host system 120 to store the host data items. In such embodiments, the processing logic may transmit a notification to the host system 120 indicating that the memory access transaction of the first request is terminated. In some embodiments, the processing logic may remove the host data items associated with the memory access transaction from the buffer 137. For example, the processing logic may identify each host data item associated with the transaction identifier of the memory access transaction and erase each identified host data item from the buffer 137. In some embodiments, the processing logic may determine whether the respective data item corresponds to the memory access transaction based on the transaction identifier stored at the buffer 137 with the respective data item. In other or similar embodiments, processing logic may access a data structure (e.g., at local memory 119 or memory device 130) that includes a mapping between each address of buffer 137 and an indication of a transaction identifier for host data stored at the respective address. In still other or similar embodiments, processing logic may access a transaction identifier data structure (e.g., at local memory 119) and may determine, based on entries of the data structure, one or more addresses of buffer 137 that include host data items for a memory access transaction.

[0059] In some embodiments, in response to removing the host data item associated with the memory access transaction, the processing logic may also modify an entry of the transaction identifier data structure corresponding to the transaction identifier of the memory access transaction to indicate that the transaction identifier is available for future memory access transactions. For example, the processing device may set a flag of the entry to indicate that the transaction identifier is available or an indication of an address range of host data for the memory access transaction may be removed from the entry.

[0060] In some embodiments, processing logic may receive from host system 120 an instruction to store host data items that exceed the amount of host data indicated for the memory access transaction in a first request from host system 120. For example, the first request may indicate that the amount of host data for the memory access transaction corresponds to approximately 100 total words of the memory. In some embodiments, after processing logic receives the first request, processing logic may receive one or more instructions to store an amount of host data that exceeds the 100 total words of the memory indicated in the first request. In other or similar embodiments, processing logic may receive an instruction to store host data items that exceed words of the memory (e.g., word lines of the memory, pages of the memory, blocks of the memory, etc.). In these embodiments, processing logic may transmit to host system 120 an indication that the memory access transaction of the first request is terminated, and in some embodiments, the processing logic may remove the host data items associated with the memory access transaction from buffer 137, as described above. In some embodiments, processing logic may also update a transaction identifier data structure, as described above.

[0061] In some embodiments, processing logic may receive an instruction from host system 120 to terminate a memory access transaction in response to receiving one or more host data items to be stored at persistent memory device 150. In such embodiments, processing logic may remove the host data items associated with the memory access transaction from buffer 137, as described above. In some embodiments, processing logic may also update a transaction identifier data structure, as described above.

[0062] At operation 216, processing logic may initiate one or more operations to commit the memory access transaction. In some embodiments, processing logic may initiate one or more operations in response to a request from host system 120 to commit the memory access transaction. As described above, for purposes of this specification, committing a memory access transaction refers to completing a memory access transaction to store a host data item at persistent memory device 150. In some embodiments, the second request may include an indication of a transaction identifier for the memory access transaction. As described above, in some embodiments, buffer 137 may store host data items associated with multiple transaction identifiers. Therefore, according to the previously described embodiments, processing logic may identify, at buffer 137, a host data item associated with the transaction identifier of the second request. As described above, processing logic may initiate one or more operations in response to a request from host system 120 to commit the memory access transaction. As described above, processing logic may initiate one or more operations in response to a request from host system 120 to commit the memory access transaction. As described above, processing logic may initiate one or more operations in response to a request from host system 120 to commit the memory access transaction. As described above, processing logic may initiate one or more operations in response to a request from host system 120 to commit the memory access transaction. Figure 3B As shown, buffer 137 may store one or more first data items associated with transaction identifier “0” and one or more additional data items associated with transaction identifier “1.” In some embodiments, processing logic may identify, at buffer 137 , a first data item associated with transaction identifier “0.”

[0063] In some embodiments, the second request may include a host transaction identifier and an indication of a memory subsystem transaction identifier of the memory access transaction. The processing logic may determine whether the memory subsystem transaction identifier included in the second request corresponds to a memory subsystem transaction identifier associated with a memory access transaction that the processing logic previously obtained and transmitted to the host system 120. For example, the processing logic may compare the memory subsystem transaction identifier of the second request with a mapped memory subsystem transaction identifier generated for the host transaction identifier of the second request. In response to determining that the memory subsystem transaction identifier of the second request corresponds to the previously obtained memory subsystem transaction identifier, the method 200 may proceed to operation 218, as described herein. In response to determining that the memory subsystem transaction identifier of the second request does not correspond to the previously obtained memory subsystem transaction identifier, the processing logic may transmit a notification to the host system 120 indicating that the host transaction identifier of the second request does not correspond to the memory subsystem transaction identifier included in the second request.

[0064] At operation 218, processing logic may transfer one or more host data items from the memory buffer to persistent memory device 150. In some embodiments, processing logic may transfer the host data items associated with the transaction identifier of the second request at buffer 137, as described herein. Processing logic may transfer the one or more host data items by copying the one or more host data items to a queue associated with persistent memory device 150. The local controller for persistent memory device 150 may store each host data item of the queue to persistent memory device 150 in the order in which the host data items were copied to the queue. In some embodiments, the queue of persistent memory device 150 may be a portion of memory supported by a local backup power of memory subsystem 110. For example, the local backup power of memory subsystem 110 may be a power storage device (e.g., a battery) that is configured to store sufficient power so that the local controller for persistent memory device 150 can successfully store all data items copied to the queue at persistent memory device 150 after a power failure of memory subsystem 110. Processing logic may also erase one or more host data items associated with the memory access transaction from buffer 137 .

[0065] In some embodiments, in response to copying one or more host data items to a queue associated with persistent memory device 150, processing logic may transmit a notification indicating completion of the memory access transaction to host system 120. In some embodiments, processing logic may also update transaction identifier data structure 312 to indicate that a transaction identifier associated with the memory access transaction is available, as previously described. Figure 3CAs shown, processing logic may transfer (e.g., copy) the first data item from buffer 137 to persistent storage 310, as described above. In some embodiments, processing logic may remove (e.g., erase) the first data item from buffer 137 in response to determining that the first data item is transferred to persistent storage 310. Processing logic may additionally or alternatively update transaction identifier data structure 312 to indicate that transaction identifier “0” associated with the first data item is available.

[0066] As described above, in additional or alternative embodiments, the host system 120 may transmit a first host data item associated with the virtual address, and may subsequently transmit a second host data item associated with the virtual address. The first host data item may represent an initial state of the host data associated with the virtual address, and the second host data item may represent an updated state of the host data, as described above. When the first host data item is received, the processing logic may store the first host data item to the buffer 137 and the persistent memory 310. When the second host data item is received, the processing logic may replace the first host data item at the persistent memory 310 with the second host data item. Thus, the persistent memory 310 may store the updated state of the host data. The processing logic may save the first host data item (e.g., the initial state of the host data) at the buffer 137. In some embodiments, the processing logic may receive a request to restore the host data to the initial state. Thus, the processing logic may replace the second host data item at the persistent memory 310 with the first host data item at the buffer 137 (e.g., by copying the first host data item from the buffer 137 to the area of ​​the persistent memory 310 associated with the virtual address). When a request to commit host data associated with the virtual address is received, processing logic may remove (eg, erase) the first host data item from buffer 137 .

[0067] Figure 2B 2 is a flowchart of an example method 250 for storing host data at a persistent memory area of ​​a memory subsystem using a persistent memory buffer according to some embodiments of the present disclosure. The method 250 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 250 is performed by Figure 1The method 250 is performed by the PM manager component 113 of the memory subsystem controller. In other or similar embodiments, one or more operations of the method 250 are performed by another component of the memory subsystem controller. Although shown in a specific order or sequence, the order of the process may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0068] At operation 252, processing logic may receive a request to initiate a memory access transaction from a host system (e.g., host system 120) according to previously described embodiments. At operation 254, processing logic may optionally initiate a timer associated with the memory access transaction. In some embodiments, the timer may be a countdown timer that counts down to a specific time period after the timer is initiated. In response to a value of the countdown timer corresponding to the specific time period, the countdown timer may transmit a notification to the processing logic indicating that the time period associated with the countdown timer has expired. At operation 256, processing logic may determine whether to initiate a write operation. In some embodiments, a write operation may be initiated in response to receiving a command to write one or more host data items of a memory access transaction to a persistent memory (e.g., persistent memory device 150). Processing logic may determine whether a command to write host data items of a memory access transaction has been received by determining whether any write command received from host system 120 includes an indication of a transaction identifier associated with the memory access transaction. In response to processing logic determining that a write command has been received, method 250 may proceed to operation 258. At operation 258, processing logic may store the one or more host data items of the write command in a memory buffer residing on a volatile memory device of the memory subsystem, such as memory buffer 137, in accordance with previously described embodiments. In some embodiments, processing logic may start a timer of operation 254 after processing logic stores the one or more host data items at memory buffer 137.

[0069] In response to the processing logic determining that the write operation was not initiated, the method 250 may proceed to operation 260. At operation 260, the processing logic may determine whether to initiate a transaction abort operation. In some embodiments, the transaction abort operation may be initiated in response to a transaction abort command received from the host system 120. The transaction abort command may cause the processing logic to terminate the memory access transaction and remove each data item associated with the memory access transaction from the buffer 127 and / or the persistent memory device 150. In response to the processing logic determining that the transaction abort command has been received from the host system 120, the method 250 may proceed to operation 262. At operation 262, the processing logic may close the memory access transaction at the memory subsystem 110. In some embodiments, the processing logic may close the memory access transaction by discarding (e.g., erasing) one or more host data items from the memory buffer 137. In some embodiments, according to the embodiments described above, the processing logic may further update the transaction identifier data structure to indicate that the transaction identifier of the memory access transaction is available for use.

[0070] In response to processing logic determining that a transaction abort operation has not been initiated, method 250 may proceed to operation 264. At operation 264, processing logic may determine whether a transaction commit command has been received from host system 120. The transaction commit command may cause processing logic to commit host data items of the memory access transaction to persistent memory device 150, as described above. In response to processing logic determining that a transaction commit command has been received, method 250 may proceed to operation 266. At operation 266, processing logic may transfer one or more host data items associated with the memory access transaction from a memory buffer to a persistent memory device, in accordance with previously described embodiments. In response to transferring one or more host data items of the memory access transaction to persistent memory device 150, processing logic may close the memory access transaction, in accordance with previously described embodiments.

[0071] In response to processing logic determining that a transaction commit operation has not been initiated, method 250 may proceed to operation 268. At operation 268, processing logic may detect whether a memory access transaction timeout has occurred by a previously set timer of operation 254. In some embodiments, processing logic may detect a memory access transaction timeout by determining that a previously set timer has expired. In response to processing logic detecting that a memory access transaction timeout has occurred, method 250 may proceed to operation 270. At operation 270, processing logic may close the memory access transaction in accordance with previously described embodiments. In some embodiments, processing logic may also transmit a notification to host system 120 indicating that the memory access transaction has been closed. In response to processing logic determining that a memory access transaction timeout has not occurred with respect to operation 268, the method may return to operation 256. As previously described, processing logic may optionally initiate a timer associated with the memory access transaction in accordance with operation 254. If processing logic does not utilize a timer to determine whether to close the memory access transaction, as described with respect to operation 268 and / or operation 270 of method 250. Alternatively, processing logic may keep the memory access transaction in progress at the memory subsystem 110 until processing logic receives a transaction abort command or a transaction commit command, as described with respect to operations 260 and 264 of method 250 .

[0072] Figure 4 4 is a flowchart of an example method 400 for storing host data at a persistent memory area of ​​a memory subsystem by a host system according to some embodiments of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by a processing device at Figure 1 The processes are performed at the host system 120 of the embodiment. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0073] At operation 410, processing logic may transmit a first request to a memory subsystem (e.g., memory subsystem 110) to initiate a memory access transaction. In some embodiments, processing logic may correspond to or may execute a thread for a process in a user space of host system 120. A process may be associated with a set of host data items used or generated by processing logic when the process is executed on host system 120. In some embodiments, processing logic may identify one or more host data items in the set of host data items to be stored at persistent memory device 150 of memory subsystem 110. In response to identifying the one or more host data items, processing logic may execute instructions to prevent an operation from being performed at host system 120 to access the identified one or more host data items at host system 120. Processing logic may transmit the first request to memory subsystem 110 in response to executing the instructions to prevent the operation from being performed at host system 120.

[0074] In some embodiments, the first request may include an indication of a virtual address range of persistent memory device 150 at which one or more host data items of the memory access transaction are to be stored. In other or similar embodiments, the first request may include an indication of an amount of host data of the memory access transaction to be stored at persistent memory device 150. In other or similar embodiments, the first request may include an indication of an amount of host data of the memory access transaction and an indication of a first virtual address in the virtual address range of persistent memory device 150.

[0075] At operation 412, in some embodiments, the processing logic may optionally receive an indication of a transaction identifier associated with the memory access transaction. As described above, the PM manager component 113 of the memory subsystem 110 may generate or obtain a transaction identifier in response to receiving a first request to initiate a memory access transaction, and may transmit an indication of the transaction identifier to the host system 120. In response to receiving the indication of the transaction identifier, the processing logic may store the indication at a memory buffer of the host system 120. In other or similar embodiments, the processing logic does not receive a transaction identifier from the memory subsystem 110, and may instead generate a transaction identifier for the memory access transaction. In such embodiments, the processing logic may include the transaction identifier in the first request transmitted to the memory subsystem 110.

[0076] At operation 414, processing logic may transmit a host data item of the one or more host data items to the memory subsystem 110 for storage at the persistent memory device. In some embodiments, processing logic may generate an instruction for the PM manager component 113 of the memory subsystem 110 to store the host data item at a specific virtual address of the persistent memory device 150. As described above, the specific virtual address may be included in the virtual address range included in the first request. Processing logic may transmit an instruction including the host data item and the specific virtual address to the memory subsystem 110. In some embodiments, the instruction may further include an indication of a transaction identifier of the memory access transaction.

[0077] At operation 416, processing logic may determine whether each host data item of the memory access transaction has been transmitted to the memory subsystem. Processing logic may determine whether each host data item has been transmitted to the memory subsystem by determining whether an instruction to store each of the one or more host data items to the persistent memory device 150 has been transmitted to the memory device 110. In response to processing logic determining that each host data item of the memory access transaction has been transmitted to the memory subsystem, method 400 may continue to operation 418. In response to processing logic determining that each host data item of the memory access transaction has not been transmitted to the memory subsystem, method 400 may return to operation 414. At operation 418, processing logic may transmit a second request to the memory subsystem to submit the memory access transaction. The second request may include an indication of a transaction identifier of the memory access transaction, as described herein. At operation 420, processing logic may receive a message from the memory subsystem indicating completion of the memory access transaction.

[0078] In some embodiments, processing logic may detect that one or more host data items associated with the process have been updated between a time period in which the host data items have been transmitted to the memory subsystem (e.g., during or near a time period in which the operation associated with block 414 is performed) and a time period in which a request to submit a memory access transaction has been transmitted (e.g., during or near a time period in which the operation associated with block 416 is performed). In such embodiments, processing logic may transmit the updated host data items to the memory subsystem 110, and may indicate to the memory subsystem 110 (e.g., via a notification and / or request transmitted to the memory subsystem 110) that the updated host data items are associated with the same virtual address as the initial host data items. According to the previously described embodiments, the PM manager 113 may store the updated host data items at the buffer 137 and / or the persistent memory 310.

[0079] Figure 5Flowchart of an example method 500 for storing host data at a persistent memory area of ​​a memory subsystem according to some embodiments of the present disclosure. The method 500 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by Figure 1 The method 500 is performed by the PM manager component 113 of the memory subsystem controller 110. In other or similar embodiments, one or more operations of the method 500 are performed by another component of the memory subsystem controller 110. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0080] At block 510, processing logic obtains an identifier associated with a memory access transaction initiated by a host system. Processing logic (e.g., PM manager 113) may obtain the memory access transaction identifier, as described above. At block 512, processing logic stores one or more host data items in a memory buffer on a first memory device residing in the memory subsystem. The one or more host data items may be associated with the memory access transaction identifier, as described above. At block 514, processing logic receives a request to submit the data items associated with the memory access transaction identifier to a persistent memory, as described above. At block 518, processing logic transfers at least a portion of the one or more host data items from the memory buffer to the persistent memory.

[0081] Figure 6 An example machine of computer system 600 is shown, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to execute corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0082] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Additionally, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0083] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0084] Processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 that communicates through a network 620.

[0085] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0086] In one embodiment, instructions 626 include instructions for implementing a voltage bin boundary component (eg, Figure 1 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0087] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively convey the substance of their work to others skilled in the art. In this document, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0088] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device to manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and to transform that data into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0089] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs, and magnetic optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0090] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0091] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method for memory operation, comprising: receiving, by a processing device of a memory subsystem from a host system, a first request to initiate a memory access transaction, wherein the first request indicates an address range associated with a host data item of the memory access transaction; allocating a region of a memory buffer resident on a volatile memory device of the memory subsystem for storing the host data items having addresses within the address range; creating a mapping in a metadata structure between a transaction identifier of the memory access transaction and the address range associated with the host data item of the memory access transaction; storing each input host data item having an address within the address range in the memory buffer resident on the volatile memory device; identifying, based on the mapping in the metadata structure, one or more host data items stored in the memory buffer and associated with the transaction identifier; transferring the one or more host data items from the memory buffer to a persistent storage device; updating the metadata structure to remove the mapping between the transaction identifier and the address range for the memory access transaction; and The memory access transaction is committed.

2. The method according to claim 1, further comprising: A notification of successful submission of the memory access transaction is transmitted to the host system.

3. The method according to claim 1, further comprising: A second request is received from the host system to commit the memory access transaction.

4. The method according to claim 1, further comprising: In response to receiving a third request from the host system to abort the memory access transaction before committing the memory access transaction, the host data item of the memory access transaction is discarded from the memory buffer.

5. The method according to claim 1, further comprising: In response to failure to receive a fourth request from the host system to commit the memory access transaction within a predefined time period, discarding the host data item of the memory access transaction from the memory buffer. The method of claim 1 , wherein the first request references the transaction identifier of the memory access transaction.

7. The method according to claim 1, further comprising: The transaction identifier is transmitted to the host system.

8. The method of claim 1, wherein the persistent memory device is a non-volatile memory device or a power protected volatile memory device.

9. The method according to claim 1, further comprising: In response to receiving the first request, the transaction identifier is selected from a plurality of unique transaction identifiers associated with the memory subsystem, wherein the mapping between the transaction identifier and the address range of the memory access transaction is created such that the transaction identifier is not available for association with other memory access transactions at the memory subsystem.

10. A memory subsystem comprising: a first memory device comprising a memory buffer; a second memory device, wherein one or more portions of the second memory device include persistent memory; as well as a processing device coupled to the first memory device and the second memory device, the processing device being configured to perform operations comprising: obtaining a memory access transaction identifier of a memory access transaction initiated by a host system, wherein a host data item of the memory access transaction is associated with an address range provided by the host system; creating a mapping in a metadata structure between the memory access transaction identifier of the memory access transaction and the address range provided by the host system; storing each input host data item having an address within the address range in a memory buffer resident on a first memory device of the memory subsystem, wherein the host data item stored in the memory buffer is associated with the memory access transaction identifier; receiving a request from the host system to commit the host data item associated with the memory access transaction identifier to the persistent memory, identifying, based on the mapping in the metadata structure, one or more host data items stored in the storage buffer and associated with the transaction identifier; thereby transferring at least a portion of the one or more host data items from the memory buffer to the persistent memory; and The metadata structure is updated to remove the mapping between the memory access transaction identifier and the address range.

11. The memory subsystem of claim 10, wherein the operations further comprise: receiving a request from the host system to store one or more additional host data items associated with the memory access transaction identifier to the persistent memory, wherein one or more of the host data items correspond to an initial state of host data associated with the host system and the one or more additional host data items correspond to an updated state of the host data; as well as The one or more additional host data items are stored to the persistent memory.

12. The memory subsystem of claim 11, wherein the operations further comprise: receiving a request from the host system to restore the host data to the initial state; as well as One or more of the host data items are copied from the memory buffer to a region of the persistent memory storing the one or more additional host data items.

13. The memory subsystem of claim 10, wherein the operations further comprise: In response to receiving a request from the host system to abort the memory access transaction before committing the memory access transaction, the host data item of the memory access transaction is discarded from the memory buffer.

14. The memory subsystem of claim 10, wherein the operations further comprise: In response to failure to receive a request from the host system to commit the memory access transaction within a predefined time period, the host data item of the memory access transaction is discarded from the memory buffer.

15. The memory subsystem of claim 10, wherein obtaining the memory access transaction identifier associated with the memory access transaction comprises: generating the memory access transaction identifier; as well as An indication of the memory access transaction identifier is transmitted to the host system.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving, from a host system, a first request to initiate a memory access transaction, wherein the first request indicates an address range associated with a host data item of the memory access transaction; allocating a region of a memory buffer resident on a volatile memory device for storing said host data items having addresses within said address range; creating a mapping in a metadata structure between a transaction identifier of the memory access transaction and the address range associated with the host data item of the memory access transaction; storing each input host data item having an address within the address range in the memory buffer resident on the volatile memory device; identifying, based on the mapping in the metadata structure, one or more host data items stored in the memory buffer and associated with the transaction identifier; transferring the one or more host data items from the memory buffer to a persistent storage device; updating the metadata structure to remove the mapping between the transaction identifier and the address range for the memory access transaction; and The memory access transaction is committed.

17. The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise: A notification of successful submission of the memory access transaction is transmitted to the host system.

18. The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise: A second request is received from the host system to commit the memory access transaction.

19. The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise: In response to receiving a third request from the host system to abort the memory access transaction before committing the memory access transaction, the host data item of the memory access transaction is discarded from the memory buffer.

20. The non-transitory computer-readable storage medium of claim 16, wherein the operations further comprise: In response to failure to receive a fourth request from the host system to commit the memory access transaction within a predefined time period, discarding the host data item of the memory access transaction from the memory buffer.

21. The non-transitory computer-readable storage medium of claim 16, wherein the persistent memory device is a non-volatile memory device or a power-protected volatile memory device.

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