A data processing system and method

Abstract

This specification discloses a data processing system and method. In an embodiment of this specification, when a first device sends target data to a second device, the first device determines a target memory area from a shared memory located in the first device or the second device, writes the target data into the target memory area, and updates the write pointer corresponding to the first device stored in a register. When the second device receives the target data, the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data. In this method, since the speed of reading and writing registers is faster than the speed of accessing the shared memory, the entire process of the first device and the second device reading and writing the target data is fast and takes a short time, thereby improving the communication efficiency between the first device and the second device.

Description

Technical Field

[0001] This specification relates to the field of computer technologies, and in particular, to a data processing system and method. Background Art

[0002] In the field of computers, communication between a computer's host and external devices can be achieved by accessing shared memory. The access to shared memory can include: reading and writing to shared memory. Among them, external devices can include: smart cards. A smart card is a PCI device, such as: an FPGA card.

[0003] Taking a smart card as an example, in the prior art, for the same shared memory between a host and a smart card, the host and the smart card can respectively manage a part of the memory in the same shared memory. When the shared memory is located in the smart card, when the host sends data to the smart card, the host can write data to the part of the memory managed by the host through the Direct Memory Access (DMA) method, and then write the address of the memory space where the data is written to the shared request area in the shared memory through the DMA method, and update the pointer of the shared request area. The smart card obtains the data written by the host according to the updated pointer of the shared request area and the memory address of the written data in the shared request area. After the smart card reads and processes the data, it writes the memory address to be recycled to the area to be recycled in the shared memory, and updates the pointer of the area to be recycled to notify the host to recycle the memory space. When the host recycles the memory space, the host reads the memory address to be recycled from the area to be recycled through the DMA method, and recycles the memory space corresponding to the memory address to be recycled.

[0004] However, in the prior art, the process of accessing shared memory during communication between a host and external devices is complex, and the total time consumed for reading and writing data and recycling memory space is relatively long, resulting in low communication efficiency between the host and external devices. Summary of the Invention

[0005] Embodiments of this specification provide a data processing system and method to partially solve the problems existing in the above prior art.

[0006] Embodiments of this specification adopt the following technical solutions:

[0007] A data processing system provided in this specification, the system includes: a first device and a second device, a shared memory is provided in the first device or the second device, and a register is provided in the first device or the second device;

[0008] When the first device sends target data to the second device, it determines a target memory area from the shared memory, writes the target data into the target memory area, and updates the write pointer corresponding to the first device stored in the register.

[0009] When the second device receives the target data sent by the first device, the second device accesses the register, and according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, reads the target data from the target memory area and processes the target data.

[0010] Optionally, after processing the target data, the second device updates the read pointer corresponding to the second device stored in the register to release the target memory area.

[0011] Optionally, the register at least includes: a write pointer register storing the write pointer corresponding to the first device, and a read pointer register storing the read pointer corresponding to the second device.

[0012] The first device updates the write pointer corresponding to the first device stored in the write pointer register.

[0013] When the second device receives the target data sent by the first device, the second device accesses the write pointer register and the read pointer register, and according to the write pointer obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, reads the target data from the target memory area and processes the target data.

[0014] Optionally, the shared memory at least includes: the write memory area of the first device, the read memory area of the first device, the write memory area of the second device, and the read memory area of the second device, where the write memory area of the first device is the same as the read memory area of the second device, and the read memory area of the first device is the same as the write memory area of the second device.

[0015] Optionally, after the second device reads part of the target data, it determines the end position after reading the part of the data, and when it determines to continue reading the target data, it reads the remaining data in the target data according to the end position.

[0016] Optionally, the register includes: a data length register; the data length of the next data stored by the first device is recorded in the data structure storing the target data in the target memory area.

[0017] When the target memory area changes from empty to non-empty after the first device writes the target data, the first device writes the data length of the target data into the data length register;

[0018] The second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the data structure, so that after the first device writes the next data into the target memory area, the next data is read from the target memory area according to the pre-read data length of the next data.

[0019] Optionally, when the second device determines that the target memory area becomes empty again, the second device deletes the stored data length in the data length register.

[0020] Optionally, before the first device writes the target data into the target memory area, the first device sets the data state identifiers at the head and tail of the target data body in the target memory area to invalid values, and the target data body is used to write the target data;

[0021] At the beginning when the first device writes the target data into the target data body, the first device sets the data state identifier at the head of the target data body to a valid value, and when the first device completely writes the target data into the target data body, the first device sets the data state identifier at the tail of the target data body to a valid value.

[0022] Optionally, when the first device is the host in the blockchain all-in-one machine, the second device is a smart card deployed on the blockchain all-in-one machine; the target data includes transaction data sent by the blockchain client to the host.

[0023] A data processing method provided in this specification includes:

[0024] The first device determines a target memory area from the shared memory located in the first device or the second device;

[0025] Write the target data sent by the first device to the second device into the target memory area, and update the write pointer corresponding to the first device in the register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data; wherein, the register is located in the first device or the second device.

[0026] Optionally, the register at least includes: a write pointer register storing a write pointer corresponding to a first device, and a read pointer register storing a read pointer corresponding to a second device;

[0027] Updating the write pointer corresponding to the first device in the register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data, specifically including:

[0028] Updating the write pointer corresponding to the first device in the write pointer register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, and processes the target data.

[0029] Optionally, the register includes: a data length register, and the method further includes:

[0030] When the target memory area changes from empty to non-empty after the first device writes the target data, the first device writes the data length of the target data into the data length register, so that the second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the data structure storing the target data in the target memory area, so as to read the next data from the target memory area according to the pre-read data length of the next data after the first device writes the next data into the target memory area.

[0031] Optionally, before writing the target data sent by the first device to the second device into the target memory area, the method further includes:

[0032] The first device sets the data state identifiers at the head and tail of the target data body in the target memory area to invalid values, and the target data body is used to write the target data.

[0033] Optionally, the method further includes:

[0034] At the beginning of the first device writing the target data into the target data body, the first device sets the data state identifier at the head of the target data body to a valid value, and when the first device completely writes the target data into the target data body, the first device sets the data state identifier at the tail of the target data body to a valid value.

[0035] This specification provides a data processing method, and the method includes:

[0036] Second device access register;

[0037] According to the write pointer corresponding to the first device and the read pointer corresponding to the second device obtained by accessing the register, read the target data sent by the first device from the target memory area, and process the target data, where the register accessed by the second device is located in the first device or the second device, the target memory area is determined from the shared memory located in the first device or the second device, and the obtained write pointer corresponding to the first device is updated after the first device writes the target data into the target memory area.

[0038] Optionally, the method further includes:

[0039] After the second device reads and processes the target data, the second device updates the read pointer corresponding to the second device to release the target memory area.

[0040] Optionally, the register at least includes: a write pointer register storing the write pointer corresponding to the first device, and a read pointer register storing the read pointer corresponding to the second device;

[0041] The second device accesses the register, specifically including:

[0042] The second device accesses the write pointer register and the read pointer register;

[0043] According to the write pointer corresponding to the first device and the read pointer corresponding to the second device obtained by accessing the register, read the target data sent by the first device from the target memory area, and process the target data, specifically including:

[0044] According to the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, read the target data sent by the first device from the target memory area, and process the target data.

[0045] Optionally, reading the target data sent by the first device from the target memory area specifically includes:

[0046] After the second device reads a part of the target data, determine the end position after reading the part of the data, and when it is determined to continue reading the target data, read the remaining data in the target data according to the end position.

[0047] Optionally, the register includes: a data length register;

[0048] Reading the target data sent by the first device from the target memory area specifically includes:

[0049] The second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the data structure storing the target data in the target memory area, so that after the first device writes the next data to the target memory area, according to the pre-read data length of the next data, reads the next data from the target memory area; wherein, the data length of the target data in the data length register is obtained after the first device writes the data length of the target data to the data length register when the target memory area changes from empty to non-empty after the first device writes the target data.

[0050] Optionally, the method further includes:

[0051] When the second device determines that the target memory area becomes empty again, the second device deletes the stored data length in the data length register.

[0052] A data processing device provided in this specification includes:

[0053] A determining memory area module, configured to enable the first device to determine a target memory area from a shared memory located in the first device or the second device;

[0054] A data processing module, configured to write the target data sent by the first device to the second device into the target memory area, and update the write pointer corresponding to the first device in the register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data; wherein, the register is located in the first device or the second device.

[0055] A data processing device provided in this specification includes:

[0056] An access module, configured to enable the second device to access the register;

[0057] A data processing module, configured to read target data sent by the first device from a target memory area according to a write pointer corresponding to the first device and a read pointer corresponding to the second device obtained from an access register, and process the target data, where a register accessed by the second device is located in the first device or the second device, the target memory area is determined from a shared memory located in the first device or the second device, and the obtained write pointer corresponding to the first device is updated after the first device writes the target data into the target memory area.

[0058] A computer-readable storage medium provided in this specification, where the storage medium stores a computer program, and when the computer program is executed by a processor, the above data processing method is implemented.

[0059] An electronic device provided in this specification includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above data processing method is implemented.

[0060] At least one of the above technical solutions adopted in the embodiments of this specification can achieve the following beneficial effects:

[0061] In the embodiments of this specification, when the first device sends target data to the second device, the first device determines a target memory area from a shared memory located in the first device or the second device, writes the target data into the target memory area, and updates the write pointer corresponding to the first device stored in the register. When the second device receives the target data, the second device reads the target data from the target memory area according to the write pointer and the read pointer corresponding to the second device obtained from the access register, and processes the target data. In this method, since the speed of reading and writing the register is faster than the speed of accessing the shared memory, compared with the prior art, the entire process of the first device and the second device reading and writing the target data is faster and takes less time, thereby improving the communication efficiency between the first device and the second device. Description of the Drawings

[0062] The drawings described herein are used to provide a further understanding of this specification, and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification, and do not constitute an improper limitation of this specification. In the drawings:

[0063] Figure 1 It is a schematic flowchart of a data processing system provided by an embodiment of this specification;

[0064] Figure 2 It is a schematic diagram of dividing a shared memory provided by an embodiment of this specification;

[0065] Figures 3a - 3cA schematic diagram of reading and writing target data provided in an embodiment of this specification;

[0066] Figure 4 A schematic diagram of a receiving device provided in an embodiment of this specification reading a target message from a next reading position;

[0067] Figures 5a - 5b A schematic diagram of setting a message status identifier for a first device provided in an embodiment of this specification;

[0068] Figure 6 A flowchart of a data processing method provided in an embodiment of this specification;

[0069] Figure 7 A flowchart of another data processing method provided in an embodiment of this specification;

[0070] Figure 8 A schematic diagram of the structure of a data processing device provided in an embodiment of this specification;

[0071] Figure 9 A schematic diagram of the structure of another data processing device provided in an embodiment of this specification;

[0072] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this specification. DETAILED DESCRIPTION

[0073] In some specified scenarios, the host of a computer needs to use external devices to perform certain specified services. In this case, the host needs to communicate with the external device. Among them, software with specified functions can be run on external devices such as smart cards, and these software can generally communicate with the host through shared memory. In addition, shared memory can be located in the host or in an external device. Both the host and the external device can access shared memory that is not inside themselves through direct memory access (DMA). When the shared memory is inside itself, it does not need to be accessed through DMA.

[0074] For example, in a blockchain all-in-one machine, the smart card deployed on the blockchain all-in-one machine is mainly responsible for executing privacy transactions to ensure the confidentiality of transactions. Among them, the smart card deployed on the blockchain all-in-one machine can be a Field Programmable Gate Array (FPGA) card. When the host receives the encrypted transaction data submitted by the blockchain client, the host writes the encrypted transaction data into the shared memory by accessing the shared memory located in the host or the FPGA card. The FPGA card reads the encrypted transaction data in the shared memory, decrypts the transaction data according to the read encrypted transaction data to obtain the decrypted transaction information, processes the transaction information, and writes the processing result into the shared memory to return the processing result to the host. The host performs accounting based on the returned processing result.

[0075] When the transaction data is transfer data, after the smart card reads the encrypted transaction data from the shared memory, it decrypts the encrypted transaction data with the private key to obtain the transfer information. Then, the smart card synchronizes the balances in the accounts of both parties to the transaction according to the account name and transfer amount in the transfer information. Finally, the account information after balance synchronization is encrypted to obtain the ciphertext of the account information, and the ciphertext of the account information is written into the shared memory, so that the host reads the ciphertext of the account information from the shared memory and performs accounting based on the ciphertext of the account information to update the world state of the blockchain.

[0076] Based on the above scenario of accessing the shared memory, in the prior art, when the host communicates with the smart card, if the shared memory is located in the smart card and a part of the shared memory is managed by the host and the other part is managed by the smart card, when the host sends the encrypted transaction data to the smart card, the host writes the encrypted transaction data into the memory managed by the host through the DMA method, writes the memory address with the encrypted transaction data into the shared request area through the DMA method, and modifies the pointer of the shared request area. The smart card first reads the memory address in the shared request area, then reads the encrypted transaction data in the memory space corresponding to the memory address, and finally writes the memory address corresponding to the memory after reading the transaction data into the area to be recycled in the shared memory and modifies the pointer of the area to be recycled. When the host reclaims the memory space, it reads the memory address from the area to be recycled through the DMA method and reclaims the memory space corresponding to the memory address by modifying the pointer of the area to be recycled.

[0077] In the prior art, when the host sends the encrypted transaction data to the smart card, it accesses the shared memory through the DMA method twice. When the host reclaims the memory space, it accesses the shared memory through the DMA method once. Also, because the speed of accessing the shared memory through the DMA method is relatively slow, the communication process between the host and the smart card is complex and time-consuming, thus reducing the communication efficiency between the host and the smart card.

[0078] In this specification, the access to the shared memory is mainly implemented by using the shared memory of the circular buffer and the register storing the read and write pointers. Based on the above scenario of accessing the shared memory, if the shared memory is located in the smart card, when the host sends encrypted transaction data to the smart card, the host writes the encrypted transaction data into the shared memory through the DMA method and updates the write pointer corresponding to the host in the register. The smart card reads and processes the encrypted transaction data in the shared memory according to the write pointer corresponding to the host in the register and the read pointer corresponding to the smart card in the register, and updates the read pointer corresponding to the smart card in the register to reclaim the memory space for writing the encrypted transaction data.

[0079] In this specification, when the host communicates with the smart card, it accesses the shared memory only once through the DMA method. Compared with the prior art, the process of accessing the shared memory adopted in this specification is simpler, and the speed of accessing the register is faster than that of accessing the shared memory through the DMA method, resulting in a faster speed of the read and write pointers in this specification than the speed of modifying the read and write pointers by accessing the shared memory through the DMA method in the prior art. Therefore, the total time consumed for one read and write operation in this specification is shorter, thus improving the communication efficiency between the host and the smart card.

[0080] It should be noted that the access speeds of different communication mechanisms of the device from fast to slow are as follows: the speed of the device accessing the local memory, the speed of the device accessing the register, and the speed of the device accessing the shared memory through the DMA method.

[0081] To make the purpose, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this specification.

[0082] The following will detail the technical solutions provided by each embodiment of this specification in conjunction with the drawings.

[0083] Figure 1 It is a schematic flowchart of the data processing system provided by the embodiment of this specification.

[0084] In Figure 1In it, the data processing system may include a first device and a second device. The first device may be a sending device for sending data or a receiving device for receiving data. Similarly, the second device may be a sending device for sending data or a receiving device for receiving data. Among them, the first device may be the host of a computer or an external device outside the host. Similarly, the second device may be the host of a computer or an external device outside the host. Among them, the external device may be a PCI device, such as a smart card. The smart card may include an FPGA card.

[0085] In addition, the first device and the second device may communicate through a shared memory. Taking the first device sending data to the second device as an example, the first device sending data means that the first device writes data into the shared memory, and the second device receiving data means that the second device reads data from the shared memory and processes the read data.

[0086] In the embodiment of this specification, the shared memory may be located in the first device or in the second device. The shared memory may adopt a circular buffer data structure to store data, and the read and write pointers in the register may indicate the memory addresses when reading and writing data in the circular buffer.

[0087] Similarly, the register may be set in the first device or in the second device. There may be multiple registers, and each register may be a physical register or a virtual register. In addition, the register may be a register that both the first device and the second device can access.

[0088] When there are multiple registers, the registers located in the first device or the second device may include a write pointer register, a read pointer register, and a data length register. The write pointer register may include a write pointer register storing the write pointer corresponding to the first device and a write pointer register storing the write pointer corresponding to the second device. The read pointer register may include a read pointer register storing the read pointer corresponding to the first device and a read pointer register storing the read pointer corresponding to the second device. Among them, the write pointer may indicate the memory address of the data to be written, and the read pointer may indicate the memory address of the written data or the memory address of the unprocessed data. The data length register may include a data length register corresponding to the data written by the first device and a data length register corresponding to the data written by the second device. Among them, the data length register may store the memory size occupied between the start position and the end position of the data content, the memory address corresponding to the start position of the data content, and the memory address corresponding to the end position of the data content. Among them, the memory size may be expressed in bytes or bit positions.

[0089] In order to ensure that the first device and the second device in the system can communicate simultaneously without interfering with each other, the shared memory can be divided into multiple memory areas according to the data transfer directions between the first device and the second device. Among them, the memory areas of the shared memory at least include: the write memory area of the first device, the read memory area of the first device, the write memory area of the second device, and the read memory area of the second device. Among them, the write memory area of the first device is the same as the read memory area of the second device, and the read memory area of the first device is the same as the write memory area of the second device. That is, based on the two data transfer directions between the first device and the second device, the shared memory can be divided into two memory areas. For each memory area, only the first device or the second device can read data or write data in this memory area, and cannot read and write data simultaneously. In addition, each memory area in the shared memory can adopt the data structure of a circular buffer to store data.

[0090] The schematic diagram of dividing the shared memory into multiple memory areas is as Figure 2 shown.

[0091] In Figure 2 , the shared memory is divided into two memory areas, namely memory area 1 and memory area 2. Memory area 1 corresponds to the situation where the first device sends data to the second device. Memory area 1 is the write memory area of the first device and the read memory area of the second device; Memory area 2 corresponds to the situation where the second device sends data to the first device. Memory area 2 is the write memory area of the second device and the read memory area of the first device.

[0092] In addition, the data structure of the circular buffer in the target memory area of the shared memory at least includes: the data body. The data body can be the data structure used to store data in the target memory area of the shared memory. The target memory area contains multiple data bodies, and each data body corresponds to the memory space for storing one piece of data. Among them, the data body can include: the data body length and the data body text. The data body length is used to store the data length of the data, and the data body text can be used to store the data content. The memory size occupied by the data body can be fixed.

[0093] In addition, when storing data in the target memory area of the shared memory, the data can be stored continuously or discontinuously.

[0094] Next, taking the first device sending data to the second device as an example, the communication between the first device and the second device will be described.

[0095] When the first device sends target data to the second device, the first device determines the target memory area from the shared memory, and then writes the target data into the target memory area and updates the write pointer corresponding to the first device stored in the register.

[0096] Among them, the target data can be the data involved when the first device and the second device execute a service, such as the transaction data generated by a blockchain client. The target memory area can be determined by the data transmission direction between the first device and the second device. When the first device is the sending device and the second device is the receiving device, the write memory area corresponding to the first device and the read memory area corresponding to the second device can be used as the target memory area. When the first device is the receiving device and the second device is the sending device, the read memory area corresponding to the first device and the write memory area corresponding to the second device can be used as the target memory area.

[0097] When writing the target data into the target memory area, the first device can also access the write pointer corresponding to the first device and the read pointer corresponding to the second device stored in the register, determine the memory space in the target memory area for writing the target data as the target memory space, and determine the data body in the target memory space, and then write the target data into the data body.

[0098] To improve the data writing speed of the first device, the first device can locally cache the write pointer corresponding to the first device and the read pointer corresponding to the second device. In this way, when writing the target data into the target memory area, the first device can determine whether there is a memory space in the target memory area that can write the target data according to the pre-cached write pointer corresponding to the first device and the pre-cached read pointer corresponding to the second device. If it exists, the first device can determine the memory space in the target memory area for writing the target data as the target memory space according to the pre-cached write pointer corresponding to the first device and the pre-cached read pointer corresponding to the second device, and determine the data body in the target memory space, and then write the target data into the data body. If not, the first device can access the read pointer register storing the read pointer corresponding to the second device to obtain the latest read pointer corresponding to the second device. Then, according to the pre-cached write pointer corresponding to the first device and the latest read pointer corresponding to the second device, determine the memory space in the target memory area for writing the target data as the target memory space, and determine the data body in the target memory space, and then write the target data into the data body.

[0099] When updating the write pointer corresponding to the first device stored in the register, the first device can determine the memory address indicated by the write pointer corresponding to the first device after writing the target data into the target memory area of the shared memory according to the data length of the target data, and modify the write pointer corresponding to the first device from the currently indicated memory address to the memory address after the first device writes the target data. Among them, the data length can represent the memory size occupied between the start position and the end position of the data content.

[0100] In addition, after the first device updates the write pointer corresponding to the first device in the write pointer register, it can locally cache the updated write pointer corresponding to the first device. At the same time, the first device can access the read pointer register storing the read pointer corresponding to the second device, obtain the read pointer corresponding to the second device, and perform local caching.

[0101] When the second device receives the target data sent by the first device, the second device can first access the register, and based on the updated write pointer corresponding to the first device and the read pointer corresponding to the second device obtained by accessing the register, read the target data written by the first device from the target memory area and process the read target data. After processing the target data, the second device can update the read pointer corresponding to the second device to release the memory space in the target memory area where the target data is written. Here, updating the read pointer corresponding to the second device may mean that the second device modifies the read pointer corresponding to the second device from the currently indicated memory address to the memory address of the next written data after reading and processing the target data.

[0102] Specifically, when the second device receives the target data sent by the first device, the second device accesses the write pointer register storing the write pointer corresponding to the first device and the read pointer register storing the read pointer corresponding to the second device, and based on the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, reads the target data from the target memory area and processes the target data.

[0103] In addition, when the second device receives the target data sent by the first device, the second device accesses the write pointer register storing the write pointer corresponding to the first device, and based on the write pointer corresponding to the first device obtained by accessing the write pointer register and the pre-cached read pointer corresponding to the second device, reads the target data from the target memory area.

[0104] After the second device updates the read pointer corresponding to the second device in the read pointer register, it can cache the updated read pointer corresponding to the second device. At the same time, the second device can access the write pointer corresponding to the first device stored in the write pointer register, obtain the write pointer corresponding to the first device, and perform local caching.

[0105] In addition, when the first device caches the write pointer corresponding to the first device and the read pointer corresponding to the second device, when the first device sends the next data to the second device again, the first device can determine the memory space in the target memory area where the next data can be written, as the next memory space, according to the cached write pointer corresponding to the first device and the cached read pointer corresponding to the second device. Then, write the next data into the next memory space in the target memory area, update the write pointer corresponding to the first device stored in the write pointer register, and cache the updated write pointer corresponding to the first device.

[0106] When the second device caches the write pointer corresponding to the first device and the read pointer corresponding to the second device, when the second device receives the next data, the second device can read the next data from the next memory space in the target memory area according to the cached read pointer corresponding to the second device and the cached write pointer corresponding to the first device, update the read pointer corresponding to the second device in the read pointer register, and cache the updated read pointer corresponding to the second device.

[0107] Based on the above description of the first device writing the target data into the target memory area in the shared memory and the second device reading the target data from the target memory area in the shared memory, the embodiments of this specification provide a schematic diagram for reading and writing the target data, as Figures 3a - 3c shown. In Figures 3a - 3c it is shown that Figure 3a the target memory area is a circular buffer, and there is no data written in the target memory area, that is, the memory addresses pointed to by the write pointer corresponding to the first device and the read pointer corresponding to the second device are the same. Figure 3b It shows that the first device writes the target data. Figure 3c It shows that the second device reads and processes the target data.

[0108] In Figure 3a both the write pointer corresponding to the first device and the read pointer corresponding to the second device point to the memory address at position A.

[0109] In Figure 3b if the first device writes target data with a data length of 30 bytes into the target memory area, the write pointer corresponding to the first device moves from position A to position B. The read pointer corresponding to the second device still points to the memory address at position A. Among them, Figure 3b the shaded area in

[0110] In Figure 3c refers to the memory space in the target memory area where data is written and not processed.

[0111] In the embodiments of this specification, during the process of the second device reading the target data, after the second device reads part of the target data, it determines the end position after reading the part of the data, and when it determines to continue reading the target data, it reads the remaining data in the target data according to the end position, rather than continuing to read the target data from the memory address indicated by the read pointer. Among them, the situations where the second device reads part of the target data are: the second device does not read the target data in the specified order, and when processing the target data, it needs to process part of the target data first. In addition, the specified order can be the first-in first-out order.

[0112] Specifically, the next reading position can be determined according to the end position, and based on the next reading position, the remaining data in the target data is read.

[0113] For example: when the second device processes data, it may process part of the target data together with the previous data and does not cache the entire target data. In this case, the second device needs to determine the next reading position of the target data according to the end position (i.e., the actual end memory address) after the part of the data that has been processed in the target data. When the second device needs to process the remaining data in the target data, it continues to read the remaining data in the target data from the next reading position and processes the remaining data. As Figure 4 shown.

[0114] In Figure 4 , the target memory area is a circular buffer. The read pointer of the second device points to the memory address at position C in the circular buffer. The previous data relative to the target data is written between position C and position D, and the target data is written between position D and position E. The write pointer corresponding to the first device points to the memory address at position E. If the second device processes part of the data (i.e., the data between position D and position F) in the target data between position D and position E together with the previous data, the read pointer corresponding to the second device should point to position D because there is still remaining data in the target data that has not been processed. In addition, the second device can use the start position of the unprocessed data (i.e., the shaded area) in the target data as the next reading position according to the end position (i.e., position F) of the processed data in the target data, and continue to read the remaining data in the target data. Among them, Figure 4 the shaded area in

[0115] In the embodiments of this specification, when the first device continuously stores data, to improve the efficiency of the second device in reading target data, the second device can obtain the data length of the next data after the target data when reading the target data, and cache the data length of the next data. In this way, when the second device reads the next data, it can directly read the content of the next data without first reading the data length of the next data and then reading the content of the next data when reading the next data.

[0116] When the target memory area is empty before writing the target data, the second device does not cache the data length of the previous next data obtained. In this case, after the first device writes the target data into the target memory area and the target memory area changes from empty to non-empty, the first device can write the data length of the target data into the data length register corresponding to when the first device sends data. When the second device reads the target data, the second device accesses the data length register and reads the target data from the target memory area based on the data length of the target data in the data length register. At the same time, during the process of the first device writing the next data into the target memory area, the first device first writes the data length of the next data into the length of the next data body in the data structure of the target memory area, and then writes the next data into the body of the next data in the data structure of the target memory area. Therefore, the data length of the next data stored by the first device is recorded in the data structure for storing the target data in the target memory area. In this way, after the second device reads the target data, it can pre-read the data length of the next data from the data structure for storing the target data in the target memory area and cache the data length of the next data. After the first device writes the next data into the target memory area, when the second device reads the next data, it can directly read the content of the next data from the target memory area according to the pre-read data length of the next data, and cache the data length of the pre-read next-next data to update the data length of the next data cached locally according to the data length of the pre-read next-next data.

[0117] In addition, to improve the speed at which the second device obtains the data length of the next data, during the process of the first device writing the data length of the next data into the target memory area, the first device can also update the data length of the next data to the data length register, and the second device can obtain the data length of the next data by accessing the data length register.

[0118] When the second device cannot obtain the valid data length through pre-reading, the second device determines that the target memory area becomes empty again. When the second device determines that the target memory area becomes empty again, the second device updates the read pointer corresponding to the second device to the memory address at the end position of the last data in the target memory area. At this time, the write pointer corresponding to the first device is the same as the read pointer corresponding to the second device. In this way, by updating the read pointer corresponding to the second device, the second device can indirectly notify the first device that the target memory area is empty and new data can be written into the target memory area again.

[0119] In addition, the way for the second device to notify the first device to write new data into the target memory area can also be: when the second device determines that the target memory area becomes empty again, the second device deletes the data length stored in the data length register, that is, sets the value in the data length register to an invalid value. The second device can delete the data length stored in the data length register after updating the read pointer corresponding to the second device, or before updating the read pointer corresponding to the second device. Among them, the data length stored in the data length register may be the data length of the target data, or the data length of the last data written into the target memory area. That is, if the second device updates the data length of the data written into the target memory area to the data length register in real time, the second device can delete the data length of the latest data in the data length register.

[0120] The first device can determine whether the target memory area becomes empty again by accessing the read pointer stored in the read pointer register corresponding to the second device and the write pointer corresponding to the first device cached in advance by the first device. If the target memory area becomes empty again, write the data length of the new data into the data length register again, and write the new data into the target memory area. If the target memory area is not empty, there is no need to write the data length of the new data into the data length register again.

[0121] In addition, after the first device accesses (which can be in a polling manner) the data length register, if the first device detects that there is a valid data length in the data length register, the first device does not need to write the new data length into the data length register again; if it detects that there is no valid data length in the data length register, the first device can write the new data length into the data length register again and write the new data into the target memory area. Among them, the valid data length in the data length register can refer to the specific numerical value of the data length, and the invalid value in the data length register can refer to the data identifier when the data length register is empty, such as: NULL.

[0122] In addition, for the data length of the next data cached by the second device, after the first device writes the data length of the next data into the target memory area, if the first device fails to write the next data into the target memory area and the second device pre-reads the data length of the next data and caches it, the second device can delete the cached data length of the next data.

[0123] In the embodiments of this specification, when the write operation of the first device and the read operation of the second device are performed simultaneously, and the second device cannot obtain a valid data length through pre-reading, taking the second device deleting the stored data length in the data length register after updating the read pointer corresponding to the second device as an example, the timing of the first device accessing the read pointer register storing the read pointer corresponding to the second device is divided into three cases:

[0124] In the first case, the second device cannot obtain a valid data length written into the target memory area through pre-reading, but the second device does not update the read pointer corresponding to the second device in the read pointer register. At this time, the first device accesses the read pointer register, and determines that the target memory area is not empty based on the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device. Then, the first device will not rewrite the data length of the new data into the data length register. After that, the second device deletes the data length in the data register.

[0125] In the second case, the second device cannot obtain a valid data length written into the target memory area through pre-reading and updates the read pointer corresponding to the second device in the read pointer register. At this time, the first device accesses the read pointer register, and determines that the target memory area is empty again based on the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device. The first device writes the data length of the new data into the data register. However, after that, the second device deletes the data length of the new data written by the first device into the data register.

[0126] In the third case, the second device cannot obtain a valid data length written into the target memory area through pre-reading and updates the read pointer corresponding to the second device in the read pointer register. Then, the second device deletes the data length in the data register. At this time, the first device accesses the read pointer register, and determines that the target memory area is empty again based on the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device. The first device writes the data length of the new data into the data register.

[0127] In addition, taking the example that the second device deletes the data length stored in the data length register before updating the read pointer corresponding to the second device, the timing of the first device accessing the read pointer register storing the read pointer corresponding to the second device is divided into three cases:

[0128] In the first case, the second device cannot obtain the valid data length written into the target memory area through pre-reading. The second device does not delete the data length stored in the data length register and does not update the read pointer corresponding to the second device. At this time, the first device accesses the read pointer register. According to the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device, it is determined that the target memory area is not empty. Then, the first device will not rewrite the data length of the new data into the data length register. After that, the second device deletes the data length in the data register.

[0129] In the second case, the second device cannot obtain the valid data length written into the target memory area through pre-reading. The second device deletes the data length stored in the data length register, but does not update the read pointer corresponding to the second device in the read pointer register. At this time, the first device accesses the read pointer register. According to the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device, it is determined that the target memory area is not empty. The first device will not rewrite the data length of the new data into the data length register.

[0130] In the third case, the second device cannot obtain the valid data length written into the target memory area through pre-reading. The second device deletes the data length stored in the data length register and updates the read pointer corresponding to the second device in the read pointer register. At this time, the first device accesses the read pointer register. According to the read pointer corresponding to the second device obtained by accessing the read pointer register and the write pointer corresponding to the first device pre-cached by the first device, it is determined that the target memory area is empty again. The first device writes the data length of the new data into the data register.

[0131] Regardless of which of the above examples, in the first and second cases, when the second device cannot obtain the valid data length written into the target memory area through pre-reading, it also cannot obtain the data length of the new data from the data register; in the third case, when the second device cannot obtain the valid data length written into the target memory area through pre-reading, it can obtain the data length of the new data from the data register by accessing the data register.

[0132] Therefore, for the first and second cases, when the second device cannot obtain the valid data length written to the target memory area through pre-reading, the second device can access the write pointer register storing the write pointer corresponding to the first device to determine whether the first device writes new data to the target memory area again. If the first device writes new data to the target memory area again, the second device can first read the data length of the new data from the target memory area, then read the new data from the target memory area, read the data length of the next data after the new data after reading the new data, and cache it.

[0133] For the third case, when the second device cannot obtain the valid data length written to the target memory area through pre-reading, it can access the data register to obtain the data length of the new data from the data register. The second device reads the new data from the target memory area based on the data length of the new data.

[0134] In the embodiments of this specification, for the update of the write pointer corresponding to the first device in the write pointer register, when the first device performs a write operation, the first device can update the write pointer corresponding to the first device in the write pointer register according to the data length of the target data. Since the shared memory may be located in the second device and the speed of accessing the register is faster than the speed of accessing the shared memory through the DMA method, this causes the speed of the first device to update the write pointer corresponding to the first device in the write pointer register to be faster than the speed of the first device writing the target data to the target memory area, which may result in incomplete target data read by the second device. Therefore, to avoid the second device reading incomplete target data, data status identifiers can be set at the head and tail of the target data body used to write the target data, and the data status identifiers are used to indicate whether the target data is completely written into the target data body. If the target data is completely written into the target data body, the data status identifiers located at the head and tail of the target data body are both set to valid values. If the target data is not completely written into the target data body, any one of the data status identifiers located at the head and tail of the target data body is set to an invalid value. That is, only when the data status identifiers located at the head and tail of the target data body are both set to valid values, the target data is completely written into the target data body. Therefore, the data structure of the circular buffer in the target memory area further includes: data status identifiers located at the head and tail of the data body. The data status identifiers can be represented by magic numbers. The magic number A indicates that the target data is not written into the target data body, the magic number BB indicates the start of writing the target data into the target data body, the magic number BE indicates the end of writing the target data into the target data body, and the magic number C indicates that the target data in the target data body has been read and processed. Among them, the valid values of the data status identifiers are BB or BE, and the invalid values of the data status identifiers are A or C.

[0135] For the first device, before the first device writes target data to the target memory area, the first device may set the data status flags at the head and tail of the target data body in the target memory area to invalid values. When the first device writes the target data to the target data body, the first device sets the data status flags at the head and tail of the target data body to valid values and updates the write pointer corresponding to the first device.

[0136] Among them, when the first device sets the data status flags at the head and tail of the target data body to invalid values, the first device may continue to set the data status flag at the head of the target data body to an invalid value during the process of the first device writing the previous data to the target memory area. For example: A. When the first device needs to write target data to the target memory area, it can set the data status flag at the head of the target data body to an invalid value.

[0137] Regarding the first device setting the data status flags at the head and tail of the target data body to valid values, when the first device needs to write target data to the target memory area, the first device may write the target data to the body of the target data, and then set the data status flags at the head and tail of the target data body to valid values. Or, during the process of the first device writing target data to the target memory area, when the first device starts writing the target data to the target data body, the first device sets the data status flag at the head of the target data body to a valid value, then writes the target data to the body of the target data, and finally, when the first device completely writes the target data to the target data body, the first device sets the data status flag at the tail of the target data body to a valid value. As Figures 5a - 5b shown.

[0138] In Figures 5a - 5b it, the data structure for storing target data in the target memory area may include: the target data body, the data status flags at the head and tail of the target data body. The target data body may include: the data body length, the data body text. Among them, Figure 5a represents the data structure before the first device writes the target data, and the magic numbers are A and C; Figure 5b represents the data structure after the first device writes the target data into the target data body, and the magic numbers are BB and BE. In addition, in the read and write operations, a fixed memory size can be read and written. Therefore, when the target data does not fill the data body text, Pad represents the padding byte, so that it is not necessary to additionally record the data length of each target data in the specified memory size.

[0139] Based on the above data processing system, an embodiment of this specification provides a data processing method, as Figure 6 shown. Figure 6 is a schematic flowchart of a data processing method provided by an embodiment of this specification. This method is applied to the first device and includes:

[0140] S600: The first device determines a target memory area from the shared memory located in the first device or the second device.

[0141] In the embodiments of this specification, according to the data transmission direction between the first device and the second device, a memory area corresponding to the data transmission direction is determined from the shared memory as the target memory area.

[0142] Specifically, when the first device is the sending device and the second device is the receiving device, the write memory area corresponding to the first device and the read memory area corresponding to the second device can be used as the target memory area. When the first device is the receiving device and the second device is the sending device, the read memory area corresponding to the first device and the write memory area corresponding to the second device can be used as the target memory area.

[0143] S602: Write the target data sent by the first device to the target memory area, and update the write pointer corresponding to the first device in the register, so that the second device can read the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and process the target data; wherein, the register is located in the first device or the second device.

[0144] In the embodiments of this specification, the first device first determines, according to the pre-cached write pointer corresponding to the first device, the data body for writing the target data in the target memory area as the target data body. Then, when the first device starts writing the target data to the target data body, the first device sets the data status flag located at the head of the target data body to a valid value. When the first device completely writes the target data to the target data body, the first device sets the data status flag located at the tail of the target data body to a valid value. At the same time, the write pointer corresponding to the first device in the write pointer register is updated, so that the second device accesses the write pointer register and the read pointer register, and reads and processes the target data from the target memory area according to the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register. After processing the target data, the read pointer corresponding to the second device stored in the read pointer register is updated.

[0145] In addition, when the first device writes to the target memory area and the target memory area changes from empty to non-empty, the first device updates the data length of the target data to the data length register, so that the second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the next data body storing the target data in the target memory area, so that after the first device completely writes the next data to the next data body, the second device reads the next data from the target memory area according to the pre-read data length of the next data.

[0146] Based on the above data processing system, another data processing method is provided in the embodiments of this specification, as Figure 7 shown. Figure 7 It is a schematic flowchart of another data processing method provided by the embodiments of this specification. This method is applied to the second device and includes:

[0147] S700: The second device accesses the register.

[0148] S702: According to the write pointer corresponding to the first device and the read pointer corresponding to the second device obtained by accessing the register, read the target data sent by the first device from the target memory area, and process the target data. Among them, the register accessed by the second device is located in the first device or the second device, the target memory area is determined from the shared memory located in the first device or the second device, and the obtained write pointer corresponding to the first device is updated after the first device writes the target data to the target memory area.

[0149] In the embodiments of this specification, the second device first accesses the write pointer register and the read pointer register. According to the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, read the target data sent by the first device from the target data body in the target memory area, and update the read pointer corresponding to the second device stored in the read pointer register. Among them, the target memory area is a memory area determined by the first device from the shared memory according to the data transmission direction between the first device and the second device, and the write pointer corresponding to the first device is updated after the first device writes the target data to the target data body in the target memory area.

[0150] Among them, during the process of the second device reading the target data, after the second device reads part of the data in the target data, it determines the end position after reading the part of the data, and when it determines to continue reading the target data, it reads the remaining data in the target data according to the end position.

[0151] In addition, the second device accesses the data length register, reads the target data from the target memory area based on the data length of the target data in the data length register, and pre-reads the data length of the next data from the next data body storing the target data in the target memory area, so that after the first device writes the next data into the next data body in the target memory area, the next data is read from the next data body in the target memory area according to the pre-read data length of the next data. The data length of the target data in the data length register is obtained after the first device writes the data length of the target data into the data length register when the target memory area changes from empty to non-empty after the first device writes the target data.

[0152] In addition, after the second device reads and processes the target data in the target data body, the second device sets the data state identifiers at the head and tail of the target data body to invalid values, and updates the read pointer corresponding to the second device stored in the read register; the target data body is used for writing the target data.

[0153] It should be noted that all actions of obtaining data or privacy transaction data in this application are carried out on the premise of complying with the corresponding data protection regulations and policies of the country where the location is located and obtaining the authorization given by the corresponding device owner.

[0154] Through the above Figure 6 and Figure 7 As can be seen from the method shown, when the first device sends the target data to the second device in this specification, the first device determines the target memory area from the shared memory located in the first device or the second device, writes the target data into the target memory area, and updates the write pointer corresponding to the first device stored in the register. When the second device receives the target data, the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer register corresponding to the second device, and processes the target data. In this method, the first device can write the target data by accessing the shared memory only once, and the second device can also read the target data by accessing the shared memory only once. In addition, the recycling of the shared memory is realized by the second device updating the read pointer corresponding to the second device without accessing the shared memory. Moreover, the speed of accessing the register is faster than that of accessing the shared memory through the DMA method. Therefore, the whole process of the first device and the second device reading and writing the target data is simple, fast, and time-consuming is short, thereby improving the communication efficiency between the first device and the second device.

[0155] The above is the data processing method provided by the embodiments of this specification. Based on the same idea, this specification also provides corresponding devices, storage media, and electronic devices.

[0156] Figure 8 The following is a schematic structural diagram of a data processing device provided by the embodiments of this specification. The device includes:

[0157] A memory area determination module 801 is configured to determine, by a first device, a target memory area from a shared memory located in the first device or the second device;

[0158] A data processing module 802 is configured to write target data sent by the first device to the second device into the target memory area, and update a write pointer corresponding to the first device in a register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and a read pointer corresponding to the second device, and processes the target data; wherein, the register is located in the first device or the second device.

[0159] Optionally, the register at least includes: a write pointer register storing a write pointer corresponding to the first device, and a read pointer register storing a read pointer corresponding to the second device; the data processing module 802 is specifically configured to update the write pointer corresponding to the first device in the write pointer register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, and processes the target data.

[0160] Optionally, the apparatus further includes: an updated data length module 803, and a data status flag setting module 804;

[0161] The register includes: a data length register;

[0162] The updated data length module 803 is configured to, when the target memory area changes from empty to non-empty after the first device writes the target data, the first device writes the data length of the target data into the data length register, so that the second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from a data structure storing the target data in the target memory area, so that after the first device writes the next data to the target memory area, the next data is read from the target memory area according to the pre-read data length of the next data.

[0163] Before writing the target data sent by the first device to the second device into the target memory area, the data status flag setting module 804 is configured to set data status flags at the head and tail of a target data body for writing the target data in the target memory area to invalid values by the first device.

[0164] The setting data status flag module 804 is configured to, when the first device starts to write the target data into the target data body, the first device sets the data status flag located at the head of the target data body to a valid value, and when the first device completely writes the target data into the target data body, the first device sets the data status flag located at the tail of the target data body to a valid value.

[0165] Figure 9 FIG. 4 is a schematic structural diagram of another data processing device provided by an embodiment of the present specification. The device includes:

[0166] An access module 901 is configured to enable a second device to access a register;

[0167] A data processing module 902 is configured to read the target data sent by the first device from a target memory area according to a write pointer corresponding to the first device and a read pointer corresponding to the second device obtained by accessing the register, and process the target data. Wherein, the register accessed by the second device is located in the first device or the second device, the target memory area is determined from a shared memory located in the first device or the second device, and the obtained write pointer corresponding to the first device is updated after the first device writes the target data into the target memory area.

[0168] Optionally, the register at least includes: a write pointer register storing a write pointer corresponding to the first device, and a read pointer register storing a read pointer corresponding to the second device; the access module 901 is specifically configured to enable the second device to access the write pointer register and the read pointer register.

[0169] Optionally, the data processing module 902 is specifically configured to read the target data sent by the first device from the target memory area according to the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, and process the target data.

[0170] Optionally, the data processing module 902 is specifically configured to, after the second device reads a part of the target data, determine an end position after reading the part of the data, and when it is determined to continue reading the target data, read the remaining data in the target data according to the end position.

[0171] Optionally, the register includes: a data length register; the data processing module 902 is specifically configured to enable the second device to access the data length register, read the target data from the target memory area based on the data length of the target data in the data length register, and pre-read the data length of the next data from the data structure storing the target data in the target memory area, so that after the first device writes the next data to the target memory area, the next data can be read from the target memory area according to the pre-read data length of the next data; wherein, the data length of the target data in the data length register is obtained after the first device writes the data length of the target data to the data length register when the target memory area changes from empty to non-empty after the first device writes the target data.

[0172] Optionally, the data processing module 902 is further configured to enable the second device to delete the stored data length in the data length register when the second device determines that the target memory area becomes empty again.

[0173] Optionally, the data processing module 902 is further configured to enable the second device to update the read pointer corresponding to the second device after the second device reads and processes the target data, so as to release the target memory area.

[0174] This specification also provides a computer-readable storage medium storing a computer program, which can be used to execute the above-mentioned Figure 6 and Figure 7 data processing methods when executed by a processor.

[0175] Based on Figure 6 and Figure 7 the data processing methods provided, embodiments of this specification also provide Figure 10 the structural schematic diagram of the electronic device shown. As Figure 10 shown, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory. Of course, it may also include other hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the above-mentioned Figure 6 and Figure 7 data processing methods.

[0176] Of course, in addition to the software implementation, this specification does not exclude other implementation manners, such as logical devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logical unit, and can also be hardware or logical devices.

[0177] In the 1990s, it was obvious to distinguish whether an improvement in a technology was a hardware improvement (e.g., improvement in circuit structures such as diodes, transistors, switches, etc.) or a software improvement (improvement in method processes). However, with the development of technology, many improvements in method processes today can be regarded as direct improvements in hardware circuit structures. Almost all designers obtain the corresponding hardware circuit structure by programming the improved method process into the hardware circuit. Therefore, it cannot be said that an improvement in a method process cannot be implemented with a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user's programming of the device. The designer programs by himself to "integrate" a digital system on a single PLD, without having to ask a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a Hardware Description Language (HDL), and there is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. Currently, the most commonly used are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be clear that as long as the method process is slightly logically programmed with the above-mentioned several hardware description languages and programmed into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method process.

[0178] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to logically program the method steps to enable the controller to be implemented in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, and embedded microcontrollers to achieve the same function. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or the structures within the hardware component.

[0179] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0180] For the convenience of description, when describing the above devices, they are described separately as various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0181] Those skilled in the art should understand that the embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, this specification can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0182] This specification is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the specification. It should be understood that each flow and / or block in the flowchart and / or block diagram, and combinations of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device generate means for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0183] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable memory produce a manufacture including instruction means that implement the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0184] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are performed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more of the flows Figure 1 one or more of the flows and / or blocks Figure 1 or means for implementing the functions specified in one or more of the blocks.

[0185] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0186] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0187] Computer readable media include permanent and non-permanent, removable and non-removable media that can be used to store messages by any method or technology. Messages can be computer readable instructions, data structures, modules of programs or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store messages that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0188] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0189] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0190] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0191] The various embodiments in this specification are described in a progressive manner. For the parts that are the same or similar among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0192] The above description is only for the embodiments of this specification and is not intended to limit this specification. For those skilled in the art, various changes and modifications can be made to this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included within the scope of the claims of this specification.

Claims

1. A data processing system, the system comprising: A first device and a second device, wherein a shared memory is provided in the first device or the second device, and a register is provided in the first device or the second device; The first device is the host of a computer, and the second device is an external device outside the host, or the first device is an external device outside the host, and the second device is the host of the computer; When the first device sends target data to the second device, the first device determines a target memory area from the shared memory, writes the target data into the target memory area, and updates the write pointer corresponding to the first device stored in the register; When the second device receives the target data sent by the first device, the second device accesses the register, and reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data; Wherein, the first device and the second device read or write the target data to / from a shared memory not provided inside themselves by means of direct memory access (DMA).

2. The system according to claim 1, after processing the target data, the second device updates the read pointer corresponding to the second device stored in the register to release the target memory area.

3. The system according to claim 1, the register at least includes: A write pointer register storing the write pointer corresponding to the first device, and a read pointer register storing the read pointer corresponding to the second device; The first device updates the write pointer corresponding to the first device stored in the write pointer register; When the second device receives the target data sent by the first device, the second device accesses the write pointer register and the read pointer register, and reads the target data from the target memory area according to the write pointer obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, and processes the target data.

4. The system according to claim 1, the shared memory at least includes: The write memory area of the first device, the read memory area of the first device, the write memory area of the second device, and the read memory area of the second device, wherein the write memory area of the first device is the same as the read memory area of the second device, and the read memory area of the first device is the same as the write memory area of the second device.

5. The system according to claim 1, after the second device reads a part of the target data, it determines the end position after reading the part of the data, and when it determines to continue reading the target data, it reads the remaining data in the target data according to the end position.

6. The system according to claim 1, the register includes: A data length register; The data length of the next data stored by the first device is recorded in the data structure storing the target data in the target memory area; When the target memory area changes from empty to non-empty after the first device writes the target data, the first device writes the data length of the target data into the data length register; The second device accesses the data length register, reads the target data from the target memory area based on the data length of the target data in the data length register, and pre-reads the data length of the next data from the data structure, so as to read the next data from the target memory area according to the pre-read data length of the next data after the first device writes the next data into the target memory area.

7. The system according to claim 6, when the second device determines that the target memory area is empty again, the second device deletes the data length stored in the data length register.

8. The system according to claim 1, before the first device writes the target data to the target memory area, the first device sets the data state identifiers at the head and tail of the target data body in the target memory area to invalid values, and the target data body is used to write the target data; When the first device starts to write the target data to the target data body, the first device sets the data state identifier at the head of the target data body to a valid value, and when the first device completely writes the target data to the target data body, the first device sets the data state identifier at the tail of the target data body to a valid value.

9. The system according to any one of claims 1 to 8, when the first device is the host in the blockchain all-in-one machine, the second device is a smart card deployed on the blockchain all-in-one machine; the target data includes transaction data sent by the blockchain client to the host.

10. A data processing method, the method comprising: The first device determines a target memory area from the shared memory located in the first device or the second device; Write the target data sent from the first device to the second device into the target memory area, and update the write pointer corresponding to the first device in the register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data; wherein, the register is located in the first device or the second device, and the first device and the second device read or write the target data to / from a shared memory not provided inside themselves through direct memory access. The first device is the host of a computer, and the second device is an external device outside the host, or the first device is an external device outside the host, and the second device is the host of a computer.

11. The method according to claim 10, wherein the register at least comprises: A write pointer register storing the write pointer corresponding to the first device, and a read pointer register storing the read pointer corresponding to the second device; Updating the write pointer corresponding to the first device in the register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and the read pointer corresponding to the second device, and processes the target data, specifically including: Updating the write pointer corresponding to the first device in the write pointer register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, and processes the target data.

12. The method according to claim 10, wherein the register comprises: A data length register, and the method further includes: When the target memory area becomes non-empty from empty after the first device writes the target data, the first device writes the data length of the target data into the data length register, so that the second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the data structure storing the target data in the target memory area, so that after the first device writes the next data to the target memory area, reads the next data from the target memory area according to the pre-read data length of the next data.

13. The method according to claim 10, before writing the target data sent by the first device to the second device into the target memory area, the method further comprises: The first device sets the data status identifiers at the head and tail of the target data body in the target memory area to invalid values, and the target data body is used for writing the target data.

14. The method according to claim 13, the method further comprises: When the first device starts to write the target data into the target data body, the first device sets the data status identifier at the head of the target data body to a valid value, and when the first device completely writes the target data into the target data body, the first device sets the data status identifier at the tail of the target data body to a valid value.

15. A data processing method, the method comprising: The second device accesses the register; According to the write pointer corresponding to the first device and the read pointer corresponding to the second device obtained from the access register, read the target data sent by the first device from the target memory area, and process the target data, where the register accessed by the second device is located in the first device or the second device, the target memory area is determined from the shared memory located in the first device or the second device, the obtained write pointer corresponding to the first device is the updated one after the first device writes the target data into the target memory area, where the first device and the second device read or write the target data to / from the shared memory not provided inside themselves through direct memory access, the first device is the host of the computer, the second device is an external device outside the host, or the first device is an external device outside the host, and the second device is the host of the computer.

16. The method according to claim 15, the method further comprises: After the second device reads and processes the target data, the second device updates the read pointer corresponding to the second device to release the target memory area.

17. The method according to claim 15, wherein the register at least comprises: A write pointer register storing the write pointer corresponding to the first device, and a read pointer register storing the read pointer corresponding to the second device; The second device accesses the register, specifically including: The second device accesses the write pointer register and the read pointer register; According to the write pointer corresponding to the first device and the read pointer corresponding to the second device obtained from the access register, read the target data sent by the first device from the target memory area, and process the target data, specifically including: According to the write pointer corresponding to the first device obtained by accessing the write pointer register and the read pointer corresponding to the second device obtained by accessing the read pointer register, read the target data sent by the first device from the target memory area, and process the target data.

18. The method according to claim 15, reading the target data sent by the first device from the target memory area, specifically comprising: After the second device reads part of the target data, determine the end position after reading the part of the data, and when it is determined to continue reading the target data, read the remaining data in the target data according to the end position.

19. The method according to claim 15, wherein the register comprises: A data length register; Reading the target data sent by the first device from the target memory area, specifically including: The second device accesses the data length register, and based on the data length of the target data in the data length register, reads the target data from the target memory area, and pre-reads the data length of the next data from the data structure storing the target data in the target memory area, so that after the first device writes the next data into the target memory area, reads the next data from the target memory area according to the pre-read data length of the next data; where the data length of the target data in the data length register is obtained after the first device writes the data length of the target data into the data length register when the target memory area changes from empty to non-empty after the first device writes the target data.

20. The method according to claim 19, the method further comprises: When the second device determines that the target memory area is empty again, the second device deletes the data length stored in the data length register.

21. A data processing apparatus, comprising: A memory area determination module, configured to enable a first device to determine a target memory area from shared memory located in the first device or the second device; A data processing module, configured to write target data sent by the first device to the target memory area, and update a write pointer corresponding to the first device in a register, so that the second device reads the target data from the target memory area according to the write pointer obtained by accessing the register and a read pointer corresponding to the second device, and processes the target data; wherein the register is located in the first device or the second device, the first device and the second device read or write the target data to / from shared memory not provided inside themselves through direct memory access, the first device is a host of a computer, the second device is an external device outside the host, or the first device is an external device outside the host, and the second device is a host of a computer.

22. A data processing device, comprising: An access module, configured to enable the second device to access the register; A data processing module, configured to read the target data sent by the first device from the target memory area according to the write pointer corresponding to the first device obtained by accessing the register and the read pointer corresponding to the second device, and process the target data, wherein the register accessed by the second device is located in the first device or the second device, the target memory area is determined from shared memory located in the first device or the second device, the obtained write pointer corresponding to the first device is updated after the first device writes the target data to the target memory area, wherein the first device and the second device read or write the target data to / from shared memory not provided inside themselves through direct memory access, the first device is a host of a computer, the second device is an external device outside the host, or the first device is an external device outside the host, and the second device is a host of a computer.

23. A computer-readable storage medium storing a computer program, which, when executed by a processor, implements the method according to any one of claims 10-20 above.

24. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the method according to any one of claims 10-20 above when executing the program.

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