A read-write control circuit, control method, chip and electronic device

Abstract

The present application provides a read-write control circuit, a control method, a chip and an electronic device, belonging to the field of electronic technology. The read-write control circuit includes a cache module; the read-write control circuit is configured to: when there are continuous read-write operations, perform a read operation, and store the data corresponding to the write operation in the cache module; and write the data corresponding to the write operation into a memory from the cache module. The present application can improve the system access efficiency.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a read-write control circuit, a control method, a chip and an electronic device. Background Art

[0002] AHB (Advanced High performance Bus) can trigger access to SRAM (Static Random-Access Memory) by initiating a read operation or a write operation.

[0003] When the AHB bus accesses SRAM, if a write operation is followed by a read operation, the read operation will wait because the SRAM write requires time, affecting the system access efficiency. Summary of the invention

[0004] In order to solve the problems of the prior art, the embodiments of the present application provide a read-write control circuit, a control method, a chip and an electronic device, which can improve the system access efficiency. The technical solution is as follows:

[0005] According to one aspect of the present application, a read-write control circuit is provided, the read-write control circuit comprising a cache module;

[0006] The read-write control circuit is configured as follows:

[0007] When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module;

[0008] The data corresponding to the write operation is written into the memory from the cache module.

[0009] Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

[0010] The read-write control circuit is configured as follows:

[0011] When there is a write operation, storing data corresponding to the write operation in the first-level write cache unit;

[0012] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0013] Optionally, the read-write control circuit is configured as:

[0014] receiving a first operation instruction, and determining that the first operation instruction is a write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit;

[0015] receiving a second operation instruction, and determining that the second operation instruction is a read operation, and if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to obtain data required by the second operation instruction and writing it back;

[0016] After the second operation instruction is executed, if there is no read operation to be executed, the suspended first operation instruction is executed, and the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

[0017] Optionally, the read-write control circuit is configured as:

[0018] receiving a third operation instruction, and determining that the third operation instruction is a read operation, executing the third operation instruction to obtain data required by the third operation instruction and writing it back;

[0019] receiving a fourth operation instruction, and determining that the fourth operation instruction is a write operation, and then executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit after the third operation instruction is executed;

[0020] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0021] Optionally, the read-write control circuit is further configured as:

[0022] receiving a fifth operation instruction, and determining that the fifth operation instruction is a write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;

[0023] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0024] Optionally, the read-write control circuit is further configured as:

[0025] When performing an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit, taking the data currently stored in the first-level write cache unit as the first data, and if the second-level write cache unit currently stores the second data, determining whether a write address corresponding to the first data and a write address corresponding to the second data satisfy an adjacent condition, wherein the adjacent condition refers to that storage locations in the memory are adjacent;

[0026] If the adjacent condition is met, writing the first data and the second data into the memory;

[0027] If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit.

[0028] Optionally, the read-write control circuit is further configured as:

[0029] When the bus is idle, the data currently stored in the cache module is written into the memory.

[0030] Optionally, the read-write control circuit is configured as:

[0031] When the cache module contains data required for the read operation, obtaining the required data from the cache module;

[0032] When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

[0033] Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

[0034] The read-write control circuit is configured as follows:

[0035] For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write cache unit, if they are the same, obtain the data of the current read operation from the first-level write cache unit; if they are not the same, enter the following determination for the second-level write cache unit;

[0036] For the second-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit; if they are the same, obtain the data of the current read operation from the second-level write cache unit.

[0037] Optionally, the cache module further includes a read cache unit;

[0038] The read-write control circuit is further configured as:

[0039] After determining whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, entering the following determination on the read cache unit;

[0040] For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit. If they are the same, obtain the data of the current read operation from the read cache unit; if they are not the same, read the required data from the memory.

[0041] Optionally, the cache module further includes a read cache unit;

[0042] The read-write control circuit is further configured as:

[0043] Based on a read address corresponding to a current read operation, reading data of the read address and its adjacent storage locations from the memory;

[0044] The data at the read address is written back as data required for the current read operation, and the data at the adjacent storage location is written into the read cache unit.

[0045] Optionally, the cache module includes a first-level write cache unit, a second-level write cache unit and a read cache unit, and the read-write control circuit also includes a first data selector, a second data selector, a third data selector, a fourth data selector and a write data selection control circuit;

[0046] The input end of the first-level write cache unit is connected to the bus, and the output end is respectively connected to the input end of the first data selector and the input end of the second data selector;

[0047] The input end of the second-level write cache unit is connected to the output end of the first data selector, and the output end is respectively connected to the input end of the write data selection control circuit and the input end of the third data selector;

[0048] The input end of the read cache unit is connected to the memory, and the output end is connected to the input end of the fourth data selector;

[0049] The input end of the first data selector is also connected to the bus, and the output end is also connected to the write data selection control circuit;

[0050] The input end of the second data selector is also connected to the output end of the third data selector, and the output end is connected to the bus;

[0051] The input end of the third data selector is also connected to the output end of the fourth data selector;

[0052] The input terminal of the fourth data selector is also connected to the memory;

[0053] The output end of the write data selection control circuit is also connected to the memory.

[0054] According to another aspect of the present application, a control method of a read-write control circuit is provided, wherein the read-write control circuit includes a cache module;

[0055] The method comprises:

[0056] When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module;

[0057] The data corresponding to the write operation is written into the memory from the cache module.

[0058] According to another aspect of the present application, a chip is provided, comprising the above-mentioned read-write control circuit.

[0059] According to another aspect of the present application, an electronic device is provided, comprising the above-mentioned read-write control circuit.

[0060] In the present application, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written to the memory, eliminating the waiting time of the read operation when the write operation comes first, and improving the system access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0062] Figure 1 A schematic diagram of a read-write control circuit provided according to an exemplary embodiment of the present application is shown;

[0063] Figure 2 A schematic diagram of a cache module provided according to an exemplary embodiment of the present application is shown;

[0064] Figure 3 A schematic diagram of a cache module provided according to an exemplary embodiment of the present application is shown;

[0065] Figure 4 A schematic diagram of a cache module provided according to an exemplary embodiment of the present application is shown;

[0066] Figure 5 A schematic diagram of a read-write control circuit provided according to an exemplary embodiment of the present application is shown;

[0067] Figure 6 shows a system timing diagram when the read-write control circuit provided by the present application is not used;

[0068] Figure 7 The system timing diagram after adopting the read-write control circuit provided by the present application is shown;

[0069] Figure 8shows a system timing diagram when the read-write control circuit provided by the present application is not used;

[0070] Fig. 9 The system timing diagram after adopting the read-write control circuit provided by the present application is shown;

[0071] Fig.10 A flow chart of a control method of a read-write control circuit provided according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0072] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be construed as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not intended to limit the scope of protection of the present application.

[0073] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0074] It should be noted that the modifications of "one" and "plurality" mentioned in the present application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0075] The names of the messages or information exchanged between multiple devices in the embodiments of the present application are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0076] An embodiment of the present application provides a read-write control circuit, which can be integrated in a chip or set in an electronic device.

[0077] Reference Figure 1 The schematic diagram of the read-write control circuit shown in the figure may include a cache module.

[0078] The read / write control circuit can be configured as:

[0079] When there are continuous read and write operations, the read operation is performed and the data corresponding to the write operation is stored in the cache module;

[0080] The data corresponding to the write operation is written into the memory from the cache module.

[0081] In a possible implementation, the read / write control circuit may be arranged between the bus and the memory to transmit data between the two. Specifically, the bus may refer to an AHB bus, and the memory may refer to an SRAM. As an example, the read / write control circuit may be applied to a 32-bit MCU (Microcontroller Unit) design, and each address of the SRAM stores 64 bits of data.

[0082] When the bus issues continuous read and write operations, the read and write control circuit can be configured to first perform a read operation to read the data required for the read operation, and then perform a write operation to store the data corresponding to the write operation in the cache module and write the data of the write operation into the memory.

[0083] When there are continuous read and write operations, especially continuous write + read operations, the waiting time of the read operation when the write operation comes first is eliminated, thereby improving the system access efficiency.

[0084] The following will introduce the write operation related configuration of the read-write control circuit.

[0085] Reference Figure 2 The schematic diagram of the cache module shown in FIG. 1 shows that the cache module may include a first-level write cache unit and a second-level write cache unit. As an example, the data stored in the first-level write cache unit and the second-level write cache unit may be 32 bits.

[0086] On this basis, the read-write control circuit can be configured as:

[0087] When there is a write operation, the data corresponding to the write operation is stored in the first-level write cache unit;

[0088] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0089] In one possible implementation, whenever the bus issues a write operation, the data corresponding to the write operation is first stored in the first-level write cache unit, and when the bus is in the next non-read address phase (that is, there is no read operation to be executed), the data of the first-level write cache unit is written to the second-level write cache unit. In other words, if the next clock cycle of the write address phase in the bus is the read address phase (that is, triggering a read operation), the write operation is temporarily suspended, and the SRAM is read first. When the bus has no read address phase, the suspended write operation is executed, that is, written to the second-level write cache unit. As an example, refer to Figure 6 When HWRITE is high and HADDR has an address phase, it indicates that the AHB bus issues a write operation, and the address phase at this time is the write address phase; when HWRITE is low and HADDR has an address phase, it indicates that the AHB bus issues a read operation, and the address phase at this time is the read address phase.

[0090] Optionally, after the data of the first-level write cache unit is written into the second-level write cache unit, the first-level write cache unit may be cleared.

[0091] The following will introduce each situation of triggering operation.

[0092] Case 1: Triggering continuous write + read operations, that is, the write operation comes first and the read operation comes later.

[0093] In this case, the read / write control circuit can be configured as:

[0094] receiving a first operation instruction, and determining that the first operation instruction is a write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in a first-level write cache unit;

[0095] receiving a second operation instruction, and determining that the second operation instruction is a read operation, and if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to obtain data required by the second operation instruction and writing it back;

[0096] After the second operation instruction is executed, if there is no read operation to be executed, the suspended first operation instruction is executed, and the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

[0097] In a possible implementation, in the first clock cycle, if a first operation instruction corresponding to a write operation is triggered in the bus, the first operation instruction can be received and the instruction type can be determined to be a write operation, and then the read-write control circuit can execute the write operation and store the data corresponding to the write operation in the first-level write cache unit. In the following second clock cycle, if a second operation instruction corresponding to a read operation is triggered in the bus, the second operation instruction can be received and the instruction type can be determined to be a write operation, and then the read-write control circuit can suspend the above-mentioned write operation, execute the read operation, obtain the data required for the read operation and write it back as the result of the second operation instruction. In the following third clock cycle, if another write operation is triggered in the bus or no operation is triggered, and there is no read address phase in the bus at this time, the read-write control circuit can execute the suspended write operation, that is, execute the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.

[0098] In addition, in the third clock cycle, if another read operation is triggered in the bus, there is still a conflict between the read operation and the suspended write operation in accessing the memory (i.e., there is a waiting time for the read operation when the write operation is in the front), which still meets the above situation 1. At this time, the write operation can continue to be suspended until there is no read operation to be executed in the bus, and then the operation of writing the data currently stored in the first-level write cache unit to the second-level write cache unit is executed.

[0099] Case 2: Triggering continuous read + write operations, that is, the read operation comes first and the write operation comes later.

[0100] In this case, the read / write control circuit can be configured as:

[0101] receiving a third operation instruction, and determining that the third operation instruction is a read operation, executing the third operation instruction to obtain data required by the third operation instruction and writing it back;

[0102] receiving a fourth operation instruction, and determining that the fourth operation instruction is a write operation, and then executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit after the third operation instruction is executed;

[0103] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0104] In a possible implementation, in the first clock cycle, a third operation instruction corresponding to a read operation is triggered in the bus, and the third operation instruction can be received and the instruction type is determined to be a read operation, and then the read-write control circuit can execute the read operation, obtain the data required for the read operation and write it back as the result of the third operation instruction. In the following second clock cycle, a fourth operation instruction corresponding to a write operation is triggered in the bus, and the fourth operation instruction can be received and the instruction type is determined to be a write operation, and it is determined whether the above-mentioned read operation is completed. After the above-mentioned read operation is completed, the read-write control circuit can execute the write operation corresponding to the fourth operation instruction, and store the data corresponding to the write operation into the first-level write cache unit. In the following third clock cycle, if another write operation is triggered in the bus or no operation is triggered, and there is no read address phase in the bus at this time, the read-write control circuit can execute the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit.

[0105] Similarly, in the third clock cycle, if another read operation is triggered in the bus, there is a conflict in accessing the memory between the read operation and the write operation corresponding to the fourth operation instruction (i.e., there is a waiting time for the read operation when the write operation is in the front), which meets the above situation 1. At this time, the write operation can be suspended until there is no read operation to be executed in the bus, and then the operation of writing the data currently stored in the first-level write cache unit to the second-level write cache unit is executed.

[0106] Case 3: Triggering continuous write+write operations or a single write operation.

[0107] In this case, the read / write control circuit can be configured as:

[0108] receiving a fifth operation instruction, and determining that the fifth operation instruction is a write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in a first-level write cache unit;

[0109] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0110] In a possible implementation, in the first clock cycle, the fifth operation instruction corresponding to the write operation is triggered in the bus, then the fifth operation instruction can be received and the instruction type can be determined to be a write operation, and then the read-write control circuit can execute the write operation and store the data corresponding to the write operation in the first-level write cache unit. In the following second clock cycle, the sixth operation instruction corresponding to another write operation is triggered in the bus or no operation is triggered (that is, there is no read operation to be executed), then the read-write control circuit can execute the operation of writing the data currently stored in the first-level write cache unit to the second-level write cache unit. Thereafter, corresponding to the situation where the sixth operation instruction is received, the read-write control circuit can also clear the first-level write cache unit and store the data corresponding to the write operation of the sixth operation instruction in the first-level write cache unit.

[0111] Optionally, the specific processing of the above-mentioned operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit may be as follows:

[0112] Using the data currently stored in the first-level write cache unit as the first data, determining whether the second-level write cache unit stores the second data;

[0113] If the second-level write cache unit currently stores the second data, determine whether the write address corresponding to the first data and the write address corresponding to the second data meet an adjacent condition, where the adjacent condition means that the storage positions in the memory are adjacent; if the adjacent condition is met, write the first data and the second data into the memory; if the adjacent condition is not met, write the second data into the memory and write the first data into the second-level write cache unit;

[0114] If the second-level write cache unit does not currently store the second data, the data currently stored in the first-level write cache unit is written into the second-level write cache unit. At this time, the data stored in the second-level write cache unit can be used as the second data when the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed next time.

[0115] As an example, the addresses of the read and write operations initiated by the AHB bus can be 0xXXXX_XXX0, 0xXXXX_XXX4, 0xXXXX_XXX8, and 0xXXXX_XXXC, each address corresponds to 32 bits of data, where 0xXXXX_XXX0 and 0xXXXX_XXX4 are adjacent, and 0xXXXX_XXX8 and 0xXXXX_XXXC are adjacent. Two adjacent addresses can be addressed to the same physical address in SRAM (bit width is 64 bits), and the 64 bits of data corresponding to the two adjacent addresses are stored in the same physical address addressed, that is, the adjacent condition is met.

[0116] Whenever data needs to be written into the second-level write cache unit, the cache empty and full flag can be used to determine whether the second-level write cache unit is full. If the cache is full, writing is not possible. At this time, it can be determined whether the address of the current data to be written (i.e., the first data) and the address of the data cached in the second-level write cache unit (i.e., the second data) meet the above-mentioned adjacent condition.

[0117] If it is satisfied, it indicates that the corresponding location can be accessed by addressing once in the SRAM and the 64-bit data can be written into the SRAM.

[0118] If not satisfied, the 32-bit data cached in the second-level write cache unit is written into the SRAM, and the 32-bit data to be written is written into the second-level write cache unit, waiting for another 32-bit data adjacent to it to be written into the SRAM together.

[0119] Through the above configuration, the second-level write cache unit can be used to cache data waiting for adjacent addresses. When data of two adjacent addresses are written twice in succession, the data of the two addresses can be written into the memory at the same time, reducing the number of times the memory is accessed, thereby reducing system power consumption.

[0120] After that, the data can be written to the memory when the bus is idle. On this basis, the read-write control circuit can also be configured to write the data currently stored in the cache module to the memory when the bus is idle. Optionally, after the data is written to the memory, the corresponding data in the cache module can be deleted, that is, the cache module is cleared.

[0121] Through the above configuration, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written to the memory, eliminating the waiting time of the read operation when the write operation comes first, and improving the system access efficiency.

[0122] The following will introduce the read operation related configuration of the read and write control circuit.

[0123] For read operations, the read / write control circuit can be configured as:

[0124] When the data required for the read operation exists in the cache module, the required data is obtained from the cache module;

[0125] When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

[0126] In a possible implementation, it can be determined whether the data is required for the read operation based on the address of the read operation and the address of the data cached in the cache module. If there is data with the same address as the read operation in the cache module, indicating that the data is the data required for the read operation, the data can be obtained from the cache module as the result of the read operation and written back. If not, the memory can be accessed to read the data required for the read operation and write it back.

[0127] Through the above configuration, the number of times the memory is accessed can also be reduced, thereby reducing system power consumption.

[0128] Optionally, when the cache module includes a first-level write cache unit and a second-level write cache unit, the read-write control circuit may be configured as follows:

[0129] For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write cache unit. If they are the same, obtain the data of the current read operation from the first-level write cache unit; if they are not the same, enter the following determination for the second-level write cache unit;

[0130] For the second-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit. If they are the same, obtain the data of the current read operation from the second-level write cache unit.

[0131] That is to say, it can be determined in sequence whether the first-level write cache unit and the second-level write cache unit store data required for the read operation. If yes, the data for the read operation comes from the corresponding write cache unit.

[0132] If the required data is still not found in the second-level write cache unit, the required data can be read from the memory, or the search can be continued using the technical solution provided below.

[0133] In order to further reduce the power consumption of the system, similar to the technical solution of writing the data of two adjacent addresses at the same time in the above text, the data of two adjacent addresses can also be read out at the same time through the cache module, and after the data required for the read operation is taken away, the data of the adjacent storage location is written into the cache module. When judging whether there is the data required for the read operation in the cache module, it is also possible to judge whether the data required for the current read operation is read out at the same time by judging whether the previous read operation reads out the data required for the current read operation, so as to judge whether it is the required data.

[0134] On this basis, as an optional solution, refer to Figure 3 As shown in the schematic diagram of the cache module, the cache module may further include a read cache unit, which may be used to store the data of the adjacent storage locations. As an example, the data stored in the read cache unit may be 32 bits.

[0135] When the read cache unit is combined with the first-level write cache unit and the second-level write cache unit, as shown in FIG. Figure 4 As shown. On this basis, the read-write control circuit can also be configured as:

[0136] After determining whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, proceed to the following determination of the read cache unit;

[0137] For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit. If they are the same, obtain the data of the current read operation from the read cache unit; if they are not the same, read the required data from the memory.

[0138] That is to say, it can be determined in sequence whether the first-level write cache unit, the second-level write cache unit and the read cache unit store data required for the read operation. If so, the data for the read operation comes from the corresponding cache unit.

[0139] Among them, the process of judging whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit, can also be achieved by judging whether the read address corresponding to the current read operation and the read address corresponding to the previous read operation satisfy the above-mentioned adjacent conditions. If so, it indicates that the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit.

[0140] Thereafter, if the required data is still not found, the required data may be read from the memory.

[0141] When data needs to be read from the memory, the read / write control circuit can be configured as follows:

[0142] Based on the read address corresponding to the current read operation, read the data of the read address and its adjacent storage locations from the memory;

[0143] After the data at the read address is written back as the data required for the current read operation, the data at the adjacent storage location is written into the read cache unit.

[0144] As a specific example, see Figure 5 A schematic diagram of a read-write control circuit is shown, and the read-write control circuit can be specifically composed of a first-level write cache unit, a second-level write cache unit, a read cache unit, a first data selector, a second data selector, a third data selector, a fourth data selector and a write data selection control circuit, wherein the first-level write cache unit, the second-level write cache unit and the read cache unit can correspond to the above-mentioned cache module, and the configuration of the above-mentioned read-write control circuit can be implemented by the first data selector, the second data selector, the third data selector, the fourth data selector and the write data selection control circuit.

[0145] The input end of the first-level write cache unit can be connected to the AHB bus, and the output end is connected to the first data selector and the second data selector respectively.

[0146] The input end of the second-level write cache unit can be connected to the first data selector, and the output end is connected to the write data selection control circuit and the third data selector respectively.

[0147] An input terminal of the read cache unit may be connected to the SRAM, and an output terminal thereof may be connected to the fourth data selector.

[0148] The input end of the first data selector can be connected to the AHB bus and the first-level write cache unit respectively, and the output end is connected to the second-level write cache unit and the write data selection control circuit respectively.

[0149] The input end of the second data selector can be connected to the first-level write cache unit and the third data selector respectively, and the output end is connected to the AHB bus.

[0150] The input end of the third data selector can be connected to the second-level write cache unit and the fourth data selector respectively, and the output end is connected to the second data selector.

[0151] The input end of the fourth data selector can be connected to the SRAM and the read cache unit respectively, and the output end is connected to the third data selector.

[0152] The input end of the write data selection control circuit can be connected to the first data selector and the second-level write cache unit respectively, and the output end is connected to the SRAM.

[0153] The embodiments of the present application can achieve the following beneficial effects:

[0154] (1) When there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written to the memory, eliminating the waiting time of the read operation when the write operation comes first, thereby improving the system access efficiency.

[0155] Figure 6 The system timing diagram when the read / write control circuit provided by the present application is not used is shown, wherein when HWRITE is at a high level and HADDR has an address phase, it indicates that the AHB bus issues a write operation, and when HWRITE is at a low level and HADDR has an address phase, it indicates that the AHB bus issues a read operation. Figure 6The write operation and the read operation are continuous, and the write operation comes first. From the timing diagram, we can see that the SRAM first triggers the write operation WR, and then triggers the read operation RD. However, since it takes time for SRAM to write, HREADYOUT is low when the read operation RD is triggered, indicating that the data is not ready to be read (the shaded part in HRDATA indicates that the read operation reads the data after one beat (indicated by RDATA in HRDATA, RDATA is not read in the next beat of RD).

[0156] Figure 7 A system timing diagram after adopting the read-write control circuit provided by the present application is shown, wherein the SRAM first triggers the read operation RD and then triggers the write operation WR, and RDATA can be read out in the next beat of RD, eliminating the time waiting for the write operation WR to be written.

[0157] (2) When the data of two adjacent addresses are written twice in succession, the data of the two addresses can be written into the memory at the same time, and / or, the data of two adjacent addresses can be read out at the same time. When the data of two adjacent addresses are read twice in succession, the data can be obtained from the cache module, thereby reducing the number of times the memory is accessed, thereby reducing system power consumption.

[0158] Figure 8 A system timing diagram is shown when the read-write control circuit provided by the present application is not used, wherein addr0 and addr1 are two adjacent write addresses, and addr2 and addr3 are two adjacent read addresses. It can be seen that each AHB bus read and write will trigger SRAM read and write (each WR corresponds to a write address, and each RD corresponds to a read address), and the system power consumption is relatively high.

[0159] Fig. 9 The system timing diagram after adopting the read-write control circuit provided by the present application is shown, in which it can be seen that the two read operations / write operations of the AHB bus only trigger one read operation / write operation of the SRAM (addr0 and addr1 trigger one WR, addr2 and addr3 trigger one RD), reducing the system power consumption.

[0160] The present application also provides a control method for a read-write control circuit, which can be used to control the above-mentioned read-write control circuit, wherein the read-write control circuit includes a cache module. Fig.10 The control method flow chart of the read-write control circuit shown in FIG. 1 may include the following steps 1001-1002:

[0161] Step 1001, when there are continuous read and write operations, execute the read operation, and store the data corresponding to the write operation in the cache module;

[0162] Step 1002: Write the data corresponding to the write operation from the cache module into the memory.

[0163] Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

[0164] The storing the data corresponding to the write operation in the cache module includes:

[0165] When there is a write operation, storing data corresponding to the write operation in the first-level write cache unit;

[0166] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0167] Optionally, when there are continuous read and write operations, executing the read operation and storing the data corresponding to the write operation in the cache module includes:

[0168] receiving a first operation instruction, and determining that the first operation instruction is a write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit;

[0169] receiving a second operation instruction, and determining that the second operation instruction is a read operation, and if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to obtain data required by the second operation instruction and writing it back;

[0170] After the second operation instruction is executed, if there is no read operation to be executed, the suspended first operation instruction is executed, and the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

[0171] Optionally, when there are continuous read and write operations, executing the read operation and storing the data corresponding to the write operation in the cache module includes:

[0172] receiving a third operation instruction, and determining that the third operation instruction is a read operation, executing the third operation instruction to obtain data required by the third operation instruction and writing it back;

[0173] receiving a fourth operation instruction, and determining that the fourth operation instruction is a write operation, and then executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit after the third operation instruction is executed;

[0174] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0175] Optionally, the method further includes:

[0176] receiving a fifth operation instruction, and determining that the fifth operation instruction is a write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit;

[0177] If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

[0178] Optionally, the performing of the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit includes:

[0179] The data currently stored in the first-level write cache unit is taken as the first data, and if the second-level write cache unit currently stores the second data, it is determined whether the write address corresponding to the first data and the write address corresponding to the second data meet an adjacent condition, wherein the adjacent condition refers to that the storage positions in the memory are adjacent;

[0180] If the adjacent condition is met, writing the first data and the second data into the memory;

[0181] If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit.

[0182] Optionally, the method further includes:

[0183] When the bus is idle, the data currently stored in the cache module is written into the memory.

[0184] Optionally, the performing a read operation includes:

[0185] When the cache module contains data required for the read operation, obtaining the required data from the cache module;

[0186] When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

[0187] Optionally, the cache module includes a first-level write cache unit and a second-level write cache unit;

[0188] When the data required for the read operation exists in the cache module, obtaining the required data from the cache module includes:

[0189] For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write cache unit, if they are the same, obtain the data of the current read operation from the first-level write cache unit; if they are not the same, enter the following determination for the second-level write cache unit;

[0190] For the second-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit; if they are the same, obtain the data of the current read operation from the second-level write cache unit.

[0191] Optionally, the cache module further includes a read cache unit;

[0192] The method further comprises:

[0193] After determining whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, entering the following determination on the read cache unit;

[0194] For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit. If they are the same, obtain the data of the current read operation from the read cache unit; if they are not the same, read the required data from the memory.

[0195] Optionally, the method further includes:

[0196] Based on a read address corresponding to a current read operation, reading data of the read address and its adjacent storage locations from the memory;

[0197] The data at the read address is written back as data required for the current read operation, and the data at the adjacent storage location is written into the read cache unit.

[0198] In an embodiment of the present application, when there are continuous read and write operations, the data of the write operation can be cached in the cache module, and the data of the read operation is read first, and then the data of the write operation is written to the memory, eliminating the waiting time of the read operation when the write operation comes first, thereby improving the system access efficiency.

[0199] The embodiment of the present application also provides a chip, including the read-write control circuit provided in the embodiment of the present application. The chip may be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. The chip is configured with the above-mentioned read-write control circuit to improve the system access efficiency.

[0200] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above that is provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights. The electronic device improves the access efficiency of the electronic device system by configuring the above-mentioned read-write control circuit.

[0201] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A read-write control circuit, characterized in that: The read-write control circuit includes a cache module, and the cache module includes a first-level write cache unit and a second-level write cache unit; the second-level write cache unit is used to cache data waiting for adjacent addresses; The read-write control circuit is configured as follows: When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module; Writing the data corresponding to the write operation from the cache module into the memory includes: when the data of two adjacent addresses are written twice in succession, writing the data of the two addresses into the memory together.

2. The read-write control circuit according to claim 1, characterized in that: The read-write control circuit is configured as follows: When there is a write operation, storing data corresponding to the write operation in the first-level write cache unit; If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

3. The read-write control circuit according to claim 2, characterized in that: The read-write control circuit is configured as follows: receiving a first operation instruction, and determining that the first operation instruction is a write operation, executing the first operation instruction and storing data corresponding to the first operation instruction in the first-level write cache unit; receiving a second operation instruction, and determining that the second operation instruction is a read operation, and if the first operation instruction is in an execution state, suspending the first operation instruction, executing the second operation instruction to obtain data required by the second operation instruction and writing it back; After the second operation instruction is executed, if there is no read operation to be executed, the suspended first operation instruction is executed, and the operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is performed.

4. The read-write control circuit according to claim 2, characterized in that: The read-write control circuit is configured as follows: receiving a third operation instruction, and determining that the third operation instruction is a read operation, executing the third operation instruction to obtain data required by the third operation instruction and writing it back; receiving a fourth operation instruction, and determining that the fourth operation instruction is a write operation, and then executing the fourth operation instruction and storing data corresponding to the fourth operation instruction in the first-level write cache unit after the third operation instruction is executed; If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

5. The read-write control circuit according to claim 2, characterized in that: The read-write control circuit is further configured as: receiving a fifth operation instruction, and determining that the fifth operation instruction is a write operation, executing the fifth operation instruction and storing data corresponding to the fifth operation instruction in the first-level write cache unit; If there is no read operation to be executed currently, an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit is executed.

6. The read-write control circuit according to any one of claims 2 to 5, characterized in that: The read-write control circuit is further configured as: When performing an operation of writing the data currently stored in the first-level write cache unit into the second-level write cache unit, taking the data currently stored in the first-level write cache unit as the first data, and if the second-level write cache unit currently stores the second data, determining whether a write address corresponding to the first data and a write address corresponding to the second data satisfy an adjacent condition, wherein the adjacent condition refers to that storage locations in the memory are adjacent; If the adjacent condition is met, writing the first data and the second data into the memory; If the adjacent condition is not satisfied, the second data is written into the memory, and the first data is written into the second-level write cache unit.

7. The read-write control circuit according to claim 1, characterized in that: The read-write control circuit is further configured as: When the bus is idle, the data currently stored in the cache module is written into the memory.

8. The read-write control circuit according to claim 1, characterized in that: The read-write control circuit is configured as follows: When the cache module contains data required for the read operation, obtaining the required data from the cache module; When the data required for the read operation does not exist in the cache module, the required data is read from the memory.

9. The read-write control circuit according to claim 8, characterized in that: The read-write control circuit is configured as follows: For the first-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the first-level write cache unit, if they are the same, obtain the data of the current read operation from the first-level write cache unit; if they are not the same, enter the following determination for the second-level write cache unit; For the second-level write cache unit: determine whether the read address corresponding to the current read operation is the same as the write address corresponding to the data of the second-level write cache unit; if they are the same, obtain the data of the current read operation from the second-level write cache unit.

10. The read-write control circuit according to claim 9, characterized in that: The cache module also includes a read cache unit; The read-write control circuit is further configured as: After determining whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the second-level write cache unit, if they are not the same, entering the following determination on the read cache unit; For the read cache unit: determine whether the read address corresponding to the current read operation is the same as the address corresponding to the data of the read cache unit. If they are the same, obtain the data of the current read operation from the read cache unit; if they are not the same, read the required data from the memory.

11. The read-write control circuit according to claim 8, characterized in that: The cache module also includes a read cache unit; The read-write control circuit is further configured as: Based on a read address corresponding to a current read operation, reading data of the read address and its adjacent storage locations from the memory; The data at the read address is written back as data required for the current read operation, and the data at the adjacent storage location is written into the read cache unit.

12. The read-write control circuit according to claim 1, characterized in that: The cache module further includes a read cache unit, and the read-write control circuit further includes a first data selector, a second data selector, a third data selector, a fourth data selector and a write data selection control circuit; The input end of the first-level write cache unit is connected to the bus, and the output end is respectively connected to the input end of the first data selector and the input end of the second data selector; The input end of the second-level write cache unit is connected to the output end of the first data selector, and the output end is respectively connected to the input end of the write data selection control circuit and the input end of the third data selector; The input end of the read cache unit is connected to the memory, and the output end is connected to the input end of the fourth data selector; The input end of the first data selector is also connected to the bus, and the output end is also connected to the write data selection control circuit; The input end of the second data selector is also connected to the output end of the third data selector, and the output end is connected to the bus; The input end of the third data selector is also connected to the output end of the fourth data selector; The input terminal of the fourth data selector is also connected to the memory; The output end of the write data selection control circuit is also connected to the memory.

13. A control method for a read-write control circuit, characterized in that: The read-write control circuit is a read-write control circuit as claimed in any one of claims 1 to 12; The method comprises: When there are continuous read and write operations, the read operation is performed, and the data corresponding to the write operation is stored in the cache module; The data corresponding to the write operation is written into the memory from the cache module.

14. A chip, characterized in that: The method comprises a read-write control circuit as claimed in any one of claims 1 to 12.

15. An electronic device, characterized in that: The method comprises a read-write control circuit as claimed in any one of claims 1 to 12.

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