Non-volatile storage device

Abstract

Embodiments provide a nonvolatile storage device including an architecture having a highly integrable three-dimensional structure. The nonvolatile storage device of an embodiment includes: a first wiring extending in a first direction; a second wiring extending in a second direction intersecting the first direction; a storage unit disposed between a first layer and a second layer and having first and second terminals, the storage unit including a variable resistance element; a first drive circuit capable of supplying a first potential and a second potential lower than the first potential; a second drive circuit supplying a third potential having a polarity different from a polarity of the first potential; a third drive circuit capable of supplying the second potential and a fourth potential higher than the second potential; a fourth drive circuit supplying a fifth potential having a polarity different from the polarity of the first potential; and a control circuit electrically connected to the first to fourth drive circuits.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims the priority of Japanese Patent Application No. 2021-036568, filed March 8, 2021, and U.S. Patent Application No. 17 / 475822, filed September 15, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to non-volatile storage devices. Background Technology

[0004] For example, a known non-volatile memory device can be a magnetoresistive random access memory (MRAM) comprising memory cells, each memory cell including a magnetic tunnel junction (MTJ) element. For such a non-volatile memory device, consider an architecture with a three-dimensional structure. Typically, in a non-volatile memory device with this architecture, circuitry (also referred to below the array circuitry (CUA)) driving these memory cells is provided beneath the array of memory cells in which the memory cells are arranged. Summary of the Invention

[0005] An embodiment provides a non-volatile storage device comprising an architecture with a highly integrated three-dimensional structure.

[0006] A non-volatile storage device according to an embodiment includes: a first wiring disposed in a first layer and extending in a first direction; a second wiring disposed in a second layer above the first layer and extending in a second direction intersecting the first direction; a storage cell disposed in a third layer located between the first and second layers and having a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring, the storage cell including a variable resistance element having a resistance that varies as a write current flows from one of the first and second terminals to the other; a first drive circuit electrically connected to one end of the first wiring and capable of supplying a first potential and a second potential lower than the first potential; a second drive circuit electrically connected to the other end of the first wiring and supplying a third potential with a polarity different from the first potential; a third drive circuit electrically connected to one end of the second wiring and capable of supplying the second potential and a fourth potential higher than the second potential; a fourth drive circuit electrically connected to the other end of the second wiring and supplying a fifth potential with a polarity different from the first potential; and a control circuit electrically connected to the first to fourth drive circuits. Attached Figure Description

[0007] Figure 1 This is a circuit diagram showing a non-volatile storage device according to a first embodiment;

[0008] Figure 2A This is a cross-sectional view showing a non-volatile storage device according to a first embodiment;

[0009] Figure 2B This is a cross-sectional view showing a non-volatile storage device according to a first embodiment;

[0010] Figure 2C This is a bird's-eye view of the storage array according to the first embodiment;

[0011] Figure 3A This is a diagram illustrating the configuration of the storage cells of a non-volatile storage device according to a first embodiment;

[0012] Figure 3B This is a cross-sectional view showing the storage element of a non-volatile storage device according to a first embodiment;

[0013] Figure 4A and Figure 4B This is a diagram illustrating a first example of a write operation of a non-volatile storage device according to a first embodiment;

[0014] Figure 5A and Figure 5B This is a diagram illustrating a second example of a write operation of a non-volatile storage device according to the first embodiment;

[0015] Figure 6 This is a circuit diagram showing a comparative example of a non-volatile memory device;

[0016] Figure 7 This is a cross-sectional view showing a non-volatile storage device according to a second embodiment;

[0017] Figure 8 This is a cross-sectional view showing a non-volatile storage device according to a second embodiment;

[0018] Figure 9 This is a cross-sectional view showing a non-volatile storage device according to a third embodiment; and

[0019] Figure 10 This is a cross-sectional view showing a non-volatile storage device according to a third embodiment. Detailed Implementation

[0020] The following is a description of a non-volatile storage device according to an embodiment of the present invention with reference to the accompanying drawings.

[0021] (First Embodiment)

[0022] Figure 1A non-volatile memory device (hereinafter also simply referred to as a memory device) according to a first embodiment is shown. The memory device includes a memory cell array 100, driving circuits 210, 220, 230 and 240, and control circuitry 300. The memory cell array 100 includes word lines WL1, WL2, WL3 and WL4, bit lines BL1, BL2, BL3 and BL4 intersecting these word lines respectively, and on word lines WL... i (i = 1, ..., 4) and bit line BL j Storage unit 11 provided in the intersecting region of (j=1,…,4) ij Storage unit 11 ij (i,j = 1,...,4) has a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line WL. i The second terminal is electrically connected to the corresponding bit line BL. j Note that in this embodiment, the memory cell array 100 includes four word lines WL1 to WL4, four bit lines BL1 to BL4, and 4×4 memory cells 11. 11 Up to 11 44 However, when m and n are natural numbers, the memory cell array 100 may include m word lines WL1 to WL2. m n bit lines BL1 to BL n and mn storage units 11 provided in its intersection region. 11 Up to 11 mn .

[0023] Word line WL i (i = 1, ..., 4) are set in the first layer and arranged to extend in the first direction (x direction), bit line BL j (j = 1, ..., 4) are located in the third layer above the first layer and are arranged to extend in the second direction (y direction) intersecting the first direction, storage unit 11 ij (i,j=1,...,4) are located in a second layer between the first and third layers, and are arranged to extend in a third direction (z direction) intersecting the first direction (x direction) and the second direction (y direction). Drive circuits 210, 220, 230, and 240, as well as control circuit 300, are located in a layer lower than the first layer in which word lines WL1 to WL4 are located. Note that drive circuits 210, 220, 230, and 240 are controlled by control circuit 300.

[0024] Figure 2A It shows along with Figure 1 The cross-section of the storage device of the first embodiment is obtained by the xz plane parallel to the word line WL2 shown. Figure 2BA cross-section obtained along the yz plane parallel to the bit line BL2 is shown. Figure 2C A bird's-eye view of the storage cell array 100 of the storage device according to the first embodiment is shown. (See also...) Figures 2A to 2C As can be seen, the storage device of the first embodiment includes an architecture with a three-dimensional structure.

[0025] Word line WL i One end of (i = 1, ..., 4) is electrically connected to drive circuit 210, and the other end is electrically connected to drive circuit 220. Bit line BL j One end of (j=1,...,4) is electrically connected to drive circuit 230, and the other end is electrically connected to drive circuit 240. In this document, "A is electrically connected to B" means that A can be directly connected to B or A can be indirectly connected to B via an electrical conductor.

[0026] The driver circuit 210 includes a driver for each word line WL i (i = 1, ..., 4) provide and connect in series a p-channel transistor 212 and an n-channel transistor 214. The source of the p-channel transistor 212 is electrically connected to a power supply at a supply potential VDD (e.g., a positive potential). The source of the n-channel transistor 214 is electrically connected to a power supply at a supply potential VSS (e.g., 0V) (also indicated as VSS). The drains of the p-channel transistor 212 and the n-channel transistor 214 are electrically connected to the corresponding word line WL. i One end of (i = 1, ..., 4). The gate of p-channel transistor 212 and the gate of n-channel transistor 214 receive control signals from control circuit 300.

[0027] The driver circuit 220 includes a driver for each word line WL i (i = 1, ..., 4) provides an n-channel transistor 222. The source of the n-channel transistor 222 is electrically connected to a power supply (also indicated as VNN) with a supply potential VNN (= -VDD), and the drain is electrically connected to the corresponding word line WL. i The other end of (i = 1, ..., 4) and the gate receives control signals from the control circuit 300.

[0028] The driver circuit 230 includes a driver for each bit line BL. j (j = 1, ..., 4) provides a p-channel transistor 232 and an n-channel transistor 234 connected in series. The source of the p-channel transistor 232 is electrically connected to the power supply VDD. The source of the n-channel transistor 234 is electrically connected to the power supply VSS (0V). The drains of the p-channel transistor 232 and the n-channel transistor 234 are electrically connected to the corresponding bit line BL. jOne end of (j=1,...,4). The gates of p-channel transistor 232 and n-channel transistor 234 receive signals from control circuit 300.

[0029] The driver circuit 240 includes a driver for each bit line BL. j (j = 1, ..., 4) provides an n-channel transistor 242. The source of the n-channel transistor 242 is electrically connected to the power supply VNN (= -VDD), and the drain is electrically connected to the corresponding bit line BL. i The other end of (i = 1, ..., 4) and the gate receives control signals from the control circuit 300.

[0030] like Figure 3B As shown, storage unit 11 ij (i,j=1,...,4) includes a storage element 12 and a switching element 14 connected in series. The storage element 12 is a variable resistor having a first resistance value and a second resistance value higher than the first resistance value. When a write current flows from one of the first and second terminals of the storage cell to the other, the storage element 12 is capable of changing its resistance value from one of the first and second resistance values ​​to the other. For example, when the first resistance value can be changed to the second resistance value when the write current flows from the first terminal to the second terminal, the second resistance value can be changed to the first resistance value when the write current flows from the second terminal to the first terminal.

[0031] The variable resistance element is, for example, a magnetic tunnel junction (MTJ) element, and includes a magnetic layer (hereinafter also referred to as a reference layer) 12a with a fixed magnetization direction, a magnetic layer (hereinafter also referred to as a storage layer) 12c with a variable magnetization direction, and a non-magnetic insulating layer (hereinafter also referred to as a tunnel barrier layer) 12b provided between the reference layer 12a and the storage layer 12c, as shown below. Figure 3A As shown. In this document, "having a fixed magnetization direction" means that the magnetization direction does not change before (before writing) and after (after writing) the write current is applied to the memory element, and "having a variable magnetization direction" means that the magnetization direction can be changed before and after the write current is applied to the memory element. When the magnetization directions of the reference layer 12a and the memory layer 12c are parallel to each other (in the same direction), the resistance of the MTJ element is low. When the magnetization directions are antiparallel to each other (in opposite directions), the resistance is high.

[0032] Although the magnetization direction is orthogonal to or opposite to the stacking direction of the reference layer and storage layer. Figure 3AThe film planes (surfaces) are parallel; however, the magnetization direction can be parallel to the stacking direction or orthogonal to the film plane. When the magnetization direction is parallel to the stacking direction, each of the storage layer 12c and the reference layer 12a has perpendicular magnetic anisotropy. When the magnetization direction is orthogonal to the stacking direction, each of the storage layer 12c and the reference layer 12a has in-plane magnetic anisotropy.

[0033] (parallel → anti-parallel)

[0034] The following describes a writing method to be implemented when the magnetization direction of storage layer 12c is parallel (parallel) to the magnetization direction of reference layer 12a, and then when the magnetization direction of storage layer 12c changes to an antiparallel (anti-parallel) direction. In this case, a write current flows from reference layer 12a through tunnel barrier layer 12b to storage layer 12c. Electrons then flow in the opposite direction to the write current and from storage layer 12c to reference layer 12a. Spin-polarized electrons flowing in storage layer 12c pass through tunnel barrier layer 12b and then reach the interface between tunnel barrier layer 12b and reference layer 12a. Most spin-polarized electrons are magnetized in the same direction as the magnetization direction of storage layer 12c, and a small portion are magnetized in the opposite direction. Electrons magnetized in the same direction as the magnetization direction of reference layer 12a cross the aforementioned interface and flow into reference layer 12a. On the other hand, electrons magnetized in a direction opposite to the magnetization direction of the reference layer 12a are reflected from the interface and flow into the storage layer 12c via the tunnel barrier layer 12b. This applies a spin torque to the magnetization in the storage layer 12c, reversing the magnetization direction in the storage layer 12c to the opposite direction to that of the reference layer 12a. In other words, the magnetization direction of the storage layer 12c becomes antiparallel to the magnetization direction of the reference layer 12a.

[0035] (antiparallel→parallel)

[0036] The following describes a writing method to be implemented when the magnetization direction of storage layer 12c is antiparallel (anti-parallel) to the magnetization direction of reference layer 12a, and then when the magnetization direction of storage layer 12c changes to parallel (parallel). In this case, a write current flows from storage layer 12c through tunnel barrier layer 12b to reference layer 12a. Electrons then flow in the opposite direction to the write current, from reference layer 12a to storage layer 12c. Spin-polarized electrons flowing in reference layer 12a pass through tunnel barrier layer 12b and then reach the interface between tunnel barrier layer 12b and storage layer 12c. Most of the spin-polarized electrons are magnetized in the same direction as the magnetization direction of reference layer 12a, and a small portion are magnetized in the opposite direction to the magnetization direction of reference layer 12a. Electrons with spin in a direction opposite to the magnetization direction of storage layer 12c flow into storage layer 12c after passing through the interface described above, applying a spin torque to the magnetization in storage layer 12c and reversing the magnetization direction in storage layer 12c to the same direction as the magnetization direction of reference layer 12a. On the other hand, electrons with spin in a direction the same as the magnetization direction of storage layer 12c flow into storage layer 12c. That is, the magnetization direction of storage layer 12c becomes parallel to the magnetization direction of reference layer 12a.

[0037] Furthermore, in each storage unit 11 ij In (i,j=1,...,4), the switching element 14, connected in series with the storage element 12, has two terminals. One of these terminals is connected to the corresponding storage element 12, and the other is connected to the word line. The switching element 14 functions as a switch, controlling the current supply to the corresponding storage element 12 during writing to and reading information (magnetization direction) from the storage element 12. More specifically, when applied to a certain storage cell 11... ij When the voltage (i,j=1,…,4) is below the threshold Vth (e.g., VDD or higher), the switching element 14 in the memory cell is switched off as an insulator with a high resistance value and enters the off state. When the voltage applied to the memory cell is equal to or higher than the threshold Vth, the memory cell is treated as a conductor with a low resistance value, and current flows into the memory cell, causing the memory cell to enter the on state. That is, the switching element 14 has the ability to switch according to the voltage applied to the memory cell 11. ij The voltage amplitude of (i,j=1,…,4) is used to switch between applying and blocking current, regardless of the direction of the current flowing in it.

[0038] (First example of a write method)

[0039] Next, refer to Figure 4A and Figure 4BA first example of a write method in a storage device according to a first embodiment is described. In this embodiment, in each storage cell 11 ij In (i,j=1,...,4), reference layer 12a is electrically connected to the corresponding word line WL. i And storage layer 12c is electrically connected to the corresponding bit line BL. j In other words, the reference layer 12a of the storage element 12 is directly connected to each storage cell 11. ij The corresponding word line WL in (i,j=1,2,3,4) i In this case, storage layer 12c is electrically connected to bit line BL via switching element 14. j The reference layer 12a of the storage element 12 is connected to the word line WL via the switching element 14. i In this case, storage layer 12c is directly connected to bit line BL. j .

[0040] Figure 4A It is used to interpret and execute the write so that storage unit 11 22 The diagram shows the case where the magnetization direction of the storage layer 12c of the storage element 12 changes from a direction parallel to the magnetization direction of the reference layer 12a to a direction antiparallel to the magnetization direction of the reference layer 12a. Note that in Figure 4A In the diagram, transistors 212, 222, 232, and 242, which are connected to word line WL2 and bit line BL2, are not shown. Figure 1 The driving circuits 210, 220, 230 and 240 are shown.

[0041] First, using driver circuits 210, 220, 230, and 240, a potential VSS is applied to all word lines WL1 to WL4 and all bit lines BL1 to BL4. This can be achieved by turning off transistor 212 of driver circuit 210, transistor 222 of driver circuit 220, transistor 232 of driver circuit 230, and transistor 242 of driver circuit 240, and turning on transistor 214 of driver circuit 210 and transistor 234 of driver circuit 230.

[0042] Next, in order to write the information into storage unit 11 22 The storage element 12 is activated by turning on transistor 212 connected to word line WL2 and turning off transistor 222. Further, transistor 232 connected to bit line BL2 is turned off, and transistor 242 (see [link to storage element 12]) is activated. Figure 4A Therefore, potential VDD is applied to word line WL2, potential VNN is applied to bit line BL2, and write voltage (=VDD-VNN) is applied to memory cell 11. 22 The storage element 12, and the write current flows from the word line WL2 into the storage cell 11.22 And bit line BL2. Due to memory cell 11 22 The reference layer 12a is electrically connected to the word line WL2, and the storage layer 12c is electrically connected to the bit line BL2. Therefore, the write current flows from the reference layer 12a to the storage layer 12c, and as described above, the magnetization direction of the storage layer 12c is reversed to the opposite (antiparallel) direction of the magnetization direction of the reference layer 12a.

[0043] At this point in time, voltage VSS is applied to the half-selected memory cell 11. 21 11 23 and 11 24 The corresponding bit lines BL1, BL3, and BL4, and the half-selected memory cell 11 21 11 23 and 11 24 The selected word line WL2, connected to a voltage VDD, is applied and does not undergo a write operation. Therefore, a voltage VDD-VSS (=VDD) equal to or lower than the threshold Vth of the switching element 14 is applied to the half-selected memory cell 11. 21 11 23 and 11 24 And no write operation is performed. In other words, erroneous writes are prevented. Furthermore, voltage VSS is applied to the half-selected memory cell 11. 12 11 32 and 11 42 The corresponding word lines WL1, WL3, and WL4, and the half-selected memory unit 11 12 11 32 and 11 42 The selected bit line BL2 is connected to a voltage VNN applied to it and does not undergo a write operation. Therefore, a voltage VDD-VSS (=VDD) equal to or lower than the threshold Vth of the switching element 14 is applied to the half-selected memory cell 11. 12 11 32 and 11 42 And no write operation is performed.

[0044] Figure 4B It is used to interpret and execute the write so that storage unit 11 22 The diagram shows the case where the magnetization direction of storage layer 12c changes from an antiparallel direction to the magnetization direction of reference layer 12a to a direction parallel to the magnetization direction of reference layer 12a. Note that in Figure 4B In the diagram, transistors 212, 222, 232, and 242, which are connected to word line WL2 and bit line BL2, are not shown. Figure 1 The driving circuits 210, 220, 230 and 240 are shown.

[0045] First, using driver circuits 210, 220, 230, and 240, a potential VSS is applied to all word lines WL1 to WL4 and all bit lines BL1 to BL4. This can be achieved by turning off transistor 212 of driver circuit 210, transistor 222 of driver circuit 220, transistor 232 of driver circuit 230, and transistor 242 of driver circuit 240, and turning on transistor 214 of driver circuit 210 and transistor 234 of driver circuit 230.

[0046] Next, in order to write the information into storage unit 11 22 The storage element 12 is turned off, transistor 212 connected to word line WL2 is turned off, and transistor 222 is turned on. Further, transistor 232 connected to bit line BL2 is turned on, and transistor 242 is turned off (see [link]). Figure 4B Therefore, potential VNN is applied to word line WL2, potential VDD is applied to bit line BL2, and write voltage (=VDD-VNN) is applied to memory cell 11. 22 And the write current flows from bit line BL2 into memory cell 11 22 And word line WL2. Due to storage unit 11 22 The reference layer 12a is electrically connected to the word line WL2, and the storage layer 12c is electrically connected to the bit line BL2. Write current flows from the storage layer 12c to the reference layer 12a, and as described above, the magnetization direction of the storage layer 12c is reversed to the same (parallel) direction as the magnetization direction of the reference layer 12a.

[0047] At this point in time, voltage VSS is applied to the half-selected memory cell 11. 12 11 32 and 11 42 The corresponding word lines WL1, WL3, and WL4, the half-selected memory unit 11 12 11 32 and 11 42 The selected bit line BL2, connected to a voltage VDD, is applied and does not undergo a write operation. Therefore, a voltage VDD-VSS equal to or lower than the threshold Vth of the switching element 14 is applied to the half-selected memory cell 11. 21 11 23 and 11 24 And no write operation is performed. In other words, erroneous writes are prevented. Furthermore, voltage VSS is applied to the half-selected memory cell 11. 21 11 23 and 11 24 The corresponding bit lines BL1, BL3, and BL4, the half-selected memory cell 11 21 11 23 and 11 24Is connected to the selected word line WL2 to which the voltage VNN is applied and does not undergo writing. Therefore, a voltage VDD-VSS (e.g., VDD) equal to or lower than the threshold Vth of the switching element 14 is applied to the semi-selected memory cell 11 21 、11 23 and 11 24 , and writing is not performed. That is, erroneous writing can be prevented.

[0048] (Second example of the writing method)

[0049] Next, refer to Figure 5A and Figure 5B to describe a second example of the writing method in the storage device of the first embodiment. Generally, in the case where the storage element is an MTJ element, when writing information from the parallel direction to the antiparallel direction, a higher voltage is required compared to the voltage required when writing information from the antiparallel direction to the parallel direction. Therefore, as Figure 5A and Figure 5B show, in the drive circuit 230 for writing information from the antiparallel direction to the parallel direction, the potential connected to the source of the transistor 232 changes from VDD to VDD”(=VDD-α,α<VDD). Moreover, the potential connected to the source of the transistor 222 in the drive circuit 220 changes from -VDD to -VDD”.

[0050] As can be seen from Figure 5A in the same manner as the writing operation of the first example shown in Figure 4A , the operation of writing information from the parallel direction to the antiparallel direction is performed.

[0051] In the case of writing information from the antiparallel direction to the parallel direction, writing is performed as shown in Figure 5B . Figure 5B is a diagram for explaining the case where writing is performed so that the magnetization direction of the storage layer 12c of the memory cell 11 22 changes from a direction antiparallel to the magnetization direction of the reference layer 12a to a direction parallel to the magnetization direction of the reference layer 12a. Note that in Figure 5B , except for the transistors 212, 222, 232, and 242 connected to the word line WL2 and the bit line BL2, the drive circuits 210, 220, 230, and 240 shown in Figure 1 are not shown.

[0052] First, using driver circuits 210, 220, 230, and 240, a potential VSS is applied to all word lines WL1 to WL4 and all bit lines BL1 to BL4. This can be achieved by turning off transistor 212 of driver circuit 210, transistor 222 of driver circuit 220, transistor 232 of driver circuit 230, and transistor 242 of driver circuit 240, and turning on transistor 214 of driver circuit 210 and transistor 234 of driver circuit 230.

[0053] Next, in order to write the information into storage unit 11 22 The storage element 12 is turned off, transistor 212 connected to word line WL2 is turned off, and transistor 222 is turned on. Further, transistor 232 connected to bit line BL2 is turned on, and transistor 242 is turned off (see [link]). Figure 5B Therefore, -VDD” is applied to word line WL2, -VDD” is applied to bit line BL2, and the write voltage (=VDD”-(-VDD”)=VDD”+VDD”) is applied to memory cell 11. 22 And the write current flows from bit line BL2 into memory cell 11 22 And word line WL2. Due to storage unit 11 22 The reference layer 12a is electrically connected to the word line WL2, and the storage layer 12c is electrically connected to the bit line BL2. Write current flows from the storage layer 12c to the reference layer 12a, and as described above, the magnetization direction of the storage layer 12c is reversed to the same (parallel) direction as the magnetization direction of the reference layer 12a.

[0054] At this point in time, voltage VSS is applied to the half-selected memory cell 11. 12 11 32 and 11 42 The corresponding word lines WL1, WL3, and WL4, the half-selected memory unit 11 12 11 32 and 11 42 The selected bit line BL2, connected to VDD, is applied and does not undergo a write operation. Therefore, VDD-VSS, equal to or lower than the threshold Vth of switching element 14, is applied to the half-selected memory cell 11. 21 11 23 and 11 24 And no write operation is performed. In other words, erroneous writes are prevented. Furthermore, voltage VSS is applied to the half-selected memory cell 11. 21 11 23 and 11 24 Corresponding to bit lines BL1, BL3, and BL4, the half-selected memory cell 11 21 11 23 and 1124 The selected word line WL2, connected to -|VDD, is applied and does not undergo a write operation. Therefore, -VDD"-VSS (e.g., -VDD") equal to or lower than the threshold Vth of switching element 14 is applied to the half-selected memory cell 11. 21 11 23 and 11 24 And it does not perform any write operations. In other words, it prevents erroneous writes.

[0055] (Reading method)

[0056] Next, refer to storage unit 11 22 This section describes an example of reading information from storage element 12, illustrating a reading method implemented in a storage device. In this case, word line WL2 and bit line BL2 are... Figure 1 The control circuit 300 shown selects and applies a read current from one of these selected wirings (e.g., word line WL2) to another (e.g., bit line BL2), and measures the voltage between the selected wirings to perform a read. The absolute value of this read current is less than the absolute value of the write current described above, and is large enough to prevent erroneous writes.

[0057] As described above, in the first embodiment, the word lines and bit lines are precharged to potential VSS before the write operation, and therefore, a stable write operation can be performed.

[0058] (Comparative Example)

[0059] Next, refer to Figure 6 A comparative example of a storage device according to a first embodiment is described. The storage device includes a storage device having a comparative embodiment with a comparative embodiment of a first embodiment. Figure 1 The storage cell array 100 shown is a storage cell array 100 with the same structure as the storage device shown. Further, one end of the transmission gate 216 formed by p-channel and n-channel transistors, and one of the source and drain of the n-channel transistor 218, are electrically connected to each word line WL. i One end of the transmission gate 216 (i = 1, 2, 3, 4) is connected to a power supply at a supply potential VHH (e.g., 5V, also referred to as VHH hereinafter) or a power supply at a supply potential VSS. The gate of the p-channel transistor of the transmission gate 216 and the gate of the n-channel transistor 218 are electrically connected. The other of the source and drain of the n-channel transistor 218 is connected to a power supply at a supply potential VHH / 2.

[0060] Meanwhile, one end of the transmission gate 236 formed by the p-channel transistor and the n-channel transistor, as well as one of the source and drain of the n-channel transistor 238, are electrically connected to each bit line BL. jOne end of the transmission gate 236 (j = 1, 2, 3, 4) is connected to a power supply at a supply potential VHH (e.g., 5V, also referred to as VHH hereinafter) or a power supply at a supply potential VSS. The gate of the p-channel transistor of the transmission gate 236 and the gate of the n-channel transistor 238 are electrically connected. The other of the source and drain of the n-channel transistor 238 is connected to a power supply at a supply potential VHH / 2.

[0061] Next, a method for writing information to the memory device of this comparative example is described. First, a potential VSS is applied to word lines WL1 to WL4 and bit lines BL1 to BL4 for writing information. This is performed as described below. The other end of transmission gate 216, which is electrically connected to each of the word lines WL1 to WL4, is electrically connected to the power supply VSS, and transmission gate 216 is turned on. At this time, n-channel transistor 218 is in the off state. Then, potential VSS is applied to all word lines WL1 to WL4. Furthermore, the other end of transmission gate 236, which is electrically connected to each of the bit lines BL1 to BL4, is electrically connected to the power supply VSS, and transmission gate 236 is turned on. At this time, n-channel transistor 238 is in the off state. Then, potential VSS is applied to all bit lines BL1 to BL4.

[0062] Next, a write operation will be performed to store cell 11. 22 The magnetization direction of the storage layer changes from parallel to the magnetization direction of the reference layer to antiparallel to the magnetization direction of the reference layer. In this case, a write current is applied to word line WL2 and storage cell 11. 22 And bit line BL2, as described with reference to Figure 4. This is performed as described below. First, the other end of transmission gate 216 is electrically connected to power supply VHH, and transmission gate 216 is turned on. At this time, one of its source and drain is electrically connected to the n-channel transistor 218 of word line WL2, which is in the off state. Then, potential VHH is applied to word line WL2. Further, transmission gate 216, which is electrically connected to each of the unselected word lines WL1, WL3, and WL4, is turned off, and n-channel transistor 218 is turned on. Then, potential VHH / 2 is applied to the unselected word lines WL1, WL3, and WL4 via n-channel transistor 218.

[0063] On the other hand, the other end of transmission gate 236 is electrically connected to power supply VSS, and transmission gate 236 is turned on. At this point, one of its source and drain terminals, which is electrically connected to bit line BL2, is in the off state. Then, potential VSS is applied to bit line BL2. Further, transmission gate 236, which is electrically connected to each of the unselected bit lines BL1, BL3, and BL4, is turned off, and n-channel transistor 238 is turned on. Then, potential VHH / 2 is applied to the unselected bit lines BL1, BL3, and BL4 via n-channel transistor 238.

[0064] As described above, the write current is at word line WL2 and memory cell 11. 22 The flow is in bit line BL2, and the write is performed to select memory cell 11. 22 The magnetization direction of the storage layer is switched from a direction parallel to the magnetization direction of the reference layer to a direction antiparallel to the magnetization direction of the reference layer, as described with reference to Figure 4. On the other hand, VHH / 2 (=VHH-VHH / 2) is applied to the half-selected storage cell 11. 21 11 23 and 11 24 A potential VHH / 2 is applied to the half-selected memory cell 11. 12 11 32 and 11 42 And no writes are performed on each of these storage units.

[0065] Next, a write operation will be performed to store cell 11. 22 The magnetization direction of the memory layer is switched from parallel to the magnetization direction of the reference layer to antiparallel to the magnetization direction of the reference layer. Before performing the write operation, a potential VSS is applied to word lines WL1 to WL4 and bit lines BL1 to BL4, as described above. Then, a write current is applied to bit line BL2 and memory cell 11. 22 And word line WL2, as described with reference to Figure 5. This is performed as described below. First, the other end of transmission gate 236 is electrically connected to power supply VHH, and transmission gate 236 is turned on. At this time, one of its source and drain is electrically connected to bit line BL2, and the n-channel transistor 238 is in the off state. Then, potential VHH is applied to bit line BL2. Further, transmission gate 236, which is electrically connected to each of the unselected bit lines BL1, BL3, and BL4, is turned off, and n-channel transistor 238 is turned on. Then, potential VHH / 2 is applied to the unselected bit lines BL1, BL3, and BL4 via n-channel transistor 238.

[0066] On the other hand, the other end of transmission gate 216 is electrically connected to power supply VSS, and transmission gate 216 is turned on. At this point, one of its source and drain is electrically connected to the n-channel transistor 218 of word line WL2, which is in the off state. Then, potential VSS is applied to word line WL2. Further, transmission gate 216, which is electrically connected to each of the unselected word lines WL1, WL3, and WL4, is turned off, and n-channel transistor 218 is turned on. Then, potential VHH / 2 is applied to the unselected word lines WL1, WL3, and WL4 via n-channel transistor 218.

[0067] As described above, the write current is at bit line BL2 and memory cell 11. 22 The flow is in word line WL2, and the write is executed to select the memory cell 11. 22 The magnetization direction of the storage layer is switched from an antiparallel direction to a direction parallel to the magnetization direction of the reference layer, as described with reference to Figure 5. On the other hand, VHH / 2 (=VHH-VHH / 2) is applied to the half-selected storage cell 11. 21 11 23 and 11 24 A potential VHH / 2 is applied to the half-selected memory cell 11. 12 11 32 and 11 42 And no writes are performed on each of these storage units.

[0068] As described above, in this comparative example, the transistors 216 and 236 that constitute the drive word lines and bit lines, as well as transistors 218 and 238, are driven at a voltage of 5V.

[0069] In the first embodiment, on the other hand, the transistors 212, 214, 222, 224, 232, 234, 242, and 244 driving the word lines and bit lines are driven by VDD. Therefore, in the first embodiment, the size of the transistors in the driving circuit (e.g., channel length) can be smaller than that in the comparative example, and the size of the CUA can be significantly reduced. Furthermore, the driving voltage can be reduced, and the power consumption can be lowered.

[0070] As described above, according to this embodiment, a non-volatile storage device can be provided, which includes an architecture with a highly integrated three-dimensional structure.

[0071] Although word lines WL1 to WL4 are positioned below bit lines BL1 to BL4 in this embodiment, word lines WL1 to WL4 may be positioned above bit lines BL1 to BL4.

[0072] Furthermore, in this embodiment, the MTJ element is used as the storage element 12. However, the same effect can be achieved by replacing the giant magnetoresistive (GMR) element of the tunnel barrier layer with a non-magnetic metal layer.

[0073] Furthermore, a storage element with a metal oxide inserted between the two electrodes can be used as storage element 12. In this case, the non-volatile storage device is resistive random access memory (ReRAM).

[0074] (Second Embodiment)

[0075] Now for reference Figure 7 and Figure 8 A non-volatile storage device (hereinafter also referred to as a storage device) according to a second embodiment is described. The storage device of the second embodiment has the following configuration: Figures 1 to 2C The storage device of the first embodiment shown provides a plurality of (e.g., four) new word lines in the fifth layer above the bit lines, and new storage cells are provided between these word lines and the bit lines described above.

[0076] Figure 7 It is along in Figure 8 The cross-sectional view of the storage device of the second embodiment is obtained from the section BB defined in the diagram. Figure 8 It is along in Figure 7 The second embodiment of the storage device is a cross-sectional view obtained from section AA as defined in the diagram. The storage device of the second embodiment includes a storage cell array 100A. The storage cell array 100A includes a first array 101 and a second array 102 provided on the first array 101.

[0077] As with the memory cell array 100 of the first embodiment, the first array 101 includes word lines WL disposed in the first layer and arranged to extend in the first direction (x direction). i 1 (i = 1, ..., 4), a bit line BL is set in the third layer above the first layer and arranged to extend in the second direction (y direction) intersecting the first direction. j 1 (j=1,...,4), and a storage cell 11 located in the second layer between the first and third layers and arranged to extend in a third direction (z direction) intersecting the first direction (x direction) and the second direction (y direction). ij 1 (i,j = 1,...,4). Storage unit 11 ij 1 (i,j = 1,…,4) are provided in word line WL i 1 With bit line BL j1 In the intersection area between them, each includes a first terminal and a second terminal. In storage unit 11 ij 1 In (i,j=1,...,4), the first terminal is electrically connected to the corresponding word line WL. i 1 The second terminal is electrically connected to the corresponding bit line BL. j 1 Each storage unit has 11 ij 1 (i,j=1,...,4) has the same... Figure 3A The storage unit 11 shown ij The same structure. Therefore, in forming storage cell 11 ij 1 In the storage element 12 (i,j=1,...,4), the reference layer 12a is electrically connected to the corresponding word line WL. i 1 Storage layer 12c is electrically connected to the corresponding bit line BL. j 1 As in the first embodiment.

[0078] The second array 102 includes: a bit line BL disposed in the third layer and arranged to extend in the second direction (y direction). j 1 (j=1,...,4), is a word line WL located in the fifth layer above the third layer and arranged to extend in the first direction (x direction). i 2 (i = 1, ..., 4), and storage cells 11 located in the fourth layer between the third and fifth layers and arranged to extend in the third direction (z direction). ij 2 (i,j = 1,...,4). That is, the first array 101 and the second array 102 share a bit line BL that is set in the third layer and arranged to extend in the second direction (y direction). j 1 (j = 1, ..., 4). Storage unit 11 ij 2 (i,j = 1,…,4) are provided in word line WL i 2 With bit line BL j 1 In the intersection area between them, each includes a first terminal and a second terminal. In storage unit 11 ij 2 In (i,j=1,...,4), the first terminal is electrically connected to the corresponding word line WL. i2 The second terminal is electrically connected to the corresponding bit line BL. j 1 Each storage unit has 11 ij 2 (i,j=1,...,4) has the same... Figure 3A The storage unit 11 shown ij The same structure. Therefore, in forming the register unit 11 ij 2 In the storage element 12 (i,j=1,...,4), the reference layer 12a is electrically connected to the corresponding word line WL. i 2 Storage layer 12c is electrically connected to the corresponding bit line BL. j 1 As in the first embodiment.

[0079] like Figure 7 As shown, the storage device of the second embodiment includes: a drive circuit 210 1 It includes each word line WL electrically connected to the first array 101. i 1 One end of (i = 1, ..., 4) and connected in series with a p-channel transistor 212 1 and n-channel transistor 214 1 ; and drive circuit 220 1 It includes an n-channel transistor 222 electrically connected to the other end. 1 Note that in this embodiment, in the drive circuit 210 1 In the middle, p-channel transistor 212 1 and n-channel transistor 214 1 The gates of the two transistors are connected together, and the word line selection signal is received from the control circuit 300, which is also connected to the gates. p-channel transistor 212 1 The source is electrically connected to the power supply VDD, and the drain is connected to the n-channel transistor 214. 1 The drain is electrically connected to the corresponding word line WL. i 1 (i = 1, ..., 4). n-channel transistor 214 1 The drain is electrically connected to the ground power supply VSS, and the source is electrically connected to the corresponding word line WL. i 1 (i = 1, ..., 4).

[0080] Furthermore, the drive circuit 220 1 n-channel transistor 222 1 The drain is electrically connected to the corresponding word line WL i 1The other end of (i = 1, ..., 4) and the source is electrically connected to the power supply VNN.

[0081] Meanwhile, the second array 102 is provided with: a driving circuit 210 2 It includes being electrically connected to each word line WL i 2 One end of (i = 1, ..., 4) and connected in series with a p-channel transistor 212 2 and n-channel transistor 214 2 ; and drive circuit 220 2 It includes an n-channel transistor 222 electrically connected to the other end. 2 Note that in this embodiment, in the drive circuit 210 2 In the middle, p-channel transistor 212 2 and n-channel transistor 214 2 The gates of the two transistors are connected together, and the word line selection signal is received from the control circuit 300, which is also connected to the gates. p-channel transistor 212 2 The source is electrically connected to the power supply VDD, and the drain is connected to the n-channel transistor 214. 2 The drain is electrically connected to the corresponding word line WL. i 2 (i = 1, ..., 4). n-channel transistor 214 2 The drain is electrically connected to the ground power supply VSS, and the source is electrically connected to the corresponding word line WL. i 2 (i = 1, ..., 4). Drive circuit 220 2 n-channel transistor 222 2 The drain is electrically connected to the corresponding word line WL i 2 At the other end of (i=1,...,4), the source is electrically connected to the power supply VNN.

[0082] Moreover, such as Figure 8 As shown, the storage device in this embodiment includes: a drive circuit 230 1 It includes a drain that is electrically connected to the bit line BL. j 1 A p-channel transistor 232 (j = 1, ..., 4) whose source is electrically connected to power supply VDD and whose gate receives a bit line selection signal from control circuit 300. 2 And the drain is electrically connected to the bit line BL. j 1 An n-channel transistor 234 (j = 1,...,4) whose source is electrically connected to ground power supply VSS and whose gate receives control signals from control circuit 300. 1 ; and drive circuit 2401 It includes n-channel transistor 242 1 Its drain is electrically connected to the bit line BL. j 1 At the other end of (j=1,...,4), the source is electrically connected to the power supply VNN, and the gate receives a control signal from the control circuit 300.

[0083] Note that the drive circuit 210 1 220 1 230 1 240 1 210 2 220 2 230 2 and 240 2 And the control circuit 300 is set in which the word line WL1 is set. 1 Up to WL4 1 In the first, lower layer.

[0084] (Write operation)

[0085] Next, reference information (magnetization direction) is written into the storage cells 11 of the first array 101. 22 1 The example scenario describes a write operation. First, before the information is written, a potential VSS is applied to all word lines WL1. 1 Up to WL4 1 and all bit lines BL1 1 Up to BL4 1 This is to perform a pre-charge operation. This can be achieved by shutting down the drive circuit 220. 1 transistor 222 1 And will be used for drive circuit 210 1 The word line select signal is set to the H (high) level to be executed. At this point, the precharge operation may or may not be performed in the second array.

[0086] Then, the information is written to the storage unit 11 in the same manner as described in the first embodiment. 22 1 Storage element 12. As shown in Figure 4 or Figure 5, for example, to the storage element 12 connected to the selected storage cell 11. 22 1 The word line WL2 1 and bit line BL2 1 Each supply potential in, and to all except word line WL2 1 Other than word lines and BL2 bit lines 1 The bit line supply potential VSS is located outside the memory cell 11. As a result, in the selected memory cell 11... 221 The voltage to be applied between the first and second terminals is set to VDD-VNN, and the voltage to be applied between the first and second terminals of each unselected memory cell is set to (VDD-VNN) / 2 or 0V.

[0087] The same operation is performed when information is written to a selected storage cell in the second array 102.

[0088] Note that information is read from the selected storage cell in the first array 101 or the second array 102 in the same manner as described in the first embodiment.

[0089] As described above, according to the second embodiment, the size of the transistors in the driving circuit (e.g., channel length) can be reduced, and the size of the CUA can be significantly reduced, as in the first embodiment. Furthermore, the driving voltage can be reduced, and power consumption can be lowered. Therefore, according to the second embodiment, a non-volatile memory device with an architecture including a highly integrated three-dimensional structure can be provided.

[0090] In the second embodiment, the storage device may have the following structure: a plurality of new bit lines are provided to house word lines WL1. 2 Up to WL4 2 The layer above the layer extends in the y-direction, and in these new bit lines and word lines WL1 2 Up to WL4 2 New storage cells are set in the intersection area between the two arrays, which is a structure with a third array on top of the second array. Furthermore, when m is an integer of 4 or greater, the storage device can have a structure including the first to the m-th arrays.

[0091] (Third Embodiment)

[0092] Now for reference Figure 9 and Figure 10 A non-volatile storage device (hereinafter also referred to as a storage device) according to a third embodiment is described.

[0093] Figure 9 It is along in Figure 10 The cross-sectional view of the storage device of the third embodiment is obtained from the section BB defined in the figure. Figure 10 It is along in Figure 9 The cross-sectional view of the storage device of the third embodiment is obtained by section AA as defined in the diagram.

[0094] The storage device of the third embodiment has the same Figure 7 and Figure 8 The storage device shown in the second embodiment has the same configuration, except that it further includes: having WL for each word line. i1 251 n-channel transistors (i = 1, ..., 4) 1 250 drive circuit 1 And having WL for each word line i 1 251 n-channel transistors (i = 1, ..., 4) 2 250 drive circuit 2 n-channel transistor 251 1 The drain is electrically connected to the corresponding word line WL i 1 At the other end of (i = 1, ..., 4), the source is electrically connected to the power supply VSS, and the gate receives control signals from the control circuit 300. n-channel transistor 251 2 The drain is electrically connected to the corresponding word line WL i 2 At the other end of (i = 1, ..., 4), the source is electrically connected to the power supply VSS, and the gate will receive control signals from the control circuit 300.

[0095] Note that the drive circuit 210 1 220 1 230 1 240 1 250 1 210 2 220 2 230 2 240 2 and 250 2 And the control circuit 300 is set in which the word line WL1 is set. 1 Up to WL4 1 In the first, lower layer.

[0096] Furthermore, in the storage device of the third embodiment, the same word line select signal is input to the drive circuit 210. 1 and drive circuit 210 2 Drive circuit 210 1 p-channel transistor 212 1 The source is electrically connected to power supply FX1, drive circuit 210 2 p-channel transistor 212 2 The source is electrically connected to power supply FX2, and the drive circuit 220 1 p-channel transistor 222 1 The source is electrically connected to power supply FY1. Each power supply FX1, FX2, and FY1 has a value of VDD or VSS. This is described below with an example write operation.

[0097] (Write operation)

[0098] In the storage cell 11 where information is to be written to the first array 101 22 1 In this case, potential VSS is supplied to all word lines WL1 of the first array 101. 1 Up to WL4 1 Furthermore, the potential VSS is supplied to all bit lines BL1. 1 Up to BL4 1 This is done by first performing pre-charging. This can be achieved by turning on the drive circuit 250. 1 n-channel transistor 251 1 and drive circuit 230 1 n-channel transistor 234 1 To achieve this.

[0099] At this point in time, the pre-charge operation may or may not be performed in the second array.

[0100] Then, the information is written to storage unit 11 in the same manner as described in the first embodiment. 22 1 Storage element 12. As shown in Figure 4 or Figure 5, for example, to the storage element 12 connected to the selected storage cell 11. 22 1 The word line WL2 1 and bit line BL2 1 Each supply potential in, and to all except word line WL2 1 Other than word lines and BL2 bit lines 1 The bit line is supplied with potential VSS. At this time, potential VDD is supplied to word line WL2. 1 In this case, power supply FX1 is set to power supply VDD, as shown in Figure 4. For example, power supply FX2 is set to power supply VSS and is used for drive circuit 210. 1 and drive circuit 210 2 The word line control signal is set to L (low) level. In this case, the driver circuit 210 2 p-channel transistor 212 2 Enter the on state, and the word line WL2 2 It enters a floating state. Therefore, the drive circuit 250 2 n-channel transistor 251 2 It is switched on to supply the potential VSS to the word line WL2. 2 .

[0101] Therefore, in the selected storage unit 11 22 1The voltage to be applied between the first and second terminals is set to VDD-VNN, and the voltage to be applied between the first and second terminals of each unselected memory cell is set to (VDD-VNN) / 2 or 0V.

[0102] Note that in the third embodiment, the power supply FY1 is fixed to VDD. However, the storage device can have a structure in which multiple new bit lines are provided to house the word line WL1. 2 Up to WL4 2 The layer above the layer extends in the y-direction, and in these new bit lines and word lines WL1 2 Up to WL4 2 New memory cells are placed in the intersection area between the two arrays, creating a structure with a third array above the second array. In this case, power supply FY2 (not shown) is supplied to multiple new bit lines, and power supplies FY1 and FY2 function the same as power supplies FX1 and FX2. That is, power supplies FY1 and FY2 have a potential value of VDD or VSS.

[0103] The same operation is performed when information is written to a selected storage cell in the second array 102.

[0104] Note that information is read from the selected storage cell in the first array 101 or the second array 102 in the same manner as described in the first embodiment.

[0105] As described above, according to the third embodiment, the size of the transistors in the driving circuit (e.g., channel length) can be reduced, and the size of the CUA can be significantly reduced, as in the first embodiment. Furthermore, the driving voltage can be reduced, and power consumption can be lowered. Therefore, according to the third embodiment, a non-volatile memory device comprising an architecture with a highly integrateable three-dimensional structure can be provided.

[0106] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel methods and systems described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications as falling within the scope and spirit of the invention.

[0107] Explanation of the mark

[0108] 11 11 ~11 44 Storage unit

[0109] 12: Storage element

[0110] 12a: Reference Layer

[0111] 12b: Tunnel barrier layer

[0112] 12c: Storage layer

[0113] 14: Switching elements

[0114] 100, 100A: Memory cell array

[0115] 101: First Array

[0116] 102: Second Array

[0117] 210, 220, 230, 240: Drive circuit

[0118] 212: p-channel transistor

[0119] 214, 234, 242: n-channel transistors

[0120] 300: Control Circuit

[0121] WL1~WL4, WL1 1 ~WL4 1 WL1 2 ~WL4 2 :Word line

[0122] BL1~BL4: Bit lines

Claims

1. A non-volatile storage device, comprising: The first wiring is disposed in the first layer and extends in the first direction; The second wiring is disposed in a second layer above the first layer and extends in a second direction intersecting the first direction; A storage cell, disposed in a third layer between the first layer and the second layer, having a first terminal electrically connected to the first wiring and a second terminal electrically connected to the second wiring, the storage cell including a variable resistance element having a resistance that varies as write current flows from one of the first terminal and the second terminal to the other; A first driving circuit is electrically connected to one end of the first wiring and is capable of supplying a first potential and a second potential lower than the first potential; The second driving circuit is electrically connected to the other end of the first wiring and supplies a third potential with a polarity different from that of the first potential. A third driving circuit is electrically connected to one end of the second wiring and is capable of supplying the second potential and a fourth potential higher than the second potential; A fourth driving circuit is electrically connected to the other end of the second wiring and supplies a fifth potential with a polarity different from that of the first potential. as well as A control circuit is electrically connected to the first drive circuit to the fourth drive circuit.

2. The non-volatile storage device according to claim 1, wherein, The second potential is the average of the first potential and the third potential.

3. The non-volatile storage device according to claim 1, wherein, The storage unit further includes a switching element connected in series between the first terminal and the second terminal to the variable resistor element, and controlling the current supply to the variable resistor element.

4. The non-volatile storage device according to claim 1, wherein, The first driving circuit includes: a first p-channel transistor having a drain electrically connected to one end of the first wiring, a source electrically connected to a first power supply supplying the first potential, and a gate for receiving a control signal from the control circuit; and a first n-channel transistor having a drain electrically connected to one end of the first wiring, a source electrically connected to a second power supply supplying the second potential, and a gate for receiving a control signal from the control circuit. The second driving circuit includes: a second n-channel transistor having a drain electrically connected to the other end of the first wiring, a source electrically connected to a third power supply supplying the third potential, and a gate for receiving a control signal from the control circuit. The third driving circuit includes: a second p-channel transistor having a drain electrically connected to one end of the second wiring, a source electrically connected to a fourth power supply supplying the fourth potential, and a gate for receiving a control signal from the control circuit; and a third n-channel transistor having a drain electrically connected to one end of the second wiring, a source electrically connected to the second power supply, and a gate for receiving a control signal from the control circuit. The fourth driving circuit includes a fourth n-channel transistor having a drain electrically connected to the other end of the second wiring, a source electrically connected to a fifth power supply supplying the fifth potential, and a gate for receiving control signals from the control circuit.

5. The non-volatile storage device according to claim 1, wherein, When current flows through the storage cell from the first wiring to the second wiring to write information to the variable resistor element, the control circuit causes the first drive circuit to supply the first potential to the first wiring, and causes the fourth drive circuit to supply the fifth potential to the second wiring. When current flows through the storage cell from the second wiring to the first wiring to write information to the variable resistor element, the control circuit causes the third drive circuit to supply the fourth potential to the second wiring and the second drive circuit to supply the third potential to the first wiring.

6. The non-volatile storage device according to claim 1, wherein, Before information is written to the variable resistor element, the control circuit causes the first drive circuit to supply the second potential to the first wiring, and causes the third drive circuit to supply the second potential to the second wiring.

7. The non-volatile storage device according to claim 1, wherein, The variable resistance element includes a first magnetic layer with a fixed magnetization direction, a second magnetic layer with a variable magnetization direction, and a non-magnetic insulating layer disposed between the first magnetic layer and the second magnetic layer.

8. A non-volatile storage device, comprising: Multiple first wirings are provided in the first layer and arranged to extend in the first direction; Multiple second wirings are disposed in a second layer above the first layer and are arranged to extend in a second direction intersecting the first direction; A plurality of first memory cells are disposed in a third layer between the first layer and the second layer, and are disposed in the intersection area between the plurality of first wirings and the plurality of second wirings. Each first memory cell includes a first terminal and a second terminal, the first terminal being electrically connected to a corresponding first wiring and the second terminal being electrically connected to a corresponding second wiring. Each first memory cell includes a first variable resistance element having a resistance that varies as a write current flows from one of the first terminal and the second terminal to the other. A first driving circuit is electrically connected to one end of the plurality of first wirings and is capable of supplying a first potential and a second potential lower than the first potential; A second driving circuit is electrically connected to the other end of the plurality of first wirings and supplies a third potential with a polarity different from that of the first potential. A third driving circuit is electrically connected to one end of the plurality of second wirings and is capable of supplying the second potential and a fourth potential higher than the second potential; A fourth driving circuit is electrically connected to the other end of the plurality of second wirings and supplies a fifth potential with a polarity different from that of the first potential. as well as A control circuit is electrically connected to the first drive circuit to the fourth drive circuit.

9. The non-volatile storage device according to claim 8, wherein, The second potential is the average of the first potential and the third potential.

10. The non-volatile storage device according to claim 8, wherein, Each of the plurality of first storage cells further includes a first switching element connected in series between the first terminal and the second terminal to the first variable resistor element, and controls the current supply to the first variable resistor element.

11. The non-volatile storage device according to claim 8, wherein, The first driving circuit is provided for the plurality of first wirings and includes: a first p-channel transistor having a drain electrically connected to one end of a corresponding first wiring, a source electrically connected to a first power supply supplying the first potential, and a gate for receiving a control signal from the control circuit; and a first n-channel transistor having a drain electrically connected to one end of the corresponding first wiring, a source electrically connected to a second power supply supplying the second potential, and a gate for receiving a control signal from the control circuit. The second driving circuit is provided for the plurality of first wirings and includes: a second n-channel transistor having a drain electrically connected to the other end of the corresponding first wiring, a source electrically connected to a third power supply supplying the third potential, and a gate for receiving a control signal from the control circuit. The third driving circuit is provided for the plurality of second wirings and includes: a second p-channel transistor having a drain electrically connected to one end of the corresponding second wiring, a source electrically connected to a fourth power supply supplying the fourth potential, and a gate for receiving a control signal from the control circuit; and a third n-channel transistor having a drain electrically connected to one end of the corresponding second wiring, a source electrically connected to the second power supply, and a gate for receiving a control signal from the control circuit. The fourth driving circuit is provided for the plurality of second wirings and includes: a fourth n-channel transistor having a drain electrically connected to the other end of the corresponding second wiring, a source electrically connected to a fifth power supply supplying the fifth potential, and a gate for receiving a control signal from the control circuit.

12. The non-volatile storage device according to claim 8, wherein, When one of the plurality of memory cells is selected and information is to be written into the first variable resistor element of the selected memory cell, In order to write information into the first variable resistor element by applying current from a first wiring corresponding to the selected memory cell to a corresponding second wiring via the selected memory cell, the control circuit causes the first drive circuit to supply the first potential to the first wiring corresponding to the selected memory cell, and causes the fourth drive circuit to supply the fifth potential to the second wiring corresponding to the selected memory cell. In order to write information into the first variable resistor element by applying current from the second wiring corresponding to the selected memory cell to the corresponding first wiring via the selected memory cell, the control circuit causes the third drive circuit to supply the fourth potential to the second wiring corresponding to the selected memory cell, and causes the second drive circuit to supply the third potential to the first wiring corresponding to the selected memory cell. The control circuit causes the first drive circuit to supply the second potential to the first wiring corresponding to the memory cell other than the selected memory cell, and causes the third drive circuit to supply the second potential to the second wiring corresponding to the memory cell other than the selected memory cell.

13. The non-volatile storage device according to claim 12, wherein, The control circuit causes the first drive circuit to supply the second potential to the first wiring corresponding to the memory cell other than the selected memory cell, and causes the third drive circuit to supply the second potential to the second wiring corresponding to the memory cell other than the selected memory cell.

14. The non-volatile storage device according to claim 12, wherein, Before information is written to the first variable resistor element of the selected storage cell, the control circuit causes the first drive circuit to supply the second potential to the plurality of first wirings, and causes the third drive circuit to supply the second potential to the plurality of second wirings.

15. The non-volatile storage device according to claim 8, wherein, The first variable resistor element includes a first magnetic layer having a fixed magnetization direction, a second magnetic layer having a variable magnetization direction, and a first non-magnetic insulating layer disposed between the first magnetic layer and the second magnetic layer.

16. The non-volatile storage device according to claim 8, further comprising: Multiple third wirings are disposed in a fourth layer above the second layer and are arranged to extend in the first direction; A plurality of second memory cells are disposed in a fifth layer between the second layer and the fourth layer, and are arranged in the intersection area between the plurality of second wirings and the plurality of third wirings. Each second memory cell includes a third terminal and a fourth terminal, the third terminal being electrically connected to a corresponding third wiring and the fourth terminal being electrically connected to a corresponding second wiring. Each second memory cell includes a second variable resistor element having a resistance that varies as a write current flows from one of the third terminal and the fourth terminal to the other. A fifth driving circuit is electrically connected to one end of the plurality of third wirings and is capable of supplying the first potential and the second potential; as well as A sixth driving circuit, which is electrically connected to the other end of the plurality of third wirings and is capable of supplying the third potential, wherein, The control circuit is electrically connected to the fifth drive circuit and the sixth drive circuit.

17. The non-volatile storage device according to claim 16, wherein, The second storage unit further includes a second switching element, which is connected in series between the third terminal and the fourth terminal to the second variable resistor element, and controls the current supply to the second variable resistor element.

18. The non-volatile storage device according to claim 16, wherein, The second variable resistor element includes a third magnetic layer having a fixed magnetization direction, a fourth magnetic layer having a variable magnetization direction, and a second non-magnetic insulating layer disposed between the third magnetic layer and the fourth magnetic layer.

19. The non-volatile storage device according to claim 16, wherein, When one of the plurality of second storage cells is selected and information is to be written to the second variable resistor element of the selected storage cell... In order to write information into the second variable resistor element by applying current from a third wiring corresponding to the selected memory cell to the corresponding second wiring via the selected memory cell, the control circuit causes the fifth drive circuit to supply the first potential to the third wiring corresponding to the selected memory cell, and causes the fourth drive circuit to supply the fifth potential to the second wiring corresponding to the selected memory cell. In order to write information into the second variable resistor element by applying current from the second wiring corresponding to the selected memory cell to the corresponding third wiring via the selected memory cell, the control circuit causes the third drive circuit to supply the fourth potential to the second wiring corresponding to the selected memory cell, and causes the sixth drive circuit to supply the third potential to the third wiring corresponding to the selected memory cell.

20. The non-volatile storage device according to claim 19, wherein, The control circuit causes the fifth drive circuit to supply the second potential to the third wiring corresponding to the memory cell other than the selected memory cell, and causes the third drive circuit to supply the second potential to the second wiring corresponding to the memory cell other than the selected memory cell.

21. The non-volatile storage device according to claim 19, wherein, Before information is written to the selected storage cell, the control circuit causes the fifth drive circuit, which is electrically connected to the selected storage cell, to supply the second potential to the plurality of third wirings, and causes the third drive circuit to supply the second potential to the plurality of second wirings.

22. The non-volatile storage device according to claim 19, further comprising: A seventh driving circuit is electrically connected to the other end of the plurality of first wirings and supplies the second potential; as well as The eighth driving circuit, which is electrically connected to the other end of the plurality of third wirings, and supplies the second potential, wherein, The seventh drive circuit and the eighth drive circuit are electrically connected to the control circuit.

23. The non-volatile storage device according to claim 22, wherein, When information is to be written into a variable resistor element included in one of the first and second memory cells, the control circuit simultaneously sends the same control signal to the first drive circuit and the fifth drive circuit, and supplies the second potential to one of the first wiring and the third wiring, wherein the first wiring and the third wiring are electrically connected to the other of the first and second memory cells.

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