Methods for manufacturing semiconductor devices and semiconductor manufacturing tools

Abstract

Methods and tools for manufacturing semiconductor devices are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance on the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control, wherein a portion of the sheath maintained on the edge ring and a portion of the sheath on the electrostatic chuck are coplanar.

Description

Technical Field

[0001] This invention discloses a semiconductor device, a method and tool for manufacturing a semiconductor device, and particularly a method and tool for manufacturing a semiconductor device by controlling an electric field to adjust a plasma sheath. Background Technology

[0002] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are essentially formed by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then patterning these material layers using photolithography to create circuit components and elements.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (such as transistors, diodes, resistors, and capacitors) by constantly shrinking the minimum feature size, allowing more components to be integrated into a specific area. Furthermore, as more components are integrated into a specific area, the integration density can be further improved using sophisticated three-dimensional integrated circuit (3DIC) packaging technology, enabling even complex systems to be integrated into 3DIC devices. However, as the minimum feature size decreases and more complex systems are integrated into 3DIC devices, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to some embodiments of this disclosure, an embodiment of this disclosure discloses a method of manufacturing a semiconductor device, wherein the method includes providing a chuck and an edge ring disposed adjacent to the chuck. The chuck includes a first electrode, and the edge ring includes a second electrode.

[0005] According to some embodiments of the present disclosure, another embodiment of the present disclosure discloses a method for manufacturing a semiconductor device, wherein the method includes: placing an edge ring adjacent to an electrostatic chuck, adsorbing a first semiconductor wafer onto the electrostatic chuck, generating a plasma sheath on the first semiconductor wafer, and applying a first electrical bias voltage to the edge ring.

[0006] According to some embodiments of this disclosure, another embodiment discloses a semiconductor manufacturing tool comprising: an electrostatic chuck, a first electrode, and an edge ring. The first electrode is electrically coupled to the electrostatic chuck, and the edge ring extends beyond the electrostatic chuck, the edge ring including a coil embedded in a dielectric material. Attached Figure Description

[0007] The accompanying drawings provide the best understanding of the features detailed below. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0008] Figures 1A to 1B This is a semiconductor wafer with fin and gate electrode materials illustrated according to some embodiments;

[0009] Figures 2A to 2B The diagram illustrates the formation of a hard mask and photoresist according to some embodiments;

[0010] Figures 3A to 3C The etching tools and etching process are illustrated according to some embodiments;

[0011] Figures 4A to 4B The formation of the gate electrode is illustrated according to some embodiments;

[0012] Figure 5 This is illustrated, according to some embodiments, the formation of the source / drain regions after the formation of the gate electrode;

[0013] Figure 6 The diagram illustrates the formation of a second opening through a deposition cavity, based on some embodiments.

[0014] [Symbol Explanation]

[0015] 100: Semiconductor wafers

[0016] 101: Substrate

[0017] 102: Edge region

[0018] 103: Trench

[0019] 104: Central Area

[0020] 105: Fins

[0021] 107: Insulation Area

[0022] 109: Gate Dielectric Material

[0023] 111: Gate electrode material

[0024] 201,203: Hard mask

[0025] 205,611: Optical Resistor

[0026] 300: Etching System

[0027] 302, 310: Piping

[0028] 303: Etching Agent Delivery System

[0029] 304: Etched cavity

[0030] 305: Manifold

[0031] 306, 308: Valves

[0032] 307: Carrier Gas Supply Unit

[0033] 311: Etching Agent Supplier

[0034] 313: Etching Agent Controller

[0035] 315: Etching agent chamber shell

[0036] 317, 319, 331: Arrow markings

[0037] 320, 321, 324: Electrodes

[0038] 322, 323: Radio Frequency Generator

[0039] 325: Vacuum Pump

[0040] 326: DC power supply

[0041] 327: Controller

[0042] 328: Electric Field Control

[0043] 329: Showerhead

[0044] 345: Setting up the platform

[0045] 347: Groove

[0046] 351: Suction Cup

[0047] 352: Edge of the suction cup

[0048] 357: Edge ring

[0049] 359: Plasma Sheath

[0050] 361: Surrounding Area

[0051] 362: Dashed line marking

[0052] 363: Horizontal support section

[0053] 364: Dashed outline

[0054] 365: Vertical support section

[0055] 367: Electric Field Coil

[0056] 401: Gate electrode

[0057] 403: Gate Dielectric

[0058] 405,621: Opening

[0059] 415: Gate Stack

[0060] 501: Spacer wall

[0061] 503: Source / Drain Region

[0062] 601, 603, 609: Interlayer dielectrics

[0063] 605: Gate contact

[0064] 607: Etching Stop Layer

[0065] 613, 617: Bottom anti-reflective coating

[0066] 615: Intermediate masking layer

[0067] 619: Top photosensitive layer

[0068] B-B': line segment

[0069] D1, D2, D3, D4, Dist1, Dist2: Distance

[0070] P1: Spacing

[0071] T2, T3: Thickness

[0072] W1, W2, W3, W5, W6: Width

[0073] ΔT2, ΔT3: Thickness difference

[0074] θ: angle Detailed Implementation

[0075] The following disclosure provides numerous different implementations or embodiments to carry out different features of the provided object. Specific embodiments of the components and arrangements described below are intended to simplify the embodiments of this disclosure. These are merely embodiments and are not intended to be limiting. For example, in the description, a first feature is formed on or over a second feature, which may include embodiments where the first and second features are formed in direct contact, or embodiments where additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, element symbols and / or letters may be repeated in various examples in this disclosure. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or configurations discussed.

[0076] In addition, spatial relative terms such as “below,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to facilitate the explanation of the relationship between one component or feature and another component (or features) as illustrated in the accompanying figures. Besides the orientations shown in the figures, these spatial relative terms are intended to encompass different orientations of the elements in use or operation. The device may be positioned in different ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptive symbols used herein can be interpreted in the same manner.

[0077] Please refer to the following: Figure 1A Its drawing shows the gate electrode material 111 (such as...) Figure 1B The drawing shows a top view of the semiconductor wafer 100. In one embodiment, the semiconductor wafer 100 can be considered as having a central region 104 and an edge region 102. Figure 1A The document states that these areas are separated from each other by dashed circles, although these circles are not readily apparent in the actual product.

[0078] In one embodiment, during processes such as etching (see...) Figures 3A to 3C (Further explanation follows) The edge region 102 of the semiconductor wafer 100 may be a region potentially affected by the curves of the electric field and the plasma sheath. For example, in one embodiment, the entire semiconductor wafer 100 has a diameter of a first distance D1, wherein the first distance is between about 149 mm and about 300 mm, and the edge region 102 may have a first width W1, wherein the first width is between about 20 mm and about 25 mm (e.g., about 24 mm).

[0079] Figure 1B A close-up view of the structure on and within the semiconductor wafer 100 is shown, and as follows: Figure 1B The structures shown in the diagram are located in Figure 1A Within the edge region 102 of the illustrated semiconductor wafer 100. For example... Figure 1B The illustration shows a substrate 101 having first trenches 130 formed in the substrate 101. The substrate 101 may be a silicon substrate, however other substrates may be used (such as semiconductor-on-insulator (SOI), strained SOI, and germanium-on-insulator). The substrate 101 may be a p-type semiconductor; however, in other embodiments, the substrate 101 may be an n-type semiconductor.

[0080] In the final forming of the first insulating region 107, the first trench 103 can be formed as an initial step. With a suitable etching process, the first trench 103 can be formed using a masking layer (not shown individually). Figure 1B (In the middle). For example, the mask layer may be a hard mask comprising silicon nitride, which is formed by a process such as chemical vapor deposition (CVD). However, other materials (such as oxides, oxynitrides, silicon carbide, combinations of the above materials, or similar materials) and other processes (such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or forming silicon oxide followed by nitridation) may be used. Once formed, the mask layer may be patterned by a suitable lithography process to expose portions of the substrate 101, and these portions will be removed to form the first trench 103.

[0081] However, as will be known to those skilled in the art, the aforementioned processes and materials for forming the masking layer are not the only methods for protecting portions of the substrate 101 when other portions of the substrate 101 are exposed to form the first trench 103. Any suitable process (such as patterning and developing photoresist) can be used to expose and remove portions of the substrate 101 to form the first trench 103. All of these methods are intended to be fully encompassed within the scope of this embodiment.

[0082] Once the mask layer is formed and patterned, a first trench 103 is formed within the substrate 101. The exposed substrate 101 can be formed with the first trench 103 within the substrate 101 using a suitable process such as reactive ion etching (RIE); however, any suitable process can be used. In one embodiment, the first trench 103 can be formed from the surface of the substrate 101 with a depth of less than [missing information]. The first depth (as per approx.) ).

[0083] However, as will be known to those skilled in the art, the process described above for forming the first trench 103 is only one possible process and not the only embodiment. More precisely, any suitable process used to form the first trench can be used. Any suitable process including any number of masking and removal steps can be used.

[0084] In addition to forming the first trench 103, the masking and etching processes additionally form fins 105 on the portion of the substrate 101 that has not yet been removed. For convenience, these fins 105 are shown in the accompanying drawings and are separated from the substrate 101 by dashed lines; however, physical markings may or may not be present. As described below, these fins 105 can be used to form the channel regions of multi-gate fin field-effect transistors (FinFETs). Although Figure 1A Only three fins 150 are shown forming from the substrate 101; any number of fins 105 may be used. Furthermore, although the first insulating region 107 is described and / or shown as separate from the substrate 101, the term "substrate" as used herein may refer to a semiconductor substrate or a semiconductor substrate containing the first insulating region 107. Additionally, although the fins 105 are shown as a single continuous material like the substrate 101, the fins 105 and / or the substrate 101 may comprise a single material or multiple materials. In this context, the fins 105 refer to portions extending between adjacent first insulating regions 107.

[0085] Fins 105 are formed such that they have a second width W2 on the surface of substrate 101, wherein this second width is between approximately 5 nm and approximately 80 nm. Additionally, fins 105 may be spaced apart by a second distance D2, wherein this second distance is between approximately 21 nm and 26 nm. By spacing the fins 105 in this manner, each fin 105 can form a separate channel region, while being sufficiently close to share a common gate (further details below).

[0086] Fin 105 can be patterned using any suitable method. For example, fin 105 can be patterned using one or more photolithography processes, wherein these photolithography processes include dual patterning or multiple patterning processes. Generally, dual patterning or multiple patterning processes combine photolithography with self-alignment processes and allow patterns to be generated, for example, with a spacing smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned on a substrate by a photolithography process. Spacer walls are formed along the patterned sacrificial layer by a self-alignment process. The sacrificial layer is then removed, and the remaining spacer walls can then be used to pattern fin 105.

[0087] Once the first trench 103 and fin 105 are formed, the first trench 103 can be filled with dielectric material, and the dielectric material within the first trench 103 can be recessed to form a first insulating region 107. The dielectric material can be an oxide material, high-density plasma (HDP) oxide, or other similar oxide materials. The dielectric material can be formed by selectively cleaning and lining the first trench 103 using CVD methods (such as HARP process), high-density plasma CVD methods, or other suitable methods well known to those skilled in the art.

[0088] By initially overfilling dielectric material into the first trench 103 and the substrate 101, the dielectric material can be used to form a first insulating region 107. Excess material is then removed from the first trench 103 and the outer side of the fin 105 through a suitable process, such as chemical mechanical polishing (CMP), etching, a combination of the aforementioned processes, or similar processes. In one embodiment, the removal process also removes any dielectric material located on the fin 105, thus exposing the surface of the fin 105 to further process steps.

[0089] Once the first trench 103 has been filled with dielectric material, the dielectric material can then be removed from the surface of the fin 105. Removal can be performed to expose at least a portion of the sidewalls of the fin 105, wherein the sidewalls of the fin 105 are adjacent to the top surface of the fin 105. The dielectric material can be removed by wet etching by immersing the top surface of the fin 105 in an etchant such as hydrofluoric acid (HF); however, other etchants (such as hydrogen (H2)) and other methods (such as reactive ion etching, dry etching with an etchant such as ammonia / nitrogen trifluoride (NH3 / NF3), chemical oxide removal, or dry chemical cleaning) can be used. The dielectric material can be removed to a third distance D3 from the base of the fin 105, wherein the third distance is approximately... Peace Treaty In addition, the excavation can also remove any remaining dielectric material on the fin 105 to ensure that the fin 105 is exposed for further processing.

[0090] However, those skilled in the art will know that the above steps are only part of the complete process flow for filling and removing dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap-filling step, a combination of the above steps, and similar steps can also be used to form and fill dielectric material in the first trench 103. All possible process steps are intended to be fully included within the scope of the embodiments disclosed herein.

[0091] After the first insulating region 107 has been formed, the gate dielectric material 109 and the gate electrode material 111 can be formed on each fin 105. In one embodiment, the gate dielectric material 109 can be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other suitable method. Depending on the technique used to form the gate dielectric, the thickness of the gate dielectric material 109 on the tip of the fin 105 may differ from the thickness of the gate dielectric on the sidewalls of the fin 105.

[0092] The gate dielectric material 109 may comprise materials such as silicon dioxide or silicon oxynitride. The gate dielectric material 109 may be formed of a high-permeability (high-k) material (e.g., a relative permittivity greater than approximately 5) such as lanthanum oxide (La₂O₃), aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), or zirconium oxide (ZrO₂), or combinations thereof. Alternatively, any combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used as the gate dielectric material 109.

[0093] The gate electrode material 111 may comprise a conductive material and may be selected from the group consisting of polycrystalline silicon (poly-Si), polycrystalline silicon-germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, metals, combinations of the above materials, and similar materials. Examples of metal nitrides include tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride, or combinations of the above metal nitrides. Examples of metal silicides include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, or combinations of the above metal silicides. Examples of metal oxides include ruthenium oxide, indium tin oxide, or combinations of the above metal oxides. Examples of metals include tungsten, titanium, aluminum, copper, molybdenum, nickel, platinum, etc.

[0094] The gate electrode material 111 can be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques suitable for depositing conductive materials. The thickness of the gate electrode material 111 can be in the range of about 150 nm to about 180 nm (e.g., about 160 nm). The top surface of the gate electrode material 111 can have a non-polar top surface and can be planarized before patterning the gate electrode material 111 or etching the gate. In this case, ions may or may not be introduced into the gate electrode material 111. For example, ions can be implanted using ion implantation techniques.

[0095] Figures 2A to 2B According to some embodiments, a hard mask and photoresist are formed on the gate electrode material 111, wherein... Figure 2B yes Figure 2A A cross-sectional view along line segment B-B'. Once the hard mask and photoresist are formed, they are used to pattern the gate dielectric material 109 and the gate electrode material 111 to form a series of gate stacks 415 on the fin 105 (illustrated in...). Figures 4A to 4BOnce the gate stack 415 is patterned, it will form multiple channel regions located on each side of the fin and below the gate dielectric material 109. In some embodiments, patterning of the gate stack 415 can be initiated by depositing a first hard mask 201 and a second hard mask 203 on the gate electrode material 111. According to some embodiments, the first hard mask 201 may be a material such as silicon oxide and formed by a deposition process such as chemical vapor deposition or physical vapor deposition, or by a thermal oxidation process. However, any suitable material and process can be used to form the first hard mask.

[0096] Once the first hard mask 201 is formed, a second hard mask is formed on top of the first hard mask. In one embodiment, the second hard mask 203 comprises a dielectric material such as silicon nitride, titanium nitride, silicon oxynitride, a combination of the above materials, or similar materials. The second hard mask 203 is formed by a process such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or similar methods. However, any other suitable materials and methods may be used to form the second hard mask.

[0097] Figures 2A to 2B Also illustrated is a first photoresist 205 placed and patterned on a second hard mask 203. In one embodiment, the first photoresist 205 is a tri-layer photoresist, wherein the tri-layer photoresist has a bottom anti-reflective coating (BARC), a middle mask layer, and a top photoresist layer (not individually shown). Figures 2A to 2B (In Chinese). However, any suitable type of photosensitive material or combination of materials can be used.

[0098] Once the first photoresist 205 has been placed on the second hard mask 203, the first photoresist 205 is patterned. In one embodiment, the first photoresist 205 can be patterned by exposing the photosensitive material (such as the top photoresist layer in a three-layer photoresist) within the first photoresist 205 to a patterning energy source (such as light) through a reticle. The impact of the energy will cause a chemical reaction in the portion of the photosensitive material impacted by the patterning energy source, thereby changing the physical properties of the exposed portion of the photoresist. Therefore, the physical properties of the exposed portion of the first photoresist 205 are different from the physical properties of the unexposed portion of the first photoresist 205. To separate the unexposed portion of the first photoresist 205 from the exposed portion, the first photoresist is then developed with a developer (not shown individually).

[0099] Furthermore, although the placement of the first photoresist 205 has been described above, the embodiments are not intended to limit the use of the first photoresist 205. Rather, any suitable patterning process can be used (such as placing the first photoresist 205 and patterning it within mandrels). Spacer walls (not shown individually) can then be formed on the opposite side of the mandrels, and the mandrels can be removed, leaving the spacer walls, which can be used to replace the first photoresist 205. Any suitable process can be used to form the mask, and all such processes are intended to be fully included within the scope of the embodiments.

[0100] In one embodiment, the first photoresist 205 is patterned so that the first photoresist 205 can be used to form a gate stack 415 (not shown). Figures 2A to 2B However, refer to Figures 4A to 4B (Illustrated and described below). Therefore, the formed first photoresist 205 has a third width W3 between approximately 20 nm and 24 nm. Additionally, the separated portions of the formed first photoresist 205 are separated by a fourth distance D4 between approximately 42 nm and 47 nm. However, any suitable dimensions can be used.

[0101] The aforementioned advanced lithography processes, methods, and materials can be used in a variety of applications, including patterned dielectric layers overlaying conductors or patterned fin-type field-effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacing between adjacent features, as previously disclosed, and are well-suited for this purpose. Furthermore, the spacer walls (also known as mandrels) used to form the fins of FinFETs can be fabricated according to the previously disclosed methods.

[0102] Figures 3A to 3C The illustration shows the start of the etching process to pattern the gate dielectric material 109 and the gate electrode material 111 using a first photoresist 205, thereby forming a gate stack 415. (Example:) Figure 3A As illustrated, an etching process can be initiated by placing a semiconductor wafer 100 (accompanied by a gate electrode material 111, a gate dielectric material 109, a first hard mask 201, and a second hard mask 203) within an etching system 300. In some embodiments, the etching system 300 may include an etchant delivery system 303 for delivering one or more vapor-phase etchants to an etching chamber 304. The etchant delivery system 303 provides various desired etchants to the etching chamber 304 via an etchant controller 313 and a manifold 305. The etchant delivery system 303 also helps control the flow rate of a single or multiple etchants entering the etching chamber 304 by controlling the airflow and pressure of the carrier gas flowing through the etchant delivery system 303.

[0103] In one embodiment, the etchant delivery system 303 may include multiple etchant suppliers 311 along with the carrier gas supplier 307. Although only two etchant suppliers 311 are shown... Figure 3A (Drawn for simplicity only), any suitable number of etchant suppliers 311 can be used (e.g., in etching system 300, one etchant supplier 311 can be used for each etchant to be used). For example, in one embodiment, five separate etchants will be used, i.e., there are five etchant suppliers 311.

[0104] Each etchant supply 311 is a container (such as a gas storage tank) and is located near or away from the etching chamber 304. In other embodiments, the etchant supply 311 is a facility that independently prepares and delivers the required etchant. Any suitable source of the required etchant may be used as the etchant supply 311, and all such sources are intended to be fully included within the scope of the embodiments.

[0105] In some embodiments, each etchant supplier 311 supplies etchant to an etchant controller 313 via a first conduit 302 having a first valve 308. The first valve 308 is controlled by a controller 327, which controls and regulates the respective etchants and carrier gases directed to the etching chamber 304.

[0106] Carrier gas supplier 307 provides the required carrier gas (or dilution gas), which can be used to assist in pushing or transporting the various etchants to the etching chamber 304. The carrier gas can be an inert gas or other gas that does not react with the etchant itself or with byproducts of the etchant reaction process. For example, the carrier gas is nitrogen (N2), helium (He), argon (Ar), combinations of the above, or similar gases; however, other suitable carrier gases can be used.

[0107] The carrier gas supplier 307 or diluent supplier is a container (such as a gas storage tank) located at or away from the etching chamber 304. In other embodiments, the carrier gas supplier 307 may be a facility that independently prepares and delivers carrier gas to the etchant controller 313. Any suitable source of carrier gas can be used as the carrier gas supplier 307, and all such sources are intended to be fully included within the scope of this embodiment. The carrier gas supplier 307 supplies the required carrier gas to the etchant controller 313 via a second conduit 310 connecting the carrier gas supplier 307 to the first conduit 302. The second valve 306 is controlled by a controller 327, which controls and regulates the various etchants and carrier gases introduced into the etching chamber 304. Once combined, these conduits lead directly to the etchant controller 313, which serves as the control inlet to the etching chamber 304.

[0108] The etching chamber 304 can be any desired shape suitable for dispersing the etchant and contacting the substrate 101 with the etchant. Figure 3A In the illustrated embodiment, the etching chamber 304 has cylindrical sidewalls and a bottom. However, the etching chamber 304 is not limited to a cylindrical shape and may use any other suitable shape (such as a hollow square tube, an octagon, or a similar shape). Furthermore, the etching chamber 304 may be surrounded by an etchant chamber housing 315, wherein the etchant chamber housing 315 is made of a material that is inert to the process materials. Therefore, the etchant chamber housing 315 may be any suitable material that can withstand the chemicals and pressures involved in the etching process, and in some embodiments, the etchant chamber housing 315 may be steel, stainless steel, nickel, aluminum, alloys of the above materials, combinations of the above materials, and similar materials.

[0109] Additionally, the etching chamber 304 and the setup platform 345 may be part of a clustered tooling system (not shown). The clustered tooling system may be combined with an automated handling system to position and place the semiconductor wafer 100 into the etching chamber 304 before the etching process, to position and hold the semiconductor wafer 100 during the etching process, and to remove the semiconductor wafer 100 from the etching chamber 304 after the etching process.

[0110] During the etching process, a platform 345 is positioned within the etching chamber 304 to position and control the semiconductor wafer 100. The platform 345 may use electrostatic force, jigs, vacuum pressure, a combination of the above methods, or similar methods to fix the semiconductor wafer 100, and the platform may also include heating and cooling mechanisms to control the temperature of the semiconductor wafer 100 during the process.

[0111] Additionally, the platform 345 may include a first electrode 320 coupled to the radio frequency generator 322. During the etching process, the first electrode 320 is electrically biased by the radio frequency generator 322 (under the control of the controller 327) at an RF voltage. According to some embodiments, the radio frequency generator 322 may provide an AC voltage. However, any suitable voltage may be used. By electrically biasing, the first electrode 320 is used to provide a bias voltage to the introduced etchant and assist in igniting the etchant into plasma and assisting in the extraction from the plasma sheath 359 (not shown). Figure 3A However, refer to Figure 3B (Illustrated and described below) Accelerated ions, wherein the ions are accelerated toward the semiconductor wafer 100 in a direction orthogonal to the upper surface of the semiconductor wafer 100.

[0112] Please refer to the following: Figure 3B and Figure 3A ,in Figure 3B The edge ring 357 is illustrated. When the edge ring 357 is newly installed, the plasma sheath 359 is located at a first distance Dist1 from the semiconductor wafer 100 and a second distance Dist2 from the edge ring 357. Additionally, during operation, although ions from the plasma sheath 359 will travel along the plasma sheath 359 (in... Figure 3B The central region (indicated by arrow 319) accelerates at an angle perpendicular to the semiconductor wafer 100, while in the surrounding region 361 of the plasma sheath 359, the plasma sheath 359 tends to bend downwards. Figure 3B and 3C (Indicated by the dashed line 362), this results in a non-planar curve in the region 361 surrounding the plasma sheath 359. This non-planar curve within the surrounding region 361 may also be referred to herein as the curvature or edge tilt of the plasma sheath 359. When the surrounding region 361 of the plasma sheath 359 is curved, and ions from the plasma enter this surrounding region 361, these ions will still be accelerated, but not at an angle perpendicular to the upper surface of the semiconductor wafer 100. Instead, the ions will be accelerated at an angle not perpendicular to the upper surface of the semiconductor wafer 100 (…). Figure 3B (As indicated by arrow 331) Acceleration. Therefore, the trenches and / or openings of the edge region 102 of the etched semiconductor wafer 100 can be formed with a non-perpendicular profile.

[0113] Therefore, during the etching process, the first electrode 320 can be used to assist in extending the plasma sheath 359 of ions beyond the edge region 102 of the semiconductor wafer 100 and onto the mounting platform 345. Extending the plasma sheath 359 beyond the edge region 102 of the semiconductor wafer 100 helps to accelerate ions from the plasma sheath 359 in a direction orthogonal to the upper surface of the semiconductor wafer 100, or even orthogonal to the edge region 102 of the semiconductor wafer 100. Consequently, the grooves 347 etched into the upper surface of the semiconductor wafer 100 (including the grooves 347 etched into the edge region 102 of the semiconductor wafer 100) form more vertical profiles.

[0114] Additionally, to further shape the plasma sheath 359, platform 345 includes a second electrode 324 coupled to a DC power supply 326. During the etching process, the second electrode 324 is electrically biased with a DC voltage by the DC power supply 326 (under the control of controller 327). According to some embodiments, the DC power supply 326 applies a DC voltage. However, any suitable voltage can be used. Although the RF generator 322 and the DC power supply 326 are depicted as separate units, according to some embodiments, a single unit can be used to generate both AC and DC voltages. The second electrode 324, via electrical bias, is used to provide electric field control 328 during the etching process to maintain the plasma sheath 359 in a horizontal plane parallel to the upper surface of the edge ring 357. Figure 3B (As indicated by arrow 317). By maintaining the surrounding region 361 of the plasma sheath 359 on a horizontal plane, it helps to accelerate the entry of ions into the surrounding region 361 and towards the edge region 102 of the semiconductor wafer 100 in a direction orthogonal to the upper surface of the semiconductor wafer 100. Therefore, the grooves 347 etched into the edge region 102 of the semiconductor wafer 100 are etched with a vertical profile.

[0115] With the additional control provided by the second electrode 324 and the DC power supply 326, the groove 347 formed in the edge region has more vertical sidewalls. For example, the groove 347 formed in the edge region has a depth between about 63.43 nm and about 84.72 nm, and the formed groove 347 has a substantially vertical profile with an angle between about 88.37 degrees and about 91.63 degrees (such as about 90.06 degrees from the horizontal plane of the upper surface of the fin 105). However, any suitable size can be used.

[0116] Look more closely Figure 3B , Figure 3BA close-up view of a portion of a setup platform 345 is shown, illustrating a portion of a semiconductor wafer 100 and the setup platform 345. As can be seen, the setup platform 345 in this view may include various components to assist in securing and holding the semiconductor wafer 100 before, during, and after the etching process. In the illustrated embodiment, the setup platform 345 includes a first chuck 351 and an edge ring 357.

[0117] In some embodiments, the first chuck 351 is an electrostatic chuck, wherein this electrostatic chuck not only uses the first electrode 320 to generate and maintain plasma during the etching process, but also uses the electrostatic force generated by the first electrode 320 to fix and support the semiconductor wafer 100 on the setting platform 345. Therefore, the first electrode 320 is attached to the first chuck 351. However, any suitable chuck combination (such as a clamp chuck or a vacuum chuck) can be used with the first electrode 320.

[0118] According to some embodiments, the first suction cup 351 includes a suction cup edge portion 352 that facilitates placement of the edge ring 357. Figure 3B (shown by dashed lines). In some embodiments, the first suction cup 351 extends inward to allow the edge ring 357 to align with the suction cup edge portion 352, wherein the suction cup edge portion 352 extends below the edge ring 357 and assists in supporting the edge ring 357. Therefore, the precise dimensions of the suction cup edge portion 352 depend at least on the size and shape of the edge ring 357.

[0119] In some embodiments, the suction cup edge portion 352 extends only partially beneath the edge ring 357. In these embodiments, a first bottom ring (not shown) may be placed adjacent to the suction cup edge portion 352 and serves to assist in supporting the edge ring 357. In these embodiments, the first bottom ring is made of a material such as quartz; however, any other suitable material (such as silicon carbide or ceramic) may also be used.

[0120] An edge ring 357 is located on the edge portion 352 of the first chuck 351 and the first bottom ring (assuming it exists), and helps to provide fine positioning of the semiconductor wafer 100 on the first chuck 351, and also includes the removal of the semiconductor wafer 100 from the first chuck 351 before the semiconductor wafer 100 is picked up onto the first chuck 351 (e.g., before applying electrostatic force if the first chuck 351 is an electrostatic chuck). Furthermore, the edge ring 357 also helps to shield the first chuck 351 from damage during the etching process. Therefore, in one embodiment, the edge ring 357 is located above the edge portion 352 of the first chuck 351 and above the first bottom ring (assuming it exists), so that a portion of the top surface of the first chuck 351 is not directly exposed to plasma during the etching process.

[0121] In one embodiment, an edge ring 357 is shaped to assist in positioning the semiconductor wafer 100. In a particular example, the edge ring 357 has, for example, a vertical support segment 365 and a horizontal support segment 363. Figure 3B and 3C The two sections shown are separated by a dashed line.

[0122] According to some embodiments, the horizontal support segment 363 may have a fifth width W5 between about 24 mm and about 25 mm, and a second thickness T2 greater than the thickness of the semiconductor wafer 100, wherein the second thickness is between about 2 mm and about 5 mm. Additionally, the vertical support segment 365 has a sixth width W6 between about 26 mm and about 27 mm, and a third thickness T3 between about 0.3 mm and about 0.7 mm. When combined, the second thickness T2 and the third thickness T3 have a combined thickness between about 2.3 mm and about 5.7 mm. However, any suitable dimensions can be used.

[0123] According to some embodiments, the edge ring 357 may be made of a material that facilitates electric field control 328 generated by the first electrode 320 and the second electrode 324 during the etching process, and this material may be electrically insulated from the first electrode 320. For example, in one embodiment, the edge ring 357 may be made of a high electron mobility material such as silicon-doped nitrogen (silicon nitride), silicon-doped carbon (silicon carbide), silicon-doped fluorine (silicon fluoride), silicon-doped oxygen (silicon oxide), combinations of the above materials, or similar materials. As further described below, by forming the edge ring 357 with a material having high electron mobility (compared to materials with low electron mobility such as quartz or diamond-zincblende structures), the electric field generated by the etching cavity 304 will extend further beyond the edge ring 357.

[0124] In one embodiment, the high electron mobility material is nitrogen-doped silicon, where nitrogen has an atomic concentration between about 55% and about 65% (e.g., about 60%). In one embodiment, the high electron mobility material is carbon-doped silicon, where carbon has an atomic concentration between about 45% and about 55% (e.g., about 50%). In one embodiment, the high electron mobility material is fluorine-doped silicon, where fluorine has an atomic concentration between about 70% and about 80% (e.g., about 75%). In one embodiment, the high electron mobility material is oxygen-doped silicon, where oxygen has an atomic concentration between about 55% and about 65% (e.g., about 60%). However, any dopant of suitable concentration can be used.

[0125] Figure 3BAccording to some embodiments, an edge ring 357 is also illustrated, wherein the edge ring 357 includes an electric field coil 367. The electric field coil 367 generates and / or modifies an electric field control 328 in response to a DC voltage applied to the second electrode 324. In some embodiments, the electric field control 328 can be generated by combining an AC voltage applied to the first electrode 320 with a DC voltage applied to the second electrode 324. However, in some embodiments, the electric field control 328 can be generated by either an AC voltage applied to the first electrode 320 or a DC voltage applied to the second electrode 324 (independent of another voltage).

[0126] Figure 3C A close-up view of a portion of the platform 345 is illustrated according to some embodiments, wherein the edge ring 357 is no longer newly installed, but wears down over time and after repeated use (such as multiple semiconductor wafers, including placing, etching, and removing a second semiconductor wafer for further processing). In particular, repeated exposure to the etchant released within the etching chamber 304 causes the edge ring 357 to wear down over time, thus reducing the thickness of the edge ring 357 and / or altering its shape. Figure 3C The second thickness T2 and the third thickness T3 are shown, where the second thickness and the third thickness have been reduced from the original thickness by thickness differences ΔT2 and ΔT3, respectively, while the second distance Dist2 has been increased (and the first distance remains unchanged).

[0127] To help explain the reduction in thickness, the electric field control 328 can be incrementally changed over time and / or after repeated use of the edge ring 357 by applying a suitable DC voltage during subsequent semiconductor wafer (such as a second semiconductor wafer) processing. The suitable DC voltage compensates for the thickness differences ΔT2 and ΔT3 and / or the shape of the edge ring. Therefore, even as the overall thickness and / or shape of the edge ring 357 wears down, the DC voltage applied during operation maintains the plasma sheath 359 in a plane parallel to the upper surface of the semiconductor wafer 100 and the edge ring 357. In some embodiments, during operation, a DC voltage can be applied to the second electrode 324 to control the electric field control 328, where this DC voltage is based on the wear of the edge ring 357. According to some embodiments, the DC voltage can be adjusted when the thickness of the edge ring 357 has decreased by thickness differences ΔT2 and ΔT3. However, any suitable voltage can be used.

[0128] Now come back for reference Figure 3AIn some embodiments, the etching chamber 304 includes a showerhead 329. In one embodiment, the showerhead 329 receives individual etchants from the manifold 305 and helps disperse the individual etchants into the etching chamber 304. To minimize unwanted process conditions that may arise from uneven dispersion, the showerhead 329 may be designed to uniformly disperse the etchant. In one embodiment, the showerhead 329 may have a circular design with openings evenly distributed around the showerhead 329 to allow the desired etchant to be dispersed into the etching chamber 304. However, any suitable method for introducing the desired etchant (such as an inlet port) may be used to introduce the desired etchant into the etching chamber 304.

[0129] The etching chamber 304 also includes an upper electrode 321 (as a plasma generator). In one embodiment, the plasma generator may be a transformer-coupled plasma generator and may be a coil. This coil may be attached to a second radio frequency generator 323, which is used to provide power to the upper electrode 321 (under the control of the controller 327) to excite plasma during the introduction of reactive etchant.

[0130] However, while the aforementioned upper electrode 321 is a transformer-coupled plasma generator, the embodiments are not intended to limit them to transformer-coupled plasma generators. Rather, any suitable method for generating plasma (such as inductively coupled plasma systems, magnetically enhanced reactive ion etching, electron cyclotron resonance, remote plasma generators, or similar methods) may be used. All of these methods are intended to be included within the scope of the embodiments.

[0131] The etching chamber 304 can also be connected to a vacuum pump 325. In one embodiment, the vacuum pump 325 is controlled by a controller 327 and used to control the pressure in the etching chamber 304 to the required pressure. Additionally, once the etching process is complete, the vacuum pump 325 can be used to evacuate the etching chamber 304 in preparation for the removal of the semiconductor wafer 100.

[0132] Furthermore, while many of the specific components of the aforementioned etching system 300 are described, other suitable components may also be included. For example, endpoint mounts, gaskets, and any components that may aid in the operation or control of the etching process may also be included. All of these components are intended to be included within the scope of this embodiment.

[0133] Please refer to Figures 3A to 3CTo begin patterning the gate electrode material 111 and the gate dielectric material 109, the process can be initiated by placing the semiconductor wafer 100 on the setup platform 345, wherein placing the semiconductor wafer 100 is at least partially guided by using an edge ring 357 to align the semiconductor wafer 100 with the first chuck 351. Once the semiconductor wafer 100 has been placed on the first chuck 351, a substrate can be attached to the first chuck 351 using additional processes. In one embodiment, where the first chuck is an electrostatic chuck, the semiconductor wafer 100 can be attached to the first chuck 351 by applying a first current (such as alternating current) to the first electrode 320, so that electrostatic force will apply a force to secure the semiconductor wafer 100 to the additional surface of the first chuck 351. During operation, the application of the first current to the first electrode 320 can be used to extend the plasma sheath 359 formed in the etching cavity 304 beyond the edge region 102 of the semiconductor wafer 100.

[0134] According to some embodiments, during operation, a second current (such as direct current) may be applied to the second electrode 324. During operation of the etching cavity 304, the second current may be used to control the plasma sheath 359 to maintain a planar orientation parallel to the upper surface of the semiconductor wafer 100 and the edge ring 357.

[0135] Once the semiconductor wafer 100 has been placed and attached to the first chuck 351, the controller 327 can begin the etching process by connecting one or more etchant suppliers 311 and another current-carrying gas supplier 307 to the etching chamber 304 to introduce a first etch combination of etchant. While the precise etchant used depends at least in part on the materials selected for the gate dielectric material 109, the gate electrode material 111, the first hard mask 201, and the second hard mask 203, in one embodiment, the first etch combination of etchant comprises a combination of hydrogen chloride (HCl) and oxygen (O2), accompanied by a second diluent such as nitrogen (N2). In one embodiment, oxygen is introduced at a rate between about 2 sccm and about 10 sccm (e.g., about 5 sccm), nitrogen is introduced at a rate between about 5 sccm and about 25 sccm (e.g., about 15 sccm), and hydrogen is introduced at a rate between about 5 sccm and about 15 sccm (e.g., about 10 sccm). However, any suitable etchant or combination of etchant and diluent can be used.

[0136] In the etching chamber 304, as part of a reactive ion etching process, a first etch combination of etchant is excited into plasma. In one embodiment, the first etch combination of etchant is excited by a controller 327, which sends a signal to a second radio frequency generator 323 to provide a power supply between approximately 150W and approximately 550W (e.g., approximately 350W) to the upper electrode 321. The controller 327 may also send a signal to a radio frequency generator 322 to provide an AC voltage in the first chuck 351 to the first electrode 320. In one embodiment, the radio frequency generator 322 provides an AC voltage between approximately 60V and approximately 180V. However, any suitable voltage may be used.

[0137] In some embodiments, the controller 327 also sends a signal to the DC power supply 326 to provide a DC voltage to the second electrode 324 of the edge ring 357, based at least in part on the length of time the edge ring 357 has been installed or on the thickness of the edge ring 357. For example, when the edge ring 357 has been newly installed, the DC power supply 326 provides a first DC voltage. However, when the edge ring 357 has been reduced in thickness by thickness differences ΔT2 and ΔT3, the DC power supply 326 provides a second, different DC voltage.

[0138] By using an RF generator 322 to provide an AC voltage to the first electrode 320 within the first chuck 351, the electric field interacts with the plasma sheath 359 (shown in solid lines). Figure 3B and 3C The ions will be generated on the surface of the semiconductor wafer 100, with the semiconductor wafer 100 facing away from the first chuck 351. The electric field control 328 and the plasma sheath 359 will assist in moving and accelerating the ions from the plasma to the surface to be etched (such as the second hard mask, the first hard mask, the gate electrode material 111 and the gate dielectric material 109).

[0139] However, as mentioned above and as Figure 3B and 3C As seen, in the region 361 surrounding the plasma sheath 359, the electric field and the plasma sheath 359 tend to bend towards the semiconductor wafer 100 and the edge ring 357. Therefore, the plasma sheath 359 will bend downwards, resulting in a non-planar curve within the region 361 surrounding the plasma sheath 359 (shown by the dashed line 362). Figure 3B and 3C(In the case of bending, without compensation, when ions from the plasma enter the surrounding region 361 of the plasma sheath 359, the plasma sheath 359 will still accelerate the ions, but not at angles perpendicular to the semiconductor wafer 100. Instead, these ions will be accelerated at angles not perpendicular to the semiconductor wafer 100, resulting in an angled pattern relative to the semiconductor wafer 100, rather than the desired perpendicular pattern transfer. Furthermore, not only does the non-perpendicular pattern transfer exist, but this non-perpendicular transfer only occurs in the edge region 102 of the semiconductor wafer 100. In particular, in the central region 104 of the semiconductor wafer 100, the plasma sheath 359 will have a relatively planar shape, allowing ions entering the plasma sheath 359 to be vertically accelerated toward the semiconductor wafer 100 in this region.) Therefore, between the vertical acceleration in the central region 104 and the non-vertical acceleration in the edge region 102 of the semiconductor wafer 100, a non-uniform effect exists across the semiconductor wafer 100, depending on the distance from the surrounding region 361 of the plasma sheath 359 to the semiconductor wafer 100.

[0140] However, as described above, by forming an edge ring 357 and applying a second voltage to the edge ring 357, the plasma sheath 359 on the semiconductor wafer 100 and the edge ring 357 can avoid being concave and maintain a planar surface. Therefore, any ions entering the surrounding region 361 of the plasma sheath 359 are accelerated at a vertical angle to impact multiple layers of the semiconductor wafer 100 to be etched (such as the second hard mask 203, the first hard mask 201, the gate electrode material 111, and the gate dielectric material 109) or directly impact the edge ring 357.

[0141] Furthermore, by extending the plasma sheath so that the surrounding region 361 is located on the edge ring 357, and by maintaining the planar orientation, ions accelerated toward the edge region 102 will move toward the semiconductor wafer 100 at a near-perpendicular angle, rather than at a non-perpendicular angle. Therefore, the pattern required for vertical transfer will occur, and a more uniform patterning across the semiconductor wafer 100 can be obtained.

[0142] In addition, such as Figure 3C The dashed outline 364 illustrates how, over time and with repeated use, the edge ring 357 gradually loses material through various etching processes. Consequently, the edge ring 357 eventually wears down over time, and its thickness and / or shape deteriorates. When the second thickness T2, the third thickness T3, and / or the shape of the edge ring 357 deteriorate, a second voltage is increased to compensate for the thickness loss and / or to change the shape of the edge ring 357. Therefore, even as the edge ring 357 wears down, the plasma sheath 359 remains planar on the semiconductor wafer 100 and the edge ring 357.

[0143] According to some embodiments, the second voltage can be increased by multiplying the usage time of the edge ring 357 by a voltage / time factor, a shape factor, and / or a thickness factor. The usage time depends on the material of the edge ring 357, the original thickness of the edge ring 357, and the type and concentration of the etchant used in each etching process. According to some embodiments, as the edge ring 357 ages, adjusting the second voltage can increase its usage time by more than approximately 800 hours. Therefore, the edge ring 357 can be reused multiple times before needing replacement, or even outlast other components of the platform.

[0144] Continued Figures 3A to 3C And refer to Figures 4A to 4B Once the plasma has been excited and the ions are oriented toward the semiconductor wafer 100, the process conditions described above are maintained to expose the second hard mask 203 to the plasma generated in the etching chamber, and the exposed portion of the second hard mask 203 is removed. Once the pattern of the first photoresist 205 has been transferred to the second hard mask 203, the etching process can then transfer the pattern to the first hard mask 201. In one embodiment, the first etch combination of the etchant etches both the first hard mask 201 and the second hard mask 203, and the etching process can be easily continued without changing the first etch combination of the etchant. In another embodiment, if necessary, the first etch combination of the etchant can be changed by a controller 327, wherein the controller 327 connects one or more other etchant suppliers 311 and another carrier gas supplier 307 to the etching chamber 304 to introduce a second etch combination of the etchant. However, any suitable method may be used.

[0145] Similarly, once the pattern of the second hard mask has been transferred to the first hard mask 201, the etching process can continue to transfer the pattern to the underlying gate electrode material 111 and generate the gate electrode 401. In one embodiment, where the first etch combination of the etchant etches the gate electrode material 111, the first hard mask 201, and the second hard mask 203, the etching process can be easily continued without changing the first etch combination of the etchant. In another embodiment, if necessary, the first etch combination of the etchant (or the second etch combination of the etchant, if the second etch combination of the etchant has been used) can be changed by a controller 327, wherein the controller 327 connects one or more other etchant suppliers 311 and another carrier gas supplier 307 to the etching chamber 304 to introduce a third etch combination of the etchant. However, any suitable method can be used.

[0146] Finally, once the pattern of the first hard mask 201 has been transferred to the gate electrode material 111 to form the gate electrode 401, an etching process can be continued to transfer the pattern to the gate dielectric material 109 to form the gate dielectric 403 and the gate stack 415 (from the gate dielectric 403 and the gate electrode 401). In one embodiment, where the first etch combination of the etchant etches the gate dielectric material 109 and the gate electrode material 111, the first hard mask 201 and the second hard mask 203, the etching process can be simply continued without changing the first etch combination of the etchant. In another embodiment, if necessary, the first etch combination of the etchant (or the second etch combination of the etchant or the third etch combination of the etchant, if the second etch combination of the etchant or the third etch combination of the etchant has been used) can be changed by a controller 327, wherein the controller 327 connects one or more other etchant suppliers 311 and another current-carrying gas supplier 307 to the etching chamber 304 to introduce a fourth etch combination of the etchant. However, any suitable etchant combination can be used.

[0147] At this point, the first photoresist 205 can be removed if necessary. In one embodiment, the first photoresist 205 can be removed by a thermal process such as ashing, thus increasing the temperature of the first photoresist until the first photoresist 205 undergoes thermal decomposition and is removed. However, any suitable removal process (such as wet or dry etching) can be used to remove the first photoresist 205.

[0148] As described above, through the etching process and edge ring 357, the ion flux used during the etching process can extend beyond the semiconductor wafer 100. Therefore, ion flux congestion occurring near the edge of the semiconductor wafer 100 can be shifted to the edge ring 357 and not onto the semiconductor wafer 100. Furthermore, the ion flux will have less congestion on the semiconductor wafer 100, thereby inducing a more uniform flux and less variation in the gate electrode 401, which is adjacent to the edge region 102 of the semiconductor wafer 100.

[0149] Figures 4A to 4B An embodiment is illustrated, wherein reference is made to Figures 3A to 3C The aforementioned etching process is used to form the four elements of the gate electrode 401 on the fin 105, and Figure 4B yes Figure 4A A cross-sectional view along line segment B-B'. For example, in one embodiment, as described above with edge ring 357, gate electrode 401 has a first pitch between about 65 nm and about 68 nm. Additionally, the opening 405 formed by the etching process between the gate electrodes 401 may have an aspect ratio greater than about 3.5 or 4.0.

[0150] According to some embodiments, Figure 4BThe diagram also shows that the opening 405 in the edge region 102 of the semiconductor wafer 100 is a recess 347 (refer to the above). Figures 3A to 3B Therefore, the opening 405 formed in the edge region 102 of the semiconductor wafer 100 can be substantially formed in a vertical profile. According to some embodiments, the opening 405 can be formed in a vertical profile, wherein this vertical profile has an angle θ (such as about 88.37 degrees, 91.63 degrees or 90.06 degrees) between about 88 degrees and about 92 degrees from the upper surface of the fin 105.

[0151] However, while the etching tools and processes for etching the gate electrode and gate dielectric have been described above, these descriptions of this embodiment are not intended to limit the embodiments to what is described herein. Rather, the aforementioned processes can be applied to any suitable etching process. For example, an etching process can be performed to etch a dielectric material located on a metal layer used for internal interconnecting wires. Any suitable etching process can utilize the foregoing, and all such processes are fully intended to be included within the scope of the embodiments.

[0152] Figure 5 The illustration shows that once the gate stack 415 has been patterned, the first hard mask 201 and the second hard mask 203 can be removed, and a first spacer wall 501 can be formed, with the fin 105 having a portion not covered by the gate stack 415 and with the first spacer wall 501 removed. In one embodiment, the first hard mask 201 and the second hard mask 203 are removed using an etching process such as wet etching or dry etching. However, any suitable removal process can be used.

[0153] A first spacer wall 501 may be formed on the opposite side of the gate stack 415. This is essentially achieved by covering and depositing a spacer wall layer (not individually shown in the diagram). Figure 5 On the previously formed structure, a first spacer 501 may be formed. The spacer layer may comprise silicon nitride (SiN), oxynitride, silicon carbide (SiC), silicon oxynitride (SiON), oxides, and similar materials, and may be formed by methods used to form this layer (such as chemical vapor deposition, plasma-assisted chemical vapor deposition, and other conventional methods). The spacer layer may comprise different materials with different etching properties or the same dielectric material as in the first insulating region 107. The first spacer 501 may then be patterned (e.g., by removing the spacer layer from the horizontal surface of the structure through one or more etching operations) to form the first spacer 501.

[0154] Figure 5The diagram also illustrates the removal of fins 105 from these areas not protected by the gate stack 415 and the first spacer wall 501. Removal can be performed by reactive ion etching (RIE) using the gate stack 415 and the first spacer wall 501 as a mask, or by any other suitable removal process. This removal continues until the fins 105 are coplanar with or below the surface of the first insulating region 107.

[0155] Once the fins 105 have been removed from the areas not protected by the gate stack 415, the source / drain regions 503 can regrow from the exposed portions of the substrate 101 and contact each fin 105. In one embodiment, the source / drain regions 503 can regrow to form a pressure source that applies pressure to the channel regions of the fins 105 located below the gate stack 415. In one embodiment, where the fins 105 comprise silicon and the FinFET is a p-type device, the source / drain regions 503 can be regrowed via a material-selective epitaxial process (such as silicon-germanium having a different lattice constant than the fins 105). The epitaxial growth process uses precursors such as silanes, dichlorosilanes, germanes, and similar materials, and lasts between approximately 5 minutes and approximately 120 minutes. The source / drain regions 503 can be formed to have a height of approximately 5 nm to 250 nm on the upper surface of the first insulating region 107.

[0156] Figure 6 Drawing about Figures 1A to 5 While the tools and processes described above can be used to form the gate electrode 401, the embodiments are not limited to these precise processes. For example, the diagram shown... Figure 6 In one embodiment, once the gate electrode 401 has been patterned, the first spacer wall 501 and the source / drain region 503 have been formed, and the first interlayer dielectric 601 has been deposited and planarized to form the second interlayer dielectric 603 and the gate contact 605, thereby creating an electrical connection to one or more of the gate electrodes 401. In one embodiment, the first interlayer dielectric 601 and the second interlayer dielectric 603 may comprise materials such as boronphosphorous silicate glass (BPSG), however any suitable dielectric may be used, and a deposition process such as PECVD may be used, however other processes (such as LPCVD) may be used. Once the second interlayer dielectric 603 has been deposited, the gate contact 605 may be formed using a damascene or dual damascene process.

[0157] Additionally, once the gate contact 605 has been formed, a first etch stop layer 607 and a third interlayer dielectric 609 are deposited on the gate contact 605. In one embodiment, the first etch stop layer 607 may be a material such as silicon nitride, silicon oxynitride, silicon oxide, a combination of the above materials, or a similar material, while the third interlayer dielectric 609 may be a material similar to the second interlayer dielectric 603. However, any suitable material may be used.

[0158] Once the third interlayer dielectric 609 has been deposited, it can be patterned using a first photoresist 611. In one embodiment, the first photoresist 611 can be a tetralayer photoresist, comprising a first bottom antireflective coating 613, an intermediate masking layer 615, a second bottom antireflective coating 617, and a top photosensitive layer 619. However, any suitable photoresist and any suitable number of layers can be used.

[0159] A first bottom anti-reflective coating 613 is used in preparation for the application of the top photosensitive layer 619. During exposure of the top photosensitive layer 619, the first bottom anti-reflective coating 613, as its name suggests, serves to prevent uncontrolled, unintended energy (such as light) from being reflected back into the top photosensitive layer 619, thereby preventing reflected light from reacting in unintended areas of the top photosensitive layer 619. Additionally, the first bottom anti-reflective coating 613 can be used to provide a flat surface and helps reduce the negative effects of energy impact at an angle.

[0160] An intermediate masking layer 615 may be placed on the first bottom antireflective coating 613. In one embodiment, the intermediate masking layer 615 is a hard masking material such as silicon nitride, oxide, oxynitride, silicon carbide, combinations of the above materials, or similar materials. The hard masking material as the intermediate masking layer 615 can be formed by a process such as chemical vapor deposition, however, other processes (such as plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, spin coating, or even formed on nitrided silicon oxide) can be used. Any suitable method or combination of methods for forming or otherwise placing the hard masking material can be used, and all such methods or combinations are intended to be fully included within the scope of the embodiments. The intermediate masking layer 615 can be formed to approximately to approximately (as promised) The thickness of ).

[0161] A second bottom anti-reflective coating 617 is deposited to improve adhesion between the intermediate masking layer 615 and the overlying top photosensitive layer 619. In one embodiment, the second bottom anti-reflective coating 617 is similar to the first bottom anti-reflective coating 613; however, in other embodiments, the second bottom anti-reflective coating 617 may be different.

[0162] In some embodiments, the second bottom antireflective coating 617, the intermediate mask layer 615, and the first bottom antireflective coating 613 are first patterned to accommodate the top photosensitive layer 619 (in a process such as double patterning). In one embodiment, a photosensitive layer (not individually shown) is used for placement, exposure, and development. Figure 6 In the first step, a portion of the second bottom anti-reflective coating 617, the intermediate mask layer 615, and the first bottom anti-reflective coating 613 is patterned. Then, a photosensitive layer is used as a mask for one or more etching processes to remove material from the second bottom anti-reflective coating 617 and the intermediate mask layer 615, and also to remove a portion, but not all, of the first bottom anti-reflective coating 613. Once the photosensitive layer has been used, it can be removed using processes such as ashing.

[0163] Once the second bottom antireflective coating 617 and the intermediate mask layer 615 have been patterned for the first time, a top photosensitive layer 619 is applied to the second bottom antireflective coating 617 using a spin coating process. The top photosensitive layer contains a photoresist polymer resin having one or more photoactive compounds (PACs) in a photoresist solvent. The PACs will absorb the patterned light source and generate reactants in the exposed portions of the top photosensitive layer 619, thereby undergoing a subsequent reaction with the developable photoresist polymer resin to repeatedly pattern the energy in the top photosensitive layer 619.

[0164] Once each of the first bottom antireflective coating 613, the intermediate mask layer 615, the second bottom antireflective coating 617, and the top photosensitive layer 619 has been used, the top photosensitive layer 619 is exposed to patterned energy (such as extreme ultraviolet (EUV) light) and developed to form a second opening 621 (such as a line opening) in the top photosensitive layer 619.

[0165] Once the top photosensitive layer 619 has been patterned, it is used to extend the second opening 621 through the first bottom anti-reflective coating 613, the third interlayer dielectric 609, and the first etch stop layer 607 to expose a portion of the gate contact 605. In one embodiment, one or more anisotropic etching processes are used in conjunction with the aforementioned... Figures 3A to 3C The etching system 300 is used to expand the second opening 621, wherein a voltage is applied to the edge ring 357 to assist in adjusting the outer edge of the plasma sheath 359, so that each of the second openings 621 through the semiconductor wafer (including the second opening 621 formed in the edge region 102) is formed in a near-vertical manner (e.g., at an angle between approximately 88.37 degrees and approximately 91.63 degrees). Once the second opening 621 has been formed, the first photoresist 611 (using a process such as ashing) can be removed, and a conductive material (not shown individually) is filled into the second opening 621 using a process such as damascene or dual damascene.

[0166] Using the tools and processes described herein, and by customizing the electric field through the conductivity of the tunably doped edge ring, a more uniform etching profile along the wafer edge can be achieved. The desired etching profile is achieved by controlling and fine-tuning the electric field using materials with different voltages and conductivity. Furthermore, by controlling the electric field during operation to maintain the plasma sheath in a plane parallel to the semiconductor wafer and the setup platform, vertical etching can be achieved in the edge regions of the semiconductor wafer, avoiding etch-induced overlay shift (EIOS) and short circuits caused by leakage current in the edge regions, and minimizing yield losses (e.g., 7%). Moreover, by controlling the electric field over time and based on the wear of the edge ring due to repeated use, the effective lifetime of the edge ring can be extended (e.g., exceeding 800 hours). Therefore, this adjustment helps overcome the limitations of other process factors (such as transformer-coupled capacitive tuning (TCCT) parameters, electrostatic chuck multi-zone temperature parameters, and gas position parameters (such as center, edge, and equal)) to achieve a more uniform process to reach the desired critical dimensions and profiles, and also extends the effective lifetime of the edge rings. Furthermore, the aforementioned process helps reduce or eliminate problems related to uniformity mismatches within the wafer or between cavities, and helps reduce the time and cost of replacing edge rings.

[0167] According to one embodiment, a method of manufacturing a semiconductor device includes: providing a chuck, wherein the chuck includes a first electrode; and placing an edge ring adjacent to the chuck, wherein the edge ring includes a second electrode. In one embodiment, the method further includes applying a DC voltage to the second electrode. In one embodiment of the method, the edge ring includes a coil and wherein applying the DC voltage to the second electrode includes inducing a current within the coil. In one embodiment of the method, the DC voltage is at least partially based on the thickness of the edge ring. In one embodiment of the method, the intensity of the DC voltage is at least partially based on the usage time of the edge ring. In one embodiment of the method, the intensity of the DC voltage is at least partially based on the shape of the edge ring. In one embodiment of the method, the edge ring is electrically insulated from the chuck.

[0168] According to another embodiment, a method of manufacturing a semiconductor device includes: placing an edge ring adjacent to an electrostatic chuck; adsorbing a first semiconductor wafer onto the electrostatic chuck; generating a plasma sheath on the first semiconductor wafer; and applying a first bias voltage to the edge ring. In one embodiment of the method, the first bias voltage is a direct current (DC) bias voltage. In one embodiment of the method, the edge ring includes a coil. In one embodiment of the method, the intensity of the DC bias voltage is at least partially based on the distance from the plasma sheath to the upper surface of the edge ring. In one embodiment of the method, the intensity of the DC bias voltage is at least partially based on the usage time of the edge ring. In one embodiment, the method further includes applying a second bias voltage to the electrostatic chuck. In one embodiment, the method further includes adsorbing a first semiconductor wafer, then adsorbing a second semiconductor wafer onto the electrostatic chuck; and applying a second bias voltage to the edge ring, wherein the second bias voltage is different from the first bias voltage.

[0169] According to another embodiment, a semiconductor manufacturing tool includes an electrostatic chuck; a first electrode electrically coupled to the electrostatic chuck; and an edge ring extending beyond the electrostatic chuck, wherein the edge ring includes a coil embedded in a dielectric material. In one embodiment, the tool further includes a voltage generator electrically connected to the coil. In one embodiment of the tool, the voltage generator is a DC voltage generator. In one embodiment, the tool further includes a radio frequency generator electrically connected to the first electrode. In one embodiment of the tool, a portion of the first electrode is located within an edge portion of the electrostatic chuck, and the coil is located on a portion of the first electrode. In one embodiment of the tool, the dielectric material of the edge ring comprises a high electron mobility material.

[0170] The foregoing disclosure has outlined the features of several embodiments, thus enabling those skilled in the art to better understand the nature of the embodiments disclosed herein. Those skilled in the art will recognize that they can readily utilize the embodiments disclosed herein as a basis to design or refine other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such peer architectures do not depart from the spirit and scope of the embodiments disclosed herein, and that various modifications, substitutions, and alterations can be made therein without departing from the spirit and scope of the embodiments disclosed herein.

Claims

1. A method for manufacturing a semiconductor device, characterized in that... This method includes: A suction cup is provided, wherein the suction cup includes a first electrode; An edge ring is placed adjacent to the suction cup, wherein the edge ring includes a second electrode and an electric field coil; A DC voltage is applied to the second electrode, wherein the electric field coil generates an electric field control in response to the DC voltage applied to the second electrode; and The DC voltage is adjusted based on the wear of the edge ring to incrementally change the electric field control.

2. The method according to claim 1, characterized in that... The method also includes generating a plasma sheath, wherein the electric field controls and maintains the plasma sheath in a horizontal plane parallel to an upper surface of the edge ring.

3. The method according to claim 1, characterized in that... The operation of applying the DC voltage to the second electrode involves inducing a current within the electric field coil.

4. The method according to claim 1, characterized in that... The wear of the edge ring includes a reduction in the thickness of the edge ring.

5. The method according to claim 1, characterized in that... By adjusting the DC voltage, the service life of the edge ring exceeds 800 hours.

6. The method according to claim 1, characterized in that... The wear of the edge ring includes a change in the shape of the edge ring.

7. The method according to claim 1, characterized in that... The edge ring is electrically insulated from the suction cup.

8. A method for manufacturing a semiconductor device, characterized in that... This method includes: An edge ring is placed adjacent to an electrostatic chuck, wherein the edge ring includes an electrode and an electric field coil; A first semiconductor wafer is adsorbed onto the electrostatic chuck. A plasma sheath is generated on the first semiconductor wafer; A first electrical bias voltage is applied to the electrode of the edge ring, wherein the electric field coil generates electric field control in response to the first electrical bias voltage applied to the electrode; as well as The first electrical bias is adjusted based on the wear of the edge ring to incrementally change the electric field control.

9. The method according to claim 8, characterized in that... The first bias voltage is a DC bias voltage.

10. The method according to claim 8, characterized in that... The electric field controls the plasma sheath to remain in a horizontal plane parallel to an upper surface of the edge ring.

11. The method according to claim 10, characterized in that... The wear of the edge ring includes a reduction in the thickness of the edge ring.

12. The method according to claim 9, characterized in that... By adjusting the DC bias voltage, the service life of the edge ring exceeds 800 hours.

13. The method according to claim 8, characterized in that... The method also includes applying a second electrical bias voltage to the electrostatic chuck.

14. The method according to claim 8, characterized in that... The method also includes: A second electrical bias voltage is applied to the edge ring, wherein the second electrical bias voltage is different from the first electrical bias voltage.

15. A semiconductor manufacturing tool, characterized in that... This semiconductor manufacturing tool includes: An electrostatic chuck; A first electrode is electrically coupled to the electrostatic chuck; An edge ring extends beyond the electrostatic chuck, wherein the edge ring includes a second electrode and an electric field coil embedded in a dielectric material; as well as A voltage generator is electrically connected to the electric field coil to apply a DC voltage to the second electrode, wherein the electric field coil generates electric field control in response to the DC voltage applied to the second electrode, and the DC voltage is adjusted based on the wear of the edge ring to incrementally change the electric field control.

16. The manufacturing tool according to claim 15, characterized in that... The edge ring has a vertical support segment and a horizontal support segment on the vertical support segment.

17. The manufacturing tool according to claim 16, characterized in that... The electric field coil is located within the vertical support section.

18. The manufacturing tool according to claim 15, characterized in that... The manufacturing tool also includes a radio frequency generator electrically connected to the first electrode.

19. The manufacturing tool according to claim 15, characterized in that... A portion of the first electrode is located within an edge portion of the electrostatic chuck, and The electric field coil is located on this part of the first electrode.

20. The manufacturing tool according to claim 15, characterized in that... The dielectric material of the edge ring contains a material with high electron mobility.

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