Semiconductor structure and method of forming the same
By forming a sulfur-containing metal layer in the semiconductor structure and converting it into a metal sulfide, the problem of insufficient diffusion barrier layer quality is solved, thereby improving the performance and electromigration capability of the semiconductor structure and reducing resistance and power consumption.
Patent Information
- Application Number
- CN202110255199.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-03-09
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2041-03-09
AI Technical Summary
In the prior art, the formation quality of the diffusion barrier layer is insufficient, resulting in poor performance of the semiconductor structure. In particular, in metal line and via interconnect structures, the high resistivity of the diffusion barrier layer material can easily degrade the resistance and RC delay of the subsequent interconnect.
By forming a sulfur-containing metal layer on the sidewalls and bottom of the trench and treating it in a sulfur-containing atmosphere, the metal layer is transformed into a metal sulfide, forming a diffusion barrier layer. This improves the uniformity of sulfur distribution and the sufficiency of the reaction, ensuring the quality of the diffusion barrier layer formation.
It improves the diffusion barrier layer's anti-diffusion capability, reduces the resistance of the interconnect structure, improves the performance of the semiconductor structure, reduces electromigration problems, and lowers power consumption.
Smart Images
Figure CN115050691B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND
[0002] In the back-end-of-line (BEOL) process of a semiconductor device, a metal interconnection structure forming process is usually needed. In the metal interconnection structure, there are usually multiple layers of via interconnection structures and metal interconnection lines, and the multiple layers of metal interconnection lines can be electrically connected through the via interconnection structures. When forming a later layer of metal interconnection line on a former layer of via interconnection structure, or forming a later layer of via interconnection structure on a former layer of metal interconnection line, an interlayer dielectric layer is usually first formed on the former layer of via interconnection structure or metal interconnection line, then a via and a trench are formed in the interlayer dielectric layer, and finally the via and the trench are filled with metal to form the later layer of via interconnection structure or metal interconnection line.
[0003] In which, after forming the via or the trench, and before filling the via and the trench with metal, a diffusion barrier layer is usually formed on the sidewall of the via or the trench, so that after forming the via interconnection structure located in the via or the metal interconnection line located in the trench, the diffusion barrier layer is located between the via interconnection structures or between the metal interconnection line and the dielectric layer, for improving the problem of electromigration.
[0004] However, the performance of the semiconductor structure still needs to be improved by using the diffusion barrier layer. SUMMARY
[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, to improve the formation quality of the diffusion barrier layer.
[0006] To solve the above problem, embodiments of the present application provide a semiconductor structure, comprising: a dielectric layer, a trench is formed in the dielectric layer, and the bottom and the sidewall of the trench contain sulfur element; a diffusion barrier layer is located on the bottom and the sidewall of the trench, and the diffusion barrier layer is formed by heat treating a sulfur-containing metal layer to convert the material of the sulfur-containing metal layer into a metal sulfide; and an interconnection structure is located on the diffusion barrier layer and fills the trench.
[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a dielectric layer, wherein a groove is formed in the dielectric layer; forming a metal layer containing sulfur on the sidewall and bottom of the groove; the step of forming the metal layer containing sulfur comprises: forming a metal layer on the sidewall and bottom of the groove in a sulfur-containing atmosphere; or, the step of forming the metal layer containing sulfur comprises: performing surface treatment on the sidewall and bottom of the groove, which is suitable for making the sidewall and bottom of the groove contain sulfur elements; forming a metal layer on the sidewall and bottom of the groove after the surface treatment; performing sulfur-doping treatment on the metal layer; or, the step of forming the metal layer containing sulfur comprises a plurality of deposition treatment cycles, and one deposition treatment comprises: forming a sub-metal layer on the sidewall and bottom of the groove; performing sulfur-doping treatment on the sub-metal layer; performing heat treatment on the metal layer containing sulfur, so that the metal layer containing sulfur is converted into a diffusion barrier layer, and the material of the diffusion barrier layer is metal sulfide; forming an interconnection structure filling the groove on the diffusion barrier layer.
[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:
[0009] The semiconductor structure provided by the embodiment of the present application is formed by converting the metal layer containing sulfur into a metal sulfide material in the process of heat treatment, and the residual sulfur elements in the bottom and sidewall of the groove ensure that the surface of the metal layer in contact with the groove can also contact the sulfur elements, thereby improving the sufficiency of the reaction between the material of the metal layer and the sulfur atoms in the process of heat treatment, and being beneficial to ensuring that the metal layer can be completely converted into a metal sulfide material, thereby improving the formation quality of the diffusion barrier layer, and being beneficial to ensuring that the diffusion barrier layer has a high diffusion barrier ability while being thin, and thereby improving the performance of the semiconductor structure.
[0010] In the forming method of the semiconductor structure of the embodiment of the present application, the step of forming the metal layer containing sulfur comprises forming a metal layer on the sidewall and bottom of the groove in a sulfur-containing atmosphere, thereby improving the uniformity of the distribution of the sulfur elements in the metal layer, and being beneficial to making the metal layer and the sulfur elements fully react in the process of heat treatment.
[0011] Alternatively, the step of forming the metal layer containing sulfur in the embodiment of the present application comprises: performing surface treatment on the sidewall and bottom of the groove, then forming a metal layer on the sidewall and bottom of the groove, and performing sulfur-doping treatment on the metal layer, so that the metal layer can contact the sulfur elements on the surface in contact with the surface of the groove and the surface not in contact with the surface of the groove, and being beneficial to improving the diffusion uniformity and distribution uniformity of the sulfur elements in the metal layer in the process of heat treatment.
[0012] Alternatively, the step of forming the metal layer containing sulfur includes a plurality of deposition processing cycles, and the deposition processing includes: forming a sub-metal layer on the sidewall and the bottom of the trench; and performing sulfur doping treatment on the sub-metal layer. The sulfur doping treatment on the sub-metal layer is beneficial to improve the uniformity of the distribution of the sulfur element in the sub-metal layer due to the thinness of the sub-metal layer. The plurality of deposition processing cycles for forming the metal layer containing sulfur can improve the uniformity of the distribution of the sulfur element in the metal layer, and thus is beneficial to fully react the metal layer with the sulfur element during the heat treatment.
[0013] In summary, the embodiments of the present application are beneficial to improve the uniformity of the distribution of the sulfur element in the metal layer, and are beneficial to fully react the metal layer with the sulfur element during the heat treatment, thereby being beneficial to ensure that the metal layer can be completely converted into a metal sulfide material, and thus is beneficial to improve the formation quality of the diffusion barrier layer, and further is beneficial to ensure that the diffusion barrier layer has a high diffusion barrier ability while the diffusion barrier layer is thin, and thus is beneficial to improve the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS
[0014] Figures 1 to 3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;
[0015] Figures 4 to 15 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;
[0016] Figures 16 to 19 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;
[0017] Figures 20 to 23 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;
[0018] Figure 24 and Figure 25 is a structure diagram of an embodiment of a semiconductor structure. DETAILED DESCRIPTION
[0019] As known from the background, the performance of the semiconductor structure needs to be improved.
[0020] Specifically, under the condition of continuous miniaturization of device size, the pitch between metal lines is also getting smaller and smaller, and the proportion of the diffusion barrier layer in the metal line or via interconnection structure is gradually increasing. The resistivity of the diffusion barrier layer material is higher than that of the via interconnection structure, and the conductivity of the diffusion barrier layer material is poorer, which leads to higher resistance of the back-end interconnection and easily deteriorates the back-end RC delay, resulting in poor performance of the semiconductor structure.
[0021] Therefore, in order to reduce the proportion of the diffusion barrier layer in the metal line or via interconnection structure to reduce the resistance of the back-end interconnection, the diffusion barrier layer needs to be thinner and thinner. Currently, a method is to select a two-dimensional material as the material of the diffusion barrier layer. However, when the two-dimensional material is selected as the material of the diffusion barrier layer, the performance of the semiconductor structure still needs to be improved.
[0022] The reasons why the performance of the semiconductor structure needs to be improved will be analyzed in combination with a forming method of a semiconductor structure. Figures 1 to 3 is a structure diagram corresponding to each step in a forming method of a semiconductor structure.
[0023] Referring to Figure 1 , a medium layer 10 is provided, and a groove 20 is formed in the medium layer 10.
[0024] Continuing to refer to Figure 1 , a metal layer 30 is formed on the bottom and sidewall of the groove 20.
[0025] Referring to Figure 2 , the metal layer 30 is subjected to plasma treatment in a sulfur-containing atmosphere, which is suitable for converting the metal layer 30 into a diffusion barrier layer 40, and the material of the diffusion barrier layer 40 is a metal sulfide.
[0026] Referring to Figure 3 , an interconnection structure 50 filling the groove 20 is formed on the diffusion barrier layer 40.
[0027] Among them, the metal sulfide material can be TaSx and TiSx, which can be used as a two-dimensional material, so that the diffusion barrier layer 40 with a two-dimensional material can be obtained, which is beneficial to make the diffusion barrier layer 40 thinner while making the diffusion barrier performance of the diffusion barrier layer 40 meet the performance requirements of the device.
[0028] However, the above method forms the metal layer 30, and then performs plasma treatment on the metal layer 30 in a sulfur-containing atmosphere to form a metal sulfide, which is easy to cause insufficient reaction of the plasma with the metal layer 30, and it is difficult to completely convert the metal layer 30 into a metal sulfide material, resulting in poor diffusion barrier performance of the diffusion barrier layer 40, and the performance of the semiconductor structure still needs to be improved.
[0029] In order to solve the technical problem, the embodiment of the present application provides a forming method of a semiconductor structure, which comprises the following steps: forming a sulfur-containing metal layer comprises forming a metal layer on the sidewall and bottom of the groove in a sulfur-containing atmosphere, thereby improving the uniformity of the distribution of sulfur elements in the metal layer, and correspondingly facilitating the sufficient reaction of the metal layer with the sulfur elements during heat treatment.
[0030] Alternatively, the step of forming the metal layer containing sulfur includes: performing surface treatment on the bottom and sidewall of the trench, then forming a metal layer on the sidewall and bottom of the trench, and performing sulfur doping treatment on the metal layer, so that the metal layer can contact sulfur element on the surface in contact with the surface of the trench and the surface not in contact with the surface of the trench, which is beneficial to improve the diffusion uniformity and distribution uniformity of the sulfur element in the metal layer during the heat treatment process.
[0031] Alternatively, the step of forming the metal layer containing sulfur includes a plurality of deposition treatment cycles, and one deposition treatment includes: forming a sub-metal layer on the sidewall and bottom of the trench; and performing sulfur doping treatment on the sub-metal layer, which is beneficial to improve the distribution uniformity of the sulfur element in the sub-metal layer due to the thinness of the sub-metal layer, and the plurality of deposition treatment cycles for forming the metal layer containing sulfur can improve the distribution uniformity of the sulfur element in the metal layer, thereby facilitating the full reaction between the metal layer and the sulfur element during the heat treatment process.
[0032] In summary, the embodiment of the present application is beneficial to improve the distribution uniformity of the sulfur element in the metal layer, facilitate the full reaction between the metal layer and the sulfur element during the heat treatment process, thereby ensuring that the metal layer can be completely converted into a metal sulfide material, improving the formation quality of the diffusion barrier layer, and further improving the performance of the semiconductor structure while ensuring that the diffusion barrier layer has high diffusion barrier ability.
[0033] To make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.
[0034] To facilitate understanding, the forming method of the semiconductor structure of the embodiment of the present application will be described in detail first. Figures 4 to 15 is a structure schematic diagram corresponding to each step in the forming method of the semiconductor structure of the embodiment of the present application.
[0035] Reference Figures 4 to 7 , a medium layer 100 is provided, and a trench 210 is formed in the medium layer 100.
[0036] The medium layer 100 is used to realize isolation between interconnection structures, and the trench 210 is used to provide a spatial position for forming an interconnection structure.
[0037] In the embodiment, the medium layer 100 includes a bottom medium layer 110 and a top medium layer 200 located on the bottom medium layer 110. The bottom medium layer 110 and the top medium layer 200 are both inter metal dielectric (IMD) layers.
[0038] In this embodiment, the bottom interconnection line 120 is formed in the bottom dielectric layer 110, and the bottom dielectric layer 110 is used to realize isolation between adjacent bottom interconnection lines 120.
[0039] As an example, the bottom interconnection line 120 is a single-layer structure, and the material of the bottom interconnection line 120 is copper. The resistivity of copper is low, which is beneficial to improve the signal delay of the back-end RC, improve the processing speed of the chip, and also beneficial to reduce the resistance of the bottom interconnection line 120, and accordingly reduce the power consumption.
[0040] In other embodiments, the material of the bottom interconnection line can also be a conductive material such as cobalt, tungsten, aluminum, etc., and the bottom interconnection line can also be a multi-layer structure.
[0041] In this embodiment, the bottom barrier layer 130 is further formed between the bottom interconnection line 120 and the bottom dielectric layer 110, which is used to improve the adhesion between the bottom interconnection line 120 and the bottom dielectric layer 110, and also used to reduce the probability of diffusion of the material of the bottom interconnection line 120 into the bottom dielectric layer 110 or diffusion of impurities in the material of the bottom dielectric layer 110 into the bottom interconnection line 120, thereby improving the problem of electromigration. In this embodiment, the material of the bottom barrier layer 130 is one or more of tantalum, tantalum nitride, titanium, titanium nitride, cobalt, manganese, manganese oxide, ruthenium nitride, and ruthenium.
[0042] It should be noted that the bottom dielectric layer 110 is usually further formed with a device structure below, and the bottom interconnection line 120 is electrically connected with the device structure, so that the device structure can be powered when the device is working. Specifically, the device structure can include a substrate, a gate structure on the substrate, and source / drain doped regions in the substrate on both sides of the gate structure.
[0043] In this embodiment, the trench 210 is formed in the top dielectric layer 200, and accordingly, the interconnection structure is formed in the trench 210 subsequently, and the top dielectric layer 200 is used to realize electrical isolation between adjacent interconnection structures.
[0044] In this embodiment, the bottom of the trench 210 exposes part of the top surface of the bottom interconnection line 120, so that after the interconnection structure is formed in the trench 210 subsequently, the interconnection structure can be in contact with the bottom interconnection line 120, and accordingly realize the electrical connection between the interconnection structure and the bottom interconnection line 120.
[0045] To this end, the material of the bottom dielectric layer 110 and the top dielectric layer 200 is low-k dielectric material (low-k dielectric material refers to dielectric material with relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with relative dielectric constant less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride, etc.
[0046] In this embodiment, the material of the bottom dielectric layer 110 and the top dielectric layer 200 is ultra-low-k dielectric material, thereby reducing the parasitic capacitance between the back-end interconnections, and further reducing the back-end RC delay. Specifically, the ultra-low-k dielectric material can be SiOCH.
[0047] In this embodiment, the dielectric layer 100 further includes a first etching stop layer 140 between the bottom dielectric layer 110 and the top dielectric layer 200, for temporarily defining the position of etching stop during the process of forming the trench 210, so as to improve the consistency of etching and reduce the damage to the bottom interconnection line 120.
[0048] The first etching stop layer 140 is made of material with etching selectivity to the material of the bottom dielectric layer 110 or the top dielectric layer 200. The material of the first etching stop layer 140 can be aluminum oxide, aluminum nitride, or NDC (Nitride doped Carbon). As an example, the material of the first etching stop layer 140 is aluminum oxide.
[0049] In this embodiment, the steps of providing the dielectric layer 200 and the trench 210 include:
[0050] As shown in Figure 4 and Figure 5 , the dielectric layer 100 is provided, including the bottom dielectric layer 110 and the top dielectric layer 200, and the bottom interconnection line 120 is formed in the bottom dielectric layer 110. Figure 4 is a perspective view, Figure 5 is Figure 4 a cross-sectional view along the xx direction.
[0051] As shown in Figure 6 and Figure 7 , the dielectric layer 100 is provided, including the bottom dielectric layer 110 and the top dielectric layer 200, and the bottom interconnection line 120 is formed in the bottom dielectric layer 110. Figure 6 is a perspective view, Figure 7 is Figure 6 a cross-sectional view along the xx direction.
[0052] As an example, the trench 210 includes an interconnection slot 212 in the top dielectric layer 200 of partial thickness, and a conductive via 211 penetrating the top dielectric layer 200 below the bottom interconnection line 120.
[0053] The interconnection groove 212 is used to form a metal interconnection line, and the conductive via 211 is used to form a via interconnection structure electrically connecting the bottom interconnection line 120 and the metal interconnection line.
[0054] In other embodiments, the trench can also be any one of an interconnection groove and a conductive via.
[0055] With reference to Figure 9 A metal layer 220 containing sulfur is formed on the sidewall and bottom of the trench 210.
[0056] The metal layer 220 contains sulfur elements, so that in the subsequent heat treatment process, the material of the metal layer 220 containing sulfur elements can be converted into a metal sulfide material, which can act as a diffusion barrier layer.
[0057] In this embodiment, the step of forming the metal layer 220 containing sulfur includes forming a metal layer 220 on the sidewall and bottom of the trench 210 in a sulfur-containing atmosphere. Compared with the scheme of performing plasma treatment on the metal layer in a sulfur-containing atmosphere after forming the metal layer, this embodiment can improve the uniformity of the distribution of sulfur elements in the metal layer 220, which is conducive to the full reaction between the metal layer 220 and the sulfur elements during heat treatment, and is conducive to ensuring that the metal layer 220 can be completely converted into a metal sulfide material, thereby improving the formation quality of the diffusion barrier layer, and further improving the performance of the semiconductor structure while ensuring that the diffusion barrier layer has a high diffusion barrier ability.
[0058] In this embodiment, the material of the metal layer 220 includes Ta, Ti, Mo or W. By selecting Ta, Ti, Mo or W as the material of the metal layer 220, the material of the metal layer 220 can react with the sulfur elements during heat treatment and be converted into a metal sulfide material. The metal sulfide material corresponding to the metal can act as a two-dimensional layered material. The two-dimensional layered material refers to a material in which electrons can only move freely in two dimensions on a nanoscale (planar motion). It is extremely difficult for electrons to pass through the two-dimensional layered material, so that the diffusion barrier layer has a high diffusion barrier ability even with a small thickness, which is conducive to improving the performance of the semiconductor structure.
[0059] As an example, the material of the metal layer 220 is Ta.
[0060] In this embodiment, forming the metal layer 220 on the sidewall and bottom of the trench 210 in a sulfur-containing atmosphere includes introducing a sulfur source into the reaction chamber during the step of forming the metal layer 220.
[0061] As an example, the sulfur source of the sulfur-containing atmosphere includes H2S gas or sulfur solid. Where the sulfur source is sulfur solid, the sulfur-containing atmosphere can be a gas carrying free-state sulfur.
[0062] As an example, the process of forming the metal layer 220 includes a physical vapor deposition (PVD) process. The PVD process is low in cost and high in compatibility with the back-end-of-line process. Specifically, the PVD process can be a sputtering process or the like.
[0063] Correspondingly, a sulfur-containing gas is introduced into the reaction chamber of the PVD process.
[0064] It is to be noted that in actual processes, based on actual process requirements, after the metal layer 220 is formed on the sidewall and bottom of the trench 210 in the sulfur-containing atmosphere, the method of forming the semiconductor structure can further include a sulfur-doping process on the sulfur-containing metal layer 220, which is advantageous to further increase the content of sulfur in the metal layer 220 and correspondingly advantageous to further improve the sufficiency of the reaction between the metal layer 220 and sulfur during subsequent heat treatment.
[0065] Specifically, the sulfur-doping process on the sulfur-containing metal layer 220 can include a plasma treatment on the sulfur-containing metal layer 220 in a sulfur-containing atmosphere or a sulfur-ion doping on the sulfur-containing metal layer 220.
[0066] In this embodiment, the sulfur source of the sulfur-containing atmosphere includes H2S gas or sulfur solid.
[0067] In this embodiment, the process of doping the sulfur-containing metal layer 220 with sulfur ions can be an ion implantation process. The ion implantation process is easy to control the doping concentration and doping depth of sulfur ions in the metal layer 220 by controlling the implantation energy, implantation dose and implantation angle.
[0068] Reference Figures 10 to 11 , Figure 10 is a perspective view, Figure 11 is a Figure 10 is a cross-sectional view along the xx direction, the sulfur-containing metal layer 220 is subjected to a heat treatment to convert the sulfur-containing metal layer 220 into a diffusion barrier layer 230, and the material of the diffusion barrier layer 230 is a metal sulfide.
[0069] The metal sulfide material can be a two-dimensional layered material, which means that the electron can only move freely in two dimensions at the nanometer scale (planar movement). The electron is extremely difficult to pass through the two-dimensional layered material, so that the diffusion barrier layer 230 has a high diffusion barrier ability even with a small thickness, thereby significantly improving the problem of electro migration (EM) and improving the performance of the semiconductor structure.
[0070] In this embodiment, the step of forming the metal layer 220 containing sulfur includes forming the metal layer 220 on the sidewall and bottom of the trench 210 in a sulfur-containing atmosphere. This can improve the uniformity of the distribution of sulfur elements in the metal layer 220, which is conducive to the full reaction between the metal layer 220 and the sulfur elements during the heat treatment, and is conducive to ensuring that the metal layer 220 can be completely converted into a metal sulfide material, thereby improving the formation quality of the diffusion barrier layer 230, and further improving the performance of the semiconductor structure while ensuring that the diffusion barrier layer 230 has a high diffusion barrier ability.
[0071] In this embodiment, the material of the metal layer 220 includes Ta, Ti, Mo or W, and the metal sulfide includes tantalum sulfide, titanium sulfide, molybdenum sulfide or tungsten sulfide. The metal sulfide is a common two-dimensional layered material, which is conducive to improving the process compatibility.
[0072] During the heat treatment of the metal layer 220 containing sulfur, the metal atoms in the metal layer 220 material can bond with the sulfur elements, thereby forming a metal sulfide material.
[0073] It should be noted that the temperature of the heat treatment should not be too low or too high. If the temperature of the heat treatment is too low, it can reduce the bonding rate of the metal atoms in the metal layer 220 material and the sulfur elements, and accordingly reduce the efficiency of forming the metal sulfide, and also increase the risk of insufficient reaction between the metal layer 220 and the sulfur elements. If the temperature of the heat treatment is too high, it can adversely affect the device structure formed in the previous stage. Therefore, in this embodiment, the temperature of the heat treatment of the metal layer 220 containing sulfur is 300-600°C.
[0074] In this embodiment, the heat treatment of the metal layer 220 containing sulfur is performed by annealing.
[0075] It should be noted that in actual processes, when the sulfur content of the sulfur-containing atmosphere is high, some sulfur elements can remain in the sidewall and bottom of the trench 210 after the heat treatment.
[0076] Reference Figure 12 and Figure 13, Figure 12 is a perspective view, Figure 13 is Figure 12 is a cross-sectional view along the xx direction, the diffusion barrier layer 230 is formed on the diffusion barrier layer 230, and the interconnection structure 240 is formed to fill the trench 210.
[0077] Specifically, the interconnection structure 240 is electrically connected to the bottom interconnection line 130, so that the device structure can be powered through the interconnection structure 240 and the bottom interconnection line 130 during device operation.
[0078] In this embodiment, the diffusion barrier layer 230 is formed between the interconnection structure 240 and the top dielectric layer 200, and the diffusion barrier layer 230 has high formation quality. The diffusion barrier layer 230 is a two-dimensional layered material, which can still have high diffusion barrier ability even in a very thin case, thereby significantly reducing the probability of diffusion of the material of the interconnection structure 240 into the top dielectric layer 200 and diffusion of impurities in the material of the top dielectric layer 200 into the interconnection structure 240, thereby significantly improving the problem of electromigration. Moreover, the diffusion barrier layer 230 is thin, which is beneficial to increase the filling space of the interconnection structure 240, thereby being beneficial to increase the volume of the interconnection structure 240, reduce the resistance of the interconnection structure 240, and improve the RC delay in the back end.
[0079] In this embodiment, the material of the interconnection structure 240 includes one or more of copper, cobalt, tungsten, and aluminum. As an example, the material of the interconnection structure 240 is copper. The resistivity of copper is low, which is beneficial to improve the signal delay of the RC in the back end and improve the processing speed of the chip, and simultaneously beneficial to reduce the resistance of the interconnection structure 240, thereby reducing power consumption.
[0080] In this embodiment, the interconnection structure 240 is one or both of a metal interconnection line and a via interconnection structure.
[0081] As an example, the trench 210 includes an interconnection groove 212 in the top dielectric layer 200 of a partial thickness, and a conductive via 211 penetrating the top dielectric layer 200 below a partial bottom of the interconnection groove 212. Correspondingly, the interconnection structure 240 includes a via interconnection structure 250 in the conductive via 211, and a metal interconnection line 260 on the via interconnection structure 250 and filling the interconnection groove 212.
[0082] In this embodiment, the metal interconnection line 260 and the via interconnection structure 250 are integrated structures, which correspondingly reduce the contact resistance of the metal interconnection line 260 and the via interconnection structure 250 and reduce the resistance of the interconnection structure 240, thereby improving the interconnection performance of the semiconductor structure.
[0083] In other embodiments, the interconnect structure can also include any one of the via interconnect structure and the metal interconnect line.
[0084] The present embodiment takes the metal interconnect line 260 and the via interconnect structure 250 as a single layer structure as an example. In other embodiments, the via interconnect structure and the metal interconnect line can also be a multi-layer structure according to actual process requirements, and the materials of the via interconnect structure and the metal interconnect line can include a plurality of conductive materials.
[0085] In the present embodiment, the step of forming the interconnect structure 240 includes: forming a conductive material layer (not shown in the figure) filled in the conductive via 211 and the interconnect trench 212, the conductive material layer also covers the top dielectric layer 200; removing the conductive material layer located on the top dielectric layer 200, the conductive material layer filled in the conductive via 211 is used as the via interconnect structure 250, and the conductive material layer filled in the interconnect trench 212 is used as the metal interconnect line 260.
[0086] Based on the material of the conductive material layer and the actual process requirements, the process of forming the conductive material layer includes one or more of electrochemical plating process, chemical vapor deposition process and physical vapor deposition process.
[0087] In the present embodiment, the planarization process is used to remove the conductive material layer located on the top dielectric layer 200, which is beneficial to improve the flatness and height consistency of the interconnect structure 240 and the top surface of the top dielectric layer 200. Specifically, the planarization process can be a chemical mechanical planarization process.
[0088] Reference Figure 14 and Figure 15 , Figure 14 is a perspective view, Figure 15 is Figure 14 is a cross-sectional view along the xx direction, a second etching stop layer 270 is formed on the dielectric layer 100, covering the top of the interconnect structure 240.
[0089] The second etching stop layer 270 is used to protect the top of the interconnect structure 240. When the subsequent process also includes forming other conductive structures electrically connected to the interconnect structure 240 on the interconnect structure 240, the second etching stop layer 270 can temporarily define the etching stop position during the formation of the conductive structure, so as to reduce the damage to the interconnect structure 240.
[0090] The material of the second etching stop layer 270 can be aluminum oxide, aluminum nitride or NDC (Nitride doped Carbon). As an example, the material of the second etching stop layer 270 is aluminum oxide.
[0091] Figures 16 to 19 is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present application. The method for forming a semiconductor structure in this embodiment is the same as in the foregoing embodiments, and the differences between the method for forming a semiconductor structure in this embodiment and the foregoing embodiments are that the step of forming the sulfur-containing metal layer is different from that in the foregoing embodiments.
[0092] The step of forming the sulfur-containing metal layer in this embodiment is described in detail below with reference to the accompanying drawings.
[0093] Referring to Figure 16 The bottom and sidewall of the trench 410 are surface treated to contain sulfur elements 400.
[0094] By surface treating the bottom and sidewall of the trench 410, the surface of the metal layer that contacts the trench 410 can contact sulfur elements when the metal layer is subsequently formed on the bottom and sidewall of the trench 410.
[0095] In this embodiment, surface treating the bottom and sidewall of the trench 410 includes plasma treating the bottom and sidewall of the trench 210 in a sulfur-containing atmosphere.
[0096] In this embodiment, the sulfur source of the sulfur-containing atmosphere includes H2S gas or a sulfur solid. When the sulfur source is a sulfur solid, the sulfur-containing atmosphere can be a gas carrying free sulfur.
[0097] Referring to Figure 17 A metal layer 420 is formed on the sidewall and bottom of the trench 210 after surface treatment.
[0098] In this embodiment, the process of forming the metal layer 410 includes a chemical vapor deposition process.
[0099] Referring to Figure 18 The metal layer 420 is sulfur-doped.
[0100] Sulfur-doping the metal layer 420 allows the surface of the metal layer 420 that contacts the surface of the trench 410 and the surface of the metal layer 420 that does not contact the surface of the trench 410 to both contact sulfur elements, which is advantageous for improving the diffusion uniformity and distribution uniformity of sulfur elements in the metal layer 420 during heat treatment, for allowing the metal layer 420 to fully react with sulfur elements during heat treatment, and for ensuring that the metal layer 420 can be completely converted into a metal sulfide material, which in turn improves the formation quality of the diffusion barrier layer and ensures that the diffusion barrier layer has high diffusion barrier ability while being thin, and which in turn improves the performance of the semiconductor structure.
[0101] In the embodiment, the step of performing sulfur-doping treatment on the metal layer 420 includes: performing plasma treatment on the metal layer 420 in a sulfur-containing atmosphere, or performing ion doping on the metal layer 420, so as to dope sulfur ions in the metal layer 420.
[0102] In the embodiment, the sulfur source of the sulfur-containing atmosphere includes H2S gas or a sulfur solid.
[0103] In the embodiment, when the step of performing sulfur-doping treatment on the metal layer 420 includes performing ion doping on the metal layer 420, ion implantation is used to perform ion doping on the metal layer 420. The ion implantation process is easy to control the doping concentration and the doping depth of the sulfur ions in the metal layer 420 by controlling the implantation energy, the implantation dose and the implantation angle.
[0104] Reference Figure 19 The sulfur-containing metal layer 420 is subjected to heat treatment, so that the sulfur-containing metal layer 420 is converted into a diffusion barrier layer 430, and the material of the diffusion barrier layer 430 is a metal sulfide.
[0105] In the process of heat treatment of the sulfur-containing metal layer 420, the surface of the metal layer 420 in contact with the trench 410 and the surface not in contact with the trench 410 can contact the sulfur element, so as to improve the diffusion uniformity and the distribution uniformity of the sulfur element in the metal layer 420 in the process of heat treatment, and correspondingly, it is beneficial to fully react between the metal element and the sulfur element of the material of the metal layer 420, so as to ensure that the metal layer 420 can be completely converted into a metal sulfide material, and the formation quality of the diffusion barrier layer 420 is improved.
[0106] It should be noted that, in the actual process, since the bottom and the sidewall of the trench 410 are subjected to plasma treatment in the sulfur-containing atmosphere before the metal layer 420 is formed, when the sulfur content of the sulfur-containing atmosphere is high, part of the sulfur element can still remain in the sidewall and the bottom of the trench 410 after the heat treatment.
[0107] The specific description of the formation method of the semiconductor structure in the embodiment can refer to the corresponding description in the foregoing embodiments, and the embodiment will not be described here.
[0108] Figures 20 to 23 is a structure diagram corresponding to each step in another embodiment of the formation method of the semiconductor structure of the present application. The formation method of the semiconductor structure in the embodiment is the same as that in the foregoing embodiments, and the difference between the formation method of the semiconductor structure in the embodiment and the foregoing embodiments is that the step of forming the sulfur-containing metal layer includes a plurality of deposition treatment cycles.
[0109] Reference Figures 20 to 21 , a deposition treatment is performed once.
[0110] The following description, in conjunction with the accompanying drawings, illustrates the steps of performing the deposition process described in this embodiment.
[0111] like Figure 20 As shown, a sub-metal layer 511 is formed on the sidewalls and bottom of the trench 510.
[0112] In this embodiment, the process for forming the sub-metal layer 511 includes physical vapor deposition.
[0113] like Figure 21 As shown, the sub-metal layer 511 is subjected to sulfur doping treatment.
[0114] In this embodiment, the step of sulfur doping the sub-metal layer 511 includes: performing plasma treatment on the sub-metal layer 511 in a sulfur-containing atmosphere, or performing ion doping on the sub-metal layer 511, which is suitable for doping sulfur ions in the sub-metal layer 511.
[0115] In this embodiment, the sulfur source of the sulfur-containing atmosphere includes H2S gas or solid sulfur. When the sulfur source is solid sulfur, the sulfur-containing atmosphere can be a gas carrying free sulfur.
[0116] In this embodiment, the process of ion doping the sub-metal layer 511 includes ion implantation. Ion implantation allows for easy control of the doping concentration and depth of sulfur ions in the sub-metal layer 511 by controlling the implantation energy, implantation dose, and implantation angle.
[0117] refer to Figure 22 Multiple deposition cycles are performed to form a sulfur-containing metal layer 520, which includes multiple stacked sub-metal layers 511, and each sub-metal layer 511 contains sulfur.
[0118] Since the metal layer 520 is formed in multiple steps, the metal layer 520 includes multiple layers of sub-metal layers 511 stacked sequentially. The sub-metal layers 511 are relatively thin. Sulfur doping of the sub-metal layers 511 makes it easier to achieve a high uniformity of sulfur distribution in the sub-metal layers 511. Accordingly, by performing multiple deposition cycles to form a sulfur-containing metal layer 520, all the multiple layers of stacked sub-metal layers 511 contain sulfur-containing elements, which can improve the uniformity of sulfur distribution in the metal layer 520.
[0119] As an example, to improve the efficiency of forming metal layer 520, two deposition cycles are performed to form two stacked sub-metal layers 511. In other embodiments, depending on the requirements for the uniformity of sulfur distribution in the metal layers, three, four, or other numbers of deposition cycles may be performed.
[0120] refer toFigure 23 The sulfur-containing metal layer 520 is subjected to heat treatment to convert the sulfur-containing metal layer into a diffusion barrier layer 530, the material of the diffusion barrier layer 530 being a metal sulfide.
[0121] In this embodiment, the deposition treatment cycle is performed multiple times to form the sulfur-containing metal layer 520, so that each of the sub-metal layers 511 of the multi-layer stack contains a sulfur-containing element, which can improve the uniformity of the distribution of the sulfur element in the metal layer 520, and is conducive to enabling the metal layer 520 and the sulfur element to fully react during the heat treatment.
Claims
1. A method of forming a semiconductor structure, characterized by, The method comprises: providing a dielectric layer, wherein a trench is formed in the dielectric layer; forming a sulfur-containing metal layer on the sidewall and bottom of the trench; wherein the step of forming the sulfur-containing metal layer comprises: forming a metal layer on the sidewall and bottom of the trench in a sulfur-containing atmosphere; or, the step of forming the sulfur-containing metal layer comprises: performing surface treatment on the sidewall and bottom of the trench, so as to make the sidewall and bottom of the trench contain sulfur element; forming a metal layer on the sidewall and bottom of the trench after the surface treatment; performing sulfur-doping treatment on the metal layer, wherein the surface treatment on the sidewall and bottom of the trench comprises: performing plasma treatment on the sidewall and bottom of the trench in a sulfur-containing atmosphere; or, the step of forming the sulfur-containing metal layer comprises a plurality of deposition treatment cycles, and each deposition treatment comprises: forming a sub-metal layer on the sidewall and bottom of the trench; performing sulfur-doping treatment on the sub-metal layer; performing heat treatment on the sulfur-containing metal layer, so as to convert the sulfur-containing metal layer into a diffusion barrier layer, and the material of the diffusion barrier layer is metal sulfide; forming an interconnection structure on the diffusion barrier layer, wherein the interconnection structure fills the trench.
2. The method of forming a semiconductor structure of claim 1, wherein, The sulfur source of the sulfur-containing atmosphere comprises H2S gas or sulfur solid.
3. The method of forming a semiconductor structure of claim 1, wherein, The material of the metal layer comprises Ta, Ti, Mo or W; and the metal sulfide comprises tantalum sulfide, titanium sulfide, molybdenum sulfide or tungsten sulfide.
4. The method of forming a semiconductor structure of claim 1, wherein, The step of performing sulfur-doping treatment on the metal layer or the sub-metal layer comprises: performing plasma treatment on the metal layer or the sub-metal layer in a sulfur-containing atmosphere, or performing ion doping on the metal layer or the sub-metal layer, so as to dope sulfur ions in the metal layer or the sub-metal layer.
5. The method of forming a semiconductor structure of claim 4, wherein, The sulfur source of the sulfur-containing atmosphere comprises H2S gas or sulfur solid.
6. The method of forming a semiconductor structure of claim 4, wherein, The ion doping on the metal layer or the sub-metal layer is performed by using ion implantation process.
7. The method of forming a semiconductor structure of claim 1, wherein, The heat treatment on the sulfur-containing metal layer is performed by using annealing treatment.
8. The method of forming a semiconductor structure of claim 1, wherein, The temperature of the heat treatment on the sulfur-containing metal layer is 300-600 °C.
9. The method of forming a semiconductor structure of claim 1, wherein, The process of forming the metal layer or the sub-metal layer comprises physical vapor deposition process.
10. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the interconnection structure, the material of the interconnection structure comprises one or more of copper, cobalt, tungsten and aluminum.
11. The method of forming a semiconductor structure of claim 1, wherein, In the step of forming the interconnection structure, the interconnection structure is one or both of metal interconnection line and via interconnection structure.
12. A semiconductor structure, characterized by The method is formed by using the method of claim 1, comprising: a dielectric layer, wherein a trench is formed in the dielectric layer, and the sidewall and bottom of the trench contain sulfur element; a diffusion barrier layer, which is located on the sidewall and bottom of the trench, and is formed by performing heat treatment on a sulfur-containing metal layer, so as to convert the material of the sulfur-containing metal layer into metal sulfide; an interconnection structure, which is located on the diffusion barrier layer and fills the trench.
13. The semiconductor structure of claim 12, wherein, The metal sulfide comprises tantalum sulfide, titanium sulfide, molybdenum sulfide or tungsten sulfide.
14. The semiconductor structure of claim 12, wherein, The material of the interconnection structure comprises one or more of copper, cobalt, tungsten and aluminum.
15. The semiconductor structure of claim 12, wherein, The interconnection structure is one or both of metal interconnection line and via interconnection structure.
Citation Information
Patent Citations
Integrated circuits and methods for forming thin film crystal layers
US20200194376A1