Electrostatic discharge protection structure and method of forming the same

Abstract

An electrostatic discharge protection structure and a forming method thereof, comprising: a substrate with a buried layer region therein; a first well region and a second well region adjacent to each other in the substrate, the first well region and the buried layer region have the same conductivity type, and the first well region and the second well region have opposite conductivity types; a first implant region and a second implant region, the first implant region is in the first well region, and the ion implant concentration of the first implant region is greater than that of the first well region, the second implant region is in the second well region, and the ion implant concentration of the second implant region is greater than that of the second well region, the first implant region and the second implant region have the same conductivity type, and the first implant region and the first well region have opposite conductivity types. The electrostatic discharge protection structure can effectively improve the electrostatic discharge protection capability of a semiconductor device when working in a negative direction or a positive direction.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to an electrostatic discharge protection structure and a forming method thereof. BACKGROUND

[0002] Integrated circuits are vulnerable to electrostatic damage, and a protection circuit is generally designed in an input / output terminal or a power supply protection device of the circuit to prevent internal circuits from being damaged by electrostatic.

[0003] In existing integrated circuit designs, an electrostatic discharge (ESD) protection structure is often used to reduce electrostatic damage. Existing electrostatic discharge protection structures mainly include a gate grounded N-type field effect transistor (GGNMOS) protection circuit, a silicon controlled rectifier (SCR) protection circuit, a lateral double diffused MOSFET (LDMOS) protection circuit, a bipolar junction transistor (BJT) protection circuit, and the like.

[0004] Among them, GGNMOS is a widely used electrostatic discharge protection structure. Its working mechanism is that, since the power consumption on a MOS tube is the product of the passing current and the voltage drop, under a certain ESD electrostatic current, if the voltage drop on the MOS tube can be reduced, the MOS tube junction temperature can be reduced, and the purpose of protecting the MOS tube can be achieved. As an ESD device, GGNMOS positively relies on a parasitic NPN BJT to discharge ESD current, and the NPN is composed of a drain N+ active region, a P-type substrate, and a source N+ active region; the reverse ESD current discharge path is composed of a PN diode and a gate-source connected NMOS diode, and the PN diode is composed of a P-type substrate and an N+ active region. In the ESD network of the whole chip, when the ESD time comes, the GGNMOS may be turned on in both the positive direction and the reverse direction, which is determined by the potential ESD path, and the ESD current will always flow to the low-resistance path. Therefore, the positive and reverse ESD performances of GGNMOS need to be considered in the design to ensure the reliability of the integrated circuit. As a BJT, GGNMOS is a breakdown device working mechanism, which relies on the avalanche breakdown between the drain and the substrate to form a low-resistance path to discharge ESD current after triggering.

[0005] However, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. SUMMARY

[0006] The present application solves the technical problem of providing an electrostatic discharge protection structure and a forming method thereof, which can effectively improve the performance of the electrostatic discharge protection structure.

[0007] To solve the above problems, the present application provides an electrostatic discharge protection structure, comprising: a substrate, the substrate having a buried layer region; a first well region and a second well region located adjacent to each other in the substrate, the first well region and the second well region being in contact with the buried layer region, the first well region and the buried layer region having the same conductivity type, and the first well region and the second well region having opposite conductivity types; a first implant region and a second implant region, the first implant region being located in the first well region, and the ion implantation concentration of the first implant region being greater than the ion implantation concentration of the first well region, the second implant region being located in the second well region, and the ion implantation concentration of the second implant region being greater than the ion implantation concentration of the second well region, the first implant region and the second implant region having the same conductivity type, and the first implant region and the first well region having opposite conductivity types.

[0008] Optionally, the ion implantation concentration of the first well region is greater than the ion implantation concentration of the buried layer region.

[0009] Optionally, the ion implanted in the first well region includes N-type ions; the N-type ions include phosphorus or arsenic.

[0010] Optionally, the ion implanted in the second well region includes P-type ions; the P-type ions include boron or indium.

[0011] Optionally, further comprising: a plurality of isolation structures located in the substrate, the first well region and the second well region being located between adjacent isolation structures, respectively.

[0012] Optionally, the material of the isolation structure includes silicon oxide or silicon nitride.

[0013] Optionally, further comprising: a first implant adjustment region and a second implant adjustment region, the first implant adjustment region being located in the first well region, the first implant adjustment region having the same conductivity type as the first implant region, and the ion implantation concentration of the first implant adjustment region being less than the ion implantation concentration of the first implant region, the second implant adjustment region having the same conductivity type as the second implant region, and the ion implantation concentration of the second implant adjustment region being less than the ion implantation concentration of the second implant region.

[0014] Optionally, further comprising: a first electrode connected to the first implant region; a second electrode connected to the second implant region, the polarities of the first electrode and the second electrode being opposite.

[0015] Optionally, the first well region is a plurality of first well regions, and the second well region is located between adjacent first well regions.

[0016] Correspondingly, the application also provides a forming method of the electrostatic discharge protection structure, comprising: providing a substrate, the substrate has a buried layer region; forming a first well region and a second well region in the substrate, the first well region and the second well region are in contact with the buried layer region, the first well region and the buried layer region have the same conductive type, and the first well region and the second well region have opposite conductive types; forming a first implant region and a second implant region, the first implant region is located in the first well region, and the ion implantation concentration of the first implant region is greater than that of the first well region, the second implant region is located in the second well region, and the ion implantation concentration of the second implant region is greater than that of the second well region, the first implant region and the second implant region have the same conductive type, and the first implant region and the first well region have opposite conductive types.

[0017] Optionally, the forming method of the buried layer region comprises: forming a first patterned layer on the substrate, the first patterned layer exposes part of the top surface of the substrate; taking the first patterned layer as a mask, performing ion implantation treatment on the substrate to form the buried layer region.

[0018] Optionally, the ion implantation concentration of the first well region is greater than the ion implantation concentration of the buried layer region.

[0019] Optionally, the forming method of the first well region and the second well region comprises: forming a second patterned layer on the substrate, the second patterned layer exposes part of the top surface of the substrate; taking the second patterned layer as a mask, performing ion implantation treatment on the substrate to form the first well region; after forming the first well region, removing the second patterned layer; forming a third patterned layer on the substrate, the third patterned layer exposes part of the top surface of the substrate; taking the third patterned layer as a mask, performing ion implantation treatment on the substrate to form the second well region.

[0020] Optionally, the ion implanted in the first well region comprises N-type ions; the N-type ions comprise phosphorus or arsenic.

[0021] Optionally, the ion implanted in the second well region comprises P-type ions; the P-type ions comprise boron or indium.

[0022] Optionally, after forming the first well region and the second well region, the method further comprises: forming a plurality of isolation structures in the substrate, the first well region and the second well region are respectively located between adjacent isolation structures.

[0023] Optionally, the forming method of the isolation structure comprises: forming a fourth patterned layer on the substrate, the fourth patterned layer exposes part of the top surface of the substrate; etching the substrate with the fourth patterned layer as a mask to form a plurality of isolation openings in the substrate; and forming the isolation structure in the isolation openings.

[0024] Optionally, before forming the first implantation region and the second implantation region, the method further comprises: forming a first implantation adjustment region and a second implantation adjustment region, the first implantation adjustment region is located in the first well region, the first implantation adjustment region has the same conductivity type as the first implantation region, and the ion implantation concentration of the first implantation adjustment region is less than that of the first implantation region, the second implantation adjustment region is located in the second well region, the second implantation adjustment region has the same conductivity type as the second implantation region, and the ion implantation concentration of the second implantation adjustment region is less than that of the second implantation region.

[0025] Optionally, after forming the first implantation region and the second implantation region, the method further comprises: connecting the first implantation region to a first electrode; and connecting the second implantation region to a second electrode, the polarities of the first electrode and the second electrode are opposite.

[0026] Optionally, the first well region is a plurality of, and the second well region is located between adjacent first well regions.

[0027] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0028] In the structure of the technical scheme of the present application, when the semiconductor structure works in the forward direction, the conduction current of electrostatic discharge is generated by a PNP triode, the base of the PNP triode is the first well region, the collector is the second well region, and the emitter is the first implantation region. In order to make the PNP triode conductive to form a conduction current, the voltage difference between the second implantation region and the first implantation region needs to be about 30V, which can generally meet the needs of circuit design without generating a conduction current of electrostatic discharge, so when the semiconductor structure works in the forward direction, it has good electrostatic discharge protection capability.

[0029] When the semiconductor structure works in the negative direction, the conduction current of electrostatic discharge is also generated by a PNP triode, the base of the PNP triode is the first well region, the collector is the first implantation region, and the emitter is the second implantation region. In order to make the PNP triode conductive to form a conduction current, the voltage difference between the second implantation region and the first implantation region needs to be about 10V, so when the semiconductor structure works in the forward direction, the electrostatic discharge protection capability is effectively improved.

[0030] In addition, when the semiconductor structure works in the negative direction, the negative direction maintaining voltage of the PNP triode is about 33V, which indicates that the negative direction discharge capacity of the PNP triode is excellent, and the PNP triode has good surge protection capacity, and is suitable for chip-level surge device design.

[0031] Further, the semiconductor structure further comprises a first injection adjustment region and a second injection adjustment region, the first injection adjustment region is located in the first well region, the first injection adjustment region has the same conductivity type as the first injection region, and the ion injection concentration of the first injection adjustment region is less than the ion injection concentration of the first injection region, the second injection adjustment region has the same conductivity type as the second injection region, and the ion injection concentration of the second injection adjustment region is less than the ion injection concentration of the second injection region. The resistance can be adjusted by the first injection adjustment region and the second injection adjustment region, so that the trigger voltage of the semiconductor structure working in the negative direction is improved.

[0032] In the forming method of the technical scheme, the first injection region is formed in the first well region, when the semiconductor structure works in the positive direction, the conduction current of the electrostatic discharge is generated by a PNP triode, the base of the PNP triode is the first well region, the collector is the second well region, and the emitter is the first injection region. In order to make the PNP triode conductive to form a conduction current, the voltage difference between the second injection region and the first injection region needs to be about 30V, which can generally meet the needs of circuit design and does not generate the conduction current of the electrostatic discharge, so that when the semiconductor structure works in the positive direction, the electrostatic discharge protection capacity is good.

[0033] When the semiconductor structure works in the negative direction, the conduction current of the electrostatic discharge is also generated by a PNP triode, the base of the PNP triode is the first well region, the collector is the first injection region, and the emitter is the second well region. In order to make the PNP triode conductive to form a conduction current, the voltage difference between the second injection region and the first injection region needs to be about 10V, so that when the semiconductor structure works in the positive direction, the electrostatic discharge protection capacity is effectively improved.

[0034] In addition, when the semiconductor structure works in the negative direction, the negative direction maintaining voltage of the PNP triode is about 33V, which indicates that the negative direction discharge capacity of the PNP triode is excellent, and the PNP triode has good surge protection capacity, and is suitable for chip-level surge device design.

[0035] Furthermore, before forming the first implantation region and the second implantation region, the method further includes forming a first implantation adjustment region and a second implantation adjustment region. The first implantation adjustment region is located within the first well region, has the same conductivity type as the first implantation region, and has a lower ion implantation concentration than the first implantation region. The second implantation adjustment region is located within the second well region, has the same conductivity type as the second implantation region, and has a lower ion implantation concentration than the second implantation region. The resistance can be adjusted through the first and second implantation adjustment regions, thereby increasing the trigger voltage when the semiconductor structure operates in the negative direction. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a semiconductor structure.

[0037] Figures 2 to 7 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0038] As described in the background section, the performance of existing electrostatic discharge protection structures needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0039] Figure 1 This is a schematic diagram of a semiconductor structure.

[0040] Please refer to Figure 1, providing a substrate 100, the substrate 100 having a buried layer region 101 therein, the buried layer region 101 having first ions therein; forming adjacent first well region 102, second well region 103 and third well region 104 in the substrate 100, the first well region 102, second well region 103 and third well region 104 being located on the buried layer region 101, and the second well region 103 being located between the first well region 102 and the third well region 104, the first well region 102 and the third well region 104 having the first ions therein, the second well region 103 having second ions therein, the first ions and the second ions being opposite in electrical type; forming first implant region 105 and second implant region 106 in the first well region 102, the first implant region 105 having the first ions therein, the second implant region 106 having the second ions therein; forming third implant region 107 in the second well region 103, the third implant region 107 having the second ions therein; forming fourth implant region 108 and fifth implant region 109 in the third well region, the fourth implant region 108 having the second ions therein, the fifth implant region 109 having the first ions therein; connecting the first implant region 105 and the second implant region 106 to first electrode 110; connecting the third implant region 107 to second electrode 111; connecting the fourth implant region 108 and the fifth implant region 109 to third electrode 112, the first electrode 110 and the second electrode 111 being opposite in polarity, the first electrode 110 and the third electrode 112 being same in polarity.

[0041] In the embodiment, the first ions are N-type ions, and the second ions are P-type ions. When the semiconductor structure works in forward direction, i.e. a first voltage applied on the first electrode 110 and the third electrode 112 is greater than a second voltage applied on the second electrode 111, a conduction current of electrostatic discharge is provided by a PNP triode, the base of the PNP triode being the first well region 102 or the third well region 104, the collector being the second well region 103, and the emitter being the second implant region 106 or the fourth implant region 108. In order to make the PNP triode conductive to form a conduction current, a voltage difference between the first voltage and the second voltage required is about 30V, which can generally meet the requirement of circuit design without generating a conduction current of electrostatic discharge. Therefore, the semiconductor structure has good electrostatic discharge protection ability when working in forward direction.

[0042] When the semiconductor structure works in the negative direction, that is, the first voltage applied on the first electrode 110 and the third electrode 112 is less than the second voltage applied on the second electrode 111, the conduction current of the electrostatic discharge is provided by the internal parasitic diode formed by the second well region 103 and the first well region 102 or the second well region 103 and the third well region 104. However, the conduction voltage of the diode is about 0.5V, which is easy to make the diode conduct, and thus form the conduction current of the electrostatic discharge. Therefore, when the semiconductor structure works in the positive direction, the electrostatic discharge protection capability is poor.

[0043] On this basis, the present application provides a kind of electrostatic discharge protection structure and forming method thereof, first implantation region is formed in the first well region. When the semiconductor structure works in the positive direction or negative direction, the conduction current of the electrostatic discharge is provided by PNP triode, which can effectively improve the electrostatic discharge protection capability of the semiconductor structure working in the negative direction, and also has good surge protection capability, suitable for chip-level surge device design.

[0044] In order to make the above-mentioned purpose, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0045] Figures 2 to 7 It is a structure schematic diagram of the forming process of a semiconductor structure of the embodiment of the present application.

[0046] Please refer to Figure 2 A substrate 200 is provided, and the substrate 200 has a buried layer region 201.

[0047] In the embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0048] In the embodiment, the function of the buried layer region 201 is to form isolation between the high-voltage device formed subsequently on the substrate 200 and the substrate 200.

[0049] In the embodiment, the forming method of the buried layer region 201 includes: forming a first patterned layer (not shown) on the substrate 200, which exposes part of the top surface of the substrate 200; taking the first patterned layer as a mask, performing ion implantation treatment on the substrate 200 to form the buried layer region 201.

[0050] Please refer to Figure 3Forming a first well region 202 and a second well region 203 in the substrate 200, the first well region 202 and the second well region 203 are in contact with the buried layer region 201, the first well region 202 and the buried layer region 201 have the same conductivity type, and the first well region 202 and the second well region 203 have opposite conductivity types.

[0051] In the embodiment, the forming method of the first well region 202 and the second well region 203 includes: forming a second patterning layer (not shown) on the substrate 200, the second patterning layer exposes part of the top surface of the substrate 200; taking the second patterning layer as a mask, performing ion implantation treatment on the substrate 200 to form the first well region 202; after forming the first well region 202, removing the second patterning layer; forming a third patterning layer (not shown) on the substrate 200, the third patterning layer exposes part of the top surface of the substrate 200; taking the third patterning layer as a mask, performing ion implantation treatment on the substrate 200 to form the second well region 203.

[0052] The first well region 202 is a plurality of, and the second well region 203 is located between adjacent first well regions 202, so that the first well region 202 and the second well region 203 formed finally are arranged in a staggered and uniform manner. In the embodiment, the first well region 202 is 2, and the second well region 203 is 1.

[0053] In the embodiment, the ion implanted in the first well region 202 is N-type ion, and correspondingly, the ion implanted in the buried layer region 201 is also N-type ion, and the N-type ion includes phosphorus or arsenic.

[0054] In the embodiment, the ion implantation concentration of the first well region 202 is greater than the ion implantation concentration of the buried layer region 201. By reducing the ion concentration of the buried layer region 201, it has better isolation effect, in addition, because the area of the buried layer region 201 is larger and the ion concentration is lower, in the subsequent electrostatic discharge process, the buried layer region 201 can be in contact with the first well region 202 to form a base region of a PNP transistor structure.

[0055] In the embodiment, the ion implanted in the second well region 203 is P-type ion; the P-type ion includes boron or indium.

[0056] Please refer to Figure 4 After forming the first well region 202 and the second well region 203, it also includes: forming a plurality of isolation structures 204 in the substrate 200, the first well region 202 and the second well region 203 are respectively located between adjacent isolation structures 204.

[0057] In the embodiment, the forming method of the isolation structure 204 includes: forming a fourth patterned layer (not shown) on the substrate 200, the fourth patterned layer exposes part of the top surface of the substrate 200; etching the substrate 200 with the fourth patterned layer as a mask, forming a plurality of isolation openings (not shown) in the substrate; forming the isolation structure 204 in the isolation openings.

[0058] In the embodiment, the material of the isolation structure 204 is silicon oxide; in other embodiments, the material of the isolation structure can also be silicon nitride.

[0059] In the embodiment, the isolation structure 204 is used to separate the first well region 202 and the second well region 203, and the breakdown voltage of the device can be adjusted by adjusting the size of the isolation structure 204 along the arrangement direction of the first well region 202 and the second well region 203, so as to meet the requirements of different voltage applications.

[0060] Please refer to Figure 5 After forming the isolation structure 204, a first implantation adjustment region 205 and a second implantation adjustment region 206 are formed, the first implantation adjustment region 205 is located in the first well region 202, and the second implantation adjustment region 206 is located in the second well region 203.

[0061] In the embodiment, the first implantation adjustment region 205 has the same conductivity type as the first implantation region formed subsequently, and the ion implantation concentration of the first implantation adjustment region 205 is less than that of the first implantation region, the second implantation adjustment region 206 has the same conductivity type as the second implantation region formed subsequently, and the ion implantation concentration of the second implantation adjustment region 206 is less than that of the second implantation region. The first implantation adjustment region 205 and the second implantation adjustment region 206 can adjust the resistance, so as to improve the trigger voltage of the semiconductor structure when working in the negative direction.

[0062] In other embodiments, the first implantation adjustment region 205 and the second implantation adjustment region 206 can also not be formed.

[0063] Please refer to Figure 6, the first implant region 207 is located in the first well region 202, and the ion implantation concentration of the first implant region 207 is greater than the ion implantation concentration of the first well region 202, the second implant region 208 is located in the second well region 203, and the ion implantation concentration of the second implant region 208 is greater than the ion implantation concentration of the second well region 203, the first implant region 207 and the second implant region 208 are of the same conductivity type, and the first implant region 207 and the first well region 202 are of opposite conductivity types.

[0064] In this embodiment, the ions implanted in the first implant region 207 and the second implant region 208 are P-type ions.

[0065] In this embodiment, the first implant region 207 is formed in the first well region 202. When the semiconductor structure is working in the forward direction, the conduction current of electrostatic discharge is generated by a PNP transistor, the base of the PNP transistor is the first well region 202, the collector is the second well region 203, and the emitter is the first implant region 207. In order to make the PNP transistor conductive to form a conduction current, the voltage difference between the second implant region 208 and the first implant region 207 needs to be about 30V, which can generally meet the needs of circuit design without generating a conduction current of electrostatic discharge, so when the semiconductor structure is working in the forward direction, it has good electrostatic discharge protection capability.

[0066] When the semiconductor structure is working in the negative direction, the conduction current of electrostatic discharge is also generated by a PNP transistor, the base of the PNP transistor is the first well region 202, the collector is the first implant region 207, and the emitter is the second well region 203. In order to make the PNP transistor conductive to form a conduction current, the voltage difference between the second implant region 208 and the first implant region 207 needs to be about 10V, so when the semiconductor structure is working in the forward direction, the electrostatic discharge protection capability is effectively improved.

[0067] In addition, when the semiconductor structure is working in the negative direction, the negative direction maintaining voltage of the PNP transistor is about 33V, which indicates that its negative direction discharge capability is excellent, and this characteristic has good surge protection capability, which is suitable for chip-level surge device design

[0068] Please refer to Figure 7 After the first implant region 207 and the second implant region 208 are formed, the first implant region 207 is connected to a first electrode 209, and the second implant region 208 is connected to a second electrode 210, the polarities of the first electrode 209 and the second electrode 210 are opposite.

[0069] In the embodiment, the first electrode 209 and the second electrode 210 are used to apply a voltage with a corresponding potential on the first electrode 209 and the second electrode 210 when the device structure works in a forward direction or a reverse direction.

[0070] Correspondingly, the embodiment of the present application also provides an electrostatic discharge protection structure, which will be described in detail in the following Figure 7 , comprising: a substrate 200, wherein the substrate 200 has a buried layer region 201; a first well region 202 and a second well region 203 located in the substrate 200 and adjacent to each other, the first well region 202 and the second well region 203 are in contact with the buried layer region 201, the first well region 202 and the buried layer region 201 have the same conductivity type, and the first well region 202 and the second well region 203 have opposite conductivity types; a first implant region 207 and a second implant region 208, the first implant region 207 is located in the first well region 202, and the ion implantation concentration of the first implant region 207 is greater than that of the first well region 202, the second implant region 208 is located in the second well region 203, and the ion implantation concentration of the second implant region 208 is greater than that of the second well region 203, the first implant region 207 and the second implant region 208 have the same conductivity type, and the first implant region 207 and the first well region 202 have opposite conductivity types.

[0071] In the embodiment, when the semiconductor structure works in a forward direction, the first implant region 207 located in the first well region 202 generates a conduction current of electrostatic discharge by a PNP triode, the base of the PNP triode is the first well region 202, the collector is the second well region 203, and the emitter is the first implant region 207. In order to make the PNP triode conductive to form a conduction current, a voltage difference of about 30V is required between the second implant region 208 and the first implant region 207, which can generally meet the needs of circuit design without generating a conduction current of electrostatic discharge, so that the semiconductor structure has good electrostatic discharge protection capability when working in a forward direction.

[0072] When the semiconductor structure works in a reverse direction, the conduction current of electrostatic discharge is also generated by a PNP triode, the base of the PNP triode is the first well region 202, the collector is the first implant region 207, and the emitter is the second well region 203. In order to make the PNP triode conductive to form a conduction current, a voltage difference of about 10V is required between the second implant region 208 and the first implant region 207, so that the electrostatic discharge protection capability is effectively improved when the semiconductor structure works in a forward direction.

[0073] In addition, when the semiconductor structure operates in the negative direction, the negative sustaining voltage of the PNP transistor is around 33V, indicating that it has excellent negative discharge capability. This characteristic provides good surge protection and is suitable for use in chip-level surge device design.

[0074] In this embodiment, the ion implantation concentration of the first well region 202 is greater than the ion implantation concentration of the buried layer region 201.

[0075] In this embodiment, the ions implanted in the first well region 202 are N-type ions; the N-type ions include phosphorus or arsenic.

[0076] In this embodiment, the ions implanted in the second well region 203 are P-type ions; the P-type ions include boron or indium.

[0077] In this embodiment, it further includes a plurality of isolation structures 204 located within the substrate 200, wherein the first well region 202 and the second well region 203 are respectively located between adjacent isolation structures 204.

[0078] In this embodiment, the material of the isolation structure 204 is silicon oxide; in other embodiments, the material of the isolation structure may also be silicon nitride.

[0079] In this embodiment, the system further includes a first implantation adjustment region 205 and a second implantation adjustment region 206. The first implantation adjustment region 205 is located within the first well region 202. The first implantation adjustment region 205 has the same conductivity type as the first implantation region 207, and the ion implantation concentration of the first implantation adjustment region 205 is lower than that of the first implantation region 207. The second implantation adjustment region 208 has the same conductivity type as the second implantation region 208, and the ion implantation concentration of the second implantation adjustment region 208 is lower than that of the second implantation region 208. The resistance can be adjusted by the first implantation adjustment region 205 and the second implantation adjustment region 206, thereby increasing the trigger voltage when the semiconductor structure operates in the negative direction.

[0080] In this embodiment, it further includes: a first electrode 209 connected to the first injection region 207; and a second electrode 210 connected to the second injection region 208, wherein the first electrode 209 and the second electrode 210 have opposite polarities.

[0081] In this embodiment, there are multiple first well regions 202, and the second well regions 203 are located between adjacent first well regions 202.

[0082] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. An electrostatic discharge protection structure, characterized by, The method comprises: providing a substrate, the substrate having a buried region therein; forming a first well region and a second well region adjacent to each other in the substrate, the first well region and the second well region being in contact with the buried region, the first well region and the buried region having the same conductivity type, and the first well region and the second well region having opposite conductivity types; forming a plurality of isolation structures in the substrate, the first well region and the second well region being located between adjacent ones of the isolation structures, respectively; forming a first implanted region and a second implanted region, the first implanted region being located in the first well region, and the first implanted region having a higher ion implantation concentration than the first well region, the second implanted region being located in the second well region, and the second implanted region having a higher ion implantation concentration than the second well region, the first implanted region and the second implanted region having the same conductivity type, and the first implanted region and the first well region having opposite conductivity types.

2. The electrostatic discharge protection structure of claim 1, wherein, The first well region has a higher ion implantation concentration than the buried region.

3. The electrostatic discharge protection structure of claim 1, wherein: The ion implanted in the first well region comprises N-type ions. The N-type ions comprise phosphorus or arsenic.

4. The electrostatic discharge protection structure of claim 1, wherein: The ion implanted in the second well region comprises P-type ions. The P-type ions comprise boron or indium.

5. The electrostatic discharge protection structure of claim 1, wherein, The material of the isolation structures comprises silicon oxide or silicon nitride.

6. The electrostatic discharge protection structure of claim 1, wherein: The method further comprises: forming a first implanted adjustment region and a second implanted adjustment region, the first implanted adjustment region being located in the first well region, the first implanted adjustment region having the same conductivity type as the first implanted region, and the first implanted adjustment region having a lower ion implantation concentration than the first implanted region, the second implanted adjustment region having the same conductivity type as the second implanted region, and the second implanted adjustment region having a lower ion implantation concentration than the second implanted region.

7. The electrostatic discharge protection structure of claim 1, wherein: The method further comprises: forming a first electrode connected to the first implanted region; forming a second electrode connected to the second implanted region, the first electrode and the second electrode having opposite polarities.

8. The electrostatic discharge protection structure of claim 1, wherein, The first well regions are a plurality of first well regions, and the second well region is located between adjacent ones of the first well regions.

9. A method of forming an electrostatic discharge protection structure, comprising: The method comprises: providing a substrate, the substrate having a buried region therein; forming a first well region and a second well region adjacent to each other in the substrate, the first well region and the second well region being in contact with the buried region, the first well region and the buried region having the same conductivity type, and the first well region and the second well region having opposite conductivity types; forming a plurality of isolation structures in the substrate after forming the first well region and the second well region, the first well region and the second well region being located between adjacent ones of the isolation structures, respectively; forming a first implanted region and a second implanted region, the first implanted region being located in the first well region, and the first implanted region having a higher ion implantation concentration than the first well region, the second implanted region being located in the second well region, and the second implanted region having a higher ion implantation concentration than the second well region, the first implanted region and the second implanted region having the same conductivity type, and the first implanted region and the first well region having opposite conductivity types.

10. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The forming method of the buried layer region comprises: forming a first patterning layer on the substrate, the first patterning layer exposing part of the top surface of the substrate; taking the first patterning layer as a mask, performing ion implantation treatment on the substrate to form the buried layer region.

11. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The ion implantation concentration of the first well region is greater than the ion implantation concentration of the buried layer region.

12. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The forming method of the first well region and the second well region comprises: forming a second patterning layer on the substrate, the second patterning layer exposing part of the top surface of the substrate; taking the second patterning layer as a mask, performing ion implantation treatment on the substrate to form the first well region; after forming the first well region, removing the second patterning layer; forming a third patterning layer on the substrate, the third patterning layer exposing part of the top surface of the substrate; taking the third patterning layer as a mask, performing ion implantation treatment on the substrate to form the second well region.

13. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The ion implanted in the first well region comprises N-type ions; the N-type ions comprise phosphorus or arsenic.

14. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The ion implanted in the second well region comprises P-type ions. The P-type ions comprise boron or indium.

15. The method for forming the electrostatic discharge protection structure as described in claim 14, characterized in that, The forming method of the isolation structure comprises: forming a fourth patterning layer on the substrate, the fourth patterning layer exposing part of the top surface of the substrate; taking the fourth patterning layer as a mask, etching the substrate to form a plurality of isolation openings in the substrate; forming the isolation structure in the isolation openings.

16. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, Before forming the first implantation region and the second implantation region, further comprising: forming a first implantation adjustment region and a second implantation adjustment region, the first implantation adjustment region being located in the first well region, the first implantation adjustment region having the same conductivity type as the first implantation region, and the ion implantation concentration of the first implantation adjustment region being less than the ion implantation concentration of the first implantation region, the second implantation adjustment region being located in the second well region, the second implantation adjustment region having the same conductivity type as the second implantation region, and the ion implantation concentration of the second implantation adjustment region being less than the ion implantation concentration of the second implantation region.

17. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, After forming the first implantation region and the second implantation region, further comprising: connecting the first implantation region to a first electrode; connecting the second implantation region to a second electrode, the polarities of the first electrode and the second electrode being opposite.

18. The method for forming the electrostatic discharge protection structure as described in claim 9, characterized in that, The first well region is a plurality of, and the second well region is located between adjacent first well regions.

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