Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate, a first transistor, and a second transistor. The first transistor is disposed on the substrate and includes a first metal oxide semiconductor layer. The second transistor is disposed on the substrate and includes a second metal oxide semiconductor layer and a third metal oxide semiconductor layer. The third metal oxide semiconductor layer is directly stacked on the second metal oxide semiconductor layer. The second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer. The oxygen concentration of the first metal oxide semiconductor layer is lower than that of the second metal oxide semiconductor layer, and the oxygen concentration of the second metal oxide semiconductor layer is lower than that of the third metal oxide semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Generally, many semiconductor elements are included in an electronic device. For example, a display device often includes many thin film transistors, and these thin film transistors are formed by depositing various different thin films (such as semiconductors, metals, dielectric layers, etc.) on a substrate. In a display device, the thin film transistors can be disposed in a pixel structure or in a driving circuit.

[0003] As the resolution of the display device increases, the size of the thin film transistors continues to shrink. In order to enable small-sized thin film transistors to provide a sufficiently large current, the semiconductor layer in the thin film transistors needs to have a high carrier mobility. However, thin film transistors with high carrier mobility usually have a relatively large leakage current, resulting in poor reliability, and are not suitable as switching elements in a pixel structure. Summary of the Invention

[0004] The present invention provides a semiconductor device, which provides a thin film transistor with high carrier mobility and a thin film transistor with high reliability.

[0005] The present invention provides a manufacturing method of a semiconductor device, which provides a thin film transistor with high carrier mobility and a thin film transistor with high reliability.

[0006] An embodiment of the present invention provides a semiconductor device, including: a substrate; a first transistor disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer; and a second transistor disposed on the substrate, and the second transistor includes a second metal oxide semiconductor layer and a third metal oxide semiconductor layer, wherein the third metal oxide semiconductor layer is directly stacked on the second metal oxide semiconductor layer, the second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than that of the second metal oxide semiconductor layer, and the oxygen concentration of the second metal oxide semiconductor layer is lower than that of the third metal oxide semiconductor layer.

[0007] An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer belong to the same film layer; forming a third metal oxide semiconductor layer directly stacked on the second metal oxide semiconductor layer; and performing an annealing process to make the oxygen concentration of the first metal oxide semiconductor layer lower than that of the second metal oxide semiconductor layer. Description of the Drawings

[0008] Figures 1A to 1G FIG. is a schematic cross-sectional view of the process flow of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein, Figure 1G FIG. is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 FIG. is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

[0010] Figure 3 FIG. is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

[0011] Figure 4 FIG. is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present invention.

[0012] Description of Reference Numerals:

[0013] 10, 20, 30, 40: Semiconductor device

[0014] 110: Substrate

[0015] 102, 112: Buffer layer

[0016] 121, 121’, 221, 421: First metal oxide semiconductor layer

[0017] 121a, 221a: First part

[0018] 121b, 221b: Second part

[0019] 121c, 221c: Channel part

[0020] 122, 122I, 222, 422: Second metal oxide semiconductor layer

[0021] 122a, 222a: First part

[0022] 122b, 222b: Second part

[0023] 122c, 222c: Channel part

[0024] 130, 230, 430: The third metal oxide semiconductor layer

[0025] 130a, 230a: The first part

[0026] 130b, 230b: The second part

[0027] 130c, 230c: The channel part

[0028] 140, 240, 440: The first insulating layer

[0029] 151, 251, 451: The first gate

[0030] 152, 252, 452: The second gate

[0031] 160, 260: The second insulating layer

[0032] 171, 271, 471: The first source

[0033] 172, 272, 472: The first drain

[0034] 173, 273, 473: The second source

[0035] 174, 274, 474: The second drain

[0036] 180: The passivation layer

[0037] IA: The doping process

[0038] T1, T1b, T1c: The first transistor

[0039] T2, T2a, T2b, T2c: The second transistor

[0040] TA: The annealing process

[0041] V1, V2, V3, V4: The vias Detailed implementation manners

[0042] Figures 1A to 1G It is a cross-sectional schematic diagram of the step flow of the manufacturing method of a semiconductor device according to an embodiment of the present invention. Hereinafter, in conjunction with Figures 1A to 1G the manufacturing method of the semiconductor device 10 will be described.

[0043] Please refer to Figure 1A , first, a substrate 110 is provided. For example, the material of the substrate 110 may include glass, quartz, organic polymers, or light-impermeable / reflection materials (such as: conductive materials, metals, wafers, ceramics, or other applicable materials) or other applicable materials.

[0044] Next, a buffer layer 102 is formed on the substrate 110. The method of forming the buffer layer 102 is, for example, physical vapor deposition, chemical vapor deposition, or other suitable methods. The buffer layer 102 can be a single-layer or multi-layer insulating layer, and the insulating layer can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (oxynitrides, SiONx), or other suitable materials or stacked layers of the above materials.

[0045] Next, a first metal oxide semiconductor layer 121 and a second metal oxide semiconductor layer 122 are formed on the substrate 110 and the buffer layer 102. For example, the method of forming the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 can include the following steps: First, a blanket semiconductor material layer (not shown) is formed on the substrate 110 and the buffer layer 102; Next, a patterned photoresist (not shown) is formed on the semiconductor material layer by a lithography process; Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the semiconductor material layer to form the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122; After that, the patterned photoresist is removed. That is to say, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 can be formed by patterning the same film layer.

[0046] The first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 may contain at least one of indium, zinc, tungsten, tin, and gallium elements. For example, the materials of the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 can include indium zinc oxide (InZnO, IZO), indium tungsten oxide (InWO, IWO), indium tungsten zinc oxide (InWZnO, IWZO), indium zinc tin oxide (InZnSnO, IZTO), indium gallium tin oxide (InGaSnO, IGTO), or indium gallium zinc tin oxide (InGaZnSnO, IGZTO), but the present invention is not limited thereto.

[0047] Please refer to Figure 1B, Next, a third metal oxide semiconductor layer 130 is formed on the second metal oxide semiconductor layer 122, and the third metal oxide semiconductor layer 130 may completely overlap the second metal oxide semiconductor layer 122, but is not limited thereto. In some embodiments, the area of the third metal oxide semiconductor layer 130 is larger than the area of the second metal oxide semiconductor layer 122, and the third metal oxide semiconductor layer 130 may completely cover the top surface and the side surface of the second metal oxide semiconductor layer 122. In some embodiments, the area of the third metal oxide semiconductor layer 130 is slightly smaller than the area of the second metal oxide semiconductor layer 122, and the third metal oxide semiconductor layer 130 does not overlap with a part of the second metal oxide semiconductor layer 122. The forming method of the third metal oxide semiconductor layer 130 may be similar to the forming methods of the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122, and will not be described herein again.

[0048] The chemical stability of the material of the third metal oxide semiconductor layer 130 may be higher than that of the material of the first metal oxide semiconductor layer 121 and / or the second metal oxide semiconductor layer 122. The third metal oxide semiconductor layer 130 may contain at least one of indium element, zinc element, and gallium element, and the oxygen concentration of the third metal oxide semiconductor layer 130 is higher than that of the first metal oxide semiconductor layer 121 or the second metal oxide semiconductor layer 122. For example, the material of the third metal oxide semiconductor layer 130 may include indium gallium oxide (InGaO, IGO) or indium gallium zinc oxide (InGaZnO, IGZO), but the present invention is not limited thereto.

[0049] Please refer to Figure 1C, then, an annealing treatment (Annealing) TA is performed. The annealing treatment TA can be carried out at a temperature between 200°C and 500°C (such as 280°C, 350°C or 420°C), and the time of the annealing treatment TA can be between 15 minutes and 120 minutes, such as 30 minutes, 60 minutes or 90 minutes, but the present invention is not limited thereto. Since the chemical stability of the third metal oxide semiconductor layer 130 is higher than that of the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122, during the annealing treatment TA, the first metal oxide semiconductor layer 121 and the second metal oxide semiconductor layer 122 are more likely to be deoxidized than the third metal oxide semiconductor layer 130. However, since the second metal oxide semiconductor layer 122 is covered by the third metal oxide semiconductor layer 130, the third metal oxide semiconductor layer 130 can block the oxygen from escaping from the second metal oxide semiconductor layer 122 and even supply oxygen to the second metal oxide semiconductor layer 122. Specifically, the annealing treatment TA can deoxidize the first metal oxide semiconductor layer 121 to transform it into the first metal oxide semiconductor layer 121', and at the same time, the third metal oxide semiconductor layer 130 can block the oxygen from escaping from the second metal oxide semiconductor layer 122. Alternatively, in some embodiments, the third metal oxide semiconductor layer 130 can supply oxygen to the second metal oxide semiconductor layer 122, such that the oxygen vacancy concentration of the first metal oxide semiconductor layer 121' is higher than that of the second metal oxide semiconductor layer 122. In this way, after the annealing treatment TA, the oxygen concentration of the first metal oxide semiconductor layer 121' will be lower than that of the second metal oxide semiconductor layer 122, and the oxygen concentration of the second metal oxide semiconductor layer 122 is still lower than that of the third metal oxide semiconductor layer 130, so that the carrier mobility of the first metal oxide semiconductor layer 121' can be greater than that of the second metal oxide semiconductor layer 122.

[0050] In some embodiments, crystalline grains can be locally formed in the deoxidized first metal oxide semiconductor layer 121', such that the crystallinity of the first metal oxide semiconductor layer 121' is higher than that of the second metal oxide semiconductor layer 122. In certain embodiments, the above-mentioned crystalline grains can have a nano-scale particle size, such as a particle size less than 1 nm. In other words, the crystallinity of the first metal oxide semiconductor layer 121' after undergoing the annealing treatment TA can be substantially between amorphous and polycrystalline.

[0051] Please refer to Figure 1D, Next, a first insulating layer 140 is formed on the substrate 110, and the first insulating layer 140 covers the first metal oxide semiconductor layer 121', the second metal oxide semiconductor layer 122, and the third metal oxide semiconductor layer 130. The first insulating layer 140 can be formed using chemical vapor deposition or other suitable methods. The material of the first insulating layer 140 can include transparent insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, organic polymers, or a stack of the above materials, but the present invention is not limited thereto.

[0052] Please refer to Figure 1E , Next, a first gate 151 and a second gate 152 are respectively formed on the first metal oxide semiconductor layer 121' and the third metal oxide semiconductor layer 130. The forming method of the first gate 151 and the second gate 152 can include the following steps. First, a gate metal layer (not shown) is formed on the first insulating layer 140. Subsequently, a patterned photoresist (not shown) is formed on the gate metal layer using a photolithography process. Then, using the patterned photoresist as a mask, a wet or dry etching process is performed on the gate metal layer to form the first gate 151 and the second gate 152. After that, the patterned photoresist is removed. The orthographic projection of the first gate 151 on the substrate 110 overlaps the orthographic projection of the first metal oxide semiconductor layer 121' on the substrate 110, and the orthographic projection of the second gate 152 on the substrate 110 overlaps the orthographic projection of the third metal oxide semiconductor layer 130 on the substrate 110. The materials of the first gate 151 and the second gate 152 can include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or an alloy of any combination of the above metals, or a stack of the above metals and / or alloys, but is not limited thereto. The first gate 151 and the second gate 152 can also use other conductive materials, such as: metal nitrides, metal oxides, metal oxynitrides, stacked layers of metals and other conductive materials, or other materials with conductive properties.

[0053] In some embodiments, after forming the first gate 151 and the second gate 152, a doping process IA may be performed. The doping process IA may use the first gate 151 and the second gate 152 as masks to dope the first metal oxide semiconductor layer 121' and the third metal oxide semiconductor layer 130. After the doping process IA, a portion of the first metal oxide semiconductor layer 121' that overlaps the first gate 151 may form a channel portion 121c, and a first portion 121a and a second portion 121b of the first metal oxide semiconductor layer 121' that do not overlap the first gate 151 may have a lower resistance than the channel portion 121c. Similarly, a portion of the third metal oxide semiconductor layer 130 that overlaps the second gate 152 may form a channel portion 130c, and a first portion 130a and a second portion 130b of the third metal oxide semiconductor layer 130 that do not overlap the second gate 152 may have a lower resistance than the channel portion 130c. The doping process IA may implant hydrogen elements into the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 130a and the second portion 130b of the third metal oxide semiconductor layer 130, so that the carrier mobility of the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 130a and the second portion 130b of the third metal oxide semiconductor layer 130 increases. In some embodiments, the doping process IA may be a hydrogen plasma treatment. In some embodiments, the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 130a and the second portion 130b of the third metal oxide semiconductor layer 130 can respectively form ohmic contacts with the subsequently formed first source 171, first drain 172, second source 173, and second drain 174.

[0054] Please refer to Figure 1F, Next, a second insulating layer 160 is formed on the first gate 151, the second gate 152, and the first insulating layer 140. The method of forming the second insulating layer 160 may include the following steps. First, a dielectric material layer (not shown) is formed on the substrate 110 by chemical vapor deposition or physical vapor deposition. Next, a patterned photoresist (not shown) is formed on the dielectric material layer by a photolithography process. Subsequently, using the patterned photoresist as a mask, a wet or dry etching process is performed on the dielectric material layer to form the second insulating layer 160 having vias V1, V2, V3, and V4. After that, the patterned photoresist is removed. The vias V1 and V2 may respectively expose a first portion 121a and a second portion 121b of the first metal oxide semiconductor layer 121', and the vias V3 and V4 may respectively expose a first portion 130a and a second portion 130b of the third metal oxide semiconductor layer 130. The material of the second insulating layer 160 includes, for example, silicon oxide, silicon oxynitride, an organic polymer, or other suitable materials, or a stacked layer of the above materials.

[0055] In some embodiments, the reactants used to form the second insulating layer 160 contain hydrogen elements, and during the formation of the second insulating layer 160 or in a subsequent heat treatment process, the hydrogen elements may migrate or diffuse into the first metal oxide semiconductor layer 121' and the third metal oxide semiconductor layer 130, thereby adjusting the hydrogen content of the first portion 121a and the second portion 121b of the first metal oxide semiconductor layer 121' and the first portion 130a and the second portion 130b of the third metal oxide semiconductor layer 130, thereby improving their conductivity.

[0056] Please refer to Figure 1G , Next, a first source 171, a first drain 172, a second source 173, and a second drain 174 are formed on the second insulating layer 160, and the first source 171 and the first drain 172 are electrically connected to the first metal oxide semiconductor layer 121', and the second source 173 and the second drain 174 are electrically connected to the third metal oxide semiconductor layer 130, thereby forming a first transistor T1 and a second transistor T2, and both the first transistor T1 and the second transistor T2 are self-aligned top gate thin film transistors.

[0057] For example, the method of forming the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may include the following steps. First, a conductive layer (not shown) is formed on the substrate 110 by chemical vapor deposition or physical vapor deposition. Next, a patterned photoresist (not shown) is formed on the conductive layer using a photolithography process. Subsequently, the patterned photoresist is used as a mask to perform a wet or dry etching process on the conductive layer to form the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174. After that, the patterned photoresist is removed. In other words, the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may belong to the same film layer. The materials of the first source electrode 171, the first drain electrode 172, the second source electrode 173, and the second drain electrode 174 may include chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, alloys of the foregoing metals, or stacked layers of the foregoing metals and / or alloys, or other conductive materials.

[0058] In this embodiment, the first source electrode 171 may be electrically connected to the first portion 121a of the first metal oxide semiconductor layer 121' through the via V1, the first drain electrode 172 may be electrically connected to the second portion 121b of the first metal oxide semiconductor layer 121' through the via V2, the second source electrode 173 may be electrically connected to the first portion 130a of the third metal oxide semiconductor layer 130 through the via V3, and the second drain electrode 174 may be electrically connected to the second portion 130b of the third metal oxide semiconductor layer 130 through the via V4.

[0059] In some embodiments, a passivation layer 180 may also be formed on the first source electrode 171, the first drain electrode 172, the second source electrode 173, the second drain electrode 174, and the second insulating layer 160. The passivation layer 180 may be formed by plasma enhanced chemical vapor deposition or other suitable processes, and the material of the passivation layer 180 may be silicon nitride or other suitable materials.

[0060] Figure 1G is a cross-sectional schematic diagram of a semiconductor device 10 according to an embodiment of the present invention. In this embodiment, the semiconductor device 10 may include: a substrate 110, a first transistor T1, and a second transistor T2, and both the first transistor T1 and the second transistor T2 are disposed on the substrate 110.

[0061] In some embodiments, the semiconductor device 10 may further include a buffer layer 102, and the buffer layer 102 may be located between the first transistor T1 and the second transistor T2 and the substrate 110 to prevent impurities in the substrate 110 from diffusing into the first transistor T1 and the second transistor T2.

[0062] The first transistor T1 includes at least a first metal oxide semiconductor layer 121'. For example, the first transistor T1 may include a first metal oxide semiconductor layer 121', a first gate 151, a first source 171, and a first drain 172, and a first insulating layer 140 may be located between the first gate 151 and the first metal oxide semiconductor layer 121', and a second insulating layer 160 may be located between the first source 171 and the first drain 172 and the first gate 151.

[0063] The first metal oxide semiconductor layer 121' may include a first portion 121a, a second portion 121b, and a channel portion 121c. The channel portion 121c overlaps the first gate 151. The first source 171 is electrically connected to the first portion 121a, the first drain 172 is electrically connected to the second portion 121b, and the channel portion 121c is located between the first portion 121a and the second portion 121b.

[0064] The second transistor T2 includes at least a second metal oxide semiconductor layer 122 and a third metal oxide semiconductor layer 130. The third metal oxide semiconductor layer 130 is directly stacked on the second metal oxide semiconductor layer 122, and the second metal oxide semiconductor layer 122 and the first metal oxide semiconductor layer 121' may belong to the same film layer. For example, the second transistor T2 may include a second metal oxide semiconductor layer 122, a third metal oxide semiconductor layer 130, a second gate 152, a second source 173, and a second drain 174, and the first insulating layer 140 is located between the second gate 152 and the third metal oxide semiconductor layer 130, and the second insulating layer 160 is located between the second source 173 and the second drain 174 and the second gate 152.

[0065] The third metal oxide semiconductor layer 130 may include a first portion 130a, a second portion 130b, and a channel portion 130c. The channel portion 130c overlaps the second gate 152. The second source 173 is electrically connected to the first portion 130a, the second drain 174 is electrically connected to the second portion 130b, and the channel portion 130c is located between the first portion 130a and the second portion 130b.

[0066] In some embodiments, the thickness of the first metal oxide semiconductor layer 121' or the second metal oxide semiconductor layer 122 may be between and For example, or However, the present invention is not limited thereto. In some embodiments, the thickness of the third metal oxide semiconductor layer 130 may be between and For example, or However, the present invention is not limited thereto.

[0067] In some embodiments, the carrier mobility of the first metal oxide semiconductor layer 121' of the first transistor T1 is greater than 50 cm 2 / Vs, and the overall carrier mobility of the second metal oxide semiconductor layer 122 and the third metal oxide semiconductor layer 130 of the second transistor T2 is about between 10 and 20 cm 2 / Vs, and the threshold voltage of the second transistor T2 is higher than that of the first transistor T1. It can be seen that in the semiconductor device 10, by directly stacking the third metal oxide semiconductor layer 130 on the second metal oxide semiconductor layer 122 and performing the annealing process TA, the oxygen concentration of the first metal oxide semiconductor layer 121' is lower than that of the second metal oxide semiconductor layer 122, and the oxygen concentration of the second metal oxide semiconductor layer 122 is lower than that of the third metal oxide semiconductor layer 130. It is indeed possible to make the carrier mobility of the first metal oxide semiconductor layer 121' greater than that of the second metal oxide semiconductor layer 122, and make the leakage current of the second transistor T2 less than that of the first transistor T1, so that the first transistor T1 is suitable for use as a driving element, while the second transistor T2 has high reliability and is suitable for use as a switching element.

[0068] Figure 2 is a cross-sectional schematic view of a semiconductor device 20 according to another embodiment of the present invention. It must be noted here that Figure 2 the embodiments of Figures 1A to 1G adopt the component numbers and some contents of the embodiments of

[0069] wherein the same or similar component numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments, which will not be elaborated here.

[0070] Figure 2 The semiconductor device 20 shown in Figure 1GThe main difference of the semiconductor device 10 shown is that: the second metal oxide semiconductor layer 122I of the second transistor T2a of the semiconductor device 20 may include a channel portion 122c, a first portion 122a and a second portion 122b with a relatively high hydrogen content.

[0071] For example, in this embodiment, during the doping process, the hydrogen element implanted into the first portion 130a of the third metal oxide semiconductor layer 130 may further diffuse into the second metal oxide semiconductor layer 122I to form the first portion 122a with a relatively high hydrogen content. Similarly, during the doping process, the hydrogen element implanted into the second portion 130b of the third metal oxide semiconductor layer 130 may further diffuse into the second metal oxide semiconductor layer 122I to form the second portion 122b with a relatively high hydrogen content, and the channel portion 122c is located between the first portion 122a and the second portion 122b. In this way, the carrier mobility of the second metal oxide semiconductor layer 122I of the second transistor T2a and the third metal oxide semiconductor layer 130 as a whole can be improved.

[0072] Figure 3 It is a cross-sectional schematic diagram of a semiconductor device 30 according to another embodiment of the present invention. It must be noted here that Figure 3 The embodiment of Figures 1A to 1G The component numbers and some contents of the embodiment of

[0073] In this embodiment, the semiconductor device 30 may include: a substrate 110, a buffer layer 112, a first transistor T1b, a second transistor T2b, and a passivation layer 180. The first transistor T1b and the second transistor T2b are disposed on the substrate 110 and between the buffer layer 112 and the passivation layer 180.

[0074] Figure 3 The semiconductor device 30 shown and as Figure 1G The main difference of the semiconductor device 10 shown is that: the first transistor T1b and the second transistor T2b of the semiconductor device 30 are self-aligned bottomgate thin film transistors.

[0075] For example, in this embodiment, the first transistor T1b may include a first metal oxide semiconductor layer 221, a first gate 251, a first source 271, and a first drain 272. The first metal oxide semiconductor layer 221 may be located between the first source 271 and the first gate 251 and between the first drain 272 and the first gate 251. And the first insulating layer 240 may be located between the first gate 251 and the first metal oxide semiconductor layer 221, and the second insulating layer 260 may be located between the first source 271 and the first drain 272 and the first metal oxide semiconductor layer 221.

[0076] The second transistor T2b may include a second metal oxide semiconductor layer 222, a third metal oxide semiconductor layer 230, a second gate 252, a second source 273, and a second drain 274. Among them, the second metal oxide semiconductor layer 222 and the third metal oxide semiconductor layer 230 may be located between the second source 273 and the second drain 274 and the second gate 252. The third metal oxide semiconductor layer 230 is directly stacked on the second metal oxide semiconductor layer 222. The second metal oxide semiconductor layer 222 and the first metal oxide semiconductor layer 221 may belong to the same film layer. The first insulating layer 240 is located between the second gate 252 and the second metal oxide semiconductor layer 222, and the second insulating layer 260 is located between the second source 273 and the second drain 274 and the third metal oxide semiconductor layer 230.

[0077] In this embodiment, the oxygen concentration of the first metal oxide semiconductor layer 221 of the semiconductor device 30 is lower than that of the second metal oxide semiconductor layer 222, and the oxygen concentration of the second metal oxide semiconductor layer 222 is lower than that of the third metal oxide semiconductor layer 230. In addition, the oxygen vacancy concentration of the first metal oxide semiconductor layer 221 is higher than that of the second metal oxide semiconductor layer 222, and the crystallinity of the first metal oxide semiconductor layer 221 is higher than that of the second metal oxide semiconductor layer 222. In this way, the carrier mobility of the first metal oxide semiconductor layer 221 can be made greater than that of the second metal oxide semiconductor layer 222, so that the first transistor T1b can be suitable for use as a driving element, and the threshold voltage of the second transistor T2b can be higher than that of the first transistor T1b, so that the leakage current of the second transistor T2b is less than that of the first transistor T1b, and the second transistor T2b has a higher reliability and is suitable for use as a switching element.

[0078] In addition, in the present embodiment, the first metal oxide semiconductor layer 221 may include a first portion 221a, a second portion 221b, and a channel portion 221c, wherein the channel portion 221c overlaps the first gate 251, the channel portion 221c connects the first portion 221a and the second portion 221b, and the first portion 221a and the second portion 221b may have a lower resistance than the channel portion 221c. The second metal oxide semiconductor layer 222 may include a first portion 222a, a second portion 222b, and a channel portion 222c, wherein the channel portion 222c overlaps the second gate 252, the channel portion 222c connects the first portion 222a and the second portion 222b, and the first portion 222a and the second portion 222b may have a lower resistance than the channel portion 222c. The third metal oxide semiconductor layer 230 may include a first portion 230a, a second portion 230b, and a channel portion 230c, wherein the channel portion 230c overlaps the second gate 252, the channel portion 230c connects the first portion 230a and the second portion 230b, and the first portion 230a and the second portion 230b may have a lower resistance than the channel portion 230c.

[0079] For example, the first gate 251 and the second gate 252 may be used as masks to perform backside excimer laser processing on the first metal oxide semiconductor layer 221, the second metal oxide semiconductor layer 222, and the third metal oxide semiconductor layer 230, so as to reduce the resistance of the first portions 221a, 222a, 230a and the second portions 221b, 222b, 230b that do not overlap the first gate 251 and the second gate 252.

[0080] Figure 4 is a cross-sectional schematic diagram of a semiconductor device 40 according to still another embodiment of the present invention. It must be noted here that Figure 4 The embodiment of Figure 3 adopts the component numbers and partial contents of the embodiment of

[0081] In the present embodiment, the semiconductor device 40 may include: a substrate 110, a buffer layer 112, a first transistor T1c, a second transistor T2c, and a passivation layer 180. The first transistor T1c and the second transistor T2c are disposed on the substrate 110 and between the buffer layer 112 and the passivation layer 180.

[0082] Figure 4 The semiconductor device 40 shown and as in Figure 3The main difference of the semiconductor device 30 shown is that the first transistor T1c and the second transistor T2c of the semiconductor device 40 are back channel etching bottom gate thin film transistors.

[0083] For example, in this embodiment, the first transistor T1c may include a first metal oxide semiconductor layer 421, a first gate 451, a first source 471, and a first drain 472. The first metal oxide semiconductor layer 421 may be located between the first source 471 and the first gate 451 and between the first drain 472 and the first gate 451. The first insulating layer 440 may be located between the first gate 451 and the first metal oxide semiconductor layer 421. The first source 471 and the first drain 472 are respectively connected to both ends of the first metal oxide semiconductor layer 421, and no second insulating layer needs to be provided between the first source 471 and the first drain 472 and the first metal oxide semiconductor layer 421. In addition, the region where the first metal oxide semiconductor layer 421 is connected to the first source 471 and the first drain 472 may overlap the first gate 451.

[0084] The second transistor T2c may include a second metal oxide semiconductor layer 422, a third metal oxide semiconductor layer 430, a second gate 452, a second source 473, and a second drain 474. Among them, the third metal oxide semiconductor layer 430 is directly stacked on the second metal oxide semiconductor layer 422. The second metal oxide semiconductor layer 422 and the third metal oxide semiconductor layer 430 may be located between the second source 473 and the second gate 452 and between the second drain 474 and the second gate 452. The second metal oxide semiconductor layer 422 and the first metal oxide semiconductor layer 421 may belong to the same film layer. The first insulating layer 440 is located between the second gate 452 and the second metal oxide semiconductor layer 422. The second source 473 and the second drain 474 are respectively connected to both ends of the second metal oxide semiconductor layer 422, and the second source 473 and the second drain 474 are respectively connected to both ends of the third metal oxide semiconductor layer 430. Similarly, no second insulating layer needs to be provided between the second source 473 and the second drain 474 and the third metal oxide semiconductor layer 430. In addition, the region where the third metal oxide semiconductor layer 430 is connected to the second source 473 and the second drain 474 may overlap the second gate 452.

[0085] In this embodiment, the oxygen concentration of the first metal oxide semiconductor layer 421 of the semiconductor device 40 is lower than that of the second metal oxide semiconductor layer 422, and the oxygen concentration of the second metal oxide semiconductor layer 422 is lower than that of the third metal oxide semiconductor layer 430. In addition, the oxygen vacancy concentration of the first metal oxide semiconductor layer 421 is higher than that of the second metal oxide semiconductor layer 422, and the crystallinity of the first metal oxide semiconductor layer 421 is higher than that of the second metal oxide semiconductor layer 422. In this way, the carrier mobility of the first metal oxide semiconductor layer 421 can be made greater than that of the second metal oxide semiconductor layer 422, so that the first transistor T1c can be suitable for use as a driving element, and the threshold voltage of the second transistor T2c can be higher than that of the first transistor T1c, so that the leakage current of the second transistor T2c is less than that of the first transistor T1c, and the second transistor T2c has a higher reliability and is suitable for use as a switching element.

[0086] In summary, in the manufacturing method of the semiconductor device of the present invention, by directly stacking the third metal oxide semiconductor layer on the second metal oxide semiconductor layer and then performing an annealing treatment, the oxygen vacancy concentration and crystallinity of the first metal oxide semiconductor layer can be made higher than those of the second metal oxide semiconductor layer. In this way, the first metal oxide semiconductor layer can have an improved carrier mobility, so that the first transistor is suitable for use as a driving element, and at the same time the second transistor can have a reduced leakage current, so that the second transistor has a high reliability and is suitable for use as a switching element.

[0087] Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the claims.

Claims

1. A semiconductor device, comprising: a substrate; a first transistor as a driving element, disposed on the substrate, and the first transistor includes a first metal oxide semiconductor layer, a first gate, a first source, and a first drain; and a second transistor as a switching element, disposed on the substrate, and the second transistor includes a second gate, a second source, a second drain, a second metal oxide semiconductor layer, and a third metal oxide semiconductor layer, wherein the second source and the second drain are in contact with the third metal oxide semiconductor layer and not in contact with the second metal oxide semiconductor layer, wherein the third metal oxide semiconductor layer is directly stacked on the second metal oxide semiconductor layer, the second metal oxide semiconductor layer and the first metal oxide semiconductor layer belong to the same film layer, and the oxygen concentration of the first metal oxide semiconductor layer is lower than the oxygen concentration of the second metal oxide semiconductor layer, the oxygen concentration of the second metal oxide semiconductor layer is lower than the oxygen concentration of the third metal oxide semiconductor layer, wherein the carrier mobility of the first metal oxide semiconductor layer is greater than the carrier mobility of the second metal oxide semiconductor layer, the chemical stability of the third metal oxide semiconductor layer is higher than the chemical stability of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer, and the threshold voltage of the second transistor is higher than the threshold voltage of the first transistor.

2. The semiconductor device according to claim 1, wherein the thickness of the first metal oxide semiconductor layer or the second metal oxide semiconductor layer is between and .

3. The semiconductor device according to claim 1, wherein the thickness of the third metal oxide semiconductor layer is between and .

4. The semiconductor device according to claim 1, wherein the oxygen vacancy concentration of the first metal oxide semiconductor layer is higher than the oxygen vacancy concentration of the second metal oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein the crystallinity of the first metal oxide semiconductor layer is higher than the crystallinity of the second metal oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer contain at least one of indium, zinc, tungsten, tin, and gallium.

7. The semiconductor device according to claim 1, wherein the first metal oxide semiconductor layer and the second metal oxide semiconductor layer include indium zinc oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc tin oxide, indium gallium tin oxide, or indium gallium zinc tin oxide.

8. The semiconductor device according to claim 1, wherein the third metal oxide semiconductor layer contains at least one of indium, zinc, and gallium.

9. The semiconductor device according to claim 1, wherein the third metal oxide semiconductor layer contains indium gallium oxide or indium gallium zinc oxide.

10. A method for manufacturing a semiconductor device, comprising: forming a first metal oxide semiconductor layer and a second metal oxide semiconductor layer on a substrate, and the first metal oxide semiconductor layer and the second metal oxide semiconductor layer belong to the same film layer; forming a third metal oxide semiconductor layer directly stacked on the second metal oxide semiconductor layer; and performing an annealing process to make the oxygen concentration of the first metal oxide semiconductor layer lower than the oxygen concentration of the second metal oxide semiconductor layer, The chemical stability of the third metal oxide semiconductor layer is higher than that of the first metal oxide semiconductor layer and the second metal oxide semiconductor layer.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the oxygen concentration of the third metal oxide semiconductor layer is higher than that of the first metal oxide semiconductor layer or the second metal oxide semiconductor layer.

12. The method of manufacturing a semiconductor device according to claim 10, wherein the annealing process includes maintaining for 15 minutes to 120 minutes between 200 °C and 500 °C.

13. The method of manufacturing a semiconductor device according to claim 10, further comprising forming a first insulating layer on the substrate after the annealing process, and the first insulating layer covers the first metal oxide semiconductor layer, the second metal oxide semiconductor layer, and the third metal oxide semiconductor layer.

14. The method of manufacturing a semiconductor device according to claim 13, further comprising forming a first gate and a second gate on the first insulating layer, and the first gate and the second gate respectively overlap the first metal oxide semiconductor layer and the third metal oxide semiconductor layer.

15. The method of manufacturing a semiconductor device according to claim 14, further comprising performing a doping process after forming the first gate and the second gate.

16. The method of manufacturing a semiconductor device according to claim 14, further comprising forming a second insulating layer on the first gate, the second gate, and the first insulating layer.

17. The method of manufacturing a semiconductor device according to claim 16, further comprising forming a first source, a first drain, a second source, and a second drain on the second insulating layer, and the first source and the first drain are electrically connected to the first metal oxide semiconductor layer, and the second source and the second drain are electrically connected to the third metal oxide semiconductor layer.

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