Tunneling oxide layer passivation contact cell back structure and its preparation method and application

Abstract

The present invention provides a back structure of a tunneling oxide layer passivation contact battery, and a preparation method and application thereof. The back structure of the battery comprises a tunneling layer, a silicon oxide layer, a boron-doped polysilicon layer, a phosphorus-doped silicon thin film layer and a passivation layer which are sequentially stacked on a crystalline silicon substrate. The passivation layer has an opening exposing the phosphorus-doped silicon thin film layer, and a nickel alloy layer is provided at the opening of the passivation layer. The surface of the nickel alloy layer is provided with an aluminum electrode layer. The back structure of the battery deposits a phosphorus-doped silicon thin film layer on the boron-doped polysilicon, and deposits a nickel alloy layer which can block aluminum and provide good contact on the surface of the phosphorus-doped silicon thin film layer. The diffusion and deposition rate of nickel in the crystalline silicon body is low, and most of the nickel will form larger particles deposited on the surface of the phosphorus-doped silicon thin film, which will not affect the battery performance. The nickel alloy layer is very dense and can effectively block the penetration of aluminum, thereby ensuring that the battery has good passivation performance.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a tunneling oxide layer passivation contact cell back structure and a preparation method and application thereof. Background Art

[0002] Polycrystalline silicon (poly-Si) and ultra-thin silicon oxide (SiOx) passivation contact technology, referred to as TOPCon, has been attracting much attention since 2013. Thanks to the efforts of photovoltaic institutions around the world, the maximum efficiency of N-type and P-type solar cells using TOPCon technology has been increased to 25.8% and 26.1%, respectively. This structure can avoid direct contact between metal electrodes and silicon wafers, significantly improve the quality of surface passivation, and thus greatly improve the performance of solar cells, with higher open circuit voltage (Voc) and fill factor (FF) than traditional passivated emitter and rear contact (PERC) solar cells. In addition, TOPCon is more than 70% compatible with PERC in terms of process and equipment, and is considered to be the most promising technology for upgrading the back of PERC cells.

[0003] Electrodes play the role of gathering and conducting current in solar cells. The back electrode of P-type TOPCon cells usually uses aluminum paste, on the one hand to form an ohmic contact with P-type polysilicon; on the other hand, aluminum is much cheaper than silver, which can significantly reduce the paste cost; however, aluminum will form an alloy phase with silicon at sintering temperature and diffuse rapidly in silicon, with a diffusion depth of up to ten microns, resulting in significant recombination in the aluminum contact area, which seriously affects the efficiency of the cell. If polysilicon is made very thick to prevent aluminum from penetrating, it will cause great optical losses. Summary of the invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is how to inhibit the diffusion of aluminum into the silicon substrate, thereby improving the efficiency of the battery.

[0005] To solve the above problems, the first aspect of the present invention provides a tunneling oxide layer passivation contact cell back structure, comprising a tunneling layer, a silicon oxide layer, a boron-doped polysilicon layer, a phosphorus-doped silicon thin film layer and a passivation layer stacked in sequence on a crystalline silicon substrate, the passivation layer having an opening exposing the phosphorus-doped silicon thin film layer, a nickel alloy layer being provided at the opening portion of the passivation layer, and an aluminum electrode layer being provided on the surface of the nickel alloy layer.

[0006] Furthermore, the main component of the nickel alloy layer is selected from one or more combinations of nickel, nickel-phosphorus alloy and nickel-boron alloy.

[0007] Furthermore, the nickel alloy layer is doped with one or more trace elements of chromium, copper, tin, silver and sulfur, and the doping amount is 0.01-1%.

[0008] Furthermore, the thickness of the silicon oxide layer is 1 to 2 nm, the thickness of the boron-doped polysilicon layer is 20 to 200 nm, the thickness of the phosphorus-doped silicon thin film layer is 20 to 500 nm, the thickness of the nickel alloy layer is 20 to 10,000 nm, preferably 100 to 200 nm, and the thickness of the aluminum electrode layer is 100 to 20,000 nm.

[0009] Furthermore, the phosphorus-doped silicon thin film layer is selected from phosphorus-doped polycrystalline silicon, phosphorus-doped amorphous silicon and phosphorus-doped microcrystalline silicon.

[0010] Furthermore, the passivation layer is a stacked layer composed of aluminum oxide and silicon nitride.

[0011] Compared with the prior art, the tunneling oxide layer passivation contact battery back structure of the present invention has the following beneficial effects: the battery back structure can take into account both low contact resistivity and passivation effect; a phosphorus-doped silicon thin film layer is deposited on the boron-doped polycrystalline silicon, and a nickel alloy layer that can block aluminum and provide good contact is deposited on the surface of the phosphorus-doped silicon thin film layer; the nickel deposition rate and the diffusion rate in the crystalline silicon body are both small, and most of the nickel will form larger particles deposited on the surface of the phosphorus-doped silicon thin film, which will not affect the battery performance; the nickel alloy layer is very dense and can effectively block the penetration of aluminum, thereby ensuring that the battery has good passivation performance; the nickel alloy layer material cost is low and easy to achieve mass production; the back electrode uses nickel and aluminum metals, which have good chemical stability.

[0012] The second aspect of the present invention provides a method for preparing the above-mentioned tunneling oxide layer passivation contact battery back structure, comprising the following steps:

[0013] S1, preparing a silicon oxide layer on the back of the crystalline silicon substrate;

[0014] S2, preparing a layer of boron-doped amorphous silicon on the silicon oxide layer;

[0015] S3, performing high temperature annealing to form a tunneling layer and a boron-doped polysilicon layer;

[0016] S4, preparing a phosphorus-doped silicon thin film layer on the boron-doped polysilicon layer;

[0017] S5, preparing a passivation layer on the phosphorus-doped silicon thin film layer;

[0018] S6, performing a hole opening process on the passivation layer to expose the phosphorus-doped silicon thin film layer;

[0019] S7, using a chemical plating method to prepare a nickel alloy layer on the phosphorus-doped silicon thin film layer corresponding to the opening portion of the passivation layer;

[0020] S8. Prepare an aluminum electrode layer on the nickel alloy layer by screen printing, and sinter to obtain a back electrode.

[0021] Furthermore, the chemical plating method in S7 is to deposit a nickel alloy layer on the phosphorus-doped amorphous silicon under the induction of a light field, an electric field or a sensitizer.

[0022] Furthermore, the method for preparing boron-doped amorphous silicon in step S2 is PECVD, LPCVD, Sputtering, MWCVD, etc., and the method for preparing phosphorus-doped silicon film by tubular PECVD method in step S4 is PECVD, LPCVD, Sputtering, MWCVD, etc.

[0023] Furthermore, the preparation method of silicon oxide in S1 is selected from any one of the following technologies: wet chemical oxidation, high temperature oxidation, plasma-assisted oxidation, ozone oxidation, and plasma-assisted atomic layer deposition.

[0024] Furthermore, in step S6, the passivation layer is opened by laser or etching.

[0025] Compared with the prior art, the preparation method of the back structure of the tunneling oxide layer passivation contact battery of the present invention has the following beneficial effects: the hole concentration in the boron-doped polycrystalline silicon is much higher than the electron concentration, and it is impossible to directly chemically plate nickel, and the nickel plating process needs to be realized by using electrical assistance, while the present invention can provide electrons for the subsequent chemical nickel plating process by depositing a layer of phosphorus-doped silicon film on the boron-doped polycrystalline silicon, thereby avoiding the use of complex electrical assistance processes; a nickel alloy layer is plated on the phosphorus-doped silicon film layer by chemical plating technology, and the nickel alloy layer has good adhesion with the phosphorus-doped silicon film, and can form a good ohmic contact by adjusting the composition of the nickel alloy layer and annealing treatment, thereby obtaining a low contact resistivity; chemical nickel plating has a self-alignment characteristic, and deposition only occurs on the phosphorus-doped silicon film layer, which is conducive to simplifying the complexity of the process; screen-printed aluminum paste is used on the nickel alloy layer, and compared with the electroplating method, its production capacity is higher and the cost is lower; the preparation method is simple, low-cost, and suitable for industrial mass production.

[0026] A third aspect of the present invention provides an application of the above-mentioned tunneling oxide passivation contact cell back structure, wherein the tunneling oxide passivation contact cell back structure is applied to an N-type or P-type tunneling oxide passivation contact solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the process of preparing the back structure of the tunnel oxide layer passivation contact cell in the embodiment;

[0028] Figure 2 This is a schematic diagram of the structure of the tunneling oxide layer passivation contact cell in Example 4.

[0029] Description of reference numerals:

[0030] 1-crystalline silicon substrate, 2-tunneling layer, 3-silicon oxide layer, 4-boron-doped polysilicon layer, 5-phosphorus-doped silicon thin film layer, 6-passivation layer, 7-nickel alloy layer, 8-aluminum electrode layer, 9-boron emitter, 10-silver electrode. DETAILED DESCRIPTION

[0031] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation method and typical parameters of the present invention, and are not used to limit the parameter range described in the present invention. Reasonable changes derived therefrom are still within the scope of protection of the claims of the present invention.

[0032] It should be noted that the endpoints and any values ​​of the ranges disclosed in this article are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in this article.

[0033] The embodiment of the present invention provides a back structure of a tunneling oxide layer passivation contact cell, comprising a tunneling layer 2, a silicon oxide layer 3, a boron-doped polysilicon layer 4, a phosphorus-doped silicon thin film layer 5 and a passivation layer 6 which are sequentially stacked on a crystalline silicon substrate 1, the passivation layer 6 having an opening exposing the phosphorus-doped silicon thin film layer 5, a nickel alloy layer 7 being provided at the opening portion of the passivation layer 6, and an aluminum electrode layer 8 being provided on the surface of the nickel alloy layer 7. The back structure of the tunneling oxide layer passivation contact cell forms a good ohmic contact through the nickel alloy layer 7 to obtain a low contact resistivity, and the nickel alloy layer 7 can inhibit the diffusion of aluminum into the silicon substrate, thereby ensuring that the cell has good passivation performance, and the structure can be applied to N-type or P-type tunneling oxide layer passivation contact solar cells, thereby improving the cell efficiency.

[0034] Combination Figure 1 As shown, the method for preparing the back structure of the tunnel oxide layer passivation contact cell includes the following steps:

[0035] S0, crystalline silicon substrate 1 is cleaned according to RCA standard

[0036] S1. A silicon oxide layer 3 is prepared on the back of a crystalline silicon substrate 1. The preparation method of silicon oxide is selected from any one of wet chemical oxidation, high temperature oxidation, plasma assisted oxidation, ozone oxidation, and plasma assisted atomic layer deposition. The thickness of the silicon oxide layer 3 is 1 to 2 nm.

[0037] S2, preparing a layer of boron-doped amorphous silicon on the silicon oxide layer 3, using PECVD, LPCVD, Sputtering, MWCVD and other methods to prepare the boron-doped amorphous silicon, the thickness of the boron-doped amorphous silicon being 20-200 nm;

[0038] S3, annealing the sample after depositing the boron-doped amorphous silicon layer at high temperature in a diffusion annealing furnace, with the crystallization temperature being 800° C. to 950° C., to form a tunneling layer 2 and a boron-doped polysilicon layer 4;

[0039] S4, preparing a phosphorus-doped silicon thin film layer 5 on the boron-doped polycrystalline silicon layer 4, the phosphorus-doped silicon thin film is phosphorus-doped polycrystalline silicon, phosphorus-doped amorphous silicon or phosphorus-doped microcrystalline silicon, and is prepared by PECVD, LPCVD, Sputtering, MWCVD and other methods, and the thickness of the phosphorus-doped silicon thin film layer 5 is 20 to 500 nm; the phosphorus-doped silicon thin film layer 5 provides electrons for the subsequent chemical nickel plating process, avoiding the use of a complex electric-assisted nickel plating process;

[0040] S5, preparing a passivation layer 6 on the phosphorus-doped silicon thin film layer 5, the passivation layer 6 is a stacked layer consisting of aluminum oxide and silicon nitride layers, the aluminum oxide is prepared by ALD method, and the silicon nitride is prepared by tubular PECVD method;

[0041] S6, the passivation layer 6 is opened to expose the phosphorus-doped silicon thin film layer 5. The opening method may be laser opening, or patterning by photolithography, spraying, printing, etc., and then the opening is formed by etching;

[0042] S7, using chemical plating to prepare a nickel alloy layer 7 on the phosphorus-doped silicon thin film layer 5 corresponding to the opening of the passivation layer 6, the main component of the nickel alloy layer 7 is selected from one or more combinations of nickel, nickel-phosphorus alloy, and nickel-boron alloy, and can be doped with one or more trace elements of chromium, copper, tin, silver and sulfur, and the doping amount is 0.01-1%. The thickness of the nickel alloy layer 7 is 20-10000nm, preferably 100-200nm; the nickel alloy layer 7 has good adhesion with the phosphorus-doped silicon thin film, and can form a good ohmic contact by adjusting the composition and annealing treatment to obtain a low contact resistivity;

[0043] S8. Prepare an aluminum electrode layer 8 on the nickel alloy layer 7 by screen printing, and the thickness of the aluminum electrode layer 8 is 100-20000nm; print the aluminum paste by screen printing, the nickel alloy layer 7 is very dense, which can effectively block the penetration of the aluminum paste, thereby ensuring that the battery has good passivation performance, and then sinter it in a chain furnace to form a good ohmic contact between the aluminum paste and the alloy nickel layer. The sintering temperature is 400-600℃ to obtain the back electrode.

[0044] If a nickel alloy layer that can block aluminum and provide good contact is deposited on the surface of polycrystalline silicon by light-induced chemical plating, the polycrystalline silicon surface is usually required to be able to provide electrons. However, for P-type TOPCon cells, the polycrystalline silicon doped with boron on the surface cannot provide electrons. If nickel plating is to be achieved, an electrically assisted chemical plating method must be used, and the process is very complicated. The above method deposits a layer of phosphorus-doped silicon film on the boron-doped polycrystalline silicon to provide electrons for the subsequent chemical nickel plating process, avoiding the use of a complex electrically assisted nickel plating process. The preparation method is simple, low-cost, and suitable for industrial mass production.

[0045] The present invention will be described in detail below through specific examples. The solar cells provided in the following examples and comparative examples are P-type tunnel oxide layer passivation contact cells.

[0046] Example 1

[0047] N-type crystalline silicon substrate, double-sided alkaline polishing, cleaning; using nitric acid oxidation method to prepare ultra-thin silicon oxide layer on the front and back sides of the silicon wafer; using PECVD method to deposit 30nm boron-doped amorphous silicon on both sides; performing high-temperature annealing at 850℃-950℃ to form a tunneling layer and a boron-doped polysilicon layer; after HF treatment to remove the oxide layer, using PECVD to deposit 30nm phosphorus-doped amorphous silicon layer on both sides, and rapid thermal annealing at 500-800℃ to crystallize it to form a phosphorus-doped polysilicon layer; using aluminum oxide and silicon nitride to cover and deposit the front and back surfaces to prepare a passivation layer; then laser drilling the passivation layer; using chemical plating method to prepare a 20nm nickel alloy layer at the opening part of the passivation layer, and performing annealing at 150-600℃ to form a nickel alloy layer; then using screen printing method to print a 100nm aluminum electrode layer on the nickel alloy layer; then performing belt furnace sintering treatment to obtain a tunneling oxide layer passivation contact battery.

[0048] Example 2

[0049] N-type crystalline silicon substrate, double-sided alkaline polishing, cleaning; using nitric acid oxidation method to prepare ultra-thin silicon oxide layer on the front and back of silicon wafer; using PECVD method to deposit 30nm boron-doped amorphous silicon on both sides; performing high-temperature annealing at 850℃-950℃ to form a tunneling layer and a boron-doped polysilicon layer; after HF treatment to remove the oxide layer, using PECVD to deposit 30nm phosphorus-doped amorphous silicon layer on both sides, and rapid thermal annealing at 500-800℃ to crystallize it to form a phosphorus-doped polysilicon layer; using aluminum oxide and silicon nitride to cover and deposit the front and back surfaces to prepare a passivation layer; then laser drilling the passivation layer; using chemical plating method to prepare a 200nm nickel alloy layer at the opening part of the passivation layer, and performing annealing at 150-600℃ to form a nickel alloy layer; then using screen printing method to print a 100nm aluminum electrode layer on the nickel alloy layer; then performing belt furnace sintering treatment to obtain a tunneling oxide layer passivation contact battery.

[0050] Example 3

[0051] N-type crystalline silicon substrate, double-sided alkaline polishing, cleaning; using nitric acid oxidation method to prepare ultra-thin silicon oxide layer on the front and back of silicon wafer; using PECVD method to deposit 30nm boron-doped amorphous silicon on both sides; high-temperature annealing at 850℃-950℃ to form a tunneling layer and a boron-doped polysilicon layer; after HF treatment to remove the oxide layer, using PECVD to deposit 30nm phosphorus-doped amorphous silicon layer on both sides, and rapid thermal annealing at 500-800℃ to crystallize it to form a phosphorus-doped polysilicon layer; using aluminum oxide and silicon nitride to cover and deposit the front and back surfaces to prepare a passivation layer; then laser drilling the passivation layer; using chemical plating method to prepare a 2000nm nickel alloy layer at the opening part of the passivation layer, and annealing at 150-600℃ to form a nickel alloy layer; then using screen printing method to print a 100nm aluminum electrode layer on the nickel alloy layer; then performing belt furnace sintering treatment to obtain a tunneling oxide layer passivation contact battery.

[0052] Comparative Example 1

[0053] N-type crystalline silicon substrate, double-sided alkaline polishing, cleaning; using nitric acid oxidation method to prepare ultra-thin silicon oxide layer on the front and back of the silicon wafer; using PECVD method to deposit 30nm boron-doped amorphous silicon on both sides; high-temperature annealing at 850℃~950℃ to form a tunneling layer and a boron-doped polysilicon layer; after HF treatment to remove the oxide layer, PECVD is used to deposit 30nm phosphorus-doped amorphous silicon layer on both sides, and rapid thermal annealing at 500-800℃ is performed to crystallize it to form a phosphorus-doped polysilicon layer; aluminum oxide and silicon nitride are used to cover and deposit the front and back surfaces to prepare a passivation layer; then the passivation layer is laser-opened; a 100nm aluminum electrode layer is printed on the phosphorus-doped amorphous silicon layer by screen printing; then a belt furnace sintering treatment is performed to obtain a tunneling oxide layer passivation contact battery.

[0054] The key parameters of the tunneling oxide layer passivation contact cells prepared in Examples 1-3 and Comparative Example 1 were tested, and the results are shown in Table 1 below.

[0055]

[0056] Table 1 Comparison of key parameters of TOPCon batteries in Example and Comparative Example

[0057] According to the test results, the key parameters such as lifespan, dark saturation current density, implicit open circuit voltage, and contact resistance of the tunneling oxide passivation contact cells prepared in Examples 1-3 are better than those in Comparative Example 1, among which Example 2 has the best performance, indicating that the back structure of the tunneling oxide passivation contact cell of the present invention has low contact resistivity and good passivation effect, which can greatly improve battery performance.

[0058] Example 4

[0059] The N-type crystalline silicon substrate 1 is cleaned, double-sided textured, and single-sided boron diffusion (front surface) is performed to form a boron emitter 9; the non-boron diffusion surface is subjected to acid etching to remove the boron coating layer and the texture surface; ultra-thin silicon oxide is prepared on the back by nitric acid oxidation to form a silicon oxide layer 3; then 30nm of boron-doped amorphous silicon is prepared on the back silicon oxide by PECVD; annealing is performed at a high temperature of 850℃ to 950℃ for different times to form a tunneling layer 2 and a boron-doped polysilicon layer 4 to obtain a TOPCon structure; after HF treatment to remove the oxide layer, 30nm of phosphorus-doped amorphous silicon is deposited on the back by PECVD. Silicon layer, and rapid thermal annealing at 500-800℃ to crystallize it to form a phosphorus-doped polysilicon layer; then aluminum oxide and silicon nitride are used to cover the front and rear surfaces to form a passivation layer 6; then the back passivation layer 6 is laser-opened; 200nm nickel is plated on the phosphorus-doped polysilicon layer by chemical plating, and annealing is performed at 150-600℃ to form a nickel alloy layer 7; then 100nm aluminum paste is printed on the nickel alloy layer 7 by screen printing, and then belt furnace sintering is performed to form an aluminum electrode layer 8; silver electrode 10 is prepared by screen printing on the front side at the same time; the following is obtained: Figure 2 The tunnel oxide layer passivated contact solar cell shown. The average efficiency of the cell tested is greater than 23.5%.

[0060] Comparative Example 2

[0061] N-type crystalline silicon substrate, cleaned, double-sided textured, single-sided boron diffusion (front surface), forming a boron emitter; acid etching treatment is performed on the non-boron diffusion surface to remove the boron coating layer and the texture surface; ultra-thin silicon oxide is prepared on the back side by nitric acid oxidation method to form a silicon oxide layer; then 30nm of boron-doped amorphous silicon is prepared on the back side by PECVD; high-temperature annealing at 850℃~950℃ for different times is performed to form a tunneling layer 2 and a boron-doped polysilicon layer to obtain a TOPCon structure; after HF treatment to remove the oxide layer, A 30nm phosphorus-doped amorphous silicon layer is deposited on the back by PECVD, and then rapidly thermally annealed at 500-800℃ to crystallize it into a phosphorus-doped polysilicon layer; then aluminum oxide and silicon nitride are deposited on the front and back surfaces to form a passivation layer; then the back passivation layer is laser-opened; then a 100nm aluminum electrode layer is printed on the phosphorus-doped polysilicon by screen printing, and then a belt furnace sintering process is performed; at the same time, a silver electrode is prepared by screen printing on the front; and a tunneling oxide layer passivated contact solar cell is obtained. After testing, the average efficiency of the cell is greater than 18.6%.

[0062] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A tunneling oxide layer passivation contact battery back structure, characterized in that: The invention comprises a tunneling layer, a silicon oxide layer, a boron-doped polysilicon layer, a phosphorus-doped silicon thin film layer and a passivation layer which are sequentially stacked on a crystalline silicon substrate, wherein the passivation layer has an opening exposing the phosphorus-doped silicon thin film layer, a nickel alloy layer is arranged at the opening portion of the passivation layer, an aluminum electrode layer is arranged on the surface of the nickel alloy layer, the phosphorus-doped silicon thin film layer is selected from phosphorus-doped polysilicon, phosphorus-doped amorphous silicon and phosphorus-doped microcrystalline silicon, and the nickel alloy layer is doped with one or more trace elements of chromium, copper, tin, silver and sulfur, and the doping amount is 0.01-1%.

2. The tunnel oxide layer passivation contact cell back structure according to claim 1, characterized in that: The main component of the nickel alloy layer is selected from one or more combinations of nickel, nickel-phosphorus alloy and nickel-boron alloy.

3. The tunnel oxide layer passivation contact cell back structure according to claim 1, characterized in that: The thickness of the silicon oxide layer is 1-2 nm, the thickness of the boron-doped polysilicon layer is 20-200 nm, the thickness of the phosphorus-doped silicon thin film layer is 20-500 nm, the thickness of the nickel alloy layer is 20-10000 nm, and the thickness of the aluminum electrode layer is 100-20000 nm.

4. The tunneling oxide layer passivation contact cell back structure according to claim 1, characterized in that: The passivation layer is a stacked layer consisting of aluminum oxide and silicon nitride.

5. A method for preparing a back side structure of a tunneling oxide layer passivated contact cell according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1, preparing a silicon oxide layer on the back of the crystalline silicon substrate; S2, preparing a layer of boron-doped amorphous silicon on the silicon oxide layer; S3, performing high temperature annealing to form a tunneling layer and a boron-doped polysilicon layer; S4, preparing a phosphorus-doped silicon thin film layer on the boron-doped polysilicon layer; S5, preparing a passivation layer on the phosphorus-doped silicon thin film layer; S6, performing a hole opening process on the passivation layer to expose the phosphorus-doped silicon thin film layer; S7, using a chemical plating method to prepare a nickel alloy layer on the phosphorus-doped silicon thin film layer corresponding to the opening portion of the passivation layer; S8. Prepare an aluminum electrode layer on the nickel alloy layer by screen printing, and sinter to obtain a back electrode.

6. The method for preparing the back side structure of a tunneling oxide layer passivated contact cell according to claim 5, characterized in that: The chemical plating method in S7 is to deposit a nickel alloy layer on the phosphorus-doped amorphous silicon under the induction of a light field, an electric field or a sensitizer.

7. The method for preparing a back side structure of a tunnel oxide passivation contact cell according to claim 5, characterized in that: The preparation method of silicon oxide in S1 is selected from any one of the following technologies: wet chemical oxidation, high temperature oxidation, plasma assisted oxidation, ozone oxidation, and plasma assisted atomic layer deposition.

8. The application of the tunneling oxide layer passivation contact battery back structure as claimed in any one of claims 1 to 4, characterized in that: The tunnel oxide layer passivation contact cell back structure is applied to an N-type or P-type tunnel oxide layer passivation contact solar cell.

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