Charge pump circuit, control circuit and control method thereof

Abstract

Disclosed are a charge pump circuit, a control circuit, and a control method thereof. The control method includes: performing a hysteresis comparison of an output voltage with a first threshold voltage and a second threshold voltage to generate a mode signal; triggering a flip of the logic states of a first control signal and a second control signal in response to a rising edge of the mode signal; and maintaining the logic states of the first control signal and the second control signal unchanged in response to a falling edge of the mode signal, wherein the first and second control signals are used to control the complementary operation of two switches in each switch pair in the charge pump circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic circuits, and more particularly to charge pump circuits and control circuits and methods thereof. Background Art

[0002] A charge pump circuit is a switching converter that uses capacitors to store energy. Requiring no inductor or control loop, the charge pump circuit uses the on / off switching of a power switch to switch the capacitor between supply and discharge states, thereby achieving voltage conversion. Compared to traditional DC switching converters with inductors, charge pump circuits offer advantages such as compact size, high efficiency, low output ripple, and simple control.

[0003] Charge pump circuits are widely used in increasingly thinner and high-performance mobile phones. For example, to maintain compatibility with existing single-cell battery applications, when a mobile phone charging system incorporates two batteries, a charge pump circuit is often required to reduce the voltage of the two batteries to the voltage range of a single battery to accommodate the downstream system load. Furthermore, to improve overall device efficiency, ensuring that the charge pump circuit operates efficiently even under light loads is a major challenge currently facing engineers. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a charge pump circuit and a control circuit and a control method thereof that work efficiently under light load.

[0005] According to one embodiment of the present invention, a control circuit for a charge pump circuit includes two switch bridge arms coupled between an input node and a reference ground and two corresponding capacitors, each switch bridge arm having two switch pairs connected in series through an output node, each switch pair having two switches connected in series with each other through a common node, and each capacitor being connected between the two common nodes of the corresponding switch bridge arm. The control circuit includes: a judgment circuit, which performs a hysteresis comparison on the output voltage of the charge pump circuit with a first threshold voltage and a second threshold voltage to generate a mode signal; and a logic circuit, which provides a first control signal and a second control signal with opposite logic states based on the mode signal to control the complementary operation of each switch pair, wherein in response to the rising edge of the mode signal, the logic circuit triggers the logic state of the first control signal and the second control signal to flip, and in response to the falling edge of the mode signal, the logic circuit maintains the logic state of the first control signal and the second control signal unchanged.

[0006] According to another embodiment of the present invention, a charge pump circuit includes: an input node for receiving an input voltage; an output node for providing an output voltage; two switching bridge arms coupled between the input node and a reference ground, each switching bridge arm having two switch pairs connected in series through the output node, wherein each switch pair has two switches connected in series to each other through a common node; two capacitors, wherein one capacitor is connected between the two common nodes of one switching bridge arm, and the other capacitor is connected between the two common nodes of the other switching bridge arm; and a control circuit as described above.

[0007] According to another embodiment of the present invention, a control method for a charge pump circuit includes two capacitors and two switch bridge arms coupled between an input node and a reference ground, each switch bridge arm has two switch pairs connected in series through an output node, and each switch pair has two switches connected in series with each other through a common node, wherein one capacitor is connected between the two common nodes of one switch bridge arm, and the other capacitor is connected between the two common nodes of the other switch bridge arm. The control method includes: performing a hysteresis comparison on the output voltage of the charge pump circuit with a first threshold voltage and a second threshold voltage to generate a mode signal; in response to a rising edge of the mode signal, triggering a flip of the logic states of a first control signal and a second control signal, wherein the first control signal and the second control signal control each switch pair to work complementary, and the logic states of the first control signal and the second control signal are opposite; and in response to a falling edge of the mode signal, keeping the logic states of the first control signal and the second control signal unchanged.

[0008] According to an embodiment of the present invention, a charge pump circuit provides complementary first and second control signals to control the eight switches in two switching arms. When light-load operation is detected, the logic states of the first and second control signals are flipped only when the output voltage is less than a first threshold voltage. Otherwise, the logic states of the first and second control signals remain unchanged. This light-load control strategy ensures that the peak output voltage of the charge pump circuit is greater than half the input voltage during light-load operation, improving overall device efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of the circuit structure of the charge pump circuit 100;

[0010] Figure 2a to Figure 2c is the current flow path of the charge pump circuit 100 when operating at a light load;

[0011] Figure 3 is a timing diagram of the charge pump circuit 100 when operating under light load;

[0012] Figure 4is a circuit schematic diagram of a charge pump circuit 200 according to an embodiment of the present invention;

[0013] Figure 5a and 5b A current flow path for the charge pump circuit 200 according to an embodiment of the present invention;

[0014] Figure 6 is a timing diagram of the charge pump circuit 200 according to an embodiment of the present invention when operating under light load;

[0015] Figure 7 is a flow chart of a control method 300 of the charge pump circuit 200 during light-load operation according to an embodiment of the present invention;

[0016] Figure 8 According to an embodiment of the present invention Figure 4 The circuit schematic diagram of the control circuit 203A is shown;

[0017] Figure 9 is a timing diagram of the charge pump circuit 200 under non-light load and light load operation according to an embodiment of the present invention;

[0018] Figure 10 FIG. 5 is a flow chart of a control method 500 for a charge pump circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to practice the present invention. In other instances, well-known circuits, materials, or methods are not specifically described to avoid obscuring the present invention.

[0020] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an "element" is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Identical reference numerals indicate identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] Figure 1 FIG. 1 is a schematic diagram of the circuit structure of the charge pump circuit 100. Figure 1 As shown, the charge pump circuit 100 is a two-phase interleaved charge pump circuit, including a left switch arm consisting of switches QA1, QB1, QC1, and QD1, and a right switch arm consisting of QA2, QB2, QC2, and QD2. Flying capacitors CFLY1 and CFLY2 are coupled to the left and right switch arms of the charge pump circuit 100, respectively. The charge pump circuit 100 controls the switching of the switches in the left and right switch arms to increase the input voltage V BATT Converted to output voltage V OUT supplied to the load.

[0022] Figure 2a to Figure 2c The current flow path of the charge pump circuit 100 during light-load operation is shown in FIG. During light-load operation, the charge pump circuit 100 will undergo multiple cycles including the operation phases 10A->10B->10A->10C.

[0023] Figure 3 1 is a timing diagram of the charge pump circuit 100 when it is working under light load. Figure 3 As shown, when the output voltage V OUT Reduced to the interval threshold voltage V SKIP_L At time 121, the charge pump circuit 100 enters the operation phase 10A.

[0024] In the operation phase 10A, if Figure 2a As shown, switches QA1, QC1, QB2, and QD2 are turned on, switches QB1, QD1, QA2, and QC2 are turned off, and the input voltage VBATT The output node OUT is charged via the flying capacitor CFLY1, and the flying capacitor CFLY1 is charged. At the same time, the flying capacitor CFLY2 is charged to the output node OUT, and the flying capacitor CFLY2 is discharged.

[0025] exist Figure 3 At time 122 shown, the charge pump circuit 100 enters the operation phase 10B. In the operation phase 10B, as shown in FIG. Figure 2b As shown, the charge pump circuit 100 controls switches QB1, QD1, QA2, and QC2 to be turned on, and controls switches QA1, QC1, QB2, and QD2 to be turned off. The input voltage V BATT The output node OUT is charged through the flying capacitor CFLY2, and the flying capacitor CFLY2 is charged. At the same time, the flying capacitor CFLY1 is charged to the output node OUT, and the flying capacitor CFLY1 is discharged. Figure 3 At time 123 shown, the charge pump circuit 100 enters the operation phase 10A again. Figure 2a shown.

[0026] exist Figure 3 As shown at the moment 124, when the output voltage V OUT Increase to the interval threshold voltage V SKIP_H , the charge pump circuit 100 enters the operation phase 10C, that is, the charge pump circuit 100 enters the idle state (IDLE). In the operation phase 10C, Figure 2c As shown, the charge pump circuit 100 controls the switches QA1 , QA2 , QC1 , and QC2 to be turned off, and controls the switches QB1 , QD1 , QB2 , and QD2 to be turned on, so that the flying capacitors CFLY1 and CFLY2 charge the output node OUT and discharge the flying capacitors CFLY1 and CFLY2 .

[0027] Continue as Figure 3 As shown, when the output voltage V OUT Reduced again to the interval threshold voltage V SKIP_L At time 125, one cycle of the charge pump circuit 100 ends and the next cycle begins. Obviously, during the entire light-load operation, the output voltage VOUT of the charge pump circuit 100 is always less than the input voltage V BATT The light-load efficiency of the charge pump circuit 100 is average, for example, only 98%, and its light-load control strategy needs to be improved.

[0028] Figure 4 FIG. 2 is a circuit diagram of a charge pump circuit 200 according to an embodiment of the present invention. Figure 4In the illustrated embodiment, charge pump circuit 200 includes an input node V2X, an output node V1X, a first switching arm 201, a second switching arm 202, flying capacitors CFLY1 and CFLY2, and a control circuit 203. The first switching arm 201 is coupled between the input node V2X and a reference ground GND and includes a switch pair 411 and 412 connected in series via the output node V1X. The second switching arm 202 is coupled between the input node V2X and the reference ground GND and includes a switch pair 421 and 422 connected in series via the output node V1X. Each of the switch pairs 411, 412, 421, and 422 has two switches connected in series via a common node. Flying capacitor CFLY1 is coupled between common nodes CF1P and CF1N of the first switching arm 201. Flying capacitor CFLY2 is coupled between common nodes CF2P and CF2N of the second switching arm 202.

[0029] The control circuit 203 is configured to provide a first control signal H1 and a second control signal H2 to control the complementary operation of the two switches in each switch pair (411, 412, 421, and 422) of the charge pump circuit 200. The first control signal H1 and the second control signal H2 have opposite logic states, wherein when the first control signal H1 is logic high, the second control signal H2 is logic low, and vice versa.

[0030] exist Figure 4 In the embodiment shown, the control circuit 203 includes a judgment circuit 204 and a logic circuit 205. The judgment circuit 204 generates a first threshold voltage V for judging light load operation. TH_L and the second threshold voltage V TH_H and the output voltage V OUT Same as the first threshold voltage V TH_L and the second threshold voltage V TH_H Perform hysteresis comparison to generate the mode signal PWM_ON. In one embodiment, when the output voltage V OUT Decreases to less than the first threshold voltage V TH_L , the mode signal PWM_ON flips from low level to high level; when the output voltage V OUT Increases to a value greater than the second threshold voltage V TH_H , indicating that the charge pump circuit enters light-load operation, and the mode signal PWM_ON flips from high level to low level.

[0031] The logic circuit 205 receives the mode signal PWM_ON and, based on the mode signal PWM_ON, provides a first control signal H1 and a second control signal H2 to control the complementary operation of each switch pair in the charge pump circuit 200. Specifically, in response to a rising edge of the mode signal PWM_ON, the logic circuit 205 triggers a logic state flip between the first control signal H1 and the second control signal H2. In response to a falling edge of the mode signal PWM_ON, the logic circuit 205 maintains the logic states of the first control signal H1 and the second control signal H2 unchanged.

[0032] Figure 5a and 5b , which is a current flow path for the charge pump circuit 200 according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the charge pump circuit 200 under light-load operation only includes two operation phases 20A and 20B.

[0033] Figure 6 FIG. 2 is a timing diagram of the charge pump circuit 200 according to an embodiment of the present invention when operating under light load. Figure 6 As shown, when the output voltage V OUT Decreases to the first threshold voltage V TH_L , the mode signal PWM_ON flips from logic low to logic high. The logic circuit 205 detects the rising edge of the mode signal PWM_ON and triggers the logic state flipping of the first control signal H1 and the first control signal H2. For example, at time 231, the first control signal H1 flips from logic low to logic high, and the second control signal H2 flips from logic high to logic low.

[0034] The charge pump circuit 200 then operates in the operation phase 20A. Figure 5a As shown, in the operation phase 20A, the first control signal H1 and the second control signal H2 provided by the logic circuit 205 control the switches QA1, QC1, QB2, and QD2 to be turned on, while the switches QB1, QD1, QA2, and QC2 are turned off. The input voltage V BATT The output node V1X is charged via the flying capacitor CFLY1, and the flying capacitor CFLY1 is charged. Simultaneously, the flying capacitor CFLY2 is charged to the output node V1X, and the flying capacitor CFLY2 is discharged.

[0035] Continue as Figure 6 As shown, the output voltage V OUT Under the control of the logic circuit 205, the output voltage VOUT increases rapidly. TH_HWhen the mode signal PWM_ON flips from logic high to logic low, it indicates that the charge pump circuit 200 enters light load operation and enters the logic state holding mode of the present invention. In response to the falling edge of the mode signal PWM_ON, the logic circuit 205 keeps the logic states of the first control signal H1 and the second control signal H2 unchanged, and the clamped charge pump circuit 200 remains in the operation phase 20A. For example, Figure 6 At the time 241 shown, the logic states of the first control signal H1 and the second control signal H2 remain unchanged.

[0036] Continue as Figure 6 As shown, when the output voltage V OUT Decreases again to the first threshold voltage V TH_L , the mode signal PWM_ON flips from logic low to logic high. Logic circuit 205 detects the rising edge of mode signal PWM_ON and triggers a logic state flip of first control signal H1 and first control signal H2. For example, at time 232, first control signal H1 flips from logic high to logic low, and second control signal H2 flips from logic low to logic high. Charge pump circuit 200 then enters operation phase 20B.

[0037] In the operation phase 20B, if Figure 5b As shown, the first control signal H1 and the second control signal H2 provided by the logic circuit 205 control the switches QA2, QC2, QB1, and QD1 to be turned on, while the switches QB2, QD2, QA1, and QC1 are turned off. The input voltage V BATT The output node V1X is charged via the flying capacitor CFLY2, and the flying capacitor CFLY2 is charged. At the same time, the flying capacitor CFLY1 is charged to the output node V1X, and the flying capacitor CFLY1 is discharged.

[0038] Continue as Figure 6 As shown, the output voltage V OUT Under the control of the logic circuit 205, the output voltage V OUT Increases to exceed the second threshold voltage V TH_H When the mode signal PWM_ON flips from logic high to logic low, the charge pump circuit 200 enters the hold mode. In response to the falling edge of the mode signal PWM_ON, the logic circuit 205 continues to clamp the logic states of the first control signal H1 and the second control signal H2, maintaining their logic states unchanged. The charge pump circuit 200 is also clamped in the operation phase 20B unchanged. Until the output voltage V OUT Decreases again to the first threshold voltage V TH_L, the mode signal PWM_ON goes high. In response to the high level of the mode signal PWM_ON, the logic states of the first control signal H1 and the second control signal H2 flip again. At this point, one cycle (20A->20B) of the charge pump circuit 200 ends, and a new cycle begins. In this embodiment of the present invention, one cycle consists of the first control signal H1 flipping its logic state twice.

[0039] As mentioned earlier, Figure 3 The charge pump circuit 100 shown in FIG. OUT Increase to the interval threshold voltage V SKIP_H When the charge pump circuit 100 enters light-load operation, the two flying capacitors CFLY1 and CFLY2 are disconnected from the input node BATT and the input voltage V BATT The two flying capacitors CFLY1 and CFLY2 are both coupled between the output node OUT and the reference ground, and the two flying capacitors CFLY1 and CFLY2 are both discharged. Figure 6 In the embodiment shown, when the output voltage V OUT Increases to the second threshold voltage V TH_H When the charge pump circuit 200 enters light-load operation, one of the two capacitors CFLY1 and CFLY2 is always electrically coupled between the input node V2X and the output node V1X, and the other of the two capacitors is electrically coupled between the output node V1X and the reference ground GND.

[0040] exist Figure 6 In the embodiment shown, before each rising edge of the mode signal PWM_ON comes, the voltage across the capacitor (CFLY1 or CFLY2) electrically coupled between the input node V2X and the output node OUT is V BATT / 2+(V BATT / 2-V TH_L ). Moreover, the capacitance of the capacitor CFLY1 or CFLY2 is generally much larger than the capacitance of the output capacitor at the output node OUT (coupled between the output node OUT and the reference ground, not shown). Therefore, when the charge pump circuit 200 operates at a light load and the rising edge of the mode signal PWM_ON arrives, the output voltage V OUT The peak value can be greater than the input voltage V BATT The efficiency of the entire charge pump circuit 200 is improved by half, for example, the efficiency of the entire device can reach 99%.

[0041] Figure 7FIG. 3 is a flow chart of a control method 300 of the charge pump circuit 200 during light-load operation according to an embodiment of the present invention. The control method 300 includes steps 301 - 303 .

[0042] In step 301, the output voltage V OUT Same as the first threshold voltage V TH_L and the second threshold voltage V TH_H Perform hysteresis comparison to generate the mode signal PWM_ON. OUT Decreases to the first threshold voltage V TH_L When the mode signal PWM_ON changes from low level to high level, the output voltage V OUT Increases to the second threshold voltage V TH_H , the mode signal PWM_ON changes from a high level to a low level, and the charge pump circuit 200 enters the holding mode.

[0043] In step 302 , in response to the rising edge of the mode signal PWM_ON, the logic circuit 205 triggers the flipping of the logic states of the first control signal H1 and the second control signal H2 , wherein the first control signal H1 and the second control signal H2 control each switch pair to operate complementary, and the logic states of the first control signal H1 and the second control signal H2 are opposite.

[0044] In step 303 , in response to the falling edge of the mode signal PWM_ON, the charge pump circuit 200 enters a holding mode to keep the logic states of the first control signal H1 and the second control signal H2 unchanged.

[0045] Figure 8 According to an embodiment of the present invention Figure 4 The control circuit 203A is a circuit diagram of the control circuit 203A. Figure 4 The charge pump circuit 200 shown provides a first control signal H1 and a second control signal H2 to control the two switches in each switch pair in the charge pump circuit 200 to operate complementary to each other.

[0046] exist Figure 8 In the embodiment shown, the control circuit 203A includes not only a judgment circuit 204A and a logic circuit 205A, but also a clock pulse generating circuit 206. The judgment circuit 204A includes a hysteresis comparator CMP1 and a threshold generating circuit 240. The threshold generating circuit 240 is used to generate a first threshold voltage V for judging a light load condition. TH_H and the second threshold voltage V TH_L .

[0047] The hysteresis comparator CMP1 has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal is coupled to the output terminal of the threshold generation circuit 240 to receive the first threshold voltage VTH_H and the second threshold voltage V TH_L , the inverting input receives the output voltage V OUT The hysteresis comparator CMP1 will output the voltage V OUT Same as the first threshold voltage V TH_L and the second threshold voltage V TH_H The threshold generation circuit 240 includes a bias voltage source V OS , resistor R HYS , current source I HYS , a first switch S1 and an inverter N1. Resistor R HYS It has a first terminal and a second terminal, wherein the first terminal receives V BATT The second end is coupled to the non-inverting input of the hysteresis comparator CMP1. HYS It has a power supply terminal and an output terminal, wherein the power supply terminal is coupled to the resistor R HYS The first switch S1 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the current source I HYS The output terminal and the second terminal are coupled to the ground, and the control terminal is coupled to the output terminal of the hysteresis comparator CMP1 via the inverter N1.

[0048] exist Figure 8 In the embodiment shown, the resistor R HYS and current source I HYS Used to generate the hysteresis loop of the hysteresis comparator CMP1, the bias voltage source V OS Used to provide bias voltage. When the output voltage V OUT Increases to exceed the second threshold voltage V TH_H When the charge pump circuit 100 enters light load operation, the hysteresis comparator CMP1 outputs a low level, the mode signal PWM_ON is pulled low, the first switch S1 is turned on, and the threshold generation circuit 240 provides a first threshold voltage V at the non-inverting input terminal of the hysteresis comparator CMP1. TH_L The first threshold voltage V TH_L =V BATT / 2-V OS -R HYS ×I HYS When the output voltage V OUT Decreases to less than the first threshold voltage V TH_L , the hysteresis comparator CMP1 outputs a high level, the mode signal PWM_ON is pulled high, the first switch S1 is turned off, and the threshold generation circuit 240 provides a second threshold voltage V at the non-inverting input terminal of the hysteresis comparator CMP1 TH_H The second threshold voltage V TH_H =V BATT / 2–VOS .

[0049] The clock pulse generating circuit 206 receives the mode signal PWM_ON and provides a clock pulse signal CLK with a fixed frequency when the mode signal PWM_ON is at a high level. Figure 8 In the embodiment shown, the clock pulse generating circuit 206 includes a current source I CLK , second switch S2, third switch S3, inverter N2, OR gate circuit OR1, capacitor C CLK , reference voltage source VREF1, comparator CMP2 and buffer circuit BUF1. Current source I CLK The second switch S2 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the current source I CLK The output terminal of the OR gate circuit OR1 receives the mode signal PWM_ON at the control terminal. The OR gate circuit OR1 has a first input terminal, a second input terminal and an output terminal, wherein the first input receives the mode signal PWM_ON via the inverter N2, and the second input terminal receives the clock pulse signal CLK. The third switch S3 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the second switch S2, the second terminal is grounded, and the control terminal is coupled to the output terminal of the OR gate circuit OR1. The comparator CMP2 has a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal is coupled to the second terminal of the second switch S2 and the first terminal of the third switch S3, the inverting input terminal is coupled to the reference voltage source VREF1 to receive the reference voltage, and the output terminal provides the clock pulse signal CLK via the buffer circuit BUF1. The capacitor C CLK The first input terminal of the comparator CMP2 is coupled between the non-inverting input terminal of the comparator CMP2 and the reference ground.

[0050] like Figure 8 As shown, during the period when the mode signal PWM_ON maintains a high level, the clock pulse generating circuit 206 controls the second switch S2 to be turned on, and the current source I CLK For capacitor C CLK When the capacitor C CLK When the voltage at both ends increases to the reference voltage, the output terminal of the comparator CMP2 provides a high level of the clock pulse signal CLK. The high level of the clock pulse signal CLK is provided to the second input terminal of the OR gate circuit OR1, so that the third switch S3 is turned on, and the capacitor C CLK The voltage across both ends is reduced, and the comparator CMP2 outputs a low level clock pulse signal CLK. The above operations are repeated, and under the control of the high level mode signal PWM_ON, the clock pulse generating circuit 240 continuously outputs the clock pulse signal CLK at its output end.

[0051] exist Figure 8In the illustrated embodiment, logic circuit 205A includes a rising edge detection circuit 251, an OR gate circuit OR2, a D flip-flop 252, and an inverter N4. The rising edge detection circuit 251 receives the mode signal PWM_ON and detects the rising edge of the mode signal PWM_ON. In one embodiment, the rising edge detection circuit 251 includes an inverter N3 and an AND gate circuit AND1. The OR gate circuit OR2 has a first input, a second input, and an output. The first input is coupled to the output of the rising edge detection circuit 251, and the second input is coupled to the output of the clock pulse generation circuit 206 to receive the clock pulse signal CLK. The D flip-flop 252 has an input, a clock, an output, and an inverting output. The input is coupled to the inverting output, the clock is coupled to the output of the OR gate circuit OR2, and the output provides a first control signal H1, which is then coupled to the second control signal H2 via inverter N4. The first control signal H1 and the second control signal H2 are logically complementary signals.

[0052] In a further embodiment, the control circuit 203A further includes a dead time generating circuit to add appropriate dead time to the first control signal H1 and the second control signal H2 to prevent the two complementary switches of each switch pair from being turned on directly.

[0053] Figure 9 FIG. 1 is a timing diagram of the charge pump circuit 200 under non-light load and light load operation according to an embodiment of the present invention. Figure 9 In the embodiment shown, the charge pump circuit 200 uses Figure 8 The control circuit 203A shown in FIG. 261 controls the output voltage V OUT Decreases to the first threshold voltage V TH_L , the mode signal PWM_ON changes from logic low to logic high. Logic circuit 205A detects the rising edge of the mode signal PWM_ON and triggers the clock terminal of D flip-flop 252, allowing the state of the inverting output terminal of D flip-flop 252 to be input to the input terminal of D flip-flop 252. The logic state of the output terminal of D flip-flop 252 changes, thereby triggering the logic states of the first control signal H1 and the second control signal H2 to flip.

[0054] When the load continues to increase and enters the non-light load mode, the output voltage V OUT is always lower than the second threshold voltage V TH_H The mode signal PWM_ON remains high, and the first switch S1 remains off. While the mode signal PWM_ON is high, the clock pulse generation circuit 206 operates, continuously providing the clock pulse signal CLK to the second input of the AND gate OR2. Triggered by the clock pulse signal CLK, the logic circuit 205A triggers the logic states of the first control signal H1 and the second control signal H2 to flip.

[0055] When the load becomes lighter, the output voltage V OUT Increases to exceed the second threshold voltage V TH_H When the mode signal PWM_ON changes from logic high to logic low, the charge pump circuit 200 exits the non-light load mode and enters the light load mode (time 271). When the mode signal PWM_ON changes to low, the clock pulse generating circuit 206 stops working. In response to the falling edge of the mode signal PWM_ON, the logic states of the first control signal H1 and the second control signal H2 output by the logic circuit 205A remain unchanged, and the charge pump circuit 200 is clamped in the holding mode. Until the output voltage V OUT Decreases again to less than the first threshold voltage V TH_L When the mode signal PWM_ON changes from logic low to logic high, for example, at time 262. In response to the rising edge of the mode signal PWM_ON, the logic circuit 205A triggers the logic state of the first control signal H1 and the second control signal H2 to flip. Thereafter, the operation of the charge pump circuit is the same as Figure 6 The working principle shown is the same and will not be described again here.

[0056] According to the embodiment of the present invention, the charge pump circuit 200 enters the light load mode, and its output voltage V OUT will increase to exceed the input voltage V BATT The efficiency of the charge pump circuit 200 is thus improved. OUT Lowered to the first threshold voltage VTH_L The speed of the charge pump circuit 200 slows down, and the time for which the charge pump circuit 200 stays in the holding mode also becomes longer.

[0057] Figure 10 This is a flow chart of a control method 500 for a charge pump circuit according to an embodiment of the present invention. The charge pump circuit includes two capacitors and two switching arms coupled between an input node and a reference ground. Each switching arm has two switch pairs connected in series via an output node. Each switch pair has two switches connected in series via a common node. One capacitor is connected between the two common nodes of one switching arm, and the other capacitor is connected between the two common nodes of the other switching arm. Control method 500 includes steps 501-505 to control the charge pump circuit to operate in light-load and non-light-load modes.

[0058] In step 501, the output voltage of the charge pump circuit is compared with a first threshold voltage and a second threshold voltage using a hysteresis function to generate a mode signal. When the output voltage decreases to the first threshold voltage, the mode signal changes from a low level to a high level; when the output voltage increases to the second threshold voltage, the mode signal changes from a high level to a low level.

[0059] In step 502 , in response to a rising edge of a mode signal, the logic states of the first control signal and the second control signal are triggered to flip, wherein the first control signal and the second control signal control each switch pair to operate complementary, and the logic states of the first control signal and the second control signal are opposite.

[0060] In step 503 , a clock pulse signal is generated based on the high-level mode signal.

[0061] In step 504 , in response to a rising edge of the mode signal or a clock pulse signal, the logic states of the first control signal and the second control signal are changed.

[0062] In step 505 , in response to the falling edge of the mode signal, the logic states of the first control signal and the second control signal are kept unchanged.

[0063] According to an embodiment of the present invention, one of the two capacitors in the charge pump circuit is always electrically coupled between the input node and the output node, and the other is always electrically coupled between the output node and the reference ground.

[0064] While the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and illustrative, rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.

Claims

1. A control circuit for a charge pump circuit, the charge pump circuit comprising two switching arms coupled between an input node and a reference ground and two corresponding capacitors, each switching arm having two switch pairs connected in series via an output node, each switch pair having two switches connected in series with each other via a common node, each capacitor being connected between the two common nodes of the corresponding switching arm, the control circuit comprising: a judgment circuit, performing a hysteresis comparison between the output voltage of the charge pump circuit and a first threshold voltage and a second threshold voltage to generate a mode signal, wherein when the output voltage decreases to less than the first threshold voltage, the mode signal changes from a low level to a high level, and when the output voltage increases to greater than the second threshold voltage, the mode signal changes from a high level to a low level; as well as The logic circuit provides a first control signal and a second control signal with opposite logic states based on a mode signal to control each switch pair to operate complementary. In response to a rising edge of the mode signal, the logic circuit triggers the logic state of the first control signal and the second control signal to flip, and in response to a falling edge of the mode signal, the logic circuit maintains the logic state of the first control signal and the second control signal unchanged. 2 . The control circuit of claim 1 , wherein one of the two capacitors is electrically coupled between the input node and the output node, and the other of the two capacitors is electrically coupled between the output node and ground.

3. The control circuit according to claim 2, further comprising: A clock pulse generating circuit generates a clock pulse signal based on a high-level mode signal; as well as In response to a rising edge of the mode signal or a clock pulse signal, the logic circuit changes the logic states of the first control signal and the second control signal.

4. The control circuit of claim 3 , wherein the logic circuit comprises: A rising edge detection circuit has an input end and an output end, wherein the input end receives a mode signal and detects a rising edge of the mode signal; An OR gate circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the rising edge detection circuit, and the second input terminal receives the clock pulse signal; as well as A D flip-flop has an input terminal, a clock terminal, an output terminal and an inverting output terminal, wherein the input terminal is coupled to the inverting output terminal, the clock terminal is coupled to the output terminal of the OR gate circuit, and the D flip-flop provides the first control signal at the output terminal and provides the second control signal through the first inverter.

5. The control circuit according to claim 2 , wherein the judgment circuit comprises: a resistor having a first end and a second end, wherein the first end receives a difference between half of the charge pump circuit input voltage and a bias voltage; a hysteresis comparator having a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the non-inverting input terminal is connected to the second terminal of the resistor, the inverting input terminal receives the output voltage, and the output terminal provides the mode signal; a current source having a power supply terminal and an output terminal, wherein the power supply terminal is coupled to the second terminal of the resistor; as well as The first switch has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the output terminal of the current source, the second terminal is coupled to the reference ground, and the control terminal is coupled to the output terminal of the hysteresis comparator via the second inverter.

6. The control circuit as claimed in claim 2, wherein a peak value of an output voltage of the charge pump circuit is greater than half of an input voltage.

7. A charge pump circuit comprising: An input node, receiving an input voltage; Output node, providing output voltage; two switching bridge arms coupled between the input node and a reference ground, each switching bridge arm having two switch pairs connected in series through an output node, wherein each switch pair has two switches connected in series to each other through a common node; two capacitors, one of which is connected between two common nodes of one switching leg and the other is connected between two common nodes of the other switching leg; and The control circuit according to any one of claims 1 to 6.

8. A method for controlling a charge pump circuit, the charge pump circuit comprising two capacitors and two switching arms coupled between an input node and a reference ground, each switching arm having two switch pairs connected in series via an output node, each switch pair having two switches connected in series via a common node, wherein one capacitor is connected between the two common nodes of one switching arm, and another capacitor is connected between the two common nodes of the other switching arm, the method comprising: Performing a hysteresis comparison of the output voltage of the charge pump circuit with a first threshold voltage and a second threshold voltage to generate a mode signal, wherein when the output voltage decreases to less than the first threshold voltage, the mode signal changes from a low level to a high level, and when the output voltage increases to greater than the second threshold voltage, the mode signal changes from a high level to a low level; In response to a rising edge of the mode signal, triggering a flip in the logic states of a first control signal and a second control signal, wherein the first control signal and the second control signal control each switch pair to operate complementary to each other, and the logic states of the first control signal and the second control signal are opposite; and In response to the falling edge of the mode signal, the logic states of the first control signal and the second control signal are kept unchanged. 9 . The control method of claim 8 , wherein one of the two capacitors is electrically coupled between the input node and the output node, and the other of the two capacitors is electrically coupled between the output node and a reference ground.

10. The control method according to claim 9, further comprising: Based on the high-level mode signal, a clock pulse signal is generated; as well as In response to a rising edge of the mode signal or a clock pulse signal, the logic states of the first control signal and the second control signal are triggered to flip.

11. The control method according to claim 8, wherein a peak value of an output voltage of the charge pump circuit is greater than half of the input voltage.

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