Method, device, equipment and storage medium for synchronizing slave and master station clocks

Abstract

This application discloses a method, apparatus, device, and storage medium for synchronizing slave and master clocks, belonging to the field of EtherCAT technology. The method includes: receiving a target synchronization signal; obtaining a current target count value and target count direction of a pulse width modulation module; and adjusting the count value of the pulse width modulation module in the next synchronization cycle based on the relationship between the target count value and a preset deviation value, as well as the target count direction, so that the count value of the pulse width modulation module at the end of the next synchronization cycle is the preset value. This application enables synchronization of slave and master clocks.

Description

Technical Field

[0001] The present application relates to the field of EtherCAT technology, and in particular to a method, apparatus, device, and storage medium for synchronizing clocks between a slave station and a master station. Background Art

[0002] Currently, Ethernet Control Automation (EtherCAT) bus communication is widely used in industrial automation control. In an EtherCAT bus-configured network, the master controller periodically sends data to each slave controller. Upon receiving data from the master controller, each slave controller sends a synchronization signal (SYNC0) to the slave's master control chip. Each slave controller corresponding to the same master can be considered to send the SYNC0 synchronization signal simultaneously, meaning that the master clock and the clocks of each slave controller are synchronized. However, the clocks of the master control chips of each slave are not identical, meaning that the clocks of each slave's master control chip are not synchronized. Consequently, when the master control chip receives the SYNC0 synchronization signal, the pulse width modulation (PWM) module in each slave's master control chip generates different count values ​​based on the master clock and does not reach zero. A slave only issues a control signal to control the automation equipment when the pulse width modulation module's count value reaches zero. This prevents synchronization between the slaves, potentially affecting the synchronized operation of the automation equipment controlled by each slave.

[0003] Therefore, a method is urgently needed to adjust the count value of the pulse width modulation module so that the count value of the pulse width modulation module is a specified value when the SYNC0 synchronization signal arrives, so that the clocks of each slave station and the master station can be synchronized, that is, the slave stations can be synchronized with each other. Summary of the Invention

[0004] The present invention provides a method, apparatus, device, and storage medium for synchronizing the clocks of a slave station and a master station, which can achieve clock synchronization between the slave station and the master station. The technical solution is as follows:

[0005] In a first aspect, a method for synchronizing clocks of a slave station and a master station is provided, the method comprising:

[0006] receiving a target synchronization signal;

[0007] Get the current target count value and target count direction of the pulse width modulation module;

[0008] According to the magnitude relationship between the target count value and the preset deviation value and the target count direction, the count value of the pulse width modulation module in the next synchronization period is adjusted so that the count value of the pulse width modulation module is the preset value at the end of the next synchronization period.

[0009] In a possible implementation, adjusting the count value of the pulse width modulation module in the next synchronization period according to the target count value, the preset deviation value, and the target count direction includes:

[0010] If the target count value is less than or equal to the preset deviation value, the current count value of the pulse width modulation module is cleared.

[0011] In a possible implementation, the method further includes:

[0012] If the target count value is greater than the preset deviation value and the target count direction is down counting, determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle;

[0013] In the next synchronization period, for each counting period to be compensated, the maximum count value of the counting period to be compensated is adjusted to a preset maximum count value minus a corresponding count compensation value.

[0014] In a possible implementation, the method further includes:

[0015] If the target count value is greater than the preset deviation value and the target count direction is up-counting, determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle;

[0016] In the next synchronization period, for each counting period to be compensated, the maximum count value of the counting period to be compensated is adjusted to a preset maximum count value plus a corresponding count compensation value.

[0017] In a possible implementation, determining the count cycles to be compensated in the next synchronization period and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles includes:

[0018] Each counting cycle in the next synchronization cycle is used as the counting cycle to be compensated;

[0019] Multiplying the preset number of counting cycles by two to obtain a first value;

[0020] Dividing the target count value by the first value to obtain a first integer and a first remainder;

[0021] Dividing the first remainder by two to obtain a remainder compensation cycle number N;

[0022] selecting N counting cycles to be compensated in the next synchronization cycle, and adding one to the first integer as a counting compensation value corresponding to the N counting cycles to be compensated;

[0023] The first integer is used as a counting compensation value corresponding to the remaining counting periods to be compensated except the N counting periods to be compensated in the next synchronization period.

[0024] In a second aspect, a device for synchronizing clocks of a slave station and a master station is provided, the device comprising:

[0025] A receiving module, configured to receive a target synchronization signal;

[0026] An acquisition module is used to obtain the current target count value and target count direction of the pulse width modulation module;

[0027] an adjustment module, configured to adjust the count value of the pulse width modulation module in the next synchronization period according to a magnitude relationship between the target count value and a preset deviation value and the target counting direction, so that the count value of the pulse width modulation module at the end of the next synchronization period is the preset value.

[0028] In a possible implementation, the adjustment module is configured to:

[0029] If the target count value is less than or equal to the preset deviation value, the current count value of the pulse width modulation module is cleared.

[0030] In a possible implementation, the adjustment module is further configured to:

[0031] If the target count value is greater than the preset deviation value and the target count direction is down counting, determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle;

[0032] In the next synchronization period, for each counting period to be compensated, the maximum count value of the counting period to be compensated is adjusted to a preset maximum count value minus a corresponding count compensation value.

[0033] In a possible implementation, the adjustment module is further configured to:

[0034] If the target count value is greater than the preset deviation value and the target count direction is up-counting, determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle;

[0035] In the next synchronization period, for each counting period to be compensated, the maximum count value of the counting period to be compensated is adjusted to a preset maximum count value plus a corresponding count compensation value.

[0036] In a possible implementation, the adjustment module is configured to:

[0037] Each counting cycle in the next synchronization cycle is used as the counting cycle to be compensated;

[0038] Multiplying the preset number of counting cycles by two to obtain a first value;

[0039] Dividing the target count value by the first value to obtain a first integer and a first remainder;

[0040] Dividing the first remainder by two to obtain a remainder compensation cycle number N;

[0041] selecting N counting cycles to be compensated in the next synchronization cycle, and adding one to the first integer as a counting compensation value corresponding to the N counting cycles to be compensated;

[0042] The first integer is used as a counting compensation value corresponding to the remaining counting periods to be compensated except the N counting periods to be compensated in the next synchronization period.

[0043] In a third aspect, a slave station device is provided, which includes a processor and a memory, wherein the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the operations performed by the method for synchronizing the slave station and master station clocks as described in the first aspect above.

[0044] In a fourth aspect, a readable storage medium is provided, in which at least one instruction is stored. The instruction is loaded and executed by a processor to implement the operations performed by the method for synchronizing the clocks of a slave station and a master station as described in the first aspect above.

[0045] In a fifth aspect, a computer program product is provided, wherein at least one instruction is stored in the computer program product, and the instruction is loaded and executed by a processor to implement the operations performed by the method for synchronizing the clocks of a slave station and a master station as described in the first aspect above.

[0046] In the method described in the embodiments of the present application, upon receiving a synchronization signal, the target count value and target count direction of the current pulse width modulation module are obtained. The target count value reflects the deviation between the synchronization signal and the control signal. Because the pulse width modulation module generates a control signal to control the servo device when the count value reaches 0, ideally, the target count value should be 0 upon receiving the synchronization signal. In this way, each slave station receives the synchronization signal simultaneously. Therefore, upon receiving the synchronization signal, each slave station will simultaneously generate a control signal to control the corresponding servo device. However, in practice, the target count value may not be 0. In this case, the present application adjusts the count value of the pulse width modulation module in the next synchronization cycle based on the relationship between the target count value and the preset deviation value, as well as the target count direction, so that the count value of the pulse width modulation module is exactly the preset value at the end of the next synchronization cycle. In this way, after adjustment, the count value of the pulse width modulation module is the preset value at the end of each synchronization cycle, thus achieving synchronization between the master control chip and the slave controller. Since the slave controller and the master clock are synchronized, the master control chip and the master clock are synchronized, that is, the slave and master clocks are synchronized. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] Figure 1 This is a schematic diagram of an implementation scenario provided by an embodiment of the present application;

[0049] Figure 2 Schematic diagram of the relationship between the synchronization period and the counting period of the pulse width modulation module provided in an embodiment of the present application;

[0050] Figure 3 This is a flowchart of a method for synchronizing the clocks of a slave station and a master station provided in an embodiment of the present application;

[0051] Figure 4 This is a schematic diagram of the relationship between a synchronization period and a counting period of a pulse width modulation module provided in an embodiment of the present application;

[0052] Figure 5 This is a schematic diagram of the relationship between a synchronization period and a counting period of a pulse width modulation module provided in an embodiment of the present application;

[0053] Figure 6 This is a schematic diagram of the relationship between a synchronization period and a counting period of a pulse width modulation module provided in an embodiment of the present application;

[0054] Figure 7 This is a schematic diagram of the relationship between a synchronization period and a counting period of a pulse width modulation module provided in an embodiment of the present application;

[0055] Figure 8 This is a flowchart of a method for synchronizing the clocks of a slave station and a master station provided in an embodiment of the present application;

[0056] Figure 9 1 is a schematic diagram of a device structure for synchronizing clocks of a slave station and a master station provided in an embodiment of the present application;

[0057] Figure 10 This is a structural diagram of a slave station device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0059] Embodiments of the present application provide a method for synchronizing the clocks of a slave and a master. This method can be applied to an EtherCAT bus-configured network. The EtherCAT bus-configured network includes a master and slaves, where the slaves can be motor drives. The method provided in the embodiments of the present application can be implemented by the slaves in the EtherCAT bus-configured network.

[0060] See also Figure 1 , shows a possible implementation scenario of the embodiment of the present application. Figure 1 The illustrated implementation scenario includes a master station 10 and a slave station 20. The slave station 20 includes an EtherCAT Slave Controller (ESC) 210 and a master control chip 220. The master control chip 220 may be a microcontroller unit (MCU). In one possible implementation, the slave station controller 210 and the master control chip 220 may be integrated into a single chip, which has all the functions of the slave station controller 210 and the master control chip 220. If the slave station 20 is a motor driver, the master control chip 220 of the slave station 20 may establish a communication connection with the motor, allowing the slave station 20 to control the motor.

[0061] The master station 10 periodically sends data to the slave station controller 210 according to the master station clock. In the case where the slave station 20 is a motor driver, the data sent by the master station 10 to the slave station controller 210 may include control commands related to position, speed, torque, etc.

[0062] After receiving the data from the master station 10, the slave controller 210 sends a synchronization signal (SYNC0) to the master control chip 220. In addition, the slave controller 210 also sends the data from the master station 10 to the master control chip 220. The slave controller 210 can also obtain information such as the position, speed, and torque of the motor from the master control chip 220.

[0063] The main control chip 220 includes a pulse width modulation module. The pulse width modulation module can count according to the main control chip clock in a combination of up-counting and down-counting. For example, it counts once every 10 microseconds (μs). In addition, the transmission period of the SYNC0 synchronization signal is typically set to N times the counting period of the pulse width modulation module, where N is a positive integer greater than 1. The transmission period of the SYNC0 synchronization signal can also be referred to as the synchronization period. That is, within one synchronization period, the pulse width modulation module ideally completes N counting cycles. Each counting cycle includes half a cycle of up-counting and half a cycle of down-counting, that is, first counting up from 0 to a preset maximum count value, and then counting down from the preset maximum count value to 0.

[0064] See also Figure 2 , shows the relationship between the synchronization cycle and the pulse width modulation module's count cycle under an ideal state. Each SYNC0 synchronization signal indicates the end of the previous synchronization cycle and the beginning of the next synchronization cycle. When a synchronization cycle ends, the pulse width modulation module's count value is exactly 0. That is, at the beginning of each synchronization cycle, the pulse width modulation module's count value is exactly 0.

[0065] The following example illustrates the relationship between the synchronization period and the counting period of the pulse width modulation module under ideal conditions:

[0066] Assuming a synchronization period of 1 millisecond (ms), a counting period of 100 μs, and a pulse width modulation module counting every 10 μs, the pulse width modulation module should complete 10 counting cycles within one synchronization period. The count value within each counting cycle increases or decreases as follows: 0, 1, 2, 3, 4, 5, 4, 3, 2, 1, 0, where 5 is the maximum count value.

[0067] However, since the clock of the main control chip 220 is different from the clock of the master station 10, it is possible that after the first synchronization cycle, the count value of the pulse width modulation module is not 0, that is, there is a deviation between the slave station and the master station clocks. As time goes by, after N synchronization cycles, the count value of the pulse width modulation module may be larger than the count value of the pulse width modulation module after the first synchronization cycle, that is, the deviation between the slave station and the master station clocks may become larger over time. The method for synchronizing the slave station and the master station clocks provided in the embodiment of the present application is to adjust the count value of the pulse width modulation module so that the count value of the pulse width modulation module and the synchronization cycle become equal again. Figure 2 The ideal situation shown.

[0068] In the method for synchronizing the clocks of a slave station and a master station provided in an embodiment of the present application, after receiving a synchronization signal, the current count value of the pulse width modulation module is obtained, and the count value of the pulse width modulation module in the next synchronization cycle is adjusted based on the relationship between the preset deviation value and the current count value of the pulse width modulation module, as well as the current counting direction, so that at the end of the next synchronization cycle, the count value of the pulse width modulation module is exactly 0, thereby achieving synchronization of the clocks of the slave station and the master station.

[0069] The following describes the method for synchronizing the clocks of the slave and master stations provided by the embodiment of the present application with reference to the accompanying drawings. Figure 3 The method for synchronizing the clocks of a slave station and a master station provided in an embodiment of the present application may include the following processing steps:

[0070] Step 301: Receive a target synchronization signal.

[0071] The target synchronization signal is the SYNC0 synchronization signal.

[0072] In practice, the master station periodically sends data to the slave station controller of the slave station according to the master station clock. In the case where the slave station is a motor drive, the data sent by the master station to the slave station controller may include control commands related to position, speed, torque, etc.

[0073] After receiving data from the master, the slave controller sends a SYNC0 synchronization signal to the slave's master chip. The master chip then receives the SYNC0 synchronization signal from the slave controller. Receiving the SYNC0 synchronization signal from the master indicates the end of the previous synchronization cycle and the beginning of the next.

[0074] Step 302: Obtain the target counting direction and target counting value of the current pulse width modulation module.

[0075] In implementation, when the main control chip receives the SYNC0 synchronization signal, it reads the current target counting direction and target counting value of the pulse width modulation module.

[0076] For example, when the main control chip receives the SYNC0 synchronization signal, it reads that the current target counting direction of the pulse width modulation module is up counting and the current target counting value is 3.

[0077] Step 303: Adjust the count value of the PWM module in the next synchronization period according to the target counting direction and the relationship between the preset deviation value and the target count value, so that the count value of the PWM module at the end of the next synchronization period is the preset value.

[0078] Among them, the preset value can be 0.

[0079] For ease of description, several parameters are given corresponding symbols below: The target count value is T c , the preset deviation value is ΔT, and the target counting direction is Dir.

[0080] In the implementation, the main control chip reads the target counting direction indication information Dir of the current pulse width modulation module and the current target counting value T c Then, the preset deviation value ΔT stored in advance is obtained, and the target count value T is determined. c and the preset deviation value ΔT.

[0081] The preset deviation value ΔT is pre-configured by a technician and can be configured to a different value based on actual conditions. The preset deviation value ΔT can be a small positive integer and must be less than the maximum count value of the pulse width modulation module.

[0082] Specifically, determine the target count value T c The relationship between the target count value T and the preset deviation value ΔT can be: c Is it greater than the preset deviation value ΔT, or determine the target count value T c Is it less than or equal to the preset deviation value ΔT?

[0083] The following describes how to determine the magnitude relationship between the preset deviation value and the target count value by way of examples.

[0084] For example, the target count value T of the pulse width modulation module is read c is 9, and the preset deviation value ΔT is 3, then the target count value T can be determined. c is greater than the preset deviation value ΔT, which can be recorded as: T c >ΔT.

[0085] For example, the target count value T of the pulse width modulation module is read. c is 2, and the preset deviation value ΔT is 3, then the target count value T can be determined. c Less than the preset deviation value ΔT, which can be written as: T c <ΔT.

[0086] For example, the target count value T of the pulse width modulation module is read. c is 3, the preset deviation value ΔT is 3, then the target count value T can be determined c Equal to the preset deviation value ΔT, which can be written as: T c =ΔT.

[0087] The target counting direction indication information Dir is described below:

[0088] The target counting direction indication information Dir is used to indicate the current counting direction of the pulse width modulation module. Specifically, the target counting direction indication information Dir can be represented by a one-bit binary number.

[0089] For example, when the target counting direction indication information Dir is 0, it indicates that the pulse width modulation module is currently counting up, and when the target counting direction indication information Dir is 1, it indicates that the pulse width modulation module is currently counting down.

[0090] Depending on the target counting direction and the relationship between the preset deviation value and the target counting value, the method for adjusting the counting value of the pulse width modulation module in the next synchronization period may also be different. Several cases are described below.

[0091] Case 1: T c <ΔT, and the target counting direction is up counting. (T c (not 0)

[0092] The following combination Figure 4 Let’s explain the situation 1. Because the current target counting direction is up counting, and the target counting value T c If it is not 0 and is less than the preset deviation value ΔT, it means that the SYNC0 synchronization signal is lagging, but the lag is not too much. In this case, the count value of the pulse width modulation module can be cleared. In this way, the pulse width modulation starts counting from 0 at the beginning of the next synchronization cycle, instead of from T c Continue counting.

[0093] Case 2: T c <ΔT, and the target counting direction is down counting. (T c (not 0)

[0094] The following combination Figure 5Explain the situation 1. Because the current target counting direction is down counting, and the target counting value T c If it is not 0 and is less than the preset deviation value ΔT, it means that the SYNC0 synchronization signal is ahead, but not by much. In this case, the count value of the pulse width modulation module can be cleared. In this way, the pulse width modulation starts counting from 0 at the beginning of the next synchronization cycle, instead of from T c Continue counting.

[0095] Case 3: T c >ΔT, and the target counting direction is up counting.

[0096] For the convenience of description, the following parameters are given corresponding symbols: the preset number of counting cycles is N, the maximum counting value is T PWM , the preset maximum count value is T period , the counting compensation value is T cmp , the counting compensation value corresponding to the i-th counting cycle to be compensated is T cmp (i).

[0097] The following combination Figure 6 The third case is described below. When the target counting direction is up counting and the target counting value T c When the deviation is greater than the preset deviation value ΔT, the number of count cycles to be compensated in the next synchronization cycle and the corresponding count compensation value for each count cycle to be compensated can be determined based on the preset number of count cycles and the target count value. In the next synchronization cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the preset maximum count value plus the corresponding count compensation value. The preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle.

[0098] Because the target counting direction is up counting, and the target counting value T c If the deviation is greater than the preset deviation value ΔT, it means that the SYNC0 synchronization signal is lagging behind and is significantly ahead. In this case, it is no longer appropriate to directly reset the count value of the pulse width modulation module to zero. In the embodiment of the present application, the count period to be compensated can be selected in the next synchronization cycle, and the target count value can be distributed and compensated to the count values ​​corresponding to each count period to be compensated. This is equivalent to extending the count period to be compensated in the next synchronization cycle. In this way, when the SYNC0 synchronization signal arrives again, the count value of the pulse width modulation module can be exactly 0.

[0099] Case 4: T c >ΔT, and the target counting direction is down counting.

[0100] The following combination Figure 7The fourth case is described below. When the target counting direction is down counting and the target counting value T c When the deviation is greater than the preset deviation value ΔT, the number of count cycles to be compensated in the next synchronization cycle and the corresponding count compensation value for each count cycle to be compensated can be determined based on the preset number of count cycles and the target count value. In the next synchronization cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the preset maximum count value minus the corresponding count compensation value. The preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle.

[0101] Because the current target counting direction is down counting, and the target counting value T c If the deviation is greater than the preset deviation value ΔT, it means that the SYNC0 synchronization signal is ahead, and the advance is large. In this case, it is no longer appropriate to directly reset the current count value of the pulse width modulation module to zero. In the embodiment of the present application, the count cycle to be compensated can be selected in the next synchronization cycle, and the target count value can be distributed and compensated to the count values ​​corresponding to each count cycle to be compensated. This is equivalent to shortening the count cycle to be compensated in the next synchronization cycle. In this way, when the SYNC0 synchronization signal arrives again, the count value of the pulse width modulation module can be exactly 0.

[0102] There are many methods for determining the counting period to be compensated and the corresponding counting compensation value. Two of them are listed below for illustration:

[0103] Method 1:

[0104] All counting cycles in the next synchronization cycle are regarded as counting cycles to be compensated.

[0105] The calculation method for the counting compensation value can be as follows:

[0106] Calculate 2 times the number of preset counting cycles to obtain a first value, divide the target count value by the first value to obtain a first integer and a first remainder. Accordingly, the formula can be as follows:

[0107] T int =T c / (2N)

[0108] T r =T c %(2N)

[0109] Among them, T int is the first integer, T r is the first remainder, 2N is the first value, the symbol “ / ” is the rounding operation of division, and the symbol “%” is the remainder operation of division.

[0110] Divide the first remainder by two to get the remainder compensation cycle number. Correspondingly, the formula can be as follows:

[0111] N r =T r / 2

[0112] Among them, N r The number of remainder compensation cycles, indicating that the remainder is compensated to N r count cycles to be compensated.

[0113] Select N in the next synchronization cycle r The counting cycles to be compensated are: the first integer plus one is N r The counting compensation value corresponding to the counting cycle to be compensated. Correspondingly, the formula can be as follows:

[0114] T cmp (i) = T int +l

[0115] The above N r The counting cycles to be compensated can be the first N in the next synchronization cycle. r count cycles to be compensated, then i is 1≤i≤N r .

[0116] The first integer is regarded as the next synchronization cycle except for the above N r The counting compensation value corresponding to the counting period to be compensated other than the counting period to be compensated. Correspondingly, the formula can be as follows:

[0117] T cmp (i) = T int

[0118] In the above N r The counting cycles to be compensated can be the first N in the next synchronization cycle. r In the case of a count cycle to be compensated, T cmp (i) = T int The value of i is N r <i≤N。

[0119] Method 2:

[0120] Determine the number of count cycles N to be compensated a , the determination method is as follows:

[0121] N a =T c / (2i)

[0122] For i in the above formula, take values ​​from 1, 2, ...N in sequence, and calculate the corresponding N after each value is taken. a .

[0123] If 1≤N a ≤N is established, then stop taking values ​​and set N at this time a As the number of counting cycles to be compensated. If i takes the value of N, 1≤N a If ≤N still does not hold, the deviation is too large to be compensated, and an alarm can be issued.

[0124] Accordingly, the calculation method of the counting compensation value can be as follows:

[0125] T cmp (i)=(2i) / 2

[0126] Among them, N a The counting cycles to be compensated can be the first N in the next synchronization cycle. a count cycles to be compensated, then i is 1≤i≤N a .

[0127] Case 5: T c =ΔT, and the target counting direction is up counting.

[0128] The processing method for this situation five can be the same as that for the above situation one, or the same as that for the above situation three, and will not be described in detail here.

[0129] Case 6: T c =ΔT, and the target counting direction is down counting.

[0130] The processing method for this case 6 can be the same as that for the above case 2, or the same as that for the above case 4, and will not be described in detail here.

[0131] In the method described in the embodiment of the present application, upon receiving a synchronization signal, the target counting direction and target counting value of the current pulse width modulation module are obtained. The target counting value reflects the deviation between the synchronization signal and the control signal. Because the pulse width modulation module generates a control signal to control the servo device when the counting value is 0, ideally, the target counting value should be 0 when the synchronization signal is received. In this way, each slave station receives the synchronization signal at the same time. Then, upon receiving the synchronization signal, each slave station will simultaneously generate a control signal to control the corresponding servo device. However, in practice, the target counting value may not be 0. In this case, the present application combines the target counting direction and the relationship between the preset deviation value and the target counting value to adjust the counting value of the pulse width modulation module in the next synchronization cycle, so that the counting value of the pulse width modulation module is exactly the preset value at the end of the next synchronization cycle. In this way, after adjustment, at the end of each synchronization cycle, the count value of the pulse width modulation module is the preset value, thereby realizing the synchronization of the master control chip and the slave controller. Since the slave controller and the master clock are synchronized, the synchronization of the master control chip and the master clock is realized, that is, the slave and master clocks are synchronized.

[0132] The present invention also provides a method for synchronizing the clocks of a slave station and a master station. Figure 8 The processing flow of the method may include the following steps:

[0133] Step 701: Receive a target synchronization signal.

[0134] Step 702: Obtain the target counting direction and target counting value of the current pulse width modulation module.

[0135] Step 703: Determine whether the target count value is greater than the preset deviation value.

[0136] Step 704: If the target count value is greater than the preset deviation value, continue to determine whether the target count direction is up-counting or down-counting.

[0137] Step 705: If the target counting direction is up-counting, the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated are determined based on the preset number of count cycles and the target count value. In the next synchronization cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the corresponding count compensation value plus the preset maximum count value.

[0138] Step 706: If the target counting direction is downcounting, the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated are determined based on the preset number of count cycles and the target count value. In the next synchronization cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the preset maximum count value minus the corresponding count compensation value.

[0139] Step 707: If the target count value is not greater than the preset deviation value, the count value of the current pulse width modulation module is cleared.

[0140] It should be noted that the specific processing of step 701 is the same as that of step 301, the specific processing of step 702 is the same as that of step 302, and the specific processing of steps 703 to 707 is the same as that of step 303, which will not be repeated here.

[0141] In the method described in the embodiment of the present application, upon receiving a synchronization signal, the target counting direction and target counting value of the current pulse width modulation module are obtained. The target counting value reflects the deviation between the synchronization signal and the control signal. Because the pulse width modulation module generates a control signal to control the servo device when the counting value is 0, ideally, the target counting value should be 0 when the synchronization signal is received. In this way, each slave station receives the synchronization signal at the same time. Then, upon receiving the synchronization signal, each slave station will simultaneously generate a control signal to control the corresponding servo device. However, in practice, the target counting value may not be 0. In this case, the present application combines the target counting direction and the relationship between the preset deviation value and the target counting value to adjust the counting value of the pulse width modulation module in the next synchronization cycle, so that the counting value of the pulse width modulation module is exactly the preset value at the end of the next synchronization cycle. In this way, after adjustment, at the end of each synchronization cycle, the count value of the pulse width modulation module is the preset value, thereby realizing the synchronization of the master control chip and the slave controller. Since the slave controller and the master clock are synchronized, the synchronization of the master control chip and the master clock is realized, that is, the slave and master clocks are synchronized.

[0142] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0143] Based on the same technical concept, the embodiment of the present application also provides a device for synchronizing the clocks of a slave station and a master station, such as Figure 9 As shown, the device 900 includes a receiving module 910 , an acquiring module 920 , and an adjusting module 930 .

[0144] Receiving module 910, configured to receive a target synchronization signal;

[0145] An acquisition module 920 is configured to acquire a current target counting direction and a target counting value of a pulse width modulation module;

[0146] The adjustment module 930 is configured to adjust the count value of the pulse width modulation module in the next synchronization period according to the target counting direction and the relationship between the preset deviation value and the target count value, so that the count value of the pulse width modulation module at the end of the next synchronization period is the preset value.

[0147] In a possible implementation, the adjustment module 930 is configured to:

[0148] If the target count value is less than or equal to the preset deviation value, the current count value of the pulse width modulation module is cleared.

[0149] In a possible implementation, the adjustment module 930 is further configured to:

[0150] If the current target counting direction is down counting and the target count value is greater than the preset deviation value, then determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles;

[0151] In the next synchronization cycle, for each counting cycle to be compensated, the maximum count value of the counting cycle to be compensated is adjusted to the preset maximum count value minus the corresponding count compensation value.

[0152] In a possible implementation, the adjustment module 930 is further configured to:

[0153] If the current target counting direction is up counting and the target count value is greater than the preset deviation value, then determining the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles;

[0154] In the next synchronization cycle, for each counting cycle to be compensated, the maximum count value of the counting cycle to be compensated is adjusted to the corresponding counting compensation value plus the preset maximum count value.

[0155] In a possible implementation, the adjustment module 930 is configured to:

[0156] Each counting cycle in the next synchronization cycle is used as the counting cycle to be compensated;

[0157] Multiplying the preset number of counting cycles by two to obtain a first value;

[0158] Dividing the target count value by the first value to obtain a first integer and a first remainder;

[0159] Dividing the first remainder by two to obtain a remainder compensation cycle number N;

[0160] selecting N counting cycles to be compensated in the next synchronization cycle, and adding one to the first integer as a counting compensation value corresponding to the N counting cycles to be compensated;

[0161] The first integer is used as a counting compensation value corresponding to the remaining counting periods to be compensated except the N counting periods to be compensated in the next synchronization period.

[0162] In the method described in the embodiment of the present application, upon receiving a synchronization signal, the target counting direction and target counting value of the current pulse width modulation module are obtained. The target counting value reflects the deviation between the synchronization signal and the control signal. Because the pulse width modulation module generates a control signal to control the servo device when the counting value is 0, ideally, the target counting value should be 0 when the synchronization signal is received. In this way, each slave station receives the synchronization signal at the same time. Then, upon receiving the synchronization signal, each slave station will simultaneously generate a control signal to control the corresponding servo device. However, in practice, the target counting value may not be 0. In this case, the present application combines the target counting direction and the relationship between the preset deviation value and the target counting value to adjust the counting value of the pulse width modulation module in the next synchronization cycle, so that the counting value of the pulse width modulation module is exactly the preset value at the end of the next synchronization cycle. In this way, after adjustment, at the end of each synchronization cycle, the count value of the pulse width modulation module is the preset value, thereby realizing the synchronization of the master control chip and the slave controller. Since the slave controller and the master clock are synchronized, the synchronization of the master control chip and the master clock is realized, that is, the slave and master clocks are synchronized.

[0163] It should be noted that the apparatus for synchronizing the clocks of a slave station and a master station provided in the above embodiment only uses the division of the above functional modules as an example to illustrate the implementation of the clock synchronization between the slave station and the master station. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the slave station can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus for synchronizing the clocks of a slave station and a master station provided in the above embodiment and the method embodiment for synchronizing the clocks of a slave station and a master station are of the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0164] Figure 10This is a schematic diagram of the structure of a slave device provided in an embodiment of the present application. The slave device 1000 may have relatively large differences due to different configurations or performances, and may include one or more processors 1001 and one or more memories 1002, wherein the memory 1002 stores at least one instruction, and the at least one instruction is loaded and executed by the processor 1001 to implement the methods provided in the above-mentioned various method embodiments. The processor may be Figure 1 Of course, the slave device may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The slave device may also include other components for realizing the functions of the device, which will not be described in detail here.

[0165] In an exemplary embodiment, a computer-readable storage medium is also provided, such as a memory including instructions, which can be executed by a processor in the slave station to perform the method for synchronizing the slave and master station clocks in the above embodiment. The computer-readable storage medium can be non-transitory. For example, the computer-readable storage medium can be a ROM (Read-Only Memory), a RAM (Random Access Memory), a CD-ROM (Compact Disc Read-Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0166] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals (including but not limited to signals transmitted between user terminals and other devices, etc.) involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions.

[0167] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0168] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be understood to indicate or imply relative importance. The term "at least one" refers to one or more, and the term "plurality" refers to two or more, unless otherwise expressly limited.

[0169] In the embodiments of this application, the term "and / or" is simply a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "" in this document generally indicates that the related objects are in an "or" relationship.

[0170] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for synchronizing clocks of a slave station and a master station, characterized in that: The method comprises: receiving a target synchronization signal; Get the current target count value and target count direction of the pulse width modulation module; If the target count value is less than or equal to the preset deviation value, clearing the current count value of the pulse width modulation module; If the target count value is greater than the preset deviation value and the target count direction is down counting, then determining the count cycles to be compensated in the next synchronous cycle and the count compensation value corresponding to each count cycle to be compensated based on the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronous cycle; in the next synchronous cycle, for each count cycle to be compensated, adjusting the maximum count value of the count cycle to be compensated to the preset maximum count value minus the corresponding count compensation value; If the target count value is greater than the preset deviation value and the target count direction is up-counting, the count cycles to be compensated in the next synchronous cycle and the count compensation value corresponding to each count cycle to be compensated are determined based on the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronous cycle; in the next synchronous cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the preset maximum count value plus the corresponding count compensation value.

2. The method according to claim 1, characterized in that The determining, based on the target count value and the preset number of count cycles, the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated includes: Taking each counting period in the next synchronization period as a counting period to be compensated; Multiplying the preset number of counting cycles by two to obtain a first value; Dividing the target count value by the first value to obtain a first integer and a first remainder; Dividing the first remainder by two to obtain a remainder compensation cycle number N; selecting N counting cycles to be compensated in the next synchronization cycle, and adding one to the first integer as a counting compensation value corresponding to the N counting cycles to be compensated; The first integer is used as a counting compensation value corresponding to the remaining counting periods to be compensated except the N counting periods to be compensated in the next synchronization period.

3. A device for synchronizing the clocks of a slave station and a master station, characterized in that: The device comprises: A receiving module, configured to receive a target synchronization signal; An acquisition module is used to obtain the current target count value and target count direction of the pulse width modulation module; The adjustment module is configured to clear the current count value of the pulse width modulation module to zero if the target count value is less than or equal to the preset deviation value; if the target count value is greater than the preset deviation value and the target counting direction is down counting, determine the count cycle to be compensated in the next synchronous cycle and the count compensation value corresponding to each count cycle to be compensated according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronous cycle; in the next synchronous cycle, for each count cycle to be compensated, the maximum value of the count cycle to be compensated is set. The maximum count value is adjusted to a preset maximum count value minus a corresponding count compensation value; if the target count value is greater than a preset deviation value and the target count direction is an increase in count, the count cycles to be compensated in the next synchronization cycle and the count compensation value corresponding to each count cycle to be compensated are determined according to the target count value and the preset number of count cycles, wherein the preset number of count cycles is the number of count cycles of the pulse width modulation module in one synchronization cycle; in the next synchronization cycle, for each count cycle to be compensated, the maximum count value of the count cycle to be compensated is adjusted to the preset maximum count value plus the corresponding count compensation value.

4. The device according to claim 3, characterized in that The adjustment module is used to: Each counting cycle in the next synchronization cycle is used as the counting cycle to be compensated; Multiplying the preset number of counting cycles by two to obtain a first value; Dividing the target count value by the first value to obtain a first integer and a first remainder; Dividing the first remainder by two to obtain a remainder compensation cycle number N; selecting N counting cycles to be compensated in the next synchronization cycle, and adding one to the first integer as a counting compensation value corresponding to the N counting cycles to be compensated; The first integer is used as a counting compensation value corresponding to the remaining counting periods to be compensated except the N counting periods to be compensated in the next synchronization period.

5. A slave device, characterized in that: The slave device includes a processor and a memory, wherein the memory stores at least one instruction, and the instruction is loaded and executed by the processor to implement the operation performed by the method for synchronizing the clocks of a slave and a master as described in any one of claims 1-2.

6. A readable storage medium, characterized in that: The readable storage medium stores at least one instruction, which is loaded and executed by the processor to implement the operations performed by the method for synchronizing the clocks of a slave station and a master station according to any one of claims 1 to 2.

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