Current Limiting in Boost Converters

Abstract

Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limiting circuit including: a first capacitive element; a charging circuit coupled to the first capacitive element; a first current source; a first resistive element coupled to the first current source, the capacitive element coupled to a node between the resistive element and the first current source; a sample-and-hold circuit coupled to the first capacitive element; and a clamping circuit coupled between the sample-and-hold circuit and the feedback path.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Application No. 17 / 159,082, filed on January 26, 2021, which claims the benefit of and priority to U.S. Provisional Application No. 62 / 966,449, filed on January 27, 2020, all of which are assigned to the assignee of the present application and are expressly incorporated herein by reference in their entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] Certain aspects of the present disclosure relate generally to electronic circuits and, more particularly, to a circuit for a power supply circuit. Background Art

[0004] A voltage regulator ideally provides a constant direct current (DC) output voltage regardless of changes in load current or input voltage. Voltage regulators can be categorized as either linear or switching regulators. While linear regulators tend to be small and compact, many applications may benefit from the increased efficiency of switching regulators. For example, a linear regulator can be implemented as a low dropout (LDO) regulator. A switching regulator can be implemented as a switch-mode power supply (SMPS), such as a buck converter, a boost converter, or a buck-boost converter.

[0005] A power management integrated circuit (power management IC or PMIC) is used to manage the power requirements of a host system and may include and / or control one or more voltage regulators (e.g., boost converters). A PMIC may be used in battery-operated devices such as mobile phones, tablets, laptops, wearable devices, etc. to control the flow and direction of power in the device. The PMIC may perform various functions for the device, such as DC-to-DC conversion (e.g., using the aforementioned regulators), battery charging, power source selection, voltage scaling, power sequencing, etc. For example, a PMIC may have a boost converter to increase the voltage level of a DC input voltage. Summary of the Invention

[0006] Certain aspects of the present disclosure are generally directed to a boost converter including a current-mode feedback control circuit.

[0007] Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limiting circuit including: a first capacitive element; a charging circuit coupled to the first capacitive element; a first current source; a first resistive element coupled to the first current source, the capacitive element coupled to a node between the resistive element and the first current source; a sample-and-hold circuit coupled to the first capacitive element; and a clamping circuit coupled between the sample-and-hold circuit and the feedback path.

[0008] Certain aspects of the present disclosure provide a method for voltage regulation. The method generally includes: generating an output voltage at an output of the SMPS via a SMPS, wherein the SMPS includes an inductive element and a first switch coupled to the inductive element, a feedback path coupled between the output of the SMPS and a control input of the first switch; and limiting current through the inductive element via a current limiting circuit. In some aspects, limiting the current includes: charging a first capacitive element; providing current across a first resistive element, the first capacitive element coupled to a node between the first resistive element and a first current source; sampling a voltage across the first capacitive element; and limiting a voltage associated with the feedback path based on the sampled voltage.

[0009] Certain aspects of the present disclosure provide an apparatus for voltage regulation. The apparatus generally includes: a SMPS configured to generate an output voltage at an output of the SMPS, wherein the SMPS includes an inductive element and a first switch coupled to the inductive element, a feedback path coupled between the output of the SMPS and a control input of the first switch; and means for limiting current through the inductive element via a current limiting circuit. In some aspects, the means for limiting current includes: means for charging a first capacitive element; means for providing current across a first resistive element, the first capacitive element coupled to a node between the first resistive element and a first current source; means for sampling a voltage across the first capacitive element; and means for limiting a voltage associated with the feedback path based on the sampled voltage.

[0010] To accomplish the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of but a few of the various ways in which the principles of the various aspects may be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the manner in which the above-described features of the present disclosure are understood in detail, a more particular description, briefly summarized above, may be obtained by reference to the various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0012] Figure 1 is a block diagram of an example device including a voltage regulator according to certain aspects of the present disclosure.

[0013] Figure 2 An example boost converter according to certain aspects of the present disclosure is illustrated.

[0014] Figure 3 Illustrated are example implementation details of an example boost converter and feedback control circuit according to certain aspects of the present disclosure.

[0015] Figure 4 Illustrated are example implementations of current sensing circuits according to certain aspects of the present disclosure.

[0016] Figure 5 Illustrated are example implementations of a current limiting circuit configured to clamp the supply voltage of an amplifier, in accordance with certain aspects of the present disclosure.

[0017] Figure 6 Illustrated are example implementations of a current limiting circuit configured to clamp the voltage at the output of an amplifier, in accordance with certain aspects of the present disclosure.

[0018] Figure 7 is a flow chart illustrating example operations for voltage regulation according to certain aspects of the present disclosure.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation. DETAILED DESCRIPTION

[0020] Certain aspects of the present disclosure relate to apparatus and techniques for limiting the inductor current of a boost converter of a power supply circuit. Certain conventional implementations use fixed voltage clamps to implement current limiting. However, due to variations in the input voltage (Vin) and output voltage (Vout) of the boost converter, using fixed voltage clamps can result in large variations in the current limit. Some aspects of the present disclosure relate to implementing current limiting circuitry in a manner independent of Vin and Vout, as described in more detail herein.

[0021] In some aspects, the power supply circuit can include a current sensing circuit that senses the current through the inductive element of the boost converter. In some aspects of the present disclosure, the configuration of the current sensing circuit can be replicated to implement a current limiting circuit for limiting the inductor current in a manner independent of Vin and Vout. In one aspect, the current limiting circuit can clamp the output voltage of the error amplifier in the feedback path of the power supply circuit. In other aspects, the current limiting circuit can clamp the supply voltage of the error amplifier in the feedback path of the power supply circuit.

[0022] Various aspects of the present disclosure are described more fully below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure is thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the present disclosure disclosed herein, whether implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods that are practiced using other structures, functionality, or structures and functionality other than or different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure disclosed herein can be implemented by one or more elements of the claims.

[0023] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0024] The techniques described herein can be used in combination with various wireless technologies, such as code division multiple access (CDMA), orthogonal frequency division multiplexing (OFDM), time division multiple access (TDMA), space division multiple access (SDMA), single carrier frequency division multiple access (SC-FDMA), time division synchronous code division multiple access (TD-SCDMA), etc. Multiple user terminals can simultaneously transmit / receive data via different (1) CDMA orthogonal code channels, (2) TDMA time slots, or (3) OFDM subbands. A CDMA system can implement IS-2000, IS-95, IS-856, Wideband CDMA (W-CDMA), or some other standards. An OFDM system can implement Institute of Electrical and Electronics Engineers (IEEE) 802.11, IEEE802.16, Long Term Evolution (LTE) (e.g., in TDD and / or FDD mode), or some other standards. A TDMA system can implement Global System for Mobile Communications (GSM) or some other standards. These various standards are known in the art.

[0025] Example device

[0026] Figure 1 Device 100 is illustrated. Device 100 may be a battery-operated device such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet computer, a personal computer, etc. Device 100 is an example of a device that may be configured to implement the various systems and methods described herein.

[0027] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). Memory 106, which may include read-only memory (ROM) and random access memory (RAM), provides instructions and data to the processor 104. A portion of the memory 106 may also include non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106. The instructions in the memory 106 may be executable to implement the methods described herein.

[0028] The device 100 may also include a housing 108, which may include a transmitter 110 and a receiver 112 to allow data to be sent and received between the device 100 and a remote location. The transmitter 110 and the receiver 112 may be combined into a transceiver 114. A plurality of antennas 116 may be attached to the housing 108 and electrically coupled to the transceiver 114. The device 100 may also include (not shown) multiple transmitters, multiple receivers, and multiple transceivers.

[0029] The device 100 may also include a signal detector 118, which may be used to attempt to detect and quantify the level of the signal received by the transceiver 114. The signal detector 118 may detect signals such as total energy, energy per subcarrier per symbol, power spectral density, and other signals. The device 100 may also include a digital signal processor (DSP) 120 for processing signals.

[0030] The device 100 may also include a battery 122 for powering the various components of the device 100. The device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing the power from the battery to the various components of the device 100. The PMIC 124 may perform various functions for the device, such as DC-to-DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In certain aspects, the DC-to-DC converter of the PMIC 124 may include a boost converter as described herein.

[0031] The various components of device 100 may be coupled together via a bus system 126 , which may include a power bus, a control signal bus, and a status signal bus in addition to a data bus.

[0032] Example Current Limited Boost Converter

[0033] Certain aspects of the present disclosure generally relate to a switched-mode power supply (e.g., a boost converter) implemented using a current limiting circuit configured to limit the inductor current of the boost converter. Using a hard current limit on the inductor of the boost converter may result in inductor current modulation and voltage overshoot at peak load current. Applying a soft limit on the inductor peak current may help smooth the inductor current waveform by allowing the voltage loop to maintain control of the inductor peak current, rather than relying on a hard current limiter. Certain aspects of the present disclosure generally relate to implementations of soft current limiters, as described in more detail herein.

[0034] Figure 2 An example power supply circuit 200 having a switched mode power supply (SMPS) (e.g., a boost converter) according to certain aspects of the present disclosure is illustrated. The boost converter includes an inductive element 202 (e.g., an inductor) coupled to a node 204 and a switch 206. The boost converter also includes a switch 208 coupled between the node 204 and an output node 210 of the boost converter. Switches 206 and 208 may be implemented by one or more transistors, such as Figure 2 The output node 210 may be coupled to an energy storage device (eg, a capacitive element 212) and a load, which may be Figure 2 In the figure, the load is represented by the resistance element Rload.

[0035] The switch 206 may be controlled by a pulse width modulation (PWM) signal to open and close the switch 206 in an attempt to regulate the boost output voltage (Vboost_out) across the capacitive element 212. For example, during a first cycle, the switch 206 may be closed, drawing power from the power supply 218 (at Figure 2 2 (represented by a voltage source in FIG1 ) transfers energy and stores the energy in the inductive element 202. The switch 206 may be opened during the second cycle, and the energy stored in the inductive element 202 may be transferred to the capacitive element 212 via the switch 208. In some aspects, the switch 208 may be replaced with a diode 216, and the energy stored in the inductive element 202 may be transferred to the capacitive element 212 via the diode.

[0036] As shown, power supply circuit 200 also includes a current-mode feedback control circuit 214 in feedback path 213. Feedback control circuit 214 can control switch 206 and, in some cases, switch 208 based on Vboost_out at output node 210 and the current at a node coupled to switch 206. For example, feedback control circuit 214 can receive a current sense signal Isense, which represents the current across switch 206. Isense also represents the current through inductive element 202 during the period when switch 206 is closed. However, in some cases, feedback control circuit 214 can directly sense the current through inductive element 202. Based on Isense and Vboost_out, feedback control circuit 214 controls the current across inductive element 202 by controlling the duty cycle of the PWM signal used to drive switch 206 (and switch 208).

[0037] As described herein, using hard current limiting on the inductor of a boost converter may result in inductor current modulation and voltage overshoot at peak load currents. For example, for a hard current limiter, a comparison may be made between the sensed inductor current (Isense) and a reference current. Isense may be driven by a resistive element to create a sense voltage (Vsns). Vsns may be compared to a reference voltage (Vref). When Vsns exceeds Vref, the high-side field effect transistor (FET) of the boost converter (e.g., switch 208) may be disconnected within the corresponding switching cycle. Once the high-side FET is disconnected, if Vref is reduced, the voltage loop may respond more slowly and the peak current may persist in the inductor, causing the output voltage of the boost converter to peak.

[0038] Certain aspects of the present disclosure generally relate to implementations of a soft current limiter that provides improved output power capability and inductor current stability for a wide range of boost output voltages compared to conventional implementations. As described in more detail herein, a voltage associated with a feedback path of a power supply circuit (e.g., a supply voltage or output voltage of an error amplifier (EA)) can be varied to limit peak inductor current, with the variation being proportional to the duty cycle and, thus, proportional to the inductor current ripple, as described in more detail herein.

[0039] Figure 3Detailed examples of implementations of an example power supply circuit 200 and a feedback control circuit 214 according to certain aspects of the present disclosure are illustrated. As illustrated, the feedback control circuit 214 includes an amplifier 302 (e.g., a transconductance (Gm) amplifier, also referred to herein as an "EA") coupled to a tap 307 of a voltage divider circuit 304. The voltage divider circuit 304 is used to reduce the voltage Vboost_out. Thus, the amplifier 302 can compare the voltage at the tap 307 with Vref and generate an output current. The output of the amplifier 302 can be coupled to an impedance 303 to convert the output current of the amplifier 302 into a voltage. In some aspects, the impedance 303 can be implemented using a resistive element Rc connected in series with a capacitive element Cc.

[0040] The feedback control circuit 214 may also include a comparator 306 configured to receive a signal representing Isense for comparison with the voltage at the output of the amplifier 302. For example, the current Isense may be converted to a current sense voltage (Vsns) via the current sense circuit 398. In certain aspects, a compensation ramp signal may be added to the current sense voltage for slope compensation and to stabilize the current loop feedback, such as by comparing the current sense voltage with respect to the current sense voltage. Figure 4 Described in more detail.

[0041] In certain aspects, the feedback control circuit 214 further includes a flip-flop 310 (e.g., a set-reset (SR) flip-flop) for controlling the switch 206 via the nls_drv signal. For example, the set (S) input of the flip-flop 310 can be coupled to the pulse generator circuit 314, and the reset (R) input of the flip-flop 310 can be coupled to the output of the comparator 306. The pulse generator circuit 314 can generate a pulse signal for driving the S input of the flip-flop 310. The pulse signal can have a periodic waveform with a duty cycle of approximately 1% to 2%. The flip-flop 310 can generate a PWM output signal whose duty cycle is controlled based on Isense and Vboost_out.

[0042] Figure 4 206 or the inductive element 202. In some cases, the fixed current source (Isns) may be used to set the current of an adjustable current source (Isns) coupled to a sense resistor (Rsns). fix ) can also be coupled to Rsns to set a nominal voltage (eg, bias voltage) at node 420, as illustrated. Rsns can be coupled to capacitive element 478 (also referred to herein as “C rmp ”), Crmp is used to generate the Figure 3 The slope voltage sensing signal (eg, Vsns) of the comparator 306 is sensed by the current source I fix and I sns The current flowing through Rsns may generate a voltage at node 420 .

[0043] Current source I rmp 470, 472 can be selectively coupled to C via switches 402, 404, respectively. rmp When the nls_drv signal is logic high, switches 402 and 404 are closed, and the C rmp When nls_drv is logic low, switch 406 is closed, and the C rmp Furthermore, when nls_drv is logic low, switches 408 and 410 may also be closed, so that I rmp Thus, Vsns can be a ramp signal whose peak value is proportional to the nls_drv signal and Isense. In some aspects, a buffer 480 can be coupled between node 420 and a node 409 between switches 408 and 410.

[0044] Certain aspects of the present disclosure provide techniques for setting the current limit of the power supply circuit 200. For example, referring back to Figure 3 The current limit circuit 312 may be used to set and / or adjust the voltage supply (referred to herein as “V gmamp_sup ”). The output current and voltage of amplifier 302 can be adjusted by changing V gmamp_sup is set to a specific voltage to limit. Therefore, by setting V gmamp_sup , the inductor current of the boost converter can be limited by limiting the duty cycle of the PWM signal used to drive the switch 206. In some implementations, the current limit circuit 312 can be configured to clamp the output voltage of the amplifier 302 (referred to herein as “V gmamp_max ”) (e.g. instead of setting V gmamp_sup ), as described in more detail herein.

[0045] The current limit circuit 312 can limit the peak current of the inductor element 202 to a predetermined value ILmax, which does not cause the inductor element to saturate. As described herein, Vsns represents the sensed inductor current. However, Vsns is implemented as a ramp voltage proportional to the duty cycle of the boost converter (e.g., generated via Iramp and switches 402, 404, as shown relative to Figure 4The duty cycle is a proportional signal that varies according to the input voltage (Vin) of the boost converter and the output voltage (Vboost_out) of the boost converter.

[0046] For a Class H boost converter, as Vin and Vout vary widely, if a fixed voltage clamp is used, the current limit may vary widely. In contrast, when tracking the duty cycle of the boost converter to set the current limit, the current limit can be set independently of variations in Vin and Vout. In certain aspects, current limit circuit 312 can limit the inductor current in a manner that tracks the duty cycle of the boost converter and is independent of Vin and Vout.

[0047] In some aspects, the current sensing circuit 398 can generate Vsns, which can be equal to the error voltage (Verr) at the output of the amplifier 302 and is proportional to (I sns +I fix )*R sns +V ramp Proportional, V ramp It is a cross-C rmp The current limiting circuit 312 can be implemented as a replica of the current sensing circuit 398, but with a tunable current source I sns Using a fixed current source I max Therefore, the current limiting circuit 312 can generate a clamping voltage (Vclamp) for Verr at the output of the clamping amplifier 302 for current limiting the inductor current, and the clamping voltage is related to (I max +I fix )*R sns +V ramp Thus, both Vsns (e.g., equal to Verr) and Vclamp track the duty cycle of the boost converter (e.g., due to V ramp parameters), the inductor current limit can be achieved in a manner independent of Vin and Vout.

[0048] Figure 5 3 shows an example implementation of a current limiting circuit 312 according to certain aspects of the present disclosure. The current limiting circuit 312 can be configured to clamp the supply voltage of the amplifier 302 in the feedback path of the power supply circuit 200. As described herein, the current sensing circuit 398 can be used to sense the current at the source of the switch 206 (e.g., when implemented as a transistor) and generate a sense voltage V at the positive input terminal of the comparator 306. sns In certain aspects of the present disclosure, a replica of current sensing circuit 398 may be used to implement current limiting circuit 312, as described. As illustrated, current limiting circuit 312 includes capacitive element 540 (e.g., having capacitance Cslope )(e.g., C of current sensing circuit 398 rmp replica) and provides current I ramp The current sources 542, 544 can be replicas of the current sources 470, 472 of the current sensing circuit 398. The current sources 542, 544 and the switches 552, 554 can form a charging circuit. The switches 552, 554 can be connected to the current sensing circuit 398 by the signal n used to control the switch 206. lsdrv To control, such as relative to Figure 3 In other words, the capacitor element 540 can be charged when the switches 552 and 554 are closed. Figure 2 In some aspects, the switch 590 can be coupled in parallel with the capacitive element 540 to selectively discharge the capacitive element 540 when closed. The switch 590 can be connected via n lsdrv_b signal (for example, complementary to the signal nlsdrv).

[0049] Figure 5 The current limiting circuit 312 also includes a current I max The current source 556 of the current Imax is configured to set the current limit for the current limit circuit 312. For example, I max It can be set according to the following equation:

[0050]

[0051] Where ILmax is the selected maximum current through the inductive element 202 , and SenseGain is the gain associated with sensing the current through the inductive element 202 (eg, the gain associated with generating Isense ).

[0052] Current I max The current can flow through the sense resistor element 522 (Rsns) to set the voltage at the node 598. The resistor element 522 can be a replica of the sense resistor element (Rsns) of the current sensing circuit 398. Thus, the switches 552, 554 and the current sources 542, 544 set the peak current to the duty cycle of the boost converter (e.g., the duty cycle of nls_drv) and I max The slope voltage V slope .

[0053] Capacitive elements C1 and C2 and switches 562 and 564 (eg, respectively, driven by signals n hsdrv_b and n hsdrvFor example, switch 562 can be closed (e.g., when switch 208 is open) to sample the voltage across capacitor element 540 onto capacitor element C1. Subsequently, switch 564 can be closed, and switch 562 can be opened, transferring charge from capacitor element C1 to capacitor element C2 to generate a sample-and-hold reference voltage (V ref_sah ). For example, as illustrated by 580, if V slope As the peak voltage increases from one charge cycle to the next, the new peak voltage is sampled, and V ref_sah increases to a new peak voltage. As shown, V ref_sah can be provided to the positive input terminal of amplifier 506. In certain aspects, the sampling time (t samp ) can be set to be sufficient to transfer the entire charge from C1 to C2 but much less than the maximum duty cycle off-time of the boost converter.

[0054] As shown in the figure, Figure 5 The current limiting circuit 312 can be implemented with an active clamp circuit 502 having an amplifier 506 and a p-type metal oxide semiconductor (PMOS) transistor 504. The active clamp circuit 502 is configured to clamp the power supply voltage (V gmamp_sup ) to limit the inductor current of the boost converter. For example, the output of amplifier 506 can be coupled to the gate of PMOS transistor 504 to achieve setting V gmamp_sup That is, the source of the PMOS transistor 504 can be coupled to a voltage rail (e.g., battery voltage VBAT), and the drain of the PMOS transistor 504 can be coupled to the negative input terminal of the amplifier 506 and the resistive element 530. As illustrated, the resistive element 530 is coupled between the transistor 504 and electrical ground (e.g., a reference potential node). As illustrated by 582, if V slope The peak voltage increases from one charging cycle to the next, then V gmamp_sup Increase to the new peak voltage.

[0055] Figure 6 302 is configured to clamp the voltage at the output of amplifier 302. As shown, the negative input terminal of amplifier 506 can be coupled to the output of amplifier 302, and the output of amplifier 506 is coupled to the gate of PMOS transistor 504. Therefore, as long as the voltage at the output of amplifier 302 is below V ref_sah , the PMOS transistor 504 is turned off. However, if the voltage (Verr) at the output of the amplifier 302 is higher than V ref_sah, then PMOS transistor 504 will begin to conduct, thereby pulling down the voltage at the output of amplifier 302, effectively limiting the inductor current of the boost converter. As illustrated by 582, if V slope The peak voltage increases from one charging cycle to the next, then V gmamp_sup Increase to the new peak voltage.

[0056] As described herein, current limit circuit 312 replicates the configuration of current sense circuit 398, but instead of receiving a sense current, it receives a current sensed by I max The current limiting circuit 312 can set V ref_sah Set equal to IL_max / SenseGain+I ramp / C slope *t_on, where t_on is the on-time of switch 206. Therefore, the error amplifier clamping level (e.g., based on V ref_sah setting) can be independent of t_on (eg, the duty cycle of the boost converter) because Vsns (eg, generated via a current sense path with current sense circuit 398) and V ref_sah (eg, generated via a current limiting path with current limiting circuit 312) depends on t_on, resulting in the effect of t_on on the error amplifier clamping level being canceled (or at least reduced). In other words, the error amplifier clamping level may depend only on the selected IL_max parameter.

[0057] Example Power Supply Circuit

[0058] Certain aspects of the present disclosure relate to a power supply circuit (e.g., power supply circuit 200). The power supply circuit generally includes a switched-mode power supply (SMPS) (e.g., a boost converter) having an inductive element (e.g., inductive element 202) and a first switch (e.g., switch 206) coupled to the inductive element. The power supply circuit may also include a feedback path (e.g., feedback path 213) coupled between an output of the SMPS and a control input of the first switch. In some aspects, the power supply circuit may include a current limiting circuit (e.g., current limiting circuit 312) having a first capacitive element (e.g., Cslope), a charging circuit (e.g., current sources 542, 544 and switches 552, 554) coupled to the first capacitive element. In some aspects, the charging circuit may be configured to charge the first capacitive element when the first switch is closed. The current limiting circuit may also include a first current source (e.g., current source 556), a first resistive element (e.g., resistive element 522) coupled to the first current source, and the first capacitive element coupled to a node (e.g., node 598) between the first resistive element and the first current source. In some aspects, the first current source can be configured to set a limit on the current flowing through the inductive element. The current limit circuit can also include a sample-and-hold circuit coupled to the first capacitive element and a clamp circuit (e.g., clamp circuit 502) coupled between the sample-and-hold circuit and the feedback path.

[0059] In some aspects, the power supply circuit may further include a current sensing circuit (eg, current sensing circuit 398) configured to sense a current across a second resistive element (eg, Figure 4 Rsns) provides the sense current (e.g. Figure 4 The sense current indicates the current passing through the inductive element. The first resistive element may be a replica of the second resistive element.

[0060] In some aspects, the sample-and-hold circuit may include a second capacitive element (e.g. Figures 5 to 6 A capacitive element C1, a second switch (eg, switch 562) coupled between the first capacitive element and the second capacitive element, a third capacitive element (eg, Figures 5 to 6 In some aspects, when the second switch is closed, the second capacitive element is coupled in parallel with the first capacitive element.

[0061] In some aspects, the clamp circuit can include an amplifier; and a transistor (e.g., transistor 504) having a gate coupled to the output of the amplifier, the drain of the transistor coupled to the feedback path. In some aspects, the feedback path can include an error amplifier (e.g., amplifier 302) coupled between the output of the SMPS and the control input of the first switch, and the source of the transistor can be coupled to the output of the error amplifier. In this case, the positive input terminal of the amplifier can be coupled to the sample-and-hold circuit, and the negative input terminal of the amplifier can be coupled to the source of the transistor.

[0062] In some aspects, the feedback path can include an error amplifier coupled between the output of the SMPS and the control input of the first switch, and the drain of the transistor can be coupled to a power supply node of the error amplifier. In this case, the positive input terminal of the amplifier can be coupled to the sample-and-hold circuit, and the negative input terminal of the amplifier can be coupled to the drain of the transistor.

[0063] In some aspects, the clamp circuit can be configured to set a voltage associated with the feedback path based on a voltage at the output of the sample-and-hold circuit. Figure 6 As described, the feedback path may include an error amplifier coupled between the output of the SMPS and the control input of the first switch, and the voltage associated with the feedback path may include the output voltage of the error amplifier. Figure 5 As described, the feedback path may include an error amplifier coupled between the output of the SMPS and the control input of the first switch, and the voltage associated with the feedback path may include a supply voltage of the error amplifier.

[0064] In some aspects, the charging circuit can include a second current source (e.g., current source 542) and a second switch (e.g., switch 552) coupled between the second current source and the first capacitive element. The second switch can be configured to close when the first switch (e.g., switch 206) is closed. The current limiting circuit can also include a third switch (e.g., switch 590) coupled in parallel with the first capacitive element, wherein the second switch is configured to open when the third switch is closed.

[0065] In some aspects, the power supply circuit can include a current sensing circuit (eg, current sensing circuit 398) configured to sense current across the inductive element. The current limiting circuit can replicate the configuration of one or more components of the current sensing circuit.

[0066] Example Techniques for Voltage Regulation

[0067] Figure 7is a flow diagram illustrating example operations 700 for voltage regulation in accordance with certain aspects of the present disclosure. Operations 700 may be performed by power supply circuit 200, for example.

[0068] Operations 700 begin in block 705, where the power supply circuit 200 generates an output voltage at an output of a switch mode power supply (SMPS) via the SMPS. The SMPS may include an inductive element (e.g., inductive element 202) and a first switch (e.g., switch 206) coupled to the inductive element, with a feedback path coupled between the output of the SMPS and a control input of the first switch. In block 710, the power supply circuit 200 may limit a current across the inductive element via a current limiting circuit (e.g., current limiting circuit 312). For example, limiting the current may include: in block 710a, charging a first capacitive element (e.g., capacitive element 540); in block 710b, providing a current (e.g., with respect to a first resistive element (e.g., resistive element 522)). Figures 5 to 6 Described I max ), the first capacitive element is coupled to a node between the first resistive element and the first current source (e.g., node 598). Limiting the current may also include: in block 710c, sampling a voltage across the first capacitive element; and in block 710d, limiting a voltage associated with the feedback path based on the sampled voltage.

[0069] In some aspects, charging the first capacitive element may include charging the first capacitive element when the first switch is closed. Operation 700 may also include discharging the first capacitive element (eg, via switch 590) when the first switch is open.

[0070] In some aspects, operation 700 may further include performing a step of switching across a second resistive element (e.g., relative to Figure 4 Description of the resistance element R sns ) provides a sense current (e.g. relative to Figure 4 Described I sns ), the sensed current indicates the current across the inductive element. In some aspects, the first resistive element can be a replica of the second resistive element. In some aspects, limiting the current across the inductive element can also include setting the current to be provided across the first resistive element (e.g., relative to Figures 5 to 6 Described I max ) to limit the current across the inductive element.

[0071] In some aspects, sampling the voltage across the first capacitive element may include sampling the second capacitive element (e.g., relative to the first capacitive element) based on the voltage across the first capacitive element. Figures 5 to 6 The capacitive element C1 described above is charged, and after charging the second capacitive element, the charge across the second capacitive element is transferred to the third capacitive element (e.g., relative to the Figures 5 to 6The sampled voltage is the voltage across the third capacitive element after the charge transfer.

[0072] In some aspects, the feedback path can include an error amplifier (e.g., amplifier 302) coupled between the output of the SMPS and the control input of the first switch. In this case, limiting the voltage associated with the feedback path can include limiting a supply voltage of the error amplifier. In some cases, limiting the voltage associated with the feedback path can include limiting an output voltage of the error amplifier.

[0073] The various operations of the above methods may be performed by any suitable component capable of performing the corresponding functions. The component may include (a plurality of) various hardware and / or software components and / or (a plurality of) modules, including but not limited to circuits, application specific integrated circuits (ASICs), or processors. Generally, where there are operations illustrated in the accompanying drawings, these operations may have corresponding corresponding parts-plus-function components, which have similar numbering.

[0074] For example, the means for limiting current may include a current limiting circuit, such as current limiting circuit 312. The means for charging and the means for supplying power may include a current source, such as current source 542, current source 544, or current source 556. The means for sampling may include a capacitive element (such as Figure 5 and 6 , C1, C2) and switches (such as switches 562, 564). In some aspects, the means for limiting the voltage may include an amplifier such as amplifier 506 or a transistor such as transistor 504. In some aspects, the means for charging the capacitive element may include a switch such as switch 562. In some aspects, the means for transferring the charge may include a switch such as switch 564.

[0075] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" may include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Furthermore, "determine" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Furthermore, "determine" may include resolving, selecting, choosing, establishing, etc.

[0076] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. As an example, "at least one of the following: a, b, or c" is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiples of the same item (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0077] The various illustrative logical blocks, modules, and circuits described in conjunction with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0078] The method disclosed herein includes one or more steps or actions for implementing the described method. Without departing from the scope of the claims, the method steps and / or actions can be interchangeable with each other. In other words, unless the specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0079] The described techniques can be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may include a processing system in a wireless node. The processing system may be implemented using a bus architecture. Depending on the specific application and overall design constraints of the processing system, the bus may include any number of interconnecting buses and bridges. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, etc., to the processing system via the bus. The network adapter may be used to implement signal processing functions at the physical (PHY) layer. In the case of a user terminal, a user interface (e.g., a keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits, such as timing sources, peripherals, voltage regulators, power management circuits, etc., which are well known in the art and will not be described further.

[0080] The processing system can be configured as a general-purpose processing system with one or more microprocessors providing processor functionality and external memory providing at least a portion of a machine-readable medium, all linked together with other supporting circuitry via an external bus architecture. Alternatively, the processing system can be implemented with an ASIC having a processor, a bus interface, a user interface in the case of an access terminal, support circuitry, and at least a portion of a machine-readable medium integrated into a single chip, or with one or more FPGAs, PLDs, controllers, state machines, gating logic, discrete hardware components, or any other suitable circuitry or any combination of circuits that can perform the various functionalities described throughout this disclosure. Those skilled in the art will recognize how to best implement the described functionality of the processing system depending on the specific application and the overall design constraints imposed on the entire system.

[0081] Example aspects

[0082] Aspect 1. A power supply circuit comprising: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limiting circuit comprising: a first capacitive element; a charging circuit coupled to the first capacitive element; a first current source; a first resistive element coupled to the first current source, the first capacitive element coupled to a node between the first resistive element and the first current source; a sample-and-hold circuit coupled to the first capacitive element; and a clamping circuit coupled between the sample-and-hold circuit and the feedback path.

[0083] Aspect 2. The power supply circuit according to aspect 1, wherein the charging circuit is configured to charge the first capacitive element when the first switch is closed.

[0084] Aspect 3. The power supply circuit according to one of aspects 1 to 2 further includes a current sensing circuit configured to provide a sense current across the second resistive element, the sense current indicating a current through the inductive element, wherein the first resistive element is a replica of the second resistive element.

[0085] Aspect 4. The power supply circuit according to one of aspects 1 to 3, wherein the first current source is configured to set a limit on a current flowing through the inductive element.

[0086] Aspect 5. A power supply circuit according to one of Aspects 1 to 4, wherein the sample-and-hold circuit includes: a second capacitive element; a second switch coupled between the first capacitive element and the second capacitive element; a third capacitive element coupled to the clamping circuit; and a third switch coupled between the second capacitive element and the third capacitive element.

[0087] Aspect 6. The power supply circuit according to aspect 5, wherein when the second switch is closed, the second capacitive element is coupled in parallel with the first capacitive element.

[0088] Aspect 7. The power supply circuit according to one of aspects 1 to 6, wherein the clamp circuit comprises: an amplifier; and a transistor having a gate coupled to an output of the amplifier, a drain of the transistor coupled to the feedback path.

[0089] Aspect 8. The power supply circuit of aspect 7, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the source of the transistor is coupled to the output of the error amplifier.

[0090] Aspect 9. The power supply circuit according to aspect 8, wherein the positive input terminal of the amplifier is coupled to the sample-and-hold circuit, and wherein the negative input terminal of the amplifier is coupled to the source of the transistor.

[0091] Aspect 10. The power supply circuit of one of aspects 7 to 9, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the drain of the transistor is coupled to a power supply node of the error amplifier.

[0092] Aspect 11. The power supply circuit according to aspect 10, wherein the positive input terminal of the amplifier is coupled to the sample-and-hold circuit, and wherein the negative input terminal of the amplifier is coupled to the drain of the transistor.

[0093] Aspect 12. The power supply circuit according to one of aspects 1 to 11, wherein the clamp circuit is configured to set a voltage associated with the feedback path based on a voltage at the output of the sample-and-hold circuit.

[0094] Aspect 13. The power supply circuit of aspect 12, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the voltage associated with the feedback path comprises an output voltage of the error amplifier.

[0095] Aspect 14. The power supply circuit of one of aspects 12 to 13, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the voltage associated with the feedback path comprises a supply voltage of the error amplifier.

[0096] Aspect 15. The power supply circuit according to one of aspects 1 to 14, wherein the clamping circuit comprises: a second current source; and a second switch coupled between the second current source and the first capacitive element.

[0097] Aspect 16. The power circuit according to aspect 15, wherein the second switch is configured to be closed when the first switch is closed.

[0098] Aspect 17. The power supply circuit according to one of aspects 15 to 16, wherein the current limiting circuit further comprises a third switch coupled in parallel with the first capacitive element, and wherein the second switch is configured to be open when the third switch is closed.

[0099] Aspect 18. The power supply circuit according to one of aspects 1 to 17, further comprising a current sensing circuit configured to sense current through the inductive element, wherein the current limiting circuit replicates the configuration of one or more components of the current sensing circuit.

[0100] Aspect 19. A method for voltage regulation, comprising: generating an output voltage at an output of a switched mode power supply (SMPS) via the SMPS, wherein the SMPS includes an inductive element and a first switch coupled to the inductive element, and a feedback path coupled between the output of the SMPS and a control input of the first switch; and limiting a current through the inductive element via a current limiting circuit, wherein limiting the current comprises: charging a first capacitive element; providing a current across a first resistive element via a first current source, the first capacitive element coupled to a node between the first resistive element and the first current source; sampling a voltage across the first capacitive element; and limiting a voltage associated with the feedback path based on the sampled voltage.

[0101] Aspect 20. The method of aspect 19, wherein charging the first capacitive element comprises charging the first capacitive element when the first switch is closed.

[0102] Aspect 21. The method according to aspect 20, further comprising: discharging the first capacitive element when the first switch is turned off.

[0103] Aspect 22. The method of one of aspects 19 to 21, further comprising providing a sense current across the second resistive element, the sense current being indicative of current through the inductive element, wherein the first resistive element is a replica of the second resistive element.

[0104] Aspect 23. The method according to one of aspects 19 to 22, wherein limiting the current through the inductive element further comprises: setting a current to be provided across the first resistive element to limit the current through the inductive element.

[0105] Aspect 24. A method according to one of Aspects 19 to 23, wherein sampling the voltage across the first capacitive element includes: charging the second capacitive element based on the voltage across the first capacitive element; and after the charging of the second capacitive element, transferring the charge across the second capacitive element to a third capacitive element, the sampled voltage being the voltage across the third capacitive element after the transfer of the charge.

[0106] Aspect 25. The method of one of aspects 19 to 24, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein limiting the voltage associated with the feedback path comprises limiting a supply voltage of the error amplifier.

[0107] Aspect 26. The method of one of aspects 19 to 25, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein limiting the voltage associated with the feedback path comprises limiting the output voltage of the error amplifier.

[0108] Aspect 27. An apparatus for voltage regulation, comprising: a switched mode power supply (SMPS) configured to generate an output voltage at an output of the SMPS, wherein the SMPS includes an inductive element and a first switch coupled to the inductive element, a feedback path coupled between the output of the SMPS and a control input of the first switch; and means for limiting current through the inductive element, wherein the means for limiting current includes: means for charging a first capacitive element; means for providing current across a first resistive element, the first capacitive element coupled to a node between the first resistive element and the means for supplying power; means for sampling a voltage across the first capacitive element; and means for limiting a voltage associated with the feedback path based on the sampled voltage.

[0109] Aspect 28. The apparatus of aspect 27, wherein the means for charging the first capacitive element comprises means for charging the first capacitive element when the first switch is closed.

[0110] Aspect 29. The apparatus of one of aspects 27 to 28, further comprising means for providing a sense current across the second resistive element, the sense current being indicative of current through the inductive element, wherein the first resistive element is a replica of the second resistive element.

[0111] Aspect 30. An apparatus according to one of Aspects 27 to 29, wherein the component for sampling the voltage across the first capacitive element includes: a component for charging the second capacitive element based on the voltage across the first capacitive element; and a component for transferring the charge across the second capacitive element to a third capacitive element after the charging of the second capacitive element, the sampled voltage being the voltage across the third capacitive element after the transfer of the charge.

[0112] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described herein without departing from the scope of the claims.

Claims

1. A power supply circuit comprising: a switch mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; as well as Current limiting circuit, including: a first capacitive element; a charging circuit coupled to the first capacitive element; a first current source; a first resistive element coupled to the first current source, the first capacitive element coupled to a node between the first resistive element and the first current source; a sample-and-hold circuit coupled to the first capacitive element; and A clamping circuit is coupled between the sample-and-hold circuit and the feedback path. 2 . The power supply circuit according to claim 1 , wherein the charging circuit is configured to charge the first capacitive element when the first switch is closed.

3. The power supply circuit of claim 1 , further comprising a current sensing circuit configured to provide a sense current across a second resistive element, the sense current being indicative of a current through the inductive element, wherein the first resistive element is a replica of the second resistive element. 4 . The power supply circuit of claim 1 , wherein the first current source is configured to set a limit on a current flowing through the inductive element.

5. The power supply circuit according to claim 1 , wherein the sample-and-hold circuit comprises: a second capacitive element; a second switch coupled between the first capacitive element and the second capacitive element; a third capacitive element coupled to the clamping circuit; as well as A third switch is coupled between the second capacitive element and the third capacitive element. 6 . The power supply circuit of claim 5 , wherein when the second switch is closed, the second capacitive element is coupled in parallel with the first capacitive element.

7. The power supply circuit according to claim 1 , wherein the clamping circuit comprises: First amplifier; as well as A transistor has a gate coupled to the output of the first amplifier, a drain of the transistor coupled to the feedback path.

8. The power supply circuit of claim 7, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the source of the transistor is coupled to the output of the error amplifier. 9 . The power supply circuit of claim 8 , wherein a positive input terminal of the first amplifier is coupled to the sample-and-hold circuit, and wherein a negative input terminal of the first amplifier is coupled to the source of the transistor.

10. The power supply circuit of claim 7, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the drain of the transistor is coupled to a power supply node of the error amplifier. 11 . The power supply circuit of claim 10 , wherein a positive input terminal of the first amplifier is coupled to the sample-and-hold circuit, and wherein a negative input terminal of the first amplifier is coupled to the drain of the transistor. 12 . The power supply circuit of claim 1 , wherein the clamp circuit is configured to set a voltage associated with the feedback path based on a voltage at an output of the sample-and-hold circuit.

13. The power supply circuit of claim 12 , wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the voltage associated with the feedback path comprises an output voltage of the error amplifier.

14. The power supply circuit of claim 12, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein the voltage associated with the feedback path comprises a supply voltage of the error amplifier.

15. The power supply circuit according to claim 1, wherein the charging circuit comprises: a second current source; as well as A second switch is coupled between the second current source and the first capacitive element. 16 . The power supply circuit of claim 15 , wherein the second switch is configured to be closed when the first switch is closed. 17 . The power supply circuit of claim 15 , wherein the current limiting circuit further comprises a third switch coupled in parallel with the first capacitive element, and wherein the second switch is configured to open when the third switch is closed.

18. The power circuit of claim 1, further comprising a current sensing circuit configured to sense current through the inductive element, wherein the current limiting circuit replicates a configuration of one or more components of the current sensing circuit.

19. A method for voltage regulation, comprising: generating an output voltage at an output of a switch mode power supply (SMPS), wherein the SMPS comprises an inductive element and a first switch coupled to the inductive element, a feedback path coupled between the output of the SMPS and a control input of the first switch; as well as limiting a current through the inductive element via a current limiting circuit, wherein limiting the current comprises: charging the first capacitive element; providing a current across a first resistive element via a first current source, the first capacitive element being coupled to a node between the first resistive element and the first current source; sampling a voltage across the first capacitive element; and A voltage associated with the feedback path is limited based on the sampled voltage.

20. The method of claim 19, wherein the charging of the first capacitive element comprises: When the first switch is closed, the first capacitive element is charged.

21. The method according to claim 20, further comprising: When the first switch is turned off, the first capacitive element is discharged.

22. The method of claim 19, further comprising providing a sense current across a second resistive element, the sense current being indicative of current through the inductive element, wherein the first resistive element is a replica of the second resistive element.

23. The method of claim 19, wherein limiting the current through the inductive element further comprises: The current to be provided across the first resistive element is set to limit the current through the inductive element.

24. The method of claim 19, wherein the sampling of the voltage across the first capacitive element comprises: charging a second capacitive element based on the voltage across the first capacitive element; as well as After the charging of the second capacitive element, the charge across the second capacitive element is transferred to a third capacitive element, the sampled voltage being the voltage across the third capacitive element after the transfer of the charge.

25. The method of claim 19, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein limiting the voltage associated with the feedback path comprises limiting a supply voltage of the error amplifier.

26. The method of claim 19, wherein the feedback path comprises an error amplifier coupled between the output of the SMPS and the control input of the first switch, and wherein limiting the voltage associated with the feedback path comprises limiting an output voltage of the error amplifier.

27. A device for voltage regulation, comprising: a switched mode power supply (SMPS) configured to generate an output voltage at an output of the SMPS, wherein the SMPS comprises an inductive element and a first switch coupled to the inductive element, a feedback path coupled between the output of the SMPS and a control input of the first switch; as well as means for limiting a current through the inductive element, wherein the means for limiting the current comprises: means for charging the first capacitive element; means for providing current across a first resistive element, the first capacitive element being coupled to a node between the first resistive element and the means for providing power; means for sampling a voltage across said first capacitive element; and Means for limiting a voltage associated with the feedback path based on the sampled voltage.

28. The apparatus of claim 27, wherein the means for charging the first capacitive element comprises means for charging the first capacitive element when the first switch is closed.

29. The apparatus of claim 27, further comprising means for providing a sense current across a second resistive element, the sense current being indicative of current through the inductive element, wherein the first resistive element is a replica of the second resistive element.

30. The apparatus of claim 27, wherein the means for sampling the voltage across the first capacitive element comprises: means for charging a second capacitive element based on the voltage across the first capacitive element; as well as means for transferring charge across the second capacitive element to a third capacitive element subsequent to the charging of the second capacitive element, the sampled voltage being the voltage across the third capacitive element subsequent to the transfer of the charge.

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