Characterization structure and method for superconducting digital circuit inductance

Abstract

The application provides a superconducting digital circuit inductance characterization structure and method, which comprises the following steps: a first superconducting film is connected between a first electrode layer of a first Josephson junction and a second superconducting film; a third superconducting film is connected between the second superconducting film and a first electrode layer of a second Josephson junction; a second electrode layer of the first Josephson junction and the second Josephson junction is grounded; a first electrode is connected to the first electrode layer of the first Josephson junction; a second electrode is connected to the first electrode layer of the second Josephson junction; a third electrode is connected between a first end and a second end of the first superconducting film; a first end of a fourth electrode is connected between a first end and a second end of the second superconducting film; and a fifth electrode is connected between a first end and a second end of the third superconducting film. The application obtains the values of different superconducting film inductances in one inductance characterization structure, simplifies the structure, and improves the efficiency and precision of inductance measurement in a superconducting digital circuit.

Description

Technical Field

[0001] This invention relates to the field of superconducting technology, and in particular to a characterization structure and method for inductors in superconducting digital circuits. Background Technology

[0002] Superconducting digital circuits based on single-flux quantum (SFQ) circuits are characterized by high frequency and low power consumption, representing an important area of ​​development in high-frequency digital circuits. Superconducting digital circuits are constructed based on the Josephson effect and flux quantization. In superconducting digital circuits, the structure corresponding to the Josephson effect is the Josephson junction, which acts as a switch in the circuit; the structure corresponding to flux quantization is mainly inductor elements composed of superconducting thin films, which play roles in signal storage and transmission. Therefore, Josephson junctions and superconducting thin-film inductors are the main structures of superconducting digital circuits, and their parameters are closely related to the performance of the superconducting digital circuits.

[0003] Superconducting digital circuits are multilayer thin-film structures fabricated using microfabrication processes. The fabrication process involves multiple steps, typically each comprising unit processes such as thin-film growth, photolithography, and etching. Within each unit process, depending on its characteristics, further details are required, including cleaning, material selection and proportioning, and process parameter adjustment and optimization. Therefore, the fabrication process of superconducting digital circuits is complex, with numerous process parameters. During fabrication, the quality of each step must be monitored to ensure the fabrication process meets circuit design requirements. Process monitoring is achieved through process control monitor (PCM) graphics. The PCM graphics of superconducting digital circuits need to monitor important parameters such as Josephson junctions, inductors, resistors, insulating layers, photolithography, and etching processes. As a key structure in superconducting digital circuits, the monitoring of inductor parameters is a crucial aspect of PCM monitoring.

[0004] Therefore, optimizing inductance characterization patterns and improving measurement efficiency has become one of the urgent problems to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a characterization structure and method for superconducting digital circuit inductors, so as to solve the problem of low efficiency in inductor characterization pattern measurement in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a characterization structure for a superconducting digital circuit inductor, wherein the characterization structure for the superconducting digital circuit inductor includes at least:

[0007] First superconducting thin film, second superconducting thin film, third superconducting thin film, first Josephson junction, second Josephson junction, first electrode, second electrode, third electrode, fourth electrode and fifth electrode;

[0008] The first end of the first superconducting thin film is connected to the first electrode layer of the first Josephson junction, and the second end is connected to the first end of the second superconducting thin film; the second end of the second superconducting thin film is connected to the first end of the third superconducting thin film; the second end of the third superconducting thin film is connected to the first electrode layer of the second Josephson junction; the first Josephson junction and the second electrode layer of the second Josephson junction are grounded;

[0009] The first end of the first electrode is connected to the first electrode layer of the first Josephson junction, and the second end is led out.

[0010] The first end of the second electrode is connected to the first electrode layer of the second Josephson junction, and the second end is led out.

[0011] The first end of the third electrode is connected between the first end and the second end of the first superconducting thin film, and the second end is led out.

[0012] The first end of the fourth electrode is connected between the first and second ends of the second superconducting thin film, and the second end is led out.

[0013] The first end of the fifth electrode is connected between the first and second ends of the third superconducting thin film, and the second end is led out.

[0014] The first superconducting thin film and the third superconducting thin film are located in the first layer, and the second superconducting thin film is located in the second layer.

[0015] Optionally, the first superconducting thin film and the third superconducting thin film are located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, and the second superconducting thin film is located in the wiring layer of the superconducting digital circuit connected to the top electrode of the Josephson junction; the first electrode layer of the first Josephson junction and the second Josephson junction is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, and the second electrode layer is located in the top electrode layer of the Josephson junction in the superconducting digital circuit.

[0016] Optionally, the first superconducting thin film and the third superconducting thin film are located in the wiring layer of the superconducting digital circuit connected to the top electrode of the Josephson junction, and the second superconducting thin film is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit; the first electrode layers of the first Josephson junction and the second Josephson junction are located in the top electrode layer of the Josephson junction in the superconducting digital circuit, and the second electrode layer is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit.

[0017] Optionally, the length between the first end of the third electrode and the second end of the first superconducting thin film is equal to the length between the first end of the third superconducting thin film and the first end of the fifth electrode.

[0018] Optionally, the length between the second end of the first superconducting thin film and the first end of the fourth electrode is equal to the length between the first end of the fourth electrode and the second end of the second superconducting thin film.

[0019] Alternatively, the characterization structure of the superconducting digital circuit inductor further includes a sixth electrode; the first end of the sixth electrode is connected between the first end of the fifth electrode and the second end of the third superconducting thin film, and the second end is led out.

[0020] To achieve the above and other related objectives, the present invention also provides a method for characterizing superconducting digital circuit inductors. Based on the characterization structure of the superconducting digital circuit inductor described above, the method for characterizing the superconducting digital circuit inductor includes at least the following:

[0021] A bias current is applied, which flows into one of the first and second electrodes and flows out from the ground terminal; a first current is applied, which flows into the third electrode and flows out from the fourth electrode; a second current is applied, which flows into the fifth electrode and flows out from the fourth electrode; wherein the first current is equal to the second current;

[0022] The voltage is read from the other electrode among the first electrode and the second electrode to obtain the first magnetic flux of the characterizing structure of the superconducting digital circuit inductance, and the inductance per unit length of the superconducting thin film in the layer where the second superconducting thin film is located is calculated based on the first magnetic flux, the first current and the second current.

[0023] Optionally, the first magnetic flux satisfies:

[0024] Φ1=(L1+L2-L3-L4)*I control1 ;

[0025] Wherein, Φ1 is the first magnetic flux, L1 is the inductance between the first end of the third electrode and the second end of the first superconducting thin film, L2 is the inductance between the second end of the first superconducting thin film and the first end of the fourth electrode, L3 is the inductance between the first end of the fourth electrode and the second end of the second superconducting thin film, L4 is the inductance between the first end of the third superconducting thin film and the first end of the fifth electrode, and I control1 The values ​​are the first current and the second current.

[0026] Alternatively, let l1 = l4, then L1 = L4. In this case, the inductance per unit length of the superconducting thin film in the layer containing the second superconducting thin film satisfies:

[0027] L UI1 =(L2-L3) / (l2-l3)=Φ1 / [(l2-l3)*I control1 ];

[0028] Wherein, LUI1 is the inductance per unit length of the superconducting thin film in the layer where the second superconducting thin film is located, l1 is the length between the first end of the third electrode and the second end of the first superconducting thin film, l2 is the length between the second end of the first superconducting thin film and the first end of the fourth electrode, l3 is the length between the first end of the fourth electrode and the second end of the second superconducting thin film, and l4 is the length between the first end of the third superconducting thin film and the first end of the fifth electrode.

[0029] Optionally, a bias current is applied, which flows in from one of the first and second electrodes and flows out from the ground terminal;

[0030] A third current is applied, flowing into the third electrode and out of the fifth electrode; the voltage is read from the other electrode among the first and second electrodes to obtain the second magnetic flux characterizing the inductor structure of the superconducting digital circuit.

[0031] A fourth current is applied, which flows into the third electrode and out of the sixth electrode; the voltage is read from the other electrode among the first and second electrodes to obtain the third magnetic flux characterizing the inductor structure of the superconducting digital circuit.

[0032] Calculate the inductance per unit length of the superconducting thin film in the layer containing the first and third superconducting thin films based on the second magnetic flux, the third magnetic flux, the third current, and the fourth current;

[0033] The first end of the sixth electrode is connected between the first end of the third electrode and the second end of the third superconducting thin film, and the second end is led out.

[0034] Alternatively, the second magnetic flux and the third magnetic flux respectively satisfy:

[0035] Φ2=(L1+L2+L3+L4)*I control3 ;

[0036] Φ3=(L1+L2+L3+L4+L5)*I control4 ;

[0037] Wherein, Φ2 is the second magnetic flux, Φ3 is the third magnetic flux, L1 is the inductance between the first end of the third electrode and the second end of the first superconducting thin film, L2 is the inductance between the second end of the first superconducting thin film and the first end of the fourth electrode, L3 is the inductance between the first end of the fourth electrode and the second end of the second superconducting thin film, L4 is the inductance between the first end of the third superconducting thin film and the first end of the fifth electrode, and L5 is the inductance between the first end of the fifth electrode and the second end of the third superconducting thin film. control3 I is the value of the third current. control4 The value of the fourth current.

[0038] Alternatively, the inductance per unit length of the superconducting thin film in the layer containing the first and third superconducting thin films satisfies:

[0039] L UI2 =L5 / l5=(Φ2 / I control3 -Φ3 / I control4 ) / l5;

[0040] Among them, L UI2 l1 is the inductance per unit length of the superconducting thin film in the layer containing the first and third superconducting thin films, and l5 is the length between the first end of the fifth electrode and the second end of the third superconducting thin film.

[0041] As described above, the characterization structure and method for superconducting digital circuit inductors of the present invention have the following beneficial effects:

[0042] The present invention provides a characterization structure and method for inductors in superconducting digital circuits. This structure allows for the acquisition of numerical values ​​for inductors of different superconducting thin films within a single inductor characterization structure, simplifying the structure and improving the efficiency and accuracy of inductor measurement in superconducting digital circuits. Attached Figure Description

[0043] Figure 1 The diagram shows a structural representation of inductance.

[0044] Figure 2 A schematic diagram of the electrode setup is shown as an inductance characterization pattern.

[0045] Figure 3 The diagram shown is a schematic representation of the superconducting digital circuit inductor of the present invention.

[0046] Figure 4 The diagram shows a schematic of the structure of the NbN / TaN / NbN trilayer film prepared on the substrate according to the present invention.

[0047] Figure 5 The diagram shown is a schematic representation of the structure of the junction region formed in this invention.

[0048] Figure 6 The diagram shows the structure of the bottom electrode, the first superconducting thin film, and the third superconducting thin film formed according to the present invention.

[0049] Figure 7 The diagram shown is a schematic representation of the structure of the first insulating material layer grown according to the present invention.

[0050] Figure 8 The diagram shown is a schematic diagram of the pre-etching structure of the junction region in this invention.

[0051] Figure 9 The diagram shown is a schematic diagram of the pre-etched bottom electrode structure of the present invention.

[0052] Figure 10 The diagram shown is a schematic representation of the planarization process of this invention.

[0053] Figure 11 The diagram shows a schematic of the structure in which a through hole is formed in the first insulating material layer according to the present invention.

[0054] Figure 12 The diagram shown is a structural schematic of the second superconducting thin film and wiring of the present invention.

[0055] Figure 13 The diagram shown is a schematic diagram of the structure for growing the second insulating material layer according to the present invention.

[0056] Figure 14 The diagram shows a schematic of the structure in which a through hole is formed in the second insulating material layer according to the present invention.

[0057] Figure 15 The diagram shows a schematic representation of the characterization structure of the grounding layer grown in this invention to form an inductor in a superconducting digital circuit.

[0058] Component designation explanation

[0059] 10 base

[0060] 11a, 11b First and second superconducting films

[0061] 12 Barrier Layers

[0062] 13 Grounding layer

[0063] 2 Characterization structure of inductors in superconducting digital circuits

[0064] 21, 22, 23 First, Second, and Third Superconducting Thin Films

[0065] 24, 25 First and Second Josephson Knots

[0066] Electrodes 26a, 26b, 26c, 26d, 26e, 26f (First, Second, Third, Fourth, Fifth, and Sixth Electrodes)

[0067] 27 Grounding layer

[0068] 3 Substrate

[0069] 4 First superconducting film layer

[0070] 5. Barrier layer

[0071] 6 Second superconducting film layer

[0072] 7 First insulating material layer

[0073] 8. Wiring layer

[0074] 9 Second insulating material layer Detailed Implementation

[0075] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0076] Please see Figures 1-15 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0077] In superconducting digital circuits, inductance is fabricated using superconducting thin films, and its value is on the order of pH. The inductance value is typically measured using voltage-flux modulation technology with SQUID devices. A SQUID device is a superconducting electronic device composed of two Josephson structures inserted into a superconducting ring. When its bias current exceeds the device's critical current, the output voltage of the SQUID device changes periodically with the induced magnetic flux, the period being a magnetic flux quantum Φ0 = 2.07 × 10⁻⁶. -15 Wb. For example... Figure 1As shown, a first superconducting film layer 11a is formed on the substrate 10. A barrier layer 12 and a second superconducting film layer 11b are disposed at both ends of the first superconducting film layer 11a. The three-layer structure of the first superconducting film layer 11a, the barrier layer 12, and the second superconducting film layer 11b constitutes a Josephson junction. The second superconducting film layer 11b is connected to the ground layer 13. When measuring the inductance of a superconducting digital circuit, the superconducting thin film and the ground of the superconducting digital circuit form a superconducting loop. A current Icontrol is passed through the superconducting inductor, generating a magnetic flux Φ in the superconducting loop. Changing the current Icontrol causes a corresponding change in the value of the magnetic flux Φ. Based on the SQUID device modulation technique described above, the relationship between the change in magnetic flux Φ and the change in current Icontrol can be measured. The magnitude of the current Icontrol that causes a change in output voltage for one cycle is selected, and the superconducting thin film inductance L = Φ / Icontrol is calculated. Since the Josephson junction is one of the main structures of the superconducting digital circuit, the fabrication process for inductance characterization is the same as that for the superconducting digital circuit.

[0078] like Figure 2 As shown, fabricating an inductor characterization pattern in a chip requires at least four electrodes: two for the SQUID device's bias current Ibias and voltage output V+, and two for passing current through the inductor. If characterizing inductance in different superconducting layers is required, corresponding inductor characterization patterns need to be designed. For example, the inductor can be fabricated using the superconducting layer containing the bottom electrode of the Josephson junction, or the superconducting layer containing the wiring layer connected to the top electrode of the Josephson junction. In this case, two corresponding inductor characterization patterns need to be designed during chip layout, requiring at least eight electrodes. The larger the area occupied by process monitoring in the chip, the less favorable it is for cost reduction and efficiency improvement.

[0079] This invention proposes a characterization structure for superconducting digital circuit inductors. The characterization structure of the superconducting digital circuit inductors is optimized to obtain the measurement results of multiple measurement objects through a single structure. The specific structure is as follows.

[0080] Example 1

[0081] like Figure 3 As shown, this embodiment provides a characterization structure 2 for a superconducting digital circuit inductor, the characterization structure 2 for the superconducting digital circuit inductor includes:

[0082] A first superconducting thin film 21, a second superconducting thin film 22, a third superconducting thin film 23, a first Josephson junction 24, a second Josephson junction 25, a first electrode 26a, a second electrode 26b, a third electrode 26c, a fourth electrode 26d, and a fifth electrode 26e. The first end of the first superconducting thin film 21 is connected to the first electrode layer of the first Josephson junction 24, and the second end is connected to the first end of the second superconducting thin film 22. The second end of the second superconducting thin film 22 is connected to the first end of the third superconducting thin film 23. The second end of the third superconducting thin film 23 is connected to the first electrode layer of the second Josephson junction 25. The second electrode layers of the first Josephson junction 24 and the second Josephson junction 25 are grounded. The first electrode 26a has its first end connected to the first electrode layer of the first Josephson junction 24, and its second end led out. The second electrode 26b has its first end connected to the first electrode layer of the second Josephson junction 25, and its second end led out. The third electrode 26c has its first end connected between the first and second ends of the first superconducting thin film 21, and its second end led out. The fourth electrode 26d has its first end connected between the first and second ends of the second superconducting thin film 22, and its second end led out. The fifth electrode 26e has its first end connected between the first and second ends of the third superconducting thin film 23, and its second end led out. The first superconducting thin film 21 and the third superconducting thin film 23 are located in the first layer, and the second superconducting thin film 22 is located in the second layer.

[0083] like Figure 3 As shown, in this embodiment, the first superconducting thin film 21 and the third superconducting thin film 23 are located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, and the second superconducting thin film 22 is located in the wiring layer connected to the top electrode of the Josephson junction in the superconducting digital circuit. The second end of the first superconducting thin film 21 is connected to the first end of the second superconducting thin film 22 through a through-hole, and the first end of the third superconducting thin film 23 is connected to the second end of the second superconducting thin film 22 through a through-hole. The first superconducting thin film 21, the second superconducting thin film 22, the third superconducting thin film 23, and the through-hole are all made of superconducting materials, including but not limited to niobium and niobium nitride, which will not be described in detail here.

[0084] like Figure 3 As shown, both the first Josephson junction 24 and the second Josephson junction 25 include a first electrode layer, an insulating layer, and a second electrode layer. In this embodiment, the first electrode layers of the first Josephson junction 24 and the second Josephson junction 25 are located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, that is, in the same layer as the first superconducting thin film 21 and the third superconducting thin film 23. The second electrode layers of the first Josephson junction 24 and the second Josephson junction 25 are connected together through a ground layer 27.

[0085] like Figure 3 As shown, the first electrode 26a is electrically connected to the first electrode layer of the first Josephson junction 24 to apply a bias current Ibias.

[0086] like Figure 3 As shown, the second electrode 26b is electrically connected to the first electrode layer of the second Josephson junction 25 for output voltage V+.

[0087] like Figure 3 As shown in the illustration, as an example, the third electrode 26c and the fifth electrode 26e are located on the same layer as the first superconducting thin film 21 and the third superconducting thin film 23; the first part of the fourth electrode 26d is located on the same layer as the second superconducting thin film 22, and the second part is located on the same layer as the third electrode 26c and the fifth electrode 26e, with the first part and the second part connected through a via. The third electrode 26c, the fourth electrode 26d, and the fifth electrode 26e are all led out from the bottom electrode layer of the Josephson junction in the superconducting digital circuit. In practical use, the positions of each electrode can be set as needed, and are not limited to this embodiment.

[0088] Specifically, in this embodiment, the first electrode 26a, the second electrode 26b, the third electrode 26c, the fourth electrode 26d, and the fifth electrode 26e are made of superconducting materials, including but not limited to niobium and niobium nitride. In practical use, each electrode can be made of a suitable conductive material as needed. The leads of each electrode can be made of any conductive material, which will not be elaborated here.

[0089] In another implementation of the present invention, the characterization structure 2 of the superconducting digital circuit inductor further includes a sixth electrode 26f. The first end of the sixth electrode 26f is connected between the first end of the fifth electrode 26e and the second end of the third superconducting thin film 23, and the second end is led out.

[0090] It should be noted that in actual use, the first superconducting thin film 21, the second superconducting thin film 22 and the third superconducting thin film 23 can be disposed in the corresponding structural layers as needed; the first superconducting thin film 21 and the third superconducting thin film need to be located in the same layer and the second superconducting thin film needs to be located in another layer, and the arrangement is not limited to the arrangement listed in this embodiment.

[0091] like Figure 3As shown, the first superconducting thin film 21, the second superconducting thin film 22, the third superconducting thin film 23, the first Josephson junction 24, the second Josephson junction 25, and the ground layer 27 constitute a SQUID device. The superconducting digital circuit inductance characterization method of the present invention involves passing current through different electrodes, which generates magnetic flux in the SQUID device, thereby enabling the measurement of unit inductance. Specifically, the method for measuring the inductance per unit length of the superconducting thin film in the layer containing the second superconducting thin film includes:

[0092] 11) Apply a bias current Ibias, which flows into the first electrode 26a and out from the ground terminal (i.e., the ground layer 27). Apply a first current I1, which flows into the third electrode 26c and out from the fourth electrode 26d. Apply a second current I2, which flows into the fifth electrode 26e and out from the fourth electrode 26d. Wherein, the first current I1 is equal to the second current I2, and the current value is denoted as I. control1 .

[0093] Specifically, firstly, a bias is applied to the characterization structure 2 of the superconducting digital circuit inductor to ensure that the SQUID device composed of the first superconducting thin film 21, the second superconducting thin film 22, the third superconducting thin film 23, the first Josephson junction 24, the second Josephson junction 25, and the ground layer 27 operates normally. Then, a current of I is passed between the third electrode 26c and the fourth electrode 26d. control1 A first current I1 is applied between the fifth electrode 26e and the fourth electrode 26d, with a current value of I. control1 The second current I2, the current flowing out of the fourth electrode 26d is 2I. control1 .

[0094] 12) Read the voltage V+ from the second electrode 26b, obtain the first magnetic flux Φ1 of the characterization structure 2 of the superconducting digital circuit inductance, and calculate the inductance L per unit length of the superconducting thin film in the layer where the second superconducting thin film is located based on the first magnetic flux Φ1, the first current I1 and the second current I2. UI1 .

[0095] Specifically, let L1 be the inductance between the first end of the third electrode 26c and the second end of the first superconducting thin film 21, L2 be the inductance between the second end of the first superconducting thin film 21 and the first end of the fourth electrode 26d, L3 be the inductance between the first end of the fourth electrode 26d and the second end of the second superconducting thin film 22, L4 be the inductance between the first end of the third superconducting thin film 23 and the first end of the fifth electrode 26e, l1 be the length between the first end of the third electrode 26c and the second end of the first superconducting thin film 21, l2 be the length between the second end of the first superconducting thin film 21 and the first end of the fourth electrode 26d, l3 be the length between the first end of the fourth electrode 26d and the second end of the second superconducting thin film 22, and l4 be the length between the first end of the third superconducting thin film 23 and the first end of the fifth electrode 26e.

[0096] Specifically, the read voltage V+ is related to the magnetic flux, and the corresponding magnetic flux can be obtained based on the voltage V+. At this time, the first magnetic flux Φ1 generated by the characterization structure 2 of the superconducting digital circuit inductor satisfies: Φ1=(L1+L2-L3-L4)*I control1 Let l1 = l4 (that is, set the length between the first end of the third electrode 26c and the second end of the first superconducting film 21 to be equal to the length between the first end of the third superconducting film 23 and the first end of the fifth electrode 26e), then L1 = L4. At this time, the inductance per unit length of the superconducting film in the layer where the second superconducting film is located is L... UI1 satisfy:

[0097] L UI1 =(L2-L3) / (l2-l3)=Φ1 / [(l2-l3)*I control1 ].

[0098] like Figure 3 As shown, the method for measuring the inductance per unit length of the superconducting thin film in the layers containing the first superconducting thin film 21 and the third superconducting thin film 23 includes:

[0099] 21) Apply a bias current Ibias, which flows into the first electrode 26a and out from the ground terminal (i.e., the ground layer 27). Apply a third current I3, which flows into the third electrode 26c and out from the fifth electrode 26e. Read the voltage V+ from the second electrode to obtain the second magnetic flux Φ2 of the characterization structure 2 of the superconducting digital circuit inductance.

[0100] Specifically, firstly, a bias is applied to the characterization structure 2 of the superconducting digital circuit inductor to ensure that the SQUID device composed of the first superconducting thin film 21, the second superconducting thin film 22, the third superconducting thin film 23, the first Josephson junction 24, the second Josephson junction 25, and the ground layer 27 operates normally. Then, a current of I is passed between the third electrode 26c and the fifth electrode 26e. control3 The third current I3, at this time, the characterization structure 2 of the superconducting digital circuit inductor generates a second magnetic flux Φ2, the second magnetic flux Φ2 satisfies: Φ2=(L1+L2+L3+L4)*I control3 .

[0101] 22) Apply a fourth current I4, which flows into the third electrode 26c and out of the sixth electrode 26f. Read the voltage V+ from the second electrode to obtain the third magnetic flux Φ3 of the characterization structure 2 of the superconducting digital circuit inductance.

[0102] Specifically, the bias current Ibias is maintained, and then a current value of I is passed between the third electrode 26c and the sixth electrode 26f. control4 The fourth current I4, at this time, the characterization structure 2 of the superconducting digital circuit inductor generates a third magnetic flux Φ3, the third magnetic flux Φ3 satisfying: Φ3=(L1+L2+L3+L4+L5)*I control4 Wherein, L5 is the inductance between the first end of the fifth electrode 26e and the second end of the third superconducting thin film 23, and l5 is the length between the first end of the fifth electrode 26e and the second end of the third superconducting thin film 23.

[0103] 23) Calculate the inductance per unit length of the superconducting thin film L of the layers containing the first superconducting thin film 21 and the third superconducting thin film 23 based on the second magnetic flux Φ2, the third magnetic flux Φ3, the third current I3, and the fourth current I4. UI2 .

[0104] Specifically, the inductance per unit length of the superconducting thin film in the layers containing the first and third superconducting thin films satisfies the following:

[0105] L UI2 =L5 / l5=(Φ2 / I control3 -Φ3 / I control4 ) / l5.

[0106] It should be noted that in actual use, either the first electrode 26a or the second electrode 26b is used to apply a bias current, while the other is used to read the voltage, and this is not limited to this embodiment.

[0107] It should be noted that, in this embodiment, the inductance L per unit length of the superconducting thin film in the layer containing the second superconducting thin film is... UI1 This refers to the inductance per unit length of the superconducting thin film in the wiring layer, specifically the inductance L per unit length of the superconducting thin film in the layers containing the first and third superconducting thin films. UI2 This refers to the inductance per unit length of the superconducting thin film in the bottom electrode layer. In practical applications, the inductance per unit length of the superconducting thin film in the corresponding structural layer can be determined based on the actual placement of each superconducting thin film, and is not limited to this embodiment. Furthermore, in practical applications, the method for obtaining the inductance per unit length of the superconducting thin film in the layers containing the first and third superconducting thin films, and the layers containing the second superconducting thin film, is not limited to the characterization method of the superconducting digital circuit in this invention, but includes, but is not limited to, obtaining the inductance per unit length of the superconducting thin film in the layers containing the first and third superconducting thin films based on the first electrode, the second electrode, the third electrode, the fourth electrode, and the fifth electrode (Φ1=(L1+L2-L3-L4)*I). control1 The length between the second end of the first superconducting thin film 21 and the first end of the fourth electrode 26d is set to be equal to the length between the first end of the fourth electrode 26d and the second end of the second superconducting thin film 22 (l2 = l3), which is not limited to this embodiment.

[0108] like Figures 4 to 15 As shown, the process flow of the characterization structure 2 of the superconducting digital circuit inductor in the fabrication process of the superconducting digital circuit is as follows:

[0109] 31) For example Figure 4 As shown, a substrate 3 is provided, on which a first superconducting film layer 4, a barrier layer 5, and a second superconducting film layer 6 of a superconducting digital circuit are sequentially grown.

[0110] Specifically, in this embodiment, the substrate 3 is made of materials including, but not limited to, single-crystal silicon, sapphire, silicon carbide, magnesium oxide, and magnesium fluoride; the first superconducting film layer 4 and the second superconducting film layer 6 are made of materials including, but not limited to, niobium and niobium nitride; the barrier layer 5 is made of materials including, but not limited to, aluminum oxide, aluminum nitride, and tantalum nitride; these will not be elaborated further here. In this embodiment, a three-layer NbN / TaN / NbN film is deposited on a Si substrate. As an example, the thickness of the first superconducting film layer 4 and the second superconducting film layer 6 is set to 50 nm to 200 nm, and the thickness of the barrier layer 5 is set to 15 nm to 35 nm.

[0111] 32) For example Figure 5 As shown, the barrier layer 5 and the second superconducting film layer 6 are etched to form the junction regions of the Josephson junction (not shown in the figure), the first Josephson junction 24 and the second Josephson junction 25 in the superconducting digital circuit, and to form the top electrode of each Josephson junction.

[0112] 33) For example Figure 6 As shown, the first superconducting film layer 4 is etched to form the bottom electrode of each Josephson junction, the first superconducting thin film 21, the third superconducting thin film 23, and the lead-out electrode.

[0113] Specifically, in this embodiment, the lead-out electrodes formed in step 33) include the first electrode 26a, the second electrode 26b, the third electrode 26c, the fifth electrode 26e, the sixth electrode 26f, and the second portion of the fourth electrode 26d. The bottom electrodes of each Josephson junction include the Josephson junction in the superconducting digital circuit and the first and second Josephson junctions used for inductance measurement.

[0114] 34) For example Figures 7-11 As shown, a first insulating material layer 7 is grown on the structure formed in step 33), the first insulating material layer 7 is etched to expose the second superconducting film layer (upper superconducting film layer) of each Josephson junction, and a connecting via is formed.

[0115] Specifically, in this embodiment, the step of etching the first insulating material layer 7 includes: performing junction pre-etching on the first insulating material layer 7 after growth, such as... Figure 8 As shown; then, the bottom electrode of the first insulating material layer 7 is pre-etched, as shown. Figure 9 As shown; the first insulating material layer 7 is planarized (CMP) to expose the upper superconducting film layer of each Josephson junction, as shown. Figure 10 As shown; the first insulating material layer 7 is then etched to form a through-hole, as shown. Figure 11 As shown, the vias include, but are not limited to, vias connecting the first superconducting thin film 21 and the second superconducting thin film 22 in the characterization structure 2 of the superconducting digital circuit inductor, vias connecting the third superconducting thin film 23 and the second superconducting thin film 22, lead-out holes of each electrode, and connection vias in the superconducting digital circuit. As an example, the material of the first insulating layer 7 is silicon dioxide, and its thickness is 200 nm to 400 nm.

[0116] It should be noted that this embodiment uses pre-etching to ensure the subsequent planarization process.

[0117] 35) For example Figure 12 As shown, a wiring layer 8 is grown and etched to form the second superconducting thin film 22.

[0118] Specifically, in this embodiment, step 35) also involves etching to form the first portion of the fourth electrode 26d and other wiring, which will not be described in detail here.

[0119] 36) For example Figures 13-14As shown, a second insulating material layer 9 is grown on the structure formed in step 35), and the second insulating material layer 9 is etched to expose the wiring layer connecting the top electrodes of each Josephson junction. As an example, the material of the second insulating material layer 8 is silicon dioxide, and the thickness is 200 nm to 400 nm.

[0120] 37) For example Figure 15 As shown, a grounding layer 27 is grown on the structure formed in step 36).

[0121] It should be noted that in this embodiment, each conductive layer is formed using a superconducting material.

[0122] Example 2

[0123] This embodiment provides a characterization structure 2 for an inductor in a superconducting digital circuit. The difference from Embodiment 1 is that the first superconducting thin film 21 and the second superconducting thin film 22 are located in the wiring layer connected to the top electrode of the Josephson junction in the superconducting digital circuit, and the second superconducting thin film 22 is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit.

[0124] Specifically, the first electrode layer (top electrode) of the first Josephson junction 24 is located in the top electrode layer of the Josephson junction in the superconducting digital circuit and is electrically connected to the first end of the first superconducting thin film 21; the second electrode layer (bottom electrode) is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit and is electrically connected to the ground layer 27 through a via. The first electrode layer (top electrode) of the second Josephson junction 25 is located in the top electrode layer of the Josephson junction in the superconducting digital circuit and is electrically connected to the second end of the third superconducting thin film 23; the second electrode layer (bottom electrode) is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit and is electrically connected to the ground layer 27 through a via.

[0125] It should be noted that the inductance characterization method based on the superconducting digital circuit inductance characterization structure 2 of this embodiment and the superconducting digital circuit inductance characterization structure 2 of this embodiment are basically the same as those in Embodiment 1. Adaptive adjustments can be made, and they will not be described in detail here.

[0126] The method for measuring superconducting thin-film inductors of the present invention can obtain the inductance values ​​of two-layer thin-film inductors in a single pattern measurement. Figure 1The previous method for measuring the inductance of two layers required two inductance characterization patterns, each containing two Josephson junctions and four electrodes, for a total of four Josephson junctions and eight electrodes. Furthermore, the SQUID device parameters needed to be adjusted twice during measurement. In contrast, the method of this invention requires only one superconducting digital circuit inductance characterization structure, containing two Josephson junctions and six electrodes, and only requires adjusting the SQUID device parameters once during measurement. It also effectively avoids the error caused by parasitic inductance at vias.

[0127] Therefore, this invention not only reduces the area occupied by the inductance characterization pattern in the chip, but also improves the measurement efficiency and accuracy, which is beneficial to the design of superconducting digital circuits.

[0128] In summary, this invention provides a characterization structure and method for inductors in superconducting digital circuits, comprising: a first superconducting thin film, a second superconducting thin film, a third superconducting thin film, a first Josephson junction, a second Josephson junction, a first electrode, a second electrode, a third electrode, a fourth electrode, and a fifth electrode; a first end of the first superconducting thin film is connected to the first electrode layer of the first Josephson junction, and a second end is connected to the first end of the second superconducting thin film; a second end of the second superconducting thin film is connected to the first end of the third superconducting thin film; a second end of the third superconducting thin film is connected to the first electrode layer of the second Josephson junction; and the second electrode layers of the first Josephson junction and the second Josephson junction... Grounded; the first end of the first electrode is connected to the first electrode layer of the first Josephson junction, and the second end is led out; the first end of the second electrode is connected to the first electrode layer of the second Josephson junction, and the second end is led out; the first end of the third electrode is connected between the first end and the second end of the first superconducting thin film, and the second end is led out; the first end of the fourth electrode is connected between the first end and the second end of the second superconducting thin film, and the second end is led out; the first end of the fifth electrode is connected between the first end and the second end of the third superconducting thin film, and the second end is led out; wherein, the first superconducting thin film and the third superconducting thin film are located in the first layer, and the second superconducting thin film is located in the second layer. The superconducting digital circuit inductance characterization structure and method of the present invention obtains the inductance values ​​of different superconducting thin films in one inductance characterization structure, simplifies the structure, and improves the efficiency and accuracy of inductance measurement in superconducting digital circuits. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

[0129] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A characterization structure for an inductor in a superconducting digital circuit, characterized in that, The characterization structure of the superconducting digital circuit inductor includes at least: First superconducting thin film, second superconducting thin film, third superconducting thin film, first Josephson junction, second Josephson junction, first electrode, second electrode, third electrode, fourth electrode and fifth electrode; The first end of the first superconducting thin film is connected to the first electrode layer of the first Josephson junction, and the second end is connected to the first end of the second superconducting thin film; the second end of the second superconducting thin film is connected to the first end of the third superconducting thin film; the second end of the third superconducting thin film is connected to the first electrode layer of the second Josephson junction; the first Josephson junction and the second electrode layer of the second Josephson junction are grounded; The first end of the first electrode is connected to the first electrode layer of the first Josephson junction, and the second end is led out. The first end of the second electrode is connected to the first electrode layer of the second Josephson junction, and the second end is led out. The first end of the third electrode is connected between the first end and the second end of the first superconducting thin film, and the second end is led out. The first end of the fourth electrode is connected between the first and second ends of the second superconducting thin film, and the second end is led out. The first end of the fifth electrode is connected between the first and second ends of the third superconducting thin film, and the second end is led out. The first superconducting thin film and the third superconducting thin film are located in the first layer, and the second superconducting thin film is located in the second layer.

2. The characterization structure of the superconducting digital circuit inductor according to claim 1, characterized in that: The first superconducting thin film and the third superconducting thin film are located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, and the second superconducting thin film is located in the wiring layer of the superconducting digital circuit connected to the top electrode of the Josephson junction; the first electrode layer of the first Josephson junction and the second Josephson junction is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit, and the second electrode layer is located in the top electrode layer of the Josephson junction in the superconducting digital circuit.

3. The characterization structure of the superconducting digital circuit inductor according to claim 1, characterized in that: The first superconducting thin film and the third superconducting thin film are located in the wiring layer of the superconducting digital circuit that is connected to the top electrode of the Josephson junction, and the second superconducting thin film is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit; the first electrode layer of the first Josephson junction and the second Josephson junction is located in the top electrode layer of the Josephson junction in the superconducting digital circuit, and the second electrode layer is located in the bottom electrode layer of the Josephson junction in the superconducting digital circuit.

4. The characterization structure of the superconducting digital circuit inductor according to claim 1, characterized in that: The length between the first end of the third electrode and the second end of the first superconducting thin film is equal to the length between the first end of the third superconducting thin film and the first end of the fifth electrode.

5. The characterization structure of the superconducting digital circuit inductor according to claim 1, characterized in that: The length between the second end of the first superconducting thin film and the first end of the fourth electrode is equal to the length between the first end of the fourth electrode and the second end of the second superconducting thin film.

6. The characterization structure of the superconducting digital circuit inductor according to any one of claims 1-5, characterized in that: The characterization structure of the superconducting digital circuit inductor also includes a sixth electrode; the first end of the sixth electrode is connected between the first end of the fifth electrode and the second end of the third superconducting thin film, and the second end is led out.

7. A method for characterizing inductors in superconducting digital circuits, implemented based on the characterization structure of inductors in superconducting digital circuits as described in any one of claims 1-6, characterized in that, The characterization method for the inductance of the superconducting digital circuit includes at least the following: A bias current is applied, which flows into one of the first and second electrodes and flows out from the ground terminal; a first current is applied, which flows into the third electrode and flows out from the fourth electrode; a second current is applied, which flows into the fifth electrode and flows out from the fourth electrode; wherein the first current is equal to the second current; The voltage is read from the other electrode among the first electrode and the second electrode to obtain the first magnetic flux of the characterizing structure of the superconducting digital circuit inductance, and the inductance per unit length of the superconducting thin film in the layer where the second superconducting thin film is located is calculated based on the first magnetic flux, the first current and the second current.

8. The method for characterizing the inductance of a superconducting digital circuit according to claim 7, characterized in that: The first magnetic flux satisfies: Φ1=(L1+L2-L3-L4)*I control1 ; Wherein, Φ1 is the first magnetic flux, L1 is the inductance between the first end of the third electrode and the second end of the first superconducting thin film, L2 is the inductance between the second end of the first superconducting thin film and the first end of the fourth electrode, L3 is the inductance between the first end of the fourth electrode and the second end of the second superconducting thin film, L4 is the inductance between the first end of the third superconducting thin film and the first end of the fifth electrode, and I control1 The values ​​are the first current and the second current.

9. The method for characterizing the inductance of a superconducting digital circuit according to claim 8, characterized in that: Let l1 = l4, then L1 = L4. At this time, the inductance per unit length of the superconducting thin film in the layer containing the second superconducting thin film satisfies: L UI1 (L2-L3) / (l2-l3) Φ1 / [(l2-l3)*I control1 ]; Among them, L UI1 l1 is the inductance per unit length of the superconducting thin film in the layer where the second superconducting thin film is located, l2 is the length between the first end of the third electrode and the second end of the first superconducting thin film, l3 is the length between the first end of the first superconducting thin film and the first end of the fourth electrode, l4 is the length between the first end of the fourth electrode and the second end of the second superconducting thin film, and l5 is the length between the first end of the third superconducting thin film and the first end of the fifth electrode.

10. The method for characterizing the inductance of a superconducting digital circuit according to claim 7, characterized in that: A bias current is applied, which flows in from one of the first and second electrodes and flows out from the ground terminal; A third current is applied, flowing into the third electrode and out of the fifth electrode; the voltage is read from the other electrode among the first and second electrodes to obtain the second magnetic flux characterizing the inductor structure of the superconducting digital circuit. A fourth current is applied, which flows into the third electrode and out of the sixth electrode; The voltage is read from the other electrode among the first electrode and the second electrode to obtain the third magnetic flux characterizing the inductor structure of the superconducting digital circuit; Calculate the inductance per unit length of the superconducting thin film in the layer containing the first and third superconducting thin films based on the second magnetic flux, the third magnetic flux, the third current, and the fourth current; The first end of the sixth electrode is connected between the first end of the third electrode and the second end of the third superconducting thin film, and the second end is led out.

11. The method for characterizing the inductance of a superconducting digital circuit according to claim 10, characterized in that: The second magnetic flux and the third magnetic flux respectively satisfy: Φ2=(L1+L2+L3+L4)*I control3 ; Φ3=(L1+L2+L3+L4+L5)*I control4 ; Wherein, Φ2 is the second magnetic flux, Φ3 is the third magnetic flux, L1 is the inductance between the first end of the third electrode and the second end of the first superconducting thin film, L2 is the inductance between the second end of the first superconducting thin film and the first end of the fourth electrode, L3 is the inductance between the first end of the fourth electrode and the second end of the second superconducting thin film, L4 is the inductance between the first end of the third superconducting thin film and the first end of the fifth electrode, and L5 is the inductance between the first end of the fifth electrode and the second end of the third superconducting thin film. control3 I is the value of the third current. control4 The value of the fourth current.

12. The method for characterizing the inductance of a superconducting digital circuit according to claim 11, characterized in that: The inductance per unit length of the superconducting thin film in the layers containing the first and third superconducting thin films satisfies: L UI2 =L5 / l5=(Φ2 / I control3 -Φ3 / I control4 ) / l5; Among them, L UI2 l1 is the inductance per unit length of the superconducting thin film in the layer containing the first and third superconducting thin films, and l5 is the length between the first end of the fifth electrode and the second end of the third superconducting thin film.

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