A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor structure comprising a semiconductor layer, an isolation structure, an active region and a gate structure; sequentially forming a barrier layer and a photoresist layer on the upper surface of the semiconductor structure; forming a first opening in the photoresist layer, the bottom of the first opening exposing the barrier layer, forming a well region on the upper surface of the active region based on the first opening, and removing the barrier layer at the bottom of the first opening to form a second opening in the barrier layer; removing the photoresist layer, and forming a source-drain region based on the second opening, the source-drain region being located on the upper surface of the well region between the gate structure and the isolation layer; and removing the barrier layer. By forming a barrier layer between the upper surface of the semiconductor structure and the photoresist layer, the application avoids the problems of device plasma damage in the process of forming the well region and poor process stability in the process of forming the source-drain region.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing and relates to a semiconductor device and its preparation method. Background Technology

[0002] Double-diffused MOS (DMOS) transistors are optimized for high current and high voltage. To improve breakdown voltage, these devices are designed with a long-channel structure. Several components are connected in parallel to achieve high current (low on-resistance) and high energy density.

[0003] Bipolar Discrete (BCD) is a monolithic integrated circuit technology. First developed by STMicroelectronics (ST) in 1986, this technology enables the fabrication of bipolar transistors, CMOS (Complementary Metal Oxide Semiconductor), and DMOS devices on the same chip, hence the name BCD process. BCD combines the high transconductance and strong load drive capability of bipolar devices with the high integration density and low power consumption of CMOS, allowing each to leverage its strengths. More importantly, it integrates DMOS power devices, which are optimized for high current and high voltage. DMOS can operate in switching mode with extremely low power consumption. High power can be transferred to the load without expensive packaging and cooling systems. Low power consumption is one of the main advantages of the BCD process. The integrated BCD process can significantly reduce power consumption, improve system performance, save on circuit packaging costs, and provide better reliability. It is widely used in wireless chargers, Power over Ethernet (PoE), USB Type-C PD controllers, smart devices, automobiles, eBikes, and data centers.

[0004] Currently, in the formation of the well and source / drain regions of MOS (Metal Oxide Semiconductor) devices using the BCD process, the process begins with exposure and development of the well after photoresist formation, followed by ion implantation to form the well region. Then, anisotropic dry etching is used to dry-etch the remaining photoresist layer (PR) to reduce its thickness and size. Next, lightly doped drains (LDDs) are formed by ion implantation to create the source / drain regions. Finally, etching is used to remove the photoresist. However, the actual results are not ideal, as it increases the difficulty of cleaning and causes plasma damage to the device. The dry etching process for the photoresist layer also has poor stability, affecting device performance and yield.

[0005] Therefore, there is an urgent need to find a method for fabricating semiconductor devices that avoids plasma damage and improves device performance and yield. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method, which solves the problem of plasma damage to the device caused during the formation of the well region in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0008] A semiconductor structure is provided, the semiconductor structure including a semiconductor layer, an isolation structure located in the semiconductor layer, an active region located between the isolation structures, and a gate structure whose sidewalls are at a predetermined distance from the isolation structures;

[0009] A barrier layer and a photoresist layer located on the upper surface of the semiconductor structure are sequentially formed thereon, and the barrier layer covers the gate structure.

[0010] A first opening is formed in the photoresist layer, the bottom of the first opening exposes the barrier layer, a first conductivity type well region is formed on the upper surface layer of the active region based on the first opening, and the barrier layer at the bottom of the first opening is removed to form a second opening located in the barrier layer, the bottom of the second opening exposes the active region and the gate structure.

[0011] Remove the photoresist layer and form a source / drain region of a second conductivity type based on the second opening. The source / drain region is located on the upper surface of the well region between the gate structure and the isolation structure.

[0012] Remove the barrier layer.

[0013] Optionally, the method of forming the barrier layer includes coating.

[0014] Optionally, the thickness range of the barrier layer is:

[0015] Optionally, the material of the barrier layer includes an anti-reflective layer.

[0016] Optionally, the method for removing the barrier layer at the bottom of the first opening includes one of dry etching and wet etching.

[0017] Optionally, the method for forming the trap region includes ion implantation.

[0018] Optionally, the method for forming the source / drain region includes ion implantation.

[0019] Optionally, the ion implantation energy range for forming the source / drain region is 3 keV to 150 keV, and the ion implantation dose range for forming the source / drain region is 1.0 × 10⁻⁶. 13 / cm 2 ~7×10 14 / cm 2 .

[0020] Optionally, the ion implantation angle range for forming the source / drain region is 15° to 75°.

[0021] The present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method described above.

[0022] As described above, the semiconductor device and its fabrication method of the present invention form a barrier layer on the upper surface of the semiconductor structure, a photoresist layer on the upper surface of the barrier layer, and a first opening in the photoresist layer. Then, a well region is formed in the semiconductor layer based on the first opening. The barrier layer prevents direct contact between plasma and the active region during well region formation, thus avoiding the risk of plasma damage to the active region. Furthermore, a second opening is formed in the barrier layer based on the first opening, and the photoresist layer is removed. The barrier layer is then used as a shielding layer to form the source / drain region based on the second opening. This improves process stability, enhances product performance and yield, and avoids the problem of poor thickness and dimensional stability of the photoresist layer during the etching process to reduce its thickness and size when using it as a shielding layer to form the source / drain region. It also avoids the difficulty of cleaning when using the photoresist layer as a shielding layer, thus possessing high industrial application value. Attached Figure Description

[0023] Figure 1The diagram shown is a process flow chart of the method for fabricating the semiconductor device of the present invention.

[0024] Figure 2 The diagram shown is a cross-sectional view of the semiconductor structure used in the fabrication method of the semiconductor device of the present invention.

[0025] Figure 3 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the formation of the barrier layer.

[0026] Figure 4 The diagram shows a cross-sectional structure of the semiconductor device fabrication method of the present invention after the formation of the photoresist layer.

[0027] Figure 5 The diagram shows a cross-sectional structure of the patterned photoresist layer after the semiconductor device fabrication method of the present invention.

[0028] Figure 6 The diagram shows a cross-sectional structure of the semiconductor device fabrication method of the present invention after the formation of the well region.

[0029] Figure 7 The diagram shows a cross-sectional structure after the formation of the second opening in the method for fabricating the semiconductor device of the present invention.

[0030] Figure 8 The diagram shows a cross-sectional structure after removing the photoresist layer in the method for fabricating the semiconductor device of the present invention.

[0031] Figure 9 The diagram shows a cross-sectional structure after the source / drain region is formed, which is a method for fabricating the semiconductor device of the present invention.

[0032] Figure 10 The diagram shown is a cross-sectional view of the semiconductor device fabrication method of the present invention after the barrier layer has been removed.

[0033] Component designation explanation

[0034] 1. Semiconductor Structure

[0035] 11 Semiconductor layer

[0036] 12. Isolation Structure

[0037] 121 Trench

[0038] 122 Isolation Layer

[0039] 13 Active Region

[0040] 14 Gate Structure

[0041] 141 Gate dielectric layer

[0042] 142 Gate conductive layer

[0043] 15 Tunnel Area

[0044] 16 Source / Leakage Zone

[0045] 2. Barrier layer

[0046] 21 Second opening

[0047] 3. Photoresist layer

[0048] 31 First Opening Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] Please see Figures 1 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] Example 1

[0052] This embodiment provides a method for fabricating a semiconductor device, such as... Figure 1 The diagram shown is a process flow chart of the method for fabricating the semiconductor device, including the following steps:

[0053] S1: The semiconductor structure includes a semiconductor layer, an isolation structure located in the semiconductor layer, an active region located between the isolation structures, and a gate structure whose sidewalls are at a predetermined distance from the isolation structures;

[0054] S2: A barrier layer and a photoresist layer located on the upper surface of the semiconductor structure are sequentially formed on the upper surface of the barrier layer, and the barrier layer covers the gate structure;

[0055] S3: A first opening is formed in the photoresist layer, the bottom of the first opening exposes the barrier layer, a first conductivity type well region is formed on the upper surface of the active region based on the first opening, and the barrier layer at the bottom of the first opening is removed to form a second opening located in the barrier layer, the bottom of the second opening exposes the active region and the gate junction structure.

[0056] S4: Remove the photoresist layer and form a second conductivity type source / drain region based on the second opening, the source / drain region being located on the upper surface of the well region between the gate structure and the isolation structure;

[0057] S5: Remove the blocking layer.

[0058] Please see Figures 2 to 4 The steps S1 and S2 are performed as follows: a semiconductor structure 1 is provided, the semiconductor structure 1 includes a semiconductor layer 11, an isolation structure 12 located in the semiconductor layer 11, an active region 13 located between the isolation structures 12, and a gate structure 14 with its sidewalls at a predetermined distance from the isolation structures 12; a barrier layer 2 and a photoresist layer 3 located on the upper surface of the semiconductor structure 1 are sequentially formed, the barrier layer 2 covering the exposed surface of the gate structure 14.

[0059] Specifically, such as Figure 2 The diagram shown is a cross-sectional view of the semiconductor structure 1. The semiconductor layer 11 is made of silicon, silicon carbide, silicon germanium, or other suitable semiconductor materials.

[0060] Specifically, the isolation structure 12 includes a trench 121 located in the semiconductor layer 11 and an isolation layer 122 filling the trench 121, with the trench 121 opening upward.

[0061] Specifically, the gate structure 14 includes a gate dielectric layer 141 and a gate conductive layer 142 located on the upper surface of the gate dielectric layer 141.

[0062] Specifically, the gate dielectric layer 141 is made of silicon oxide, silicon nitride, or other suitable dielectric materials. In this embodiment, the gate dielectric layer 141 is made of silicon oxide.

[0063] Specifically, while ensuring device performance, the thickness and size of the gate dielectric layer 141 can be selected according to the actual situation, and are not limited here.

[0064] Specifically, the gate conductive layer 142 is made of polycrystalline silicon or other suitable conductive materials. In this embodiment, the gate conductive layer 142 is made of polycrystalline silicon.

[0065] Specifically, while ensuring device performance, the size of the gate conductive layer 142 can be selected according to the actual situation, and is not limited here.

[0066] As an example, such as Figure 3 The diagram shown is a cross-sectional view of the barrier layer 2 after its formation. The method for forming the barrier layer 2 includes coating or other suitable methods.

[0067] As an example, the thickness range of the barrier layer 2 is... In this embodiment, the thickness of the barrier layer 2 is

[0068] As an example, the barrier layer 2 includes an anti-reflective layer, but it can also be other suitable film layers. In this embodiment, an organic anti-reflective layer is used as the barrier layer 2 to avoid the barrier layer 2 affecting the development of the photoresist layer in subsequent processes.

[0069] Specifically, such as Figure 4 The diagram shown is a cross-sectional view of the photoresist layer 3 after its formation. The method for forming the photoresist layer 3 includes coating or other suitable methods. In this embodiment, the photoresist layer 3 is formed using a coating method.

[0070] Specifically, the thickness range of the photoresist layer 3 is as follows: In this embodiment, the thickness of the photoresist layer 3 is

[0071] Please see again Figures 5 to 10 The following steps are performed: Step S3, Step S4, and Step S5: A first opening 31 is formed in the photoresist layer 3, the bottom of the first opening 31 exposes the barrier layer 2; a first conductivity type well region 15 is formed on the upper surface of the active region 13 based on the first opening 31; the barrier layer 2 at the bottom of the first opening 31 is removed to form a second opening 21 located in the barrier layer 2, the bottom of the second opening 21 exposes the active region 13 and the gate structure 14; the photoresist layer 3 is removed, and a second conductivity type source / drain region 16 is formed based on the second opening 21, the source / drain region 16 being located on the upper surface of the well region 15 between the gate structure 14 and the isolation structure 12; the barrier layer 2 is removed.

[0072] Specifically, such as Figure 5 The diagram shows a cross-sectional view of the structure after the first opening 31 is formed. The opening size of the first opening 31 ranges from 0.8 μm to 1 μm. In this embodiment, the opening size of the first opening 31 is 0.9 μm.

[0073] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0074] As an example, such as Figure 6The diagram shown is a cross-sectional view of the well region 15 after its formation. The method for forming the well region 15 includes ion implantation or other suitable methods. In this embodiment, the well region 15 is formed using ion implantation.

[0075] Specifically, when the well region 15 is formed using ion implantation, the ion implantation energy range is 100 keV to 1000 keV, and the ion implantation dose range is 1.0 × 10⁻⁶. 12 / cm 2 ~2×10 13 / cm 2 In this embodiment, the ion implantation energy for forming the well region 15 is 500 keV, and the ion implantation dose is 1 × 10⁻⁶. 13 / cm 2 .

[0076] Specifically, the ion implantation energy range is 100 keV to 1000 keV, so as to ensure that the doped ions can penetrate the barrier layer 2 and enter the semiconductor layer 11 to form the well region 15.

[0077] Specifically, after ion implantation forms the well region 15, the process also includes a push-well step, which involves pushing the well region 15 to a preset well depth while ensuring that impurity particles diffuse into the active region 13 below the gate structure 14.

[0078] Specifically, the photoresist layer 3 and the blocking layer 2 are made of different materials, and under the same etching environment, etching the photoresist layer 3 has no effect on the blocking layer 2.

[0079] As an example, such as Figure 7 The diagram shows a cross-sectional view of the structure after the second opening 21 is formed. The method for removing the barrier layer 2 at the bottom of the first opening 31 includes either dry etching or wet etching. In this embodiment, dry etching is used to remove the barrier layer 2 at the bottom of the first opening 31, wherein the etchant used in the dry etching includes CF4.

[0080] Specifically, the formed second opening 21 exposes the outer surface of the gate structure 14, and removes all the barrier layers 2 covering the outer surface of the gate structure 14.

[0081] Specifically, the methods for removing the photoresist layer 3 include dry etching, wet stripping, or other suitable methods. In this embodiment, a photoresist stripping solution is used to wash away the photoresist layer 3.

[0082] As an example, such as Figure 9The diagram shown is a cross-sectional view of the source / drain region 16 after its formation. The method for forming the source / drain region 16 includes ion implantation or other suitable methods. In this embodiment, the source / drain region 16 is formed using a lightly doped drain (a type of ion implantation) process.

[0083] Specifically, since ion implantation at a preset tilt angle is required when forming the source / drain region 16, the shielding layer for forming the source / drain region 16 should be as thin as possible to reduce the channel effect in order to ensure the quality of the formed source / drain region 16 and the performance of the device.

[0084] As an example, the ion implantation energy range for forming the source / drain region 16 is 3 keV to 150 keV, and the ion implantation dose range for forming the source / drain region 16 is 1.0 × 10⁻⁶. 13 / cm 2 ~7×10 14 / cm 2 In this embodiment, the ion implantation energy for forming the source / drain region 16 is 100 keV, and the ion implantation dose is 1 × 10⁻⁶. 14 / cm 2 .

[0085] Specifically, when the ion implantation energy range is 3 keV to 150 keV, the blocking layer 2 can completely block doped ions from entering the semiconductor layer 11, so as to ensure that the source / drain region 16 located on the upper surface of the well region 15 is formed without affecting the performance of the device.

[0086] As an example, the ion implantation angle range for forming the source / drain region 16 is 15° to 75°. In this embodiment, ion implantation is performed at an ion implantation angle of 45° to obtain the source / drain region 16.

[0087] Specifically, a barrier layer 2 of a predetermined thickness is formed between the photoresist layer 3 and the upper surface of the semiconductor structure 1. The barrier layer 2 is used to block the plasma (doped ions) when the well region 15 is formed, thereby preventing high-energy plasma from directly contacting the semiconductor layer 11 and reducing the energy of doped ions entering the semiconductor layer 11, so as to reduce the risk of plasma damage to the semiconductor layer 11.

[0088] Specifically, by using the barrier layer 2 as a shielding layer to form the source / drain region 16, the problems of poor process stability (i.e., the thickness and size of the photoresist layer 3 are difficult to control due to the influence of etching conditions, resulting in poor process stability) and difficulty in cleaning are avoided when using the photoresist layer 3 as a shielding layer. This improves process stability and thus enhances product performance and yield.

[0089] Specifically, such as Figure 10 The diagram shown is a cross-sectional view of the structure after the barrier layer 2 is removed. The source / drain region 16 is followed by a step of removing the barrier layer 2 located on the upper surface of the semiconductor layer 11.

[0090] Specifically, the method for removing the barrier layer 2 includes dry etching, wet etching, or other suitable methods.

[0091] Specifically, after removing the barrier layer 2, the process further includes forming an interlayer dielectric layer, a gate, a source, and a drain. The interlayer dielectric layer covers the exposed surfaces of the active region 13 and the gate structure 14. The gate is electrically connected to the gate conductive layer 142, and the source and drain are electrically connected to the source and drain regions 16 located on both sides of the gate structure 14, respectively.

[0092] Specifically, the process for forming the interlayer dielectric layer, the gate, the source, and the drain is conventional and will not be described in detail here.

[0093] The semiconductor device fabrication method of this embodiment redesigns the process steps for forming the well region 15 and the source / drain region 16 of the device. A barrier layer 2 of a predetermined thickness is formed on the upper surface of the semiconductor structure 1. The semiconductor structure 1 includes the semiconductor layer 11, an isolation structure 12 located within the semiconductor layer 11, an active region 13 located between two adjacent isolation structures 12, and a gate structure 14 with its sidewalls at a predetermined distance from the isolation structures 12. A photoresist layer 3 is then formed on the upper surface of the barrier layer 2, and a first opening 31 is formed in the photoresist layer 3, exposing the bottom of the barrier layer 2. Based on the first opening 31, the well region 15 is formed in the semiconductor layer 11. The barrier layer 2 prevents the plasma from directly contacting the active region 13 and reduces the energy of doped ions entering the active region 13, thereby reducing the risk of plasma damage to the active region 13. Based on the first opening 31, the second opening 21 is formed in the barrier layer 2. The barrier layer 2 is used as a shielding layer for forming the source / drain region 16, avoiding the use of the photoresist layer 3 as a shielding layer. This improves process stability by avoiding the problems of poor process stability and difficult cleaning during the thinning of the photoresist layer 3.

[0094] Example 2

[0095] This embodiment provides a semiconductor device, such as Figure 10 The diagram shown is a cross-sectional view of the semiconductor device, which is prepared using the semiconductor device preparation method described in Example 1.

[0096] Specifically, the semiconductor device includes a semiconductor structure 1, a first conductivity type well region 15, and a second conductivity type source / drain region 16. The semiconductor structure 1 includes a semiconductor layer 11, an isolation structure 12 located in the semiconductor layer 11, an active region 13 located between two adjacent isolation structures 12, and a gate structure 14 with its sidewalls at a predetermined distance from the isolation structures 12. The well region 15 is located on the upper surface of the active region 13, and the source / drain region 16 is located on the upper surface of the well region 15.

[0097] Specifically, while ensuring device performance, the thickness of the semiconductor layer 11 can be selected according to the actual situation, and is not limited here.

[0098] Specifically, the isolation structure 12 includes a trench 121 located in the semiconductor layer 11 and an isolation layer 122 filling the trench 121. While ensuring device performance, the opening size and depth of the trench 121 can be selected according to the actual situation, and are not limited here.

[0099] Specifically, the material of the isolation layer 122 includes silicon oxide, silicon nitride, or other suitable high-dielectric materials.

[0100] Specifically, the gate structure 14 further includes a gate dielectric layer 141 and a gate conductive layer 142.

[0101] Specifically, the semiconductor device further includes an interlayer dielectric layer, a gate, a source, and a drain. The interlayer dielectric layer covers the exposed surfaces of the active region 13 and the gate structure 14. The gate is electrically connected to the gate conductive layer 142, and the source and the drain are respectively electrically connected to the source and drain regions located on both sides of the gate structure 14.

[0102] Specifically, the semiconductor device is prepared using the semiconductor device preparation method described in Example 1, which improves the performance and yield of the semiconductor device.

[0103] The semiconductor device in this embodiment is prepared by using the semiconductor device preparation method described in Embodiment 1, thereby improving the performance and yield of the semiconductor device.

[0104] In summary, the semiconductor device and its fabrication method of the present invention improve the process for fabricating the well region and source / drain region by forming a barrier layer of predetermined thickness between the upper surface of the semiconductor structure and the photoresist layer. During the formation of the well region, a first opening is formed in the photoresist layer to expose the barrier layer. The barrier layer blocks plasma, preventing direct contact between plasma and the active region and reducing the energy of plasma entering the active region, thus reducing the risk of plasma damage to the active region during the formation of the well region. During the formation of the source / drain region, a second opening is formed in the barrier layer based on the first opening, and the photoresist layer is removed. By using the barrier layer as a shielding layer, the poor process stability and difficulty in cleaning the photoresist layer when directly using it as a shielding layer are avoided, thus improving process stability and enhancing the performance and yield of the semiconductor device. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0105] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor structure is provided, the semiconductor structure including a semiconductor layer, an isolation structure located in the semiconductor layer, an active region located between the isolation structures, and a gate structure whose sidewalls are at a predetermined distance from the isolation structures; A barrier layer and a photoresist layer located on the upper surface of the semiconductor structure are sequentially formed. The barrier layer covers the exposed surface of the gate structure. The barrier layer includes an anti-reflection layer. The thickness of the barrier layer ranges from 5000 Å to 10000 Å. A first opening is formed in the photoresist layer, the bottom of the first opening exposes the barrier layer, a first conductivity type well region is formed on the upper surface layer of the active region based on the first opening, and the barrier layer at the bottom of the first opening is removed to form a second opening located in the barrier layer, the bottom of the second opening exposes the active region and the gate structure. Remove the photoresist layer and form a source / drain region of a second conductivity type based on the second opening. The source / drain region is located on the upper surface of the well region between the gate structure and the isolation structure. Remove the barrier layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method of forming the barrier layer includes coating.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method for removing the barrier layer at the bottom of the first opening includes one of dry etching and wet etching.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method for forming the trap region includes ion implantation.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that: The method for forming the source / drain region includes ion implantation.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that: The ion implantation energy range for forming the source / drain region is 3 keV to 150 keV, and the ion implantation dose range for forming the source / drain region is 1.0 × 10⁻⁶. 13 / cm 2 ~7×10 14 / cm 2 .

7. The method for fabricating a semiconductor device according to claim 5, characterized in that: The ion implantation angle range for forming the source / drain region is 15° to 75°.

8. A semiconductor device, characterized in that: The semiconductor device is fabricated using the semiconductor device fabrication method as described in any one of claims 1 to 7.

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